FN4910 Rev.24.00 Page 1 of 39
May 30, 2019
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
±15kV ESD Protected, +3V to +5.5V, 1µA, 250kbps, RS-232 Transmitters/Receivers
Datasheet
The ICL3221E, ICL3222E, ICL3223E, ICL3232E,
ICL3241E, and ICL3243E are 3.0V to 5.5V powered
RS-232 transmitters/receivers that meet ElA/TIA-232
and V.28/V.24 specifications, even at VCC = 3.0V.
Additionally, they provide ±15kV ESD protection
(IEC61000-4-2 Air Gap and Human Body Model) on
transmitter outputs and receiver inputs (RS-232 pins).
Targeted applications are notebook and laptop
computers in which the low operational power
consumption and even lower standby power
consumption is critical. Efficient on-chip charge
pumps, coupled with manual and automatic
power-down functions (except for the ICL3232E),
reduce the standby supply current to a 1µA trickle.
Small footprint packaging and the use of small, low
value capacitors ensure board space savings. Data
rates greater than 250kbps are ensured at worst case
load conditions. This family is fully compatible with
3.3V-only systems, mixed 3.3V and 5.0V systems,
and 5.0V-only systems.
The ICL324XE are 3-driver, 5-receiver devices that
provide a complete serial port suitable for laptop or
notebook computers. Both devices also include
noninverting always-active receivers for “wake-up”
capability.
The ICL3221E, ICL3223E, and ICL3243E feature an
automatic power-down function that powers down the
on-chip power supply and driver circuits. Power-down
occurs when an attached peripheral device is shut off
or the RS-232 cable is removed, which conserves
system power automatically without changes to the
hardware or operating system. These devices power
up again when a valid RS-232 voltage is applied to
any receiver input.
Table 1 on page 2 summarizes the features of the
devices represented by this datasheet, and
Application Note AN9863 summarizes the features of
each device in the ICL32xxE 3V family.
Related Literature
For a full list of documents, visit our website:
•ICL3221E, ICL3222E, ICL3223E, ICL3232E,
ICL3241E, and ICL3243E device pages
Features
• ESD protection for RS-232 I/O pins to ±15kV
(IEC61000)
• Drop-in replacements for the MAX3221E,
MAX3222E, MAX3223E, MAX3232E, MAX3241E,
MAX3243E, and SP3243E
• The ICL3221E is a low-power, pin-compatible
upgrade for the 5V MAX221E
• The ICL3222E is a low-power, pin-compatible
upgrade for the 5V MAX242E and SP312E
• The ICL3232E is a low-power upgrade for the
HIN232E, ICL232, and pin-compatible competitor
devices
• RS-232 compatible with VCC = 2.7V
• Meets EIA/TIA-232 and V.28/V.24 specifications
at 3V
• Latch-up free
• On-chip voltage converters require only four
external 0.1µF capacitors at VCC = 3.3V
• Manual and automatic power-down features
• Ensured mouse driveability (ICL324xE only)
• Receiver hysteresis for improved noise immunity
• Ensured minimum data rate: 250kbps
• Wide power supply range: single +3V to +5.5V
• Low supply current in power-down state: 1µA
• Pb-free (RoHS compliant)
Applications
• Any system requiring RS-232 communication ports
○ Battery powered, hand-held, and portable
equipment
○ Laptop computers and notebooks
○ Modems, printers, and other peripherals
○ Digital cameras
○ Cellular/mobile phones
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
FN4910 Rev.24.00 Page 2 of 39
May 30, 2019
Table 1. Summary of Features
Part
Number
Number of
Tx
Number of
Rx
Number of
Monitor
Receivers
(Routb)
Data
Rate
(kbps)
Receiver
Enable
Function?
Ready
Output?
Manual
Power-Down?
Automatic
Power-Down
Function?
ICL3221E 1 1 0 250 Yes No Yes Yes
ICL3222E 2 2 0 250 Yes No Yes No
ICL3223E 2 2 0 250 Yes No Yes Yes
ICL3232E 2 2 0 250 No No No No
ICL3241E 3 5 2 250 Yes No Yes No
ICL3243E 3 5 1 250 No No Yes Yes
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
FN4910 Rev.24.00 Page 3 of 39
May 30, 2019
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1 Typical Operating Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2. Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3. Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4. Application Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Charge-Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1.1 Charge-Pump Abs Max Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 Receivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4 Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5 Power-Down Functionality (Except ICL3232E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5.1 Software Controlled (Manual) Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5.2 INVALID Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5.3 Automatic Power-Down (ICL3221E, ICL3223E, and ICL3243E Only) . . . . . . . . . . . . . . . . . . . . . . 20
4.6 Receiver ENABLE Control (ICL3221E, ICL3222E, ICL3223E, and ICL3241E Only) . . . . . . . . . . . . . 21
4.7 Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.8 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.9 Operation Down to 2.7V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.10 Transmitter Outputs when Exiting Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.11 Mouse Driveability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.12 High Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.13 Interconnection with 3V and 5V Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.14 Pin-Compatible Replacements for 5V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5. ±15kV ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 Human Body Model (HBM) Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 IEC61000-4-2 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3 Air-Gap Discharge Test Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.4 Contact Discharge Test Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6. Die Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8. Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 1. Overview
FN4910 Rev.24.00 Page 4 of 39
May 30, 2019
1. Overview
1.1 Typical Operating Circuits
ICL3221E
ICL3222E
15
VCC
T1OUT
T1IN
T1
0.1µF
+0.1µF
+
0.1µF
11 13
2
4
3
7
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
5
6
R1OUT R1IN
R1
89
5kΩ
C1
C2
+C3
C4
EN
1
GND
+3.3V +0.1µF
14
TTL/CMOS
Logic Levels
RS-232
Levels
FORCEON
FORCEOFF
12
16 VCC
10
INVALID To Power
Control Logic
+
C3 (Optional Connection, Note)
Note: The negative terminal of C3 can be connected to either VCC or GND
17
VCC
T1OUT
T2OUT
T1IN
T2IN
T1
T2
0.1µF
+0.1µF
+
0.1µF
12
11
15
8
2
4
3
7
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
5
6
R1OUT R1IN
14
5kΩ
R2OUT R2IN
9
10
5kΩ
13
C1
C2
+C3
C4
EN
SHDN
1
GND
18
+3.3V +0.1µF
16
VCC
TTL/CMOS
Logic Levels
RS-232
Levels
R1
R2
+
C3 (Optional Connection, Note)
Note: The negative terminal of C3 can be connected to either VCC or GND
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 1. Overview
FN4910 Rev.24.00 Page 5 of 39
May 30, 2019
ICL3223E
ICL3232E
19
VCC
T1OUT
T2OUT
T1IN
T2IN
T1
T2
0.1µF
+0.1µF
+
0.1µF
13
12
17
8
2
4
3
7
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
5
6
R1OUT R1IN
16
5kΩ
R2OUT R2IN
910
5kΩ
15
C1
C2
+C3
C4
EN
1
GND
+3.3V +0.1µF
18
TTL/CMOS
Logic Levels
RS-232
Levels
R1
R2
FORCEON
FORCEOFF
14
20 VCC
11
INVALID To Power
Control Logic
16
VCC
T1OUT
T2OUT
T1IN
T2IN
T1
T2
0.1µF
+
0.1µF
+
0.1µF
11
10
14
7
1
3
2
6
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
4
5
R1OUT R1IN
13
5kΩ
R2OUT R2IN
8
9
5kΩ
12
C1
C2
+C3
C4
GND
+3.3V +0.1µF
15
TTL/CMOS
Logic Levels
RS-232
Levels
R1
R2
+
C3 (Optional Connection, Note)
Note: The negative terminal of C3 can be connected to either VCC or GND
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 1. Overview
FN4910 Rev.24.00 Page 6 of 39
May 30, 2019
1.2 Ordering Information
ICL3241E ICL3243E
Part Number
(Notes 2, 3)
Part
Marking
Temp
Range (°C)
Tape and Reel
(Units) (Note 1)
Package (RoHS
Compliant)
Pkg.
Dwg. #
ICL3221ECAZ ICL32 21ECAZ 0 to +70 - 16 Ld SSOP M16.209
ICL3221ECAZ-T ICL32 21ECAZ 0 to +70 1k 16 Ld SSOP M16.209
ICL3221ECAZ-T7A ICL32 21ECAZ 0 to +70 250 16 Ld SSOP M16.209
ICL3221ECVZ 3221 ECVZ 0 to +70 - 16 Ld TSSOP M16.173
ICL3221ECVZ-T 3221 ECVZ 0 to +70 2.5k 16 Ld TSSOP M16.173
ICL3221EIAZ ICL32 21EIAZ -40 to +85 - 16 Ld SSOP M16.209
ICL3221EIAZ-T ICL32 21EIAZ -40 to +85 1k 16 Ld SSOP M16.209
ICL3221EIAZ-T7A ICL32 21EIAZ -40 to +85 250 16 Ld SSOP M16.209
ICL3221EIVZ 3221 EIVZ -40 to +85 - 16 Ld TSSOP M16.173
ICL3221EIVZ-T 3221 EIVZ -40 to +85 2.5k 16 Ld TSSOP M16.173
ICL3221EIVZ-T7A 3221 EIVZ -40 to +85 250 16 Ld TSSOP M16.173
ICL3222ECAZ ICL32 22ECAZ 0 to +70 - 20 Ld SSOP M20.209
26
VCC
T1OUT
T2OUT
T3OUT
T1IN
T2IN
T3IN
T1
T2
T3
0.1µF
+0.1µF
+
0.1µF
14
13
9
10
12 11
28
24
27
3
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
1
2
R1OUT R1IN
4
5kΩ
R2OUT R2IN
518
5kΩ
R3OUT R3IN
617
5kΩ
R4OUT R4IN
716
5kΩ
R5OUT R5IN
R5
815
5kΩ
19
R2OUTB
C1
C2
+C3
C4
EN
SHDN
23
GND
22
+3.3V +0.1µF
20
25
VCC
TTL/CMOS
Logic
RS-232
Levels
RS-232
Levels
R1OUTB
21
R1
R2
R3
R4
Levels
26
VCC
T1OUT
T2OUT
T3OUT
T1IN
T2IN
T3IN
T1
T2
T3
0.1µF
+0.1µF
+
0.1µF
14
13
9
10
12 11
28
24
27
3
V+
V-
C1+
C1-
C2+
C2-
+
0.1µF
1
2
R1OUT R1IN
4
5kΩ
R2OUT R2IN
518
5kΩ
R3OUT R3IN
617
5kΩ
R4OUT R4IN
716
5kΩ
R5OUT R5IN
R5
815
5kΩ
19
R2OUTB
C1
C2
+C3
C4
FORCEON
FORCEOFF
23
GND
22
+3.3V +0.1µF
20
25
VCC
TTL/CMOS
Logic
RS-232
Levels
RS-232
Levels
R1
R2
R3
R4
21
INVALID
To Power
Control
Levels
Logic
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 1. Overview
FN4910 Rev.24.00 Page 7 of 39
May 30, 2019
ICL3222ECAZ-T ICL32 22ECAZ 0 to +70 1k 20 Ld SSOP M20.209
ICL3222ECVZ ICL32 22ECVZ 0 to +70 - 20 Ld TSSOP M20.173
ICL3222ECVZ-T ICL32 22ECVZ 0 to +70 2.5k 20 Ld TSSOP M20.173
ICL3222EIAZ ICL32 22EIAZ -40 to +85 - 20 Ld SSOP M20.209
ICL3222EIAZ-T ICL32 22EIAZ -40 to +85 1k 20 Ld SSOP M20.209
ICL3222EIBZ 3222EIBZ -40 to +85 - 18 Ld SOIC M18.3
ICL3222EIBZ-T 3222EIBZ -40 to +85 1k 18 Ld SOIC M18.3
ICL3222EIVZ ICL32 22EIVZ -40 to +85 - 20 Ld TSSOP M20.173
ICL3222EIVZ-T ICL32 22EIVZ -40 to +85 2.5k 20 Ld TSSOP M20.173
ICL3223ECAZ ICL32 23ECAZ 0 to +70 - 20 Ld SSOP M20.209
ICL3223ECAZ-T ICL32 23ECAZ 0 to +70 1k 20 Ld SSOP M20.209
ICL3223ECVZ (No longer
available, recommended
replacement: ICL3223EIVZ)
ICL32 23ECVZ 0 to +70 - 20 Ld TSSOP M20.173
ICL3223ECVZ-T (No longer
available, recommended
replacement: ICL3223EIVZ-T)
ICL32 23ECVZ 0 to +70 2.5k 20 Ld TSSOP M20.173
ICL3223EIAZ ICL32 23EIAZ -40 to +85 - 20 Ld SSOP M20.209
ICL3223EIAZ-T ICL32 23EIAZ -40 to +85 1k 20 Ld SSOP M20.209
ICL3223EIVZ ICL32 23EIVZ -40 to +85 - 20 Ld TSSOP M20.173
ICL3223EIVZ-T ICL32 23EIVZ -40 to +85 2.5k 20 Ld TSSOP M20.173
ICL3232ECAZ 3232 ECAZ 0 to +70 - 16 Ld SSOP M16.209
ICL3232ECAZ-T 3232 ECAZ 0 to +70 1k 16 Ld SSOP M16.209
ICL3232ECAZ-T7A 3232 ECAZ 0 to +70 250 16 Ld SSOP M16.209
ICL3232ECBZ 3232ECBZ 0 to +70 - 16 Ld SOIC M16.3
ICL3232ECBZ-T 3232ECBZ 0 to +70 1k 16 Ld SOIC M16.3
ICL3232ECBNZ 3232ECBNZ 0 to +70 - 16 Ld SOIC M16.15
ICL3232ECBNZ-T 3232ECBNZ 0 to +70 2.5k 16 Ld SOIC M16.15
ICL3232ECBNZ-T7A 3232ECBNZ 0 to +70 250 16 Ld SOIC M16.15
ICL3232ECV-16Z 3232E CV-16Z 0 to +70 - 16 Ld TSSOP M16.173
ICL3232ECV-16Z-T 3232E CV-16Z 0 to +70 2.5k 16 Ld TSSOP M16.173
ICL3232ECV-16Z-T7A 3232E CV-16Z 0 to +70 250 16 Ld TSSOP M16.173
ICL3232ECV-20Z (No longer
available, recommended
replacement: ICL3232EIV-16Z)
ICL3232 ECV-20Z 0 to +70 - 20 Ld TSSOP M20.173
ICL3232ECV-20Z-T (No longer
available, recommended
replacement:
ICL3232EIV-16Z-T)
ICL3232 ECV-20Z 0 to +70 2.5k 20 Ld TSSOP M20.173
ICL3232EFV-16Z (No longer
available, recommended
replacement:
ICL3232EIV-16Z)
3232E FV-16Z -40 to +125 - 16 Ld TSSOP M16.173
ICL3232EFV-16Z-T (No longer
available, recommended
replacement: ICL3232EIV-16Z-T)
3232E FV-16Z -40 to +125 2.5k 16 Ld TSSOP M16.173
ICL3232EIAZ 3232 EIAZ -40 to +85 - 16 Ld SSOP M16.209
ICL3232EIAZ-T 3232 EIAZ -40 to +85 1k 16 Ld SSOP M16.209
ICL3232EIBZ 3232EIBZ -40 to +85 - 16 Ld SOIC M16.3
Part Number
(Notes 2, 3)
Part
Marking
Temp
Range (°C)
Tape and Reel
(Units) (Note 1)
Package (RoHS
Compliant)
Pkg.
Dwg. #
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 1. Overview
FN4910 Rev.24.00 Page 8 of 39
May 30, 2019
ICL3232EIBZ-T 3232EIBZ -40 to +85 1k 16 Ld SOIC M16.3
ICL3232EIBNZ 3232EIBNZ -40 to +85 - 16 Ld SOIC M16.15
ICL3232EIBNZ-T 3232EIBNZ -40 to +85 2.5k 16 Ld SOIC M16.15
ICL3232EIV-16Z 3232E IV-16Z -40 to +85 - 16 Ld TSSOP M16.173
ICL3232EIV-16Z-T 3232E IV-16Z -40 to +85 2.5k 16 Ld TSSOP M16.173
ICL3232EIV-16Z-T7A 3232E IV-16Z -40 to +85 250 16 Ld TSSOP M16.173
ICL3232EIV-20Z ICL3232 EIV-20Z -40 to +85 - 20 Ld TSSOP M20.173
ICL3232EIV-20Z-T ICL3232 EIV-20Z -40 to +85 2.5k 20 Ld TSSOP M20.173
ICL3241ECAZ ICL3241 ECAZ 0 to +70 - 28 Ld SSOP M28.209
ICL3241ECAZ-T ICL3241 ECAZ 0 to +70 1k 28 Ld SSOP M28.209
ICL3241ECVZ ICL3241 ECVZ 0 to +70 - 28 Ld TSSOP M28.173
ICL3241ECVZ-T ICL3241 ECVZ 0 to +70 2.5k 28 Ld TSSOP M28.173
ICL3241EIAZ ICL3241 EIAZ -40 to +85 - 28 Ld SSOP M28.209
ICL3241EIAZ-T ICL3241 EIAZ -40 to +85 1k 28 Ld SSOP M28.209
ICL3241EIVZ ICL3241 EIVZ -40 to +85 - 28 Ld TSSOP M28.173
ICL3241EIVZ-T ICL3241 EIVZ -40 to +85 2.5k 28 Ld TSSOP M28.173
ICL3243ECAZ ICL32 43ECAZ 0 to +70 - 28 Ld SSOP M28.209
ICL3243ECAZ-T ICL32 43ECAZ 0 to +70 1k 28 Ld SSOP M28.209
ICL3243ECBZ ICL3243ECBZ 0 to +70 - 28 Ld SOIC M28.3
ICL3243ECBZ-T ICL3243ECBZ 0 to +70 1k 28 Ld SOIC M28.3
ICL3243ECVZ ICL3243 ECVZ 0 to +70 - 28 Ld TSSOP M28.173
ICL3243ECVZ-T ICL3243 ECVZ 0 to +70 2.5k 28 Ld TSSOP M28.173
ICL3243EIAZ ICL32 43EIAZ -40 to +85 - 28 Ld SSOP M28.209
ICL3243EIAZ-T ICL32 43EIAZ -40 to +85 1k 28 Ld SSOP M28.209
ICL3243EIVZ ICL3243 EIVZ -40 to +85 - 28 Ld TSSOP M28.173
ICL3243EIVZ-T ICL3243 EIVZ -40 to +85 2.5k 28 Ld TSSOP M28.173
ICL3243EIVZ-T7A ICL3243 EIVZ -40 to +85 250 28 Ld TSSOP M28.173
Notes:
1. See TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
3. For Moisture Sensitivity Level (MSL), see the ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E device pages. For more
information about MSL, see TB363.
Part Number
(Notes 2, 3)
Part
Marking
Temp
Range (°C)
Tape and Reel
(Units) (Note 1)
Package (RoHS
Compliant)
Pkg.
Dwg. #
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 1. Overview
FN4910 Rev.24.00 Page 9 of 39
May 30, 2019
1.3 Pin Configurations
ICL3221E
(16 LD SSOP, TSSOP)
Top View
ICL3222E
(18 LD SOIC)
Top View
ICL3222E
(20 LD SSOP, TSSOP)
Top View
ICL3223E
(20 LD SSOP, TSSOP)
Top View
ICL3232E
(16 LD SOIC, SSOP, TSSOP-16)
Top View
ICL3232E
(20 LD TSSOP-20)
Top View
EN
C1+
V+
C1-
C2+
C2-
V-
R1IN
FORCEOFF
GND
T1OUT
FORCEON
T1IN
R1OUT
VCC
INVALID
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
EN
C1+
V+
C1-
C2+
C2-
V-
T2OUT
R2IN
SHDN
GND
T1OUT
R1IN
R1OUT
T2IN
VCC
T1IN
R2OUT
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
EN
C1+
V+
C1-
C2+
C2-
V-
T2OUT
R2IN
SHDN
GND
T1OUT
R1IN
R1OUT
T1IN
NC
VCC
NC
T2IN
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
R2OUT
EN
C1+
V+
C1-
C2+
C2-
V-
T2OUT
R2IN
FORCEOFF
GND
T1OUT
R1IN
R1OUT
T1IN
INVALID
VCC
FORCEON
T2IN
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
R2OUT
C1+
V+
C1-
C2+
C2-
V-
T2OUT
R2IN
VCC
T1OUT
R1IN
R1OUT
T1IN
R2OUT
GND
T2IN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
NC
C1+
V+
C1-
C2+
C2-
V-
T2OUT
R2IN
NC
GND
T1OUT
R1IN
R1OUT
T1IN
NC
VCC
T2IN
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
NC
R2OUT
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 1. Overview
FN4910 Rev.24.00 Page 10 of 39
May 30, 2019
1.4 Pin Descriptions
ICL3241E
(28 ld SOIC, SSOP, TSSOP)
Top View
ICL3243E
(28 ld SOIC, SSOP, TSSOP)
Top VIew
Pin Function
VCC System power supply input (3.0V to 5.5V)
V+ Internally generated positive transmitter supply (+5.5V)
V- Internally generated negative transmitter supply (-5.5V)
GND Ground connection
C1+ External capacitor (voltage doubler) is connected to this lead
C1- External capacitor (voltage doubler) is connected to this lead
C2+ External capacitor (voltage inverter) is connected to this lead
C2- External capacitor (voltage inverter) is connected to this lead
TIN TTL/CMOS compatible transmitter inputs
TOUT ±15kV ESD protected, RS-232 level (nominally ±5.5V) transmitter outputs
RIN ±15kV ESD protected, RS-232 compatible receiver inputs
ROUT TTL/CMOS level receiver outputs
ROUTB TTL/CMOS level, noninverting, always enabled receiver outputs
INVALID Active low output that indicates no valid RS-232 levels are present on any receiver input
EN Active low receiver enable control; does not disable ROUTB outputs
SHDN Active low input to shut down transmitters and on-board power supply to place device in low-power mode
FORCEOFF Active low to shut down transmitters and on-chip power supply, which overrides any automatic circuitry and FORCEON (see
Table 5 on page 18)
FORCEON Active high input to override automatic power-down circuitry, which keeps transmitters active (FORCEOFF must be high)
C2+
C2-
V-
R1IN
R2IN
R3IN
R4IN
R5IN
T1OUT
T3OUT
T3IN
T2IN
T1IN
C1+
VCC
GND
C1-
EN
R1OUTB
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
V+
SHDN
R2OUTB
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T2OUT
C2+
C2-
V-
R1IN
R2IN
R3IN
R4IN
R5IN
T1OUT
T3OUT
T3IN
T2IN
T1IN
C1+
VCC
GND
C1-
FORCEON
INVALID
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
V+
FORCEOFF
R2OUTB
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
T2OUT
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 2. Specifications
FN4910 Rev.24.00 Page 11 of 39
May 30, 2019
2. Specifications
2.1 Absolute Maximum Ratings
2.2 Thermal Information
Parameter Minimum Maximum Unit
VCC to GND -0.3 6 V
V+ to GND -0.3 7 V
V- to GND +0.3 -7 V
V+ to V- 14 V
Input Voltages
TIN, FORCEOFF, FORCEON, EN, SHDN -0.3 6 V
RIN ±28V
Output Voltages
TOUT ±13.2 V
ROUT
, INVALID -0.3 VCC + 0.3 V
Short-Circuit Duration
TOUT Continuous
ESD Rating See “Electrical Specifications” on page 12
Thermal Resistance (Typical) Note 4 θJA (°C/W)
16 Ld Wide SOIC Package 100
16 Ld Narrow SOIC Package 115
18 Ld SOIC Package 75
28 Ld SOIC Package 75
16 Ld SSOP Package 135
20 Ld SSOP Package 122
16 Ld TSSOP Package 145
20 Ld TSSOP Package 140
28 Ld SSOP and TSSOP Packages 100
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely
impact product reliability and result in failures not covered by warranty.
Note:
4. θJA is measured with the component mounted on a low-effective thermal conductivity test board in free air. See TB379 for details.
Parameter Minimum Maximum Unit
Maximum Junction Temperature (Plastic Package) +150 °C
Maximum Storage Temperature Range -65 +150 °C
Pb-Free Reflow Profile see TB493
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 2. Specifications
FN4910 Rev.24.00 Page 12 of 39
May 30, 2019
2.3 Recommended Operating Conditions
2.4 Electrical Specifications
Parameter Minimum Maximum Unit
Temperature Range
ICL32xxECX 0° +70 °C
ICL32xxEFX -40° +125 °C
ICL32xxEIX -40 +85 °C
Supply Voltage (VCC) 3.35V
Rx Input Voltage -15 +15 V
Test conditions: VCC = 3.0V to 5.5V, C1 - C4 = 0.1µF; unless otherwise specified. Typicals are at TA = +25°C. Boldface limits apply across the
operating temperature range.
Parameter Test Conditions
Temp
(°C)
Min
(Note 6)Typ
Max
(Note 6)Unit
DC Characteristics
Supply Current, Automatic
Power-Down
All RIN Open, FORCEON = GND, FORCEOFF = VCC
(ICL3221E, ICL3223E, ICL3243E Only)
25 - 1.0 10 µA
Supply Current, Power-Down FORCEOFF = SHDN = GND (Except ICL3232E) 25 - 1.0 10 µA
Supply Current,
Automatic Power-Down
Disabled
All Outputs Unloaded,
FORCEON =
FORCEOFF = SHDN =
VCC
VCC = 3.0V, ICL3241,
ICL3243
25 - 0.3 1.0 mA
VCC = 3.0V, ICL3223 25 - 0.7 3.0 mA
VCC = 3.15V, ICL3221,
ICL3222, ICL3223,
ICL3232
25 - 0.3 1.0 mA
Logic and Transmitter Inputs, Receiver Outputs
Input Logic Threshold Low TIN, FORCEON, FORCEOFF, EN, SHDN Full --0.8 V
Input Logic Threshold High TIN, FORCEON,
FORCEOFF, EN, SHDN
VCC = 3.3V Full 2.0 --V
VCC = 5.0V Full 2.4 --V
Input Leakage Current TIN, FORCEON,
FORCEOFF, EN, SHDN
All but ICL3232EF Full -±0.01 ±1.0 µA
ICL3232EF Full -±0.01 ±10 µA
Output Leakage Current
(Except ICL3232E)
FORCEOFF = GND or EN = VCC Full -±0.05 ±10 µA
Output Voltage Low IOUT = 1.6mA Full --0.4 V
Output Voltage High IOUT = -1.0mA All but ICL3232EF Full VCC - 0.6 VCC - 0.1 -V
ICL3232EF Full VCC - 0.9 VCC - 0.1 -V
Automatic Powerdown (ICL3221E, ICL3223E, ICL3243E only, FORCEON = GND, FORCEOFF = VCC)
Receiver Input Thresholds to
Enable Transmitters
ICL32xxE Powers Up (see Figure 6 on page 14)Full-2.7 -2.7 V
Receiver Input Thresholds to
Disable Transmitters
ICL32xxE Powers Down (see Figure 6 on page 14)Full -0.3 -0.3 V
INVALID Output Voltage Low IOUT = 1.6mA Full --0.4 V
INVALID Output Voltage High IOUT = -1.0mA Full VCC - 0.6 --V
Receiver Threshold to
Transmitters Enabled Delay
(tWU)
25 -100 -µs
Receiver Positive or Negative
Threshold to INVALID High
Delay (tINVH)
25 -1-µs
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 2. Specifications
FN4910 Rev.24.00 Page 13 of 39
May 30, 2019
Receiver Positive or Negative
Threshold to INVALID Low
Delay (tINVL)
25 - 30 - µs
Receiver Inputs
Input Voltage Range 25 -25 - 25 V
Input Threshold Low VCC = 3.3V 25 0.6 1.2 - V
VCC = 5.0V 25 0.8 1.5 - V
Input Threshold High VCC = 3.3V 25 - 1.5 2.4 V
VCC = 5.0V 25 - 1.8 2.4 V
Input Hysteresis 25 - 0.5 - V
Input Resistance 25 3 5 7 kΩ
Transmitter Outputs
Output Voltage Swing All Transmitter Outputs Loaded with 3kΩ to Ground Full ±5.0 ±5.4 -V
Output Resistance VCC = V+ = V- = 0V, Transmitter Output = ±2V Full 300 10M -Ω
Output Short-Circuit Current Full -±35 ±60 mA
Output Leakage Current VOUT = ±12V, VCC = 0V or 3V to 5.5V,
Automatic Power-Down or
FORCEOFF = SHDN = GND
Full --±25 µA
Mouse Driveability (ICL324XE Only)
Transmitter Output Voltage
(see Figure 15 on page 22)
T1IN = T2IN = GND, T3IN = VCC, T3OUT Loaded with
3kΩ to GND, T1OUT and T2OUT Loaded with 2.5mA
Each
Full ±5 --V
Timing Characteristics
Maximum Data Rate RL = 3kΩ, CL = 1000pF, One Transmitter Switching Full 250 500 - kbps
Receiver Propagation Delay Receiver Input to
Receiver Output,
CL= 150pF
tPHL 25 - 0.15 - µs
tPLH 25 - 0.15 - µs
Receiver Output Enable Time Normal Operation (Except ICL3232E) 25 - 200 - ns
Receiver Output Disable Time Normal Operation (Except ICL3232E) 25 - 200 - ns
Transmitter Skew tPHL to tPLH (Note 5) 25 - 100 - ns
Receiver Skew tPHL to tPLH 25 - 50 - ns
Transition Region Slew Rate VCC = 3.3V,
RL = 3kΩ to 7kΩ,
Measured from 3V to
-3V or -3V to 3V
CL = 150pF to 2500pF 25 4 - 30 V/µs
CL = 150pF to 1000pF 25 6 - 30 V/µs
ESD Performance
RS-232 Pins (TOUT, RIN) Human Body Model 25 - ±15 - kV
IEC61000-4-2 Contact Discharge 25 - ±8 - kV
IEC61000-4-2 Air Gap Discharge 25 - ±15 - kV
All Other Pins Human Body Model 25 - ±2 - kV
Notes:
5. Transmitter skew is measured at the transmitter zero crossing points.
6. Parameters with Min and/or Max limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
Test conditions: VCC = 3.0V to 5.5V, C1 - C4 = 0.1µF; unless otherwise specified. Typicals are at TA = +25°C. Boldface limits apply across the
operating temperature range. (Continued)
Parameter Test Conditions
Temp
(°C)
Min
(Note 6)Typ
Max
(Note 6)Unit
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 3. Typical Performance Curves
FN4910 Rev.24.00 Page 14 of 39
May 30, 2019
3. Typical Performance Curves
VCC = 3.3V, TA = +25°C.
Figure 1. Transmitter Output Voltage vs Load
Capacitance
Figure 2. Slew Rate vs Load Capacitance
Figure 3. Supply Current vs Load Capacitance When
Transmitting Data
Figure 4. Supply Current vs Load Capacitance When
Transmitting Data
Figure 5. Supply Current vs Load Capacitance When
Transmitting Data
Figure 6. Supply Current vs Supply Voltage
-6
-4
-2
0
2
4
6
1000 2000 3000 4000 50000
Load Capacitance (pF)
Transmitter Output Voltage (V)
1 Transmitter at 250kbps
VOUT+
VOUT -
1 or 2 Transmitters at 30kbps
Load Capacitance (pF)
Slew Rate (V/µs)
0 1000 2000 3000 4000 5000
5
10
15
20
25
+Slew
-Slew
0
5
10
15
20
25
30
45
35
40
0 1000 2000 3000 4000 5000
Load Capacitance (pF)
Supply Current (mA)
20kbps
250kbps
120kbps
ICL3221E
0
5
10
15
20
25
30
45
35
40
0 1000 2000 3000 4000 5000
Load Capacitance (pF)
Supply Current (mA)
20kbps
250kbps
120kbps
ICL3222E, ICL3223E, ICL3232E
10
15
20
25
30
45
35
40
01000 2000 3000 4000 5000
Load Capacitance (pF)
Supply Current (mA)
20kbps
250kbps
120kbps
ICL324XE
Supply Current (mA)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
0.5
1.0
1.5
2.0
Supply Voltage (V)
2.5
3.0
3.5 No Load
All Outputs Static
ICL3221E, ICL3222E, ICL3223E, ICL3232E
ICL324XE
ICL324XE
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 4. Application Information
FN4910 Rev.24.00 Page 15 of 39
May 30, 2019
4. Application Information
The ICL32xxE interface ICs operate from a single +3V to +5.5V supply, ensure a 250kbps minimum data rate,
require only four small external 0.1µF capacitors, feature low power consumption, and meet all ElA RS-232C and
V.28 specifications.
4.1 Charge-Pump
The ICL32xxE family uses regulated on-chip dual charge-pumps as voltage doublers, and voltage inverters to
generate ±5.5V transmitter supplies from a VCC supply as low as 3.0V. The charge-pumps allow the devices to
maintain RS-232 compliant output levels over the ±10% tolerance range of 3.3V powered systems. The efficient
on-chip power supplies require only four small external 0.1µF capacitors for the voltage doubler and inverter
functions at VCC = 3.3V. See “Capacitor Selection” on page 21 and Table 6 on page 21 for capacitor
recommendations for other operating conditions. The charge-pumps operate discontinuously (they turn off as
soon as the V+ and V- supplies are pumped up to the nominal values) and provide significant power savings.
4.1.1 Charge-Pump Abs Max Ratings
These 3V to 5V RS-232 transceivers have been fully characterized for 3.0V to 3.6V operation, and at critical
points for 4.5V to 5.5V operation. Furthermore, load conditions were favorable using static logic states only.
The specified maximum values for V+ and V- are +7V and -7V, respectively. These limits apply for VCC values set
to 3.0V and 3.6V (see Tab le 2). For VCC values set to 4.5V and 5.5V, the maximum values for V+ and
V- can approach +9V and -7V, respectively (Tab le 3). The breakdown characteristics for V+ and V- were
measured with ±13V.
Table 2. V+ and V- Values for VCC = 3.0V to 3.6V
C1 (μF) C2, C3, C4 (μF) Load
T1IN
(Logic State)
V+ (V) V- (V)
VCC = 3.0V VCC = 3.6V VCC = 3.0V VCC = 3.6V
0.1 0.1 Open H 5.80 6.56 -5.60 -5.88
L 5.80 6.56 -5.60 -5.88
2.4kbps 5.80 6.56 -5.60 -5.88
3kΩ // 1000pF H 5.88 6.60 -5.56 -5.92
L 5.76 6.36 -5.56 -5.76
2.4kbps 6.00 6.64 -5.64 -5.96
0.047 0.33 Open H 5.68 6.00 -5.60 -5.60
L 5.68 6.00 -5.60 -5.60
2.4kbps 5.68 6.00 -5.60 -5.60
3kΩ // 1000pF H 5.76 6.08 -5.64 -5.64
L 5.68 6.04 -5.60 -5.60
2.4kbps 5.84 6.16 -5.64 -5.72
1 1 Open H 5.88 6.24 -5.60 -5.60
L 5.88 6.28 -5.60 -5.64
2.4kbps 5.80 6.20 -5.60 -5.60
3kΩ // 1000pF H 5.88 6.44 -5.64 -5.72
L 5.88 6.04 -5.64 -5.64
2.4kbps 5.92 6.40 -5.64 -5.64
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 4. Application Information
FN4910 Rev.24.00 Page 16 of 39
May 30, 2019
The resulting new maximum voltages at V+ and V- are listed in Tab le 4.
4.2 Transmitters
The transmitters are proprietary, low dropout, inverting drivers that translate TTL/CMOS inputs to EIA/TIA-232
output levels. The transmitters are coupled with the on-chip ±5.5V supplies and deliver true RS-232 levels across
a wide range of single supply system voltages.
Except for the ICL3232E, all transmitter outputs disable and assume a high impedance state when the device
enters the power-down mode (see Table 5 on page 18). The outputs can be driven to ±12V when disabled.
All devices operate at a 250kbps data rate for full load conditions (3kΩ and 1000pF), VCC ≥ 3.0V, with one
transmitter operating at full speed. Under more typical conditions of VCC ≥ 3.3V, RL = 3kΩ, and CL = 250pF, one
transmitter easily operates at 900kbps.
The transmitter inputs float if left unconnected and can increase ICC. Connect unused inputs to GND for the best
performance.
4.3 Receivers
All the ICL32xxE devices except for the ICL3232E contain standard inverting receivers that three-state from the
EN or FORCEOFF control lines. The two ICL324XE devices include noninverting (monitor) receivers (denoted by
the ROUTB label) that are always active, regardless of the state of any control lines. All the receivers convert
RS-232 signals to CMOS output levels and accept inputs up to ±25V while presenting the required 3kΩ to 7kΩ
input impedance (see Figure 7) even if the power is off (VCC = 0V). The receivers’ Schmitt trigger input stage uses
hysteresis to increase noise immunity and decrease errors due to slow input signal transitions.
Table 3. V+ and V- Values for VCC = 4.5V to 5.5V
C1 (μF) C2, C3, C4 (μF) Load
T1IN
(Logic State)
V+ (V) V- (V)
VCC = 4.5V VCC = 5.5V VCC = 4.5V VCC = 5.5V
0.1 0.1 Open H 7.44 8.48 -6.16 -6.40
L 7.44 8.48 -6.16 -6.44
2.4kbps 7.44 8.48 -6.17 -6.44
3kΩ // 1000pF H 7.76 8.88 -6.36 -6.72
L 7.08 8.00 -5.76 -5.76
2.4kbps 7.76 8.84 -6.40 -6.64
0.047 0.33 Open H 6.44 6.88 -5.80 -5.88
L 6.48 6.88 -5.84 -5.88
2.4kbps 6.44 6.88 -5.80 -5.88
3kΩ // 1000pF H 6.64 7.28 -5.92 -6.04
L 6.24 6.60 -5.52 -5.52
2.4kbps 6.72 7.16 -5.92 -5.96
1 1 Open H 6.84 7.60 -5.76 -5.76
L 6.88 7.60 -5.76 -5.76
2.4kbps 6.92 7.56 -5.72 -5.76
3kΩ // 1000pF H 7.28 8.16 -5.80 -5.92
L 6.44 6.84 -5.64 -6.84
2.4kbps 7.08 7.76 -5.80 -5.80
Table 4. New Measured Withstanding Voltages
V+, V- to Ground ±13V
V+ to V- 20V
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 4. Application Information
FN4910 Rev.24.00 Page 17 of 39
May 30, 2019
The ICL3221E, ICL3222E, ICL3223E, and ICL3241E inverting receivers disable only when EN is driven high. The
ICL3243E receiver disables during forced (manual) power-down, but not during automatic power-down (see
Table 5 on page 18).
The ICL3241E and ICL3243E monitor receivers remain active even during manual power-down and forced
receiver disable, which makes them extremely useful for Ring Indicator monitoring. Standard receivers driving
powered down peripherals must be disabled to prevent current flow through the peripheral’s protection diodes
(see Figures 8 and 9). When disabled, the receivers cannot be used for wake up functions, but the corresponding
monitor receiver can be dedicated to this task, as shown in Figure 9.
RXOUT
GND ≤ VROUT ≤ VCC
5kΩ
RXIN
-25V ≤ VRIN ≤ +25V
GND
VCC
Figure 7. Inverting Receiver Connections
Figure 8. Power Drain Through Powered Down Peripheral
Old
VCC
Powered
GND SHDN = GND
VCC
Rx
Tx
VCC
Current
VOUT = VCC
Flow
RS-232 Chip
Down
UART
Figure 9. Disabled Receivers Prevent Power Drain
ICL324XE
Transition
RX
TX
R2OUTB
R2OUT
T1IN
FORCEOFF = GND
VCC
VCC
To
R2IN
T1OUT
VOUT = HI-Z
Powered
or SHDN = GND, EN = VCC
Detector
Down
UART
Wake-up
Logic
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 4. Application Information
FN4910 Rev.24.00 Page 18 of 39
May 30, 2019
4.4 Low Power Operation
These 3V devices require a nominal supply current of 0.3mA, even at VCC = 5.5V, during normal operation (not in
power-down mode). This current is considerably less than the 5mA to 11mA current required by comparable 5V
RS-232 devices and allows you to reduce system power simply by switching to this family.
4.5 Power-Down Functionality (Except ICL3232E)
The already low current requirement drops significantly when the device enters power-down mode. In
power-down, the supply current drops to 1µA because the on-chip charge pump turns off (V+ collapses to VCC
and V- collapses to GND), and the transmitter outputs three-state. Inverting receiver outputs may disable in
power-down; see Ta bl e 5 for details. This micro-power mode makes these devices ideal for battery powered and
portable applications.
4.5.1 Software Controlled (Manual) Power-Down
Most devices in the ICL32xxE family provide pins that allow you to force the IC into the low power standby state.
On the ICL3222E and ICL3241E, the power-down control is a simple shutdown (SHDN) pin. Driving this pin high
enables normal operation, and driving it low forces the IC into its power-down state. Connect SHDN to VCC if the
power-down function is not needed. Note that all the receiver outputs remain enabled during shutdown (see
Tab le 5 ). For the lowest power consumption during power-down, the receivers should also be disabled by driving
the EN input high (see “Receiver ENABLE Control (ICL3221E, ICL3222E, ICL3223E, and ICL3241E Only)” on
page 21 and Figures 8 and 9).
The ICL3221E, ICL3223E, and ICL3243E use a two pin approach in which the FORCEON and FORCEOFF
inputs determine the IC’s mode. For always enabled operation, FORCEON and FORCEOFF are both strapped
high. Under logic or software control, only the FORCEOFF input needs to be driven to switch between active and
power-down modes. The FORCEON state is not critical because FORCEOFF overrides FORCEON. However, if
strictly manual control over power-down is needed, you must strap FORCEON high to disable the automatic
power-down circuitry. The ICL3243E inverting (standard) receiver outputs also disable when the device is in
manual power-down, which eliminates the possible current path through a shutdown peripheral’s input protection
diode (see Figures 8 and 9).
Table 5. Power-Down and Enable Logic Truth Table
RS-232
Signal
Present at
Receiver
Input?
FORCEOFF
or SHDN
Input
FORCEON
Input
EN
Input
Transmitter
Outputs
Receiver
Outputs
ROUTB
Outputs
(Note 7)
INVALID
Output
Mode of
Operation
ICL3222E, ICL3241E
N/A L N/A L High-Z Active Active N/A Manual Power-Down
N/A L N/A H High-Z High-Z Active N/A Manual Power-Down
with Receiver Disabled
N/A H N/A L Active Active Active N/A Normal Operation
N/A H N/A H Active High-Z Active N/A Normal Operation with
Receiver Disabled
ICL3221E, ICL3223E
No H H L Active Active N/A L Normal Operation
(Auto Power-Down
Disabled)
No H H H Active High-Z N/A L
Yes H L L Active Active N/A H Normal Operation
(Auto Power-Down
Enabled)
Yes H L H Active High-Z N/A H
No H L L High-Z Active N/A L Power-Down Due to
Auto Power-Down
Logic
No H L H High-Z High-Z N/A L
Yes L X L High-Z Active N/A H Manual Power-Down
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 4. Application Information
FN4910 Rev.24.00 Page 19 of 39
May 30, 2019
4.5.2 INVALID Output
The INVALID output always indicates whether a valid RS-232 signal is present at any of the receiver inputs (see
Tab le 5 ) and provides an easy way to determine when the interface block should power down. If an interface
cable is disconnected and all the receiver inputs are floating (but pulled to GND by the internal receiver pull down
resistors), the INVALID logic detects the invalid levels and drives the output low. The power management logic
then uses this indicator to power down the interface block. Reconnecting the cable restores valid levels at the
receiver inputs, INVALID switches high, and the power management logic wakes up the interface block. INVALID
can also indicate the DTR or RING INDICATOR signal as long as the other receiver inputs are floating or driven to
GND (as in the case of a powered down driver). Connecting FORCEOFF and FORCEON together disables the
automatic power-down feature and enables them to function as a manual SHUTDOWN input (see Figure 10).
With any of the control schemes, the time required to exit power-down and resume transmission is 100µs. A
mouse or other application may need more time to wake up from shutdown. If automatic power-down is used, the
RS-232 device reenters power-down if valid receiver levels are not reestablished within 30µs of the ICL32xxE
Yes L X H High-Z High-Z N/A H Manual Power-Down
with Receiver Disabled
No L X L High-Z Active N/A L Manual Power-Down
No L X H High-Z High-Z N/A L Manual Power-Down
with Receiver Disabled
ICL3243E
No H H N/A Active Active Active L Normal Operation
(Auto Power-Down
Disabled)
Yes H L N/A Active Active Active H Normal Operation
(Auto Power-Down
Enabled)
No H L N/A High-Z Active Active L Power-Down Due to
Auto Power-Down
Logic
Yes L X N/A High-Z High-Z Active H Manual Power-Down
No L X N/A High-Z High-Z Active L Manual Power-Down
Note:
7. Applies only to the ICL3241E and ICL3243E.
Table 5. Power-Down and Enable Logic Truth Table (Continued)
RS-232
Signal
Present at
Receiver
Input?
FORCEOFF
or SHDN
Input
FORCEON
Input
EN
Input
Transmitter
Outputs
Receiver
Outputs
ROUTB
Outputs
(Note 7)
INVALID
Output
Mode of
Operation
Figure 10. Connections For Manual Power-Down When no Valid Receiver Signals are Present
FORCEOFF
INVALID
CPU
I/O
FORCEON
ICL3221E,
UART
ICL3243E
ICL3223E,
Power
Management
Logic
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 4. Application Information
FN4910 Rev.24.00 Page 20 of 39
May 30, 2019
powering up. Figure 11 shows a circuit that prevents the ICL32xxE from initiating automatic power-down for
100ms after powering up. The delay gives the slow-to-wake peripheral circuit time to reestablish valid RS-232
output levels.
4.5.3 Automatic Power-Down (ICL3221E, ICL3223E, and ICL3243E Only)
Even greater power savings are available by using the ICL3221E, ICL3223E, or ICL3243E’s automatic
power-down function. When no valid RS-232 voltages are sensed on any receiver input for 30µs (see Figure 12),
the charge-pump and transmitters power down and reduce the supply current to 1µA. Invalid receiver levels occur
whenever the driving peripheral’s outputs are shut off (powered down) or when the RS-232 interface cable is
disconnected. The ICL32xxE powers back up whenever it detects a valid RS-232 voltage level on any receiver
input. The automatic power-down feature provides additional system power savings without changes to the
existing operating system.
Automatic power-down operates when the FORCEON input is low and the FORCEOFF input is high. Tying
FORCEON high disables automatic power-down, but manual power-down is always available with the overriding
FORCEOFF input. Table 5 on page 18 summarizes the automatic power-down functionality.
Devices with the automatic power-down feature include an INVALID output signal that switches low to indicate
that invalid levels have persisted on all of the receiver inputs for more than 30µs (see Figure 13). INVALID
switches high 1µs after detecting a valid RS-232 level on a receiver input. INVALID operates in all modes (forced
or automatic power-down, or forced on), so it is also useful for systems employing manual power-down circuitry.
When automatic power-down is used, INVALID = 0 indicates that the ICL32xxE is in power-down mode.
The time to recover from automatic power-down mode is typically 100µs.
Figure 12. Definition of Valid RS-232 Receiver Levels
Figure 11. Circuit to Prevent Auto Power-Down For 100ms After Forced Power-Up
ICL3221E, ICL3223E, ICL3243E
FORCEOFF FORCEON
Power Master Power-Down Line
1MΩ
0.1µF
Management
Unit
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 4. Application Information
FN4910 Rev.24.00 Page 21 of 39
May 30, 2019
4.6 Receiver ENABLE Control (ICL3221E, ICL3222E, ICL3223E, and ICL3241E Only)
The ICL3221E, ICL3222E, ICL3223E, and ICL3241E also feature an EN input to control the receiver outputs.
Driving EN high disables all the inverting (standard) receiver outputs and places them in a high impedance state.
The high impedance state is useful for eliminating supply current, due to a receiver output forward biasing the
protection diode when driving the input of a powered down (VCC = GND) peripheral (see Figure 8 on page 17).
The enable input has no effect on transmitter or monitor (ROUTB) outputs.
4.7 Capacitor Selection
The charge-pumps require 0.1µF capacitors for 3.3V operation. For other supply voltages, see Tab l e 6 for
capacitor values. Do not use values smaller than those listed in Ta b le 6 . Increasing the capacitor values (by a
factor of 2) reduces ripple on the transmitter outputs and slightly reduces power consumption. C2, C3, and C4 can
be increased without increasing C1’s value; however, do not increase C1 without also increasing C2, C3, and C4 to
maintain the proper ratios (C1 to the other capacitors).
When using minimum required capacitor values, make sure that capacitor values do not degrade excessively with
temperature. If in doubt, use capacitors with a larger nominal value. The capacitor’s Equivalent Series Resistance
(ESR) usually rises at low temperatures and it influences the amount of ripple on V+ and V-.
4.8 Power Supply Decoupling
In most circumstances, a 0.1µF bypass capacitor is adequate. In applications that are particularly sensitive to
power supply noise, decouple VCC to ground with a capacitor of the same value as the charge-pump capacitor C1.
Connect the bypass capacitor as close as possible to the IC.
4.9 Operation Down to 2.7V
The ICL32xxE transmitter outputs meet RS-562 levels (±3.7V) at full data rate, with VCC as low as 2.7V. RS-562
levels typically ensure interoperability with RS-232 devices.
Table 6. Required Capacitor ValueS
VCC (V) C1 (µF) C2, C3, C4 (µF)
3.0 to 3.6 0.1 0.1
4.5 to 5.5 0.047 0.33
3.0 to 5.5 0.1 0.47
Receiver
Inputs
Transmitter
Outputs
INVALID
Output
V+
VCC
0
V-
VCC
0
tINVL tINVH
Invalid
Region
}
Figure 13. Automatic Power-Down and INVALID Timing Diagrams
AUTOPWDN PWR UP
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 4. Application Information
FN4910 Rev.24.00 Page 22 of 39
May 30, 2019
4.10 Transmitter Outputs when Exiting Power-Down
Figure 14 shows the response of two transmitter outputs when exiting power-down mode. As they activate, the
two transmitter outputs properly go to opposite RS-232 levels, with no glitching, ringing, or undesirable transients.
Each transmitter is loaded with 3kΩ in parallel with 2500pF. Note that the transmitters enable only when the
magnitude of the supplies exceeds approximately 3V.
4.11 Mouse Driveability
The ICL3241E and ICL3243E are specifically designed to power a serial mouse while operating from low voltage
supplies. Figure 15 shows the transmitter output voltages under increasing load current. The on-chip switching
regulator ensures the transmitters supply at least ±5V during worst case conditions (15mA for paralleled V+
transmitters, 7.3mA for a single V- transmitter). The Automatic Power-Down feature does not work with a mouse,
so FORCEOFF and FORCEON should be connected to VCC.
4.12 High Data Rates
The ICL32xxE devices maintain the RS-232 ±5V minimum transmitter output voltages even at high data rates.
Figure 16 shows a transmitter loopback test circuit and Figure 17 shows the loopback test result at 120kbps. For
this test, all transmitters were simultaneously driving RS-232 loads in parallel with 1000pF at 120kbps. Figure 18
shows the loopback results for a single transmitter driving 1000pF and an RS-232 load at 250kbps. The static
transmitters were also loaded with an RS-232 receiver.
Time (20µs/Div)
T1
T2
2V/Div
5V/Div
VCC = +3.3V
FORCEOFF
Figure 14. TRansmitter Outputs When Exiting Power-Down
C1 - C4 = 0.1µF
Figure 15. Transmitter Output Voltage vs Load Current (Per Transmitter,
Double Current Axis for Total VOUT+ Current)
Transmitter Output Voltage (V)
Load Current pPer Transmitter (mA)
0246810
-6
-4
-2
0
2
4
6
-5
-3
-1
1
3
5
13579
VOUT+
VOUT -
VCC
VOUT+
VOUT -
T1
T2
T3
VCC = 3.0V
ICL3241E, ICL3243E
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 4. Application Information
FN4910 Rev.24.00 Page 23 of 39
May 30, 2019
Figure 16. Transmitter Loopback Test Circuit
Figure 17. Loopback Test at 120kbps
Figure 18. Loopback Test at 250kbps
ICL32xxE
VCC FORCEOFF
C1
C2C4
C3
+
+
+
+
1000pF
V+
V-
5K
TIN
ROUT
C1+
C1-
C2+
C2-
RIN
TOUT
+
VCC
0.1µF
VCC
EN
SHDN or
T1IN
T1OUT
R1OUT
5µs/Div
VCC = +3.3V
5V/Div
C1 - C4 = 0.1µF
T1IN
T1OUT
R1OUT
2µs/Div
5V/Div
VCC = +3.3V
C1 - C4 = 0.1µF
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 4. Application Information
FN4910 Rev.24.00 Page 24 of 39
May 30, 2019
4.13 Interconnection with 3V and 5V Logic
The ICL32Exx devices directly interface with 5V CMOS and TTL logic families. The AC, HC, and CD4000 outputs
can drive ICL32Exx inputs with the ICL32Exx at 3.3V and the logic supply at 5V, but ICL32Exx outputs do not
reach the minimum VIH for these logic families. See Table 7 .
4.14 Pin-Compatible Replacements for 5V Devices
The ICL3221E, ICL3222E, and ICL3232E are pin-compatible with existing 5V RS-232 transceivers. See
“Features” on page 1 for more information.
The pin compatibility coupled with the low ICC and wide operating supply range make the ICL32xxE potential
lower power, higher performance drop-in replacements for existing 5V applications. The ICL32xxE works in most
5V applications as long as the ±5V RS-232 output swings are acceptable and transmitter input pull-up resistors
are not required.
When replacing a device in an existing 5V application, you can terminate C3 to VCC as shown in the “Typical
Operating Circuits” on page 4. If possible, terminate C3 to GND for slightly better performance.
Table 7. Logic Family Compatibility with Various Supply Voltages
System Power Supply
Voltage (V)
VCC Supply
Voltage (V) Compatibility
3.3 3.3 Compatible with all CMOS families
5 5 Compatible with all TTL and CMOS logic families
5 3.3 Compatible with ACT and HCT CMOS, and with TTL. ICL32XX
outputs are incompatible with AC, HC, and CD4000 CMOS inputs
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 5. ±15kV ESD Protection
FN4910 Rev.24.00 Page 25 of 39
May 30, 2019
5. ±15kV ESD Protection
All pins on the ICL32Exx devices include ESD protection structures, but the ICL32xxE family incorporates
advanced structures that allow the RS-232 pins (transmitter outputs and receiver inputs) to survive ESD events
up to ±15kV. The RS-232 pins are particularly vulnerable to ESD damage because they typically connect to an
exposed port on the exterior of the finished product. Touching the port pins or connecting a cable, can cause an
ESD event that might destroy unprotected ICs. The ESD structures protect the device whether or not it is powered
up, protect without allowing any latch-up mechanism to activate, and do not interfere with RS-232 signals as large
as ±25V.
5.1 Human Body Model (HBM) Testing
This test method emulates the ESD event delivered to an IC during human handling. The tester delivers the
charge through a 1.5kΩ current limiting resistor and makes the test less severe than the IEC61000 test, which
uses a 330Ω limiting resistor. The HBM method determines an IC’s ability to withstand the ESD transients
typically present during handling and manufacturing. Due to the random nature of these events, each pin is tested
with respect to all other pins. The RS-232 pins on “E” family devices can withstand HBM ESD events to ±15kV.
5.2 IEC61000-4-2 Testing
The IEC61000 test method applies to finished equipment rather than to an individual IC. Therefore, the pins most
likely to suffer an ESD event are those that are exposed to the outside world (the RS-232 pins in this case), and
the IC is tested in its typical application configuration (power applied) rather than testing each pin-to-pin
combination. The lower current limiting resistor coupled with the larger charge storage capacitor yields a test that
is much more severe than the HBM test. The extra ESD protection built into this device’s RS-232 pins allows the
design of equipment meeting level 4 criteria without the need for additional board level protection on the
RS-232 port.
5.3 Air-Gap Discharge Test Method
For the air-gap discharge test method, a charged probe tip moves toward the IC pin until the voltage arcs to it.
The current waveform delivered to the IC pin depends on factors such as approach speed, humidity, and
temperature, so it is difficult to obtain repeatable results. The “E” device RS-232 pins withstand ±15kV air-gap
discharges.
5.4 Contact Discharge Test Method
During the contact discharge test, the probe contacts the tested pin before the probe tip is energized and
eliminates the variables associated with the air-gap discharge. The test is more repeatable and predictable, but
equipment limits prevent testing devices at voltages higher than ±8kV. All “E” family devices survive ±8kV contact
discharges on the RS-232 pins.
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 6. Die Characteristics
FN4910 Rev.24.00 Page 26 of 39
May 30, 2019
6. Die Characteristics
Table 8. Die and Assembly Related Information
Substrate and QFN Thermal Pad Potential (Powered Up) GND
Transistor Count
ICL3221E 286
ICL3222E 338
ICL3223E 357
ICL3232E 296
ICL324xE 464
Process Si Gate CMOS
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 7. Revision History
FN4910 Rev.24.00 Page 27 of 39
May 30, 2019
7. Revision History
Rev. Date Description
FN4910.24 5/30/19 Applied new formatting.
Updated the Ordering Information table:
Removed:
ICL3222ECP
ICL3241ECBZ
ICL3241ECBZ-T
ICL3241EIBZ
ICL3241EIBZ-T
Added:
ICL3221ECVZ
ICL3221ECVZ-T
ICL3232ECV-16Z-T7A
ICL3232EIV-16Z-T7A
Added Charge-Pump Abs Max Ratings section on pages 14 and 15.
Removed package outline drawing E18.3.
Updated disclaimer.
FN4910.23 9/24/18 -Updated on-chip voltage converter VCC conditions from 2.7V to 3.3V on page 1
-Added product information page links to Related Literature section on page 1
-Updated Ordering Information table on page 8:
-Added Tape and Reel (Units) column
-Removed the following retired parts:
-ICL3221ECA, ICL3221ECA-T
-ICL3221ECAZA, ICL3221ECAZA-T
-ICL3221ECV, ICL3221ECV-T
-ICL3221EIA, ICL3221EIA-T
-ICL3221ECA, ICL3221ECA-T
-ICL3222ECV, ICL3222ECV-T
-ICL3222EIAZ, ICL3222EIAZ-T
-ICL3222EIB, ICL3222EIB-T
-ICL3223ECA, ICL3223ECA-T
-ICL3223ECV, ICL3223ECV-T
-ICL3223EIAZ, ICL3223EIAZ-T
-Added retirement notifications and replacement recommendations for the following parts:
-ICL3232ECV-20Z
-ICL3232ECV-20Z-T
-ICL3232EFV-16Z
-ICL3232EFV-16Z
-Updated RIN from ±25V to ±28V in the Absolute Maximum Ratings on page 12
-Updated Package Outline Drawing M16.15 from Rev. 1 to Rev. 2 on page 25
-Updated graphics to new standard layout and removed the dimensions table
-Removed About Intersil section
-Added Renesas disclaimer
FN4910.22 12/9/15 -Updated Ordering Information table starting on page 8
-Updated “Products” section to “About Intersil”
-POD E18.3 updated from rev 2 to rev 3. Changes since rev 2:
1) Removed the dimension chart and replaced with new standard format values for each dimension letter.
2) Updated D dimension (in side view; length of package) from 0.845(min) : 0.880(max) to 0.880(33.27)(min) :
0.920(34.65)(max)
3) Change JEDEC reference from MS-001-BC issue D to MS-001-AC issue D
-POD M16.173 updated from rev 1 to rev 2. Changes since rev 1: Converted to new POD format by moving
dimensions from table onto drawing and adding land pattern. No dimension changes.
-POD M20.173 updated from rev 1 to rev 2. Changes since rev 1: Converted to new POD format by moving
dimensions from table onto drawing and adding land pattern. No dimension changes.
-POD M28.173 udpated from rev 0 to rev 1. Changes since rev 1: Converted to new POD format by moving
dimensions from table onto drawing and adding land pattern. No dimension changes.
-POD M28.3 updated from rev 0 to rev 1. Changes since rev 1: Added land pattern
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 7. Revision History
FN4910 Rev.24.00 Page 28 of 39
May 30, 2019
FN4910.21 2/22/10 Revision history begins with this revision.
-Converted to new Intersil template.
-Added new temp grade (F = extended industrial) to ICL3232. Updated ordering info table, Operating
Conditions, and added 125°C specs for input lkg currents, and rcvr output high voltage.
-Pages 8-10: Removed all withdrawn devices from Ordering Information table.
-Pages 12-14: Added "Boldface limits apply over the operating temperature range." to common conditions of
Electrical Specs table. Replaced Note 6 "Parts are 100% tested at +25°C. Full temp limits are guaranteed by
bench and tester characterization." with "Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production tested."
Rev. Date Description
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 8. Package Outline Drawings
FN4910 Rev.24.00 Page 29 of 39
May 30, 2019
8. Package Outline Drawings
M16.15 (JEDEC MS-012-AC ISSUE C)
16 Lead Narrow Body Small Outline Plastic Package
Rev 2, 11/17
For the most recent package outline drawing, see M16.15.
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 8. Package Outline Drawings
FN4910 Rev.24.00 Page 30 of 39
May 30, 2019
M16.173
16 Lead Thin Shrink Small Outline Package (TSSOP)
Rev 2, 5/10
0.09-0.20
SEE DETAIL "X"
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
SIDE VIEW
END VIEW
Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
Dimensions are measured at datum plane H.
Dimensioning and tolerancing per ASME Y14.5M-1994.
Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
is 0.07mm.
Dimension in ( ) are for reference only.
Conforms to JEDEC MO-153.
6.
3.
5.
4.
2.
1.
NOTES:
7.
(0.65 TYP)
(5.65)
(0.35 TYP)
0.90 +0.15/-0.10
0.60 ±0.15
0.15 MAX
0.05 MIN
PLANE
GAUGE
0°-8°
0.25
1.00 REF
(1.45)
16
2
1
3
8
B
1 3
9
A
PIN #1
I.D. MARK
5.00 ±0.10
6.40
4.40 ±0.10
0.65
1.20 MAX
SEATING
PLANE
0.25 +0.05/-0.06 5
C
H
0.20 C B A
0.10 C
-
0.05
0.10 C B A
M
For the most recent package outline drawing, see M16.173.
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 8. Package Outline Drawings
FN4910 Rev.24.00 Page 31 of 39
May 30, 2019
Notes:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.13mm (0.005 inch) total in excess of “B”
dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
C
H0.25(0.010) BM M
α
0.25
0.010
GAUGE
PLANE
A2
M16.209 (JEDEC MO-150-AC ISSUE B)
16 Lead Shrink Small Outline Plastic Package (SSOP)
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.078 - 2.00 -
A1 0.002 - 0.05 - -
A2 0.065 0.072 1.65 1.85 -
B 0.009 0.014 0.22 0.38 9
C 0.004 0.009 0.09 0.25 -
D 0.233 0.255 5.90 6.50 3
E 0.197 0.220 5.00 5.60 4
e 0.026 BSC 0.65 BSC -
H 0.292 0.322 7.40 8.20 -
L 0.022 0.037 0.55 0.95 6
N16 167
α0° 8° 0° 8° -
Rev. 3 6/05
For the most recent package outline drawing, see M16.209.
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 8. Package Outline Drawings
FN4910 Rev.24.00 Page 32 of 39
May 30, 2019
Notes:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
α
M16.3 (JEDEC MS-013-AA ISSUE C)
16 Lead Wide Body Small Outline Plastic Package (SOIC)
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.3977 0.4133 10.10 10.50 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N16 167
α0° 8° 0° 8° -
Rev. 1 6/05
For the most recent package outline drawing, see M16.3.
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 8. Package Outline Drawings
FN4910 Rev.24.00 Page 33 of 39
May 30, 2019
Notes:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
α
M18.3 (JEDEC MS-013-AB ISSUE C)
18 Lead Wide Body Small Outline Plastic Package (SOIC)
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.4469 0.4625 11.35 11.75 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N18 187
α0° 8° 0° 8° -
Rev. 1 6/05
For the most recent package outline drawing, see M18.3.
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 8. Package Outline Drawings
FN4910 Rev.24.00 Page 34 of 39
May 30, 2019
M20.173
20 Lead Thin Shrink Small Outline Package (TSSOP)
Rev 2, 5/10
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
SIDE VIEW
END VIEW
Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
Dimensions are measured at datum plane H.
Dimensioning and tolerancing per ASME Y14.5M-1994.
Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
is 0.07mm.
Dimension in ( ) are for reference only.
Conforms to JEDEC MO-153.
6.
3.
5.
4.
2.
1.
NOTES:
7.
0.09-0.20
SEE DETAIL "X"
(0.65 TYP)
(5.65)
(0.35 TYP)
0.90 +0.15/-0.10
0.60 ±0.15
0.15 MAX
0.05 MIN
PLANE
GAUGE
0°-8°
0.25
1.00 REF
(1.45)
20
0.20 C B A
2
1
3
9
B
1 3
10
A
PIN #1
I.D. MARK
6.50 ±0.10
6.40
4.40 ±0.10
0.65
0.10 C
SEATING
PLANE
0.25 +0.05/-0.06 5
C
H
-
0.05
1.20 MAX
0.10 C B A
M
For the most recent package outline drawing, see M20.173.
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 8. Package Outline Drawings
FN4910 Rev.24.00 Page 35 of 39
May 30, 2019
Notes:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
α
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C A
MBS
e
-A-
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
C
H0.25(0.010) B
MM
L
0.25
0.010
GAUGE
PLANE
A2
M20.209 (JEDEC MO-150-AE ISSUE B)
20 Lead Shrink Small Outline Plastic Package (SSOP)
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.068 0.078 1.73 1.99
A1 0.002 0.008’ 0.05 0.21
A2 0.066 0.070’ 1.68 1.78
B 0.010’ 0.015 0.25 0.38 9
C 0.004 0.008 0.09 0.20’
D 0.278 0.289 7.07 7.33 3
E 0.205 0.212 5.20’ 5.38 4
e 0.026 BSC 0.65 BSC
H 0.301 0.311 7.65 7.90’
L 0.025 0.037 0.63 0.95 6
N20 207
α0 deg. 8 deg. 0 deg. 8 deg.
Rev. 3 11/02
For the most recent package outline drawing, see M20.209.
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 8. Package Outline Drawings
FN4910 Rev.24.00 Page 36 of 39
May 30, 2019
M28.173
28 Lead Thin Shrink Small Outline Package (TSSOP)
Rev 1, 5/10
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
SIDE VIEW
END VIEW
Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
Dimensions are measured at datum plane H.
Dimensioning and tolerancing per ASME Y14.5M-1994.
Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
is 0.07mm.
Dimension in ( ) are for reference only.
Conforms to JEDEC MO-153.
6.
3.
5.
4.
2.
1.
NOTES:
7.
5
SEATING PLANE
C
H
32
1
28
B
14
1 3
15
A
PLANE
GAUGE
0.05 MIN
0.15 MAX
0°-8°
0.60 ±0.15
0.90
1.00 REF
0.25
SEE DETAIL "X"
0.25
(0.65 TYP)
(5.65)
(0.35 TYP)
(1.45)
6.40
4.40 ± 0.10
0.65
1.20 MAX
PIN #1
I.D. MARK
9.70± 0.10
-0.06
0.15 +0.05
-0.10
+0.15
-0.06
+0.05
0.20 C B A
0.10 C
-
0.05
0.10 C B A
M
For the most recent package outline drawing, see M28.173.
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 8. Package Outline Drawings
FN4910 Rev.24.00 Page 37 of 39
May 30, 2019
Notes:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess of
“B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
C
H0.25(0.010) BM M
α
0.25
0.010
GAUGE
PLANE
A2
M28.209 (JEDEC MO-150-AH ISSUE B)
28 Lead Shrink Small Outline Plastic Package (SSOP)
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.078 - 2.00 -
A1 0.002 - 0.05 - -
A2 0.065 0.072 1.65 1.85 -
B 0.009 0.014 0.22 0.38 9
C 0.004 0.009 0.09 0.25 -
D 0.390 0.413 9.90 10.50 3
E 0.197 0.220 5.00 5.60 4
e 0.026 BSC 0.65 BSC -
H 0.292 0.322 7.40 8.20 -
L 0.022 0.037 0.55 0.95 6
N28 287
α0° 8° 0° 8° -
Rev. 2 6/05
For the most recent package outline drawing, see M28.209.
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E 8. Package Outline Drawings
FN4910 Rev.24.00 Page 38 of 39
May 30, 2019
a
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H0.25(0.010) BM M
(1.50mm)
(9.38mm)
(1.27mm TYP) (0.51mm TYP)
TYPICAL RECOMMENDED LAND PATTERN
M28.3 (JEDEC MS-013-AE ISSUE C)
28 Lead Wide Body Small Outline Plastic Package (SOIC)
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.6969 0.7125 17.70 18.10 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.01 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N28 287
α0o8o0o8o-
Rev. 1, 1/13
Notes:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
For the most recent package outline drawing, see M28.3.
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