ADNS-5030 Low Power Optical Mouse Sensor Data Sheet Description The Avago Technologies ADNS-5030 is a low power, small form factor optical mouse sensor. It has a new low-power architecture and automatic power management modes, making it ideal for battery, power-sensitive applications - such as cordless input devices. The ADNS-5030 is capable of high-speed motion detection - up to 14 ips and 2g. In addition, it has an on-chip oscillator and LED driver to minimize external components. Features x Low power architecture x Small form factor x Self-adjusting power-saving modes for prolonging battery life x High speed motion detection up to 14 ips and 2 g x Self-adjusting frame rate for optimum performance x Internal oscillator - no clock input needed x Selectable 500 and 1000 cpi resolution The ADNS-5030 along with the ADNS-5100/ADNS-5100001 lens, ADNS-5200 clip, and HLMP-ED80 LED form a complete and compact mouse tracking system. There are no moving parts, which means high reliability and less maintenance for the end user. In addition, precision optical alignment is not required, facilitating high volume assembly. x Operating voltage: 3.3 V nominal The sensor is programmed via registers through a fourwire serial port. It is housed in an 8-pin staggered dual in-line package (DIP). x Integrated input devices Theory of Operation The ADNS-5030 is based on Optical Navigation Technology, which measures changes in position by optically acquiring sequential surface images (frames) and mathematically determining the direction and magnitude of movement. The ADNS-5030 contains an Image Acquisition System (IAS), a Digital Signal Processor (DSP), and a four wire serial port. The IAS acquires microscopic surface images via the lens and illumination system. These images are processed by the DSP to determine the direction and distance of motion. The DSP calculates the 'x and 'y relative displacement values. An external microcontroller reads the 'x and 'y information from the sensor serial port. The microcontroller then translates the data into PS2, USB, or RF signals before sending them to the host PC. x Four wire serial port interface x Minimal number of passive components Applications x Optical mice and optical trackballs x Battery-powered input devices Pinout of ADNS-5030 Optical Mouse Sensor Name Description 1 MISO Serial Data Output (Master In/Slave Out) LED Control Reset Pin (active low input) Chip Select (active low input) Serial Clock Input Ground Supply Voltage Serial Data Input (Master Out/Slave In) 2 3 4 5 6 7 8 XY_LED NRESET NCS SCLK GND VDD3 MOSI 4 NCS 5 SCLK 6 GND 7 VDD3 A5030 XYYWWZ Pin 3 NRESET 2 XY_LED 1 MISO 8 MOSI Figure 1. Package outline drawing (top view). A5030 Figure 2. Package outline drawing. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. 2 Overview of Optical Mouse Sensor Assembly Avago Technologies provides an IGES file drawing describing the base plate molding features for lens and PCB alignment. imaging of the surface as well as illumination of the surface at the optimum angle. Features on the lens align it to the sensor, base plate, and clip with the LED. The ADNS-5030 sensor is designed for mounting on a through-hole PCB, looking down. There is an aperture stop and features on the package that align to the lens. The ADNS-5200 clip holds the LED in relation to the lens. The LED must be inserted into the clip and the LED's leads formed prior to loading on the PCB. The ADNS-5100/5100-001 lens provides optics for the The HLMP-ED80 LED is recommended for illumination. Figure 3. Recommended PCB mechanical cutouts and spacing. 3 33.45 (1.317) TOP VIEW 13.10 (0.516) BASE PLATE CROSS SECTION SIDE VIEW LED CLIP SENSOR 10.58 (0.417) 7.45 TOP PCB to SURFACE (0.293) PCB 2.40 BOTTOM of LENS FLANGE to SURFACE (0.094) DIMENSIONS IN mm (INCHES) Figure 4. 2D Assembly drawing of ADNS-5030 (top and side view). 4 LENS LED NAVIGATION SURFACE BASE PLATE ALIGNMENT POST (OPTIONAL) HLMP-ED80 (LED) ADNS-5200 (LED CLIP) SENSOR CUSTOMER SUPPLIED PCB ADNS-5100 (LENS) CUSTOMER SUPPLIED BASE PLATE WITH RECOMMENDED ALIGNMENT FEATURES PER IGES DRAWING Figure 5. Exploded view drawing. PCB Assembly Considerations 3. Insert the LED clip assembly into PCB. 4. Wave solder the entire assembly in a no-wash solder process utilizing solder fixture. The solder fixture is needed to protect the sensor during the solder process. It also sets the correct sensor-to-PCB distance as the lead shoulders do not normally rest on the PCB surface. The fixture should be designed to expose the sensor leads to solder while shielding the optical aperture from direct solder contact. 5. Place the lens onto the base plate. 6. Remove the protective kapton tape from optical aperture of the sensor. Care must be taken to keep contaminants from entering the aperture. Recommend not to place the PCB facing up during the entire mouse assembly process. Recommend to hold the PCB first vertically for the kapton removal process. 7. Insert PCB assembly over the lens onto the base plate aligning post to retain PCB assembly. The sensor aperture ring should self-align to the lens. 5 9. Install mouse top case. There MUST be a feature in the top case to press down onto the PCB assembly to ensure all components are interlocked to the correct vertical height. ADNS-5030 VDD3 GND IMAGE ARRAY DSP SERIAL PORT AND REGISTERS 2. Insert the LED into the assembly clip and bend the leads 90 degrees. 8. The optical position reference for the PCB is set by the base plate and lens. Note that the PCB motion due to button presses must be minimized to maintain optical alignment. POWER AND CONTROL 1. Insert the sensor and all other electrical components into PCB. NCS SCLK MOSI MISO NRESET OSCILLATOR XY_LED LED DRIVE Figure 6. Block diagram of ADNS-5030 optical mouse sensor. Design Considerations for Improved ESD Performance For improved electrostatic discharge performance, typical creepage and clearance distance are shown in the table below. Assumption: base plate construction as per the Avago Technologies supplied IGES file and ADNS5100/5100-001 lens. Typical Distance Millimeters Creepage 16.0 Clearance 2.1 Note that the lens material is polycarbonate or polystyrene HH30, therefore, cyanoacrylate based adhesives or other adhesives that may damage the lens should NOT be used. CLIP SENSOR LED PCB LENS/LIGHT PIPE BASE PLATE SURFACE Figure 7. Sectional view of PCB assembly highlighting optical mouse components. 6 7 D- Vreg D- GND XTALIN 6 MHz (OPTIONAL) XTALOUT MCU with USB Features VDD P0.7 P0.6 P0.5 RF RECEIVER CIRCUITRY SHLD GND VDD Z LED VDD GND QB QA 1 F 15 F 40 pF P3.2 P3.1 P3.0 P3.5 P3.4 VCC C3 - GND 20 11 NC C2C3+ LM3352 C2+ C1 - C1+ 40 pF M L P1.4 R P1.3 0.1 F 0.33 F 0.33 F 0.33 F 4 8 3 5 1 6 100 F 7 NCS MOSI NRESET SCLK MISO XY_LED 2 SURFACE ADNS-5100 LENS BIN K AND ABOVE (K, L, M, N, ...) RECOMMENDED LED BIN: ADNS-5030 INTERNAL IMAGE SENSOR R2 2.7 VDD GND BUTTONS 3.3 V P1.2 P1.1 P1.0 P1.7 P1.6 P1.5 4.7 F GND 1 2 3 4 5 6 7 8 XTAL1 RST 12 MHz XTAL2 3.0-VOLT MICROCONTROLLER GND GND GND GND CFIL NSD VIN P3.3 16 14 12 9 15 13 10 VOUT Recommended Typical Application (Transmitter Side) R RF TRANSMITTER CIRCUITRY VDD (3 V) Figure 8. Schematic diagram for interface between ADNS-5030 and microcontroller (cordless application). 1.3 K D+ D+ SHLD Vpp VDD (5 V) 0.1 F Recommended Typical Application (Receiver Side) HLMP ED80 Regulatory Requirements x Passes FCC B and worldwide analogous emission limits when assembled into a mouse with shielded cable and following Avago Technologies recommendations. x Passes IEC-1000-4-3 radiated susceptibility level when assembled into a mouse with shielded cable and following Avago Technologies recommendations. x Passes EN61000-4-4/IEC801-4 EFT tests when assembled into a mouse with shielded cable and following Avago Technologies recommendations. x UL flammability level UL94 V-0. x Provides sufficient ESD creepage/clearance distance to avoid discharge up to 15 kV when assembled into a mouse using ADNS-5100 round lens according to usage instructions above. Absolute Maximum Ratings Parameter Symbol Minimum Maximum Units Storage Temperature TS -40 85 C 260 C 3.7 V 2 kV All pins, human body model MIL 883 Method 3015 VDD + 0.5 V All I/O pins 7 mA MISO pin Lead Solder Temperature Supply Voltage VDD -0.5 ESD Input Voltage VIN Output Current Iout -0.5 Notes Recommended Operating Conditions Parameter Symbol Minimum Operating Temperature TA 0 Power Supply VDD 3.0 Power Supply Rise Time VRT 0.005 Supply Noise (Sinusoidal) Maximum Units 40 C 3.6 V 100 ms 0 to VDD min VNA 100 mVp-p 10 kHz - 50 MHz Serial Port Clock Frequency fSCLK 1 MHz 50% duty cycle Distance from Lens Reference Plane to Tracking Surface (Z) Z 2.3 2.5 mm Speed S 0 14 ips Acceleration a 2 g Load Capacitance Cout 100 pF 8 Typical 3.3 2.4 Notes MISO LENS SENSOR OBJECT SURFACE LENS REFERENCE PLANE Z = 2.40 (0.094) Figure 9. Distance from lens reference plane to tracking surface (Z). AC Electrical Specifications Electrical Characteristics over recommended operating conditions. Typical values at 25 C, VDD = 3.3 V. Parameter Symbol Minimum Reset Pulse Width tRESET 250 Motion Delay after Reset tMOT-RST Forced Rest Enable Typical Units Notes ns Active low 50 ms From NRESET pull high to valid motion, assuming VDD and motion is present tREST-EN 1 s From Rest Mode(RM) bits set to target rest mode Wake from Forced Rest tREST-DIS 1 s From Rest Mode(RM) bits cleared to valid motion Power Down tPD 50 ms From PD (when bit 1 of register 0x0d is set) to low current Wake from Power Down tWAKEUP 55 ms From PD inactive (when NRESET pin is asserted low to high or write 0x5a to register 0x3a) to valid motion MISO Rise Time tr-MISO 40 200 ns CL = 100 pF MISO Fall Time tf-MISO 40 MISO Delay after SCLK tDLY-MISO MISO Hold Time thold-MISO 0.5 MOSI Hold Time thold-MOSI 50 Maximum 200 ns CL = 100 pF 120 ns From SCLK falling edge to MISO data valid, no load conditions 1/fSCLK s Data held until next falling SCLK edge 200 ns Amount of time data is valid after SCLK rising edge MOSI Setup Time tsetup-MOSI 120 ns From data valid to SCLK rising edge SPI Time between Write Commands tSWW 30 s From rising SCLK for last bit of the first data byte, to rising SCLK for last bit of the second data byte SPI Time between Write and tSWR 20 s From rising SCLK for last bit of the first data byte, to rising SCLK for last bit of the second address byte tSRW 250 ns From rising SCLK for last bit of the first data byte, to falling SCLK for the first bit of the next address Read Commands SPI Time between Read and Subsequent Commands tSRR SPI Read Address-Data Delay tSRAD 4 s From rising SCLK for last bit of the address byte, to falling SCLK for first bit of data being read NCS Inactive after Motion tBEXIT 250 ns Minimum NCS inactive time after motion burst before next SPI usage NCS to SCLK Active tNCS-SCLK 120 ns From NCS falling edge to first SCLK rising edge SCLK to NCS Inactive (for Read Operation) tSCLK-NCS 120 ns From last SCLK rising edge to NCS rising edge, for valid MISO data transfer SCLK to NCS Inactive tSCLK-NCS 20 s From last SCLK rising edge to NCS rising edge, for valid MOSI data transfer Burst (for Write Operation) NCS to MISO high-Z tNCS-MISO 250 ns From NCS rising edge to MISO high-Z state Transient Supply Current IDDT 60 mA Max supply current during a VDD ramp from 0 to VDD 9 DC Electrical Specifications Electrical Characteristics over recommended operating conditions. Typical values at 25C, VDD = 3.3 V. Parameter Symbol Typical Maximum Units Notes DC Supply Current in Various Mode IDD_AVG_HIGH Minimum 15.2 17 mA Average current, including LED current, at max frame rate. No load on MISO. Bit 0 of register 0x40 set to "0" IDD_AVG_LOW 11.3 13.1 mA Average current, including LED current, at max frame rate. No load on MISO. Bit 0 of register 0x40 set to "1" IDD_REST1 0.34 0.54 mA IDD_REST2 0.09 0.16 mA IDD_REST3 0.03 0.06 mA Power Down 2 uA 0.5 Input Low Voltage VIL Input High Voltage VIH Input hysteresis VI_HYS 200 Input leakage current Ileak 1 VDD - 0.5 Output Low Voltage VOL Output High Voltage VOH Input Capacitance Cin V SCLK, MOSI, NCS, NRESET V SCLK, MOSI, NCS, NRESET mV SCLK, MOSI, NCS, NRESET 10 mA Vin=VDD-0.6V, SCLK, MOSI, NCS, NRESET 0.7 V Iout=1mA, MISO V Iout=-1mA, MISO pF MOSI, NCS, SCLK, NRESET VDD -0.7 50 Typical Performance Characteristics (Bit 0 of register 0x40 set to "0") 1200 White paper Manila White Melamine bookshelf Black Formica Mean Resolution (CPI) 1000 800 600 400 200 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 Distance from Lens Reference Plane to Tracking Surface (Z) Figure 10. Mean resolution vs. distance from lens reference plane to surface. 1.0 White paper Manila White Melamine bookshelf Black Formica Maximun Distance (mouse count) 45 40 35 30 25 20 15 0.8 0.7 0.6 0.5 0.4 0.3 10 0.2 5 0.1 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 Distance from Lens Reference Plane to Tracking Surface (Z) Figure 11. Typical path deviation. 10 0.9 Normalized Response 50 3.2 0 400 500 600 700 800 900 1000 Wavelength (nm) Figure 12. Relative wavelength responsivity. Power Management Modes The ADNS-5030 has three power-saving modes. Each mode has a different motion detection period, affecting response time to mouse motion (Response Time). The sensor automatically changes to the appropriate mode, depending on the time since the last reported motion (Downshift Time). The parameters of each mode are shown in the following table. Mode Response Time (Typical) Downshift Time (Typical) Rest 1 14 ms <1s The lines that comprise the SPI port: SCLK: Clock input. It is always generated by the master (the micro-controller). MOSI: Input data. (Master Out/Slave In) MISO: Output data. (Master In/Slave Out) NCS: Chip select input (active low). NCS needs to be low to activate the serial port; otherwise, MISO will be high Z, and MOSI & SCLK will be ignored. NCS can also be used to reset the serial port in case of an error. Rest 2 68 ms 7s Chip Select Operation Rest 3 340 ms 410 s The serial port is activated after NCS goes low. If NCS is raised during a transaction, the entire transaction is aborted and the serial port will be reset. This is true for all transactions. After a transaction is aborted, the normal address-to-data or transaction-to-transaction delay is still required before beginning the next transaction. To improve communication reliability, all serial transactions should be framed by NCS. In other words, the port should not remain enabled during periods of non-use because ESD and EFT/B events could be interpreted as serial communication and put the chip into an unknown state. In addition, NCS must be raised after each burstmode transaction is complete to terminate burst-mode. The port is not available for further use until burst-mode is terminated. LED Mode For power savings, the LED will not be continuously on. ADNS-5030 will pulse the LED only when needed. Synchronous Serial Port The synchronous serial port is used to set and read parameters in the ADNS-5030, and to read out the motion information. The port is a four wire serial port. The host micro-controller always initiates communication; the ADNS-5030 never initiates data transfers. SCLK, MOSI, and NCS may be driven directly by a micro-controller. The port pins may be shared with other SPI slave devices. When the NCS pin is high, the inputs are ignored and the output is tri-stated. Write Operation Write operation, defined as data going from the microcontroller to the ADNS-5030, is always initiated by the micro-controller and consists of two bytes. The first byte contains the address (seven bits) and has a "1" as its MSB to indicate data direction. The second byte contains the data. The ADNS-5030 reads MOSI on rising edges of SCLK. NCS 1 2 3 4 5 6 7 8 9 10 11 12 13 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 14 15 16 1 2 SCLK MOSI 1 MISO MOSI DRIVEN BY MICRO-CONTROLLER Write Operation 11 D2 D1 D0 1 A6 SCLK MOSI thold, MOSI tsetup, MOSI MOSI Setup and Hold Time Read Operation A read operation, defined as data going from the ADNS5030 to the micro-controller, is always initiated by the micro-controller and consists of two bytes. The first byte contains the address, is sent by the micro-controller over MOSI, and has a "0" as its MSB to indicate data direction. The second byte contains the data and is driven by the ADNS-5030 over MISO. The sensor outputs MISO bits on falling edges of SCLK and samples MOSI bits on every rising edge of SCLK. NCS SCLK CYCLE # 1 2 3 4 5 6 7 A6 A5 A4 A3 A2 A1 8 9 10 11 12 13 14 15 16 SCLK 0 MOSI A0 D7 MISO tSRAD DELAY Read Operation SCLK tDLY-MISO MISO tHOLD-MISO D0 MISO Delay and Hold Time NOTE: The 200 ns minimum high state of SCLK is also the minimum MISO data hold time of the ADNS-5030. Since the falling edge of SCLK is actually the start of the next read or write command, the ADNS-5030 will hold the state of data on MISO until the falling edge of SCLK. 12 D6 D5 D4 D3 D2 D1 D0 Required Timing between Read and Write Commands There are minimum timing requirements between read and write commands on the serial port. tSWW SCLK ADDRESS DATA ADDRESS WRITE OPERATION DATA WRITE OPERATION Timing between Two Write Commands If the rising edge of the SCLK for the last data bit of the second write command occurs before the required delay (tSWW ), then the first write command may not complete correctly. tSWR SCLK ADDRESS DATA ADDRESS WRITE OPERATION NEXT READ OPERATION Timing between Write and Read Commands If the rising edge of SCLK for the last address bit of the read command occurs before the required delay (tSWR), the write command may not complete correctly. tSRW & tSRR tSRAD SCLK DATA ADDRESS ADDRESS READ OPERATION Timing between Read and Either Write or Subsequent Read Commands During a read operation SCLK should be delayed at least tSRAD after the last address data bit to ensure that the ADNS-5030 has time to prepare the requested data. The falling edge of SCLK for the first address bit of either the read or write command must be at least tSRR or tSRW after the last SCLK rising edge of the last data bit of the previous read operation. 13 NEXT READ or WRITE OPERATION Motion Burst Timing tSRAD SCLK MOTION_BURST REGISTER ADDRESS READ FIRST BYTE FIRST READ OPERATION READ SECOND BYTE READ THIRD BYTE Burst Mode Operation Notes on Power-up and Reset Burst mode is a special serial port operation mode that may be used to reduce the serial transaction time for a motion read. The speed improvement is achieved by continuous data clocking to or from multiple registers without the need to specify the register address, and by not requiring the normal delay period between data bytes. The ADNS-5030 does not perform an internal power up self-reset; the NRESET pin must be asserted low every time power is applied. There are two ways to reset the chip, either assert low NRESET pin or by writing 0x5a to register 0x3a. A full reset will thus be executed. Any register settings must then be reloaded. Burst mode is activated by reading the Motion_Burst register. The ADNS-5030 will respond with the contents of the Delta_X, Delta_Y, SQUAL, Shutter_Upper, Shutter_ Lower, and Maximum_Pixel and Pixel_Sum registers in that order. The burst transaction can be terminated anywhere in the sequence after the Delta_X value by bringing the NCS pin high. After sending the register address, the micro-controller must wait tSRAD and then begin reading data. All data bits can be read with no delay between bytes by driving SCLK at the normal rate. The data are latched into the output buffer after the last address bit is received. After the burst transmission is complete, the micro-controller must raise the NCS line for at least tBEXIT to terminate burst mode. The serial port is not available for use until it is reset with NCS, even for a second burst transmission. Avago Technologies highly recommends the usage of burst mode operation in optical mouse sensor design applications. During power-up there will be a period of time after the power supply is high but before any clocks are available. The table below shows the state of the various pins during power-up and reset. State of Signal Pins after VDD is Valid Pin During Reset After Reset NCS Ignored Functional MISO Low Depends on NCS SCLK Ignored Depends on NCS MOSI Ignored Depends on NCS XY_LED High Functional Notes on Power Down The ADNS-5030 can be set in Power Down mode by setting bit 1 of Register 0x0d. In addition, the SPI port should not be accessed during power down. (Other ICs on the same SPI bus can be accessed, as long as the sensor's NCS pin is not asserted.) The table below shows the state of various pins during power down. There are 2 ways to exit power down, either assert low NRESET pin or by writing 0x5a to Register 0x3a. A full reset will thus be executed. Wait tWAKEUP before accessing the SPI port. Any register settings must then be reloaded. Pin Power Down Active NRESET Functional NCS Functional* MISO Undefined SCLK Functional* MOSI Functional* XY_LED Low current * NCS pin must be held to 1 (high) if SPI bus is shared with other devices. It can be in either state if the sensor is the only device in addition to the controller microprocessor. Note: There is long wakeup time from power down. This feature should not be used for power management during normal mouse motion. 14 Registers The ADNS-5030 registers are accessible via the serial port. The registers are used to read motion data and status as well as to set the device configuration. Address Register 0x00 Product_ID R 0x11 0x01 Revision_ID R 0x00 0x02 Motion R 0x00 0x03 Delta_X R Any 0x04 Delta_Y R Any 0x05 SQUAL R Any 0x06 Shutter_Upper R Any 0x07 Shutter_Lower R Any 0x08 Maximum_Pixel R Any 0x09 Pixel_Sum R Any 0x0a Minimum_Pixel R Any 0x0b Pixel_Grab R/W Any R/W 0x00 W N/A 0x0c Reserved 0x0d Mouse Control 0x0e - 0x39 Reserved 0x3a Chip_Reset Read/Write Default Value 0x3b - 0x3e Reserved 0x3f Inv_Rev_ID R 0xff 0x40 Sensor_Current_Setting W N/A 0x41 - 0x44 Reserved 0x45 Rest_mode_configuration R/W 0x00 0x46 - 0x62 Reserved 0x63 Motion_Burst R 0x00 15 Product_ID Access: Read Address: 0x00 Reset Value: 0x11 Bit Field 7 PID7 6 PID6 5 PID5 4 PID4 3 PID3 2 PID2 1 PID1 0 PID0 Data Type: 8-Bit unsigned integer USAGE: This register contains a unique identification assigned to the ADNS-5030. The value in this register does not change; it can be used to verify that the serial communications link is functional. Revision_ID Access: Read Address: 0x01 Reset Value: 0x00 Bit Field 7 RID7 6 RID6 5 RID5 4 RID4 3 RID3 2 RID2 1 RID1 0 RID0 Data Type: 8-Bit unsigned integer USAGE: This register contains the IC revision. It is subject to change when new IC versions are released. Motion Access: Read/Write Bit Field Address: 0x02 Reset Value: 0x00 7 MOT 6 5 4 Reserved Reserved Reserved 3 Reserved 2 Reserved 1 Reserved 0 Reserved Data Type: Bit field USAGE: Register 0x02 allows the user to determine if motion has occurred since the last time it was read. If the MOT bit is set, then the user should read registers 0x03 and 0x04 to get the accumulated motion. Read this register before reading the Delta_X and Delta_Y registers. Writing anything to this register clears the MOT bit, Delta_X and Delta_Y registers. The written data byte is not saved. Field Name MOT Reserved 16 Description Motion since last report 0 = No motion 1 = Motion occurred, data ready for reading in Delta_X and Delta_Y registers Reserved Delta X Access: Read Address: 0x03 Reset Value: 0x00 Bit Field 7 X7 6 X6 5 X5 4 X4 3 X3 2 X2 1 X1 0 X0 Data Type: Eight bit 2's complement number USAGE: X movement is counts since last report. Absolute value is determined by resolution. Reading clears the register. MOTION -128 -127 -2 -1 0 +1 +2 +126 +127 DELTA_X 80 81 FE FF 00 01 02 7E 7F NOTE: Avago Technologies RECOMMENDS that registers 0x03 and 0x04 be read sequentially. Delta_Y Access: Read Address: 0x04 Reset Value: 0x00 Bit Field 7 Y7 6 Y6 5 Y5 4 Y4 3 Y3 2 Y2 1 Y1 0 Y0 Data Type: Eight bit 2's complement number USAGE: Y movement is counts since last report. Absolute value is determined by resolution. Reading clears the register. MOTION -128 -127 -2 -1 0 +1 +2 +126 +127 DELTA_Y 80 81 FE FF 00 01 02 7E 7F NOTE: Avago Technologies RECOMMENDS that registers 0x03 and 0x04 be read sequentially. 17 Squal Access: Read Address: 0x05 Reset Value: 0x00 Bit Field 7 SQ7 6 SQ6 5 SQ5 4 SQ4 3 SQ3 2 SQ2 1 SQ1 0 SQ0 Data Type: Upper 8 bits of a 9-bit unsigned integer USAGE: SQUAL (Surface Quality) is a measure of the number of valid features visible by the sensor in the current frame. The maximum SQUAL register value is 144. Since small changes in the current frame can result in changes in SQUAL, variations in SQUAL when looking at a surface are expected. The graph below shows 250 sequentially acquired SQUAL values, while a sensor was moved slowly over white paper. SQUAL is nearly equal to zero, if there is no surface below the sensor. SQUAL is typically maximized when the navigation surface is at the optimum distance from the imaging lens (the nominal Zheight). Squal (White paper) 100 90 Squal value 80 70 60 50 40 30 20 10 0 1 101 201 301 401 501 601 701 801 Count Figure 13. Squal values (white paper). Mean Squal vs Z (White paper) Squal value (Count) 70 Avg-3sigma 60 Avg 50 Avg+3sigma 40 30 20 10 0 -10 1.6 1.8 2 2.2 2.4 2.6 Delta from Nominal Focus (mm) Figure 14. Mean squal vs. Z (white paper). 18 2.8 3 3.2 Shutter_Upper Access: Read Address: 0x06 Reset Value: 0x00 Bit Field 7 S15 Shutter_Lower Access: Read 6 S14 5 S13 4 S12 3 S11 2 S10 1 S9 0 S8 5 S5 4 S4 3 S3 2 S2 1 S1 0 S0 Address: 0x07 Reset Value: 0x00 Bit Field 7 S7 6 S6 Data Type: Sixteen bit unsigned integer USAGE: Units are clock cycles. Read Shutter_Upper first, then Shutter_Lower. They should be read consecutively. The shutter is adjusted to keep the average and maximum pixel values within normal operating ranges. The shutter value is automatically adjusted. Shutter (White Paper) 300 Shutter Value 250 200 150 100 50 0 1 101 201 301 401 501 601 701 801 Count Figure 15. Shutter (white paper). 500 Avg-3sigma Avg Avg+3sigma Mean Shutter value (Count) 450 400 350 300 250 200 150 100 50 0 1.6 1.8 2 2.2 2.4 2.6 2.8 Distance from Lens Reference Plane to Tracking Surface (Z) Figure 16. Mean shutter vs. Z (white paper). 19 3 3.2 Maximum_Pixel Access: Read Address: 0x08 Reset Value: 0x00 Bit Field 7 MP0 6 MP6 5 MP5 4 MP4 3 MP3 2 MP2 1 MP1 0 MP0 Data Type: Eight-bit number USAGE: Maximum Pixel value in current frame. Minimum value = 0, maximum value = 127. The maximum pixel value can vary with every frame. Pixel_Sum Access: Read Address: 0x09 Reset Value: 0x00 Bit Field 7 AP7 6 AP6 5 AP5 4 AP4 3 AP3 2 AP2 1 AP1 0 AP0 Data Type: High 8 bits of an unsigned 15-bit integer USAGE: This register is the accumulated pixel value from the last image taken. The maximum accumulator value is 28,575, but only bits [14:7] are reported. It may be described as the full sum divided by 1.76. The maximum register value is 223. The minimum is 0. The pixel sum value can change on every frame. Minimum_Pixel Access: Read Address: 0x0a Reset Value: 0x00 Bit Field 7 MP0 6 MP6 5 MP5 4 MP4 3 MP3 2 MP2 1 MP1 0 MP0 Data Type: Eight-bit number USAGE: Minimum Pixel value in current frame. Minimum value = 0, maximum value = 127. The minimum pixel value can vary with every frame. 20 Pixel_Grab Access: Read/Write Bit Field Address: 0x0b Reset Value: 0x00 7 Valid 6 PD6 5 PD5 4 PD4 3 PD3 2 PD2 1 PD1 0 PD0 Data Type: Eight-bit word USAGE: The pixel grabber captures 1 pixel per frame. If there is a valid pixel in the grabber when this register is read, the MSB will be set, an internal counter will incremented to capture the next pixel and the grabber will be armed to capture the next pixel. It will take 225 reads to upload the complete image. Any write to this register will reset and arm the grabber to grab pixel 0 on the next image. Physical Pixel Address Map - readout order of the array (looking through the sensor aperture at the bottom of the package) Top X-ray view of mouse RB Positive Y LB Positive X Last Pixel 224 209 194 179 164 149 134 119 104 89 74 59 44 29 14 223 208 193 178 163 148 133 118 103 88 73 58 43 28 13 Bottom view of mouse 222 207 192 177 162 147 132 117 102 87 72 57 42 27 12 221 206 191 176 161 146 131 116 101 86 71 56 41 26 11 219 204 189 174 159 144 129 114 99 84 69 54 39 24 9 218 203 188 173 158 143 128 113 98 83 68 53 38 23 8 217 202 187 172 157 142 127 112 97 82 67 52 37 22 7 216 201 186 171 156 141 126 111 96 81 66 51 36 21 6 215 200 185 170 155 140 125 110 95 80 65 50 35 20 5 214 199 184 169 154 139 124 109 94 79 64 49 34 19 4 213 198 183 168 153 138 123 108 93 78 63 48 33 18 3 212 197 182 167 152 137 122 107 92 77 62 47 32 17 2 211 196 181 166 151 136 121 106 91 76 61 46 31 16 1 First 0 Pixel 210 195 180 165 150 135 120 105 90 75 60 45 30 15 Positive Y 220 205 190 175 160 145 130 115 100 85 70 55 40 25 10 Positive X 21 Hole at mouse bottom cover for lens Reserved Address: 0x0c Mouse_control Access: Read/Write Address: 0x0d Reset Value: 0x00 Bit Field 7 6 5 4 Reserved Reserved Reserved Reserved 3 Reserved 2 Reserved 1 PD 0 RES Data Type: Eight bit number USAGE: Mouse sensor resolution and power down settings can be accessed or to be edited by this register. Field Name PD Description Power Down 0 = normal 1 = Power Down Set Resolution 0 = 500 cpi 1 = 1000 cpi Reserved RES Reserved Reserved Address: 0x0e-0x39 Chip_Reset Access: Write Address: 0x3a Reset Value: 0x00 Bit Field 7 CR7 6 CR6 5 CR5 Data Type: 8-Bit unsigned integer USAGE: Write 0x5a to initiate chip RESET. Reserved Address: 0x3b-0x3e Inv_Rev_ID Access: Read Address: 0x3f Reset Value: 0xff Bit Field 7 RRID7 6 RRID6 5 RRID5 4 CR4 3 CR3 2 CR2 1 CR1 0 CR0 4 RRID4 3 RRID3 2 RRID2 1 RRID1 0 RRID0 Data Type: Inverse 8-Bit unsigned integer USAGE: This register contains the inverse of the revision ID which is located at register 0x01. 22 Sensor_Current_Setting Access: Write Bit Field Address: 0x40 Reset Value: N/A 7 6 5 4 Reserved Reserved Reserved Reserved 3 Reserved 2 Reserved Data Type: 8-bit number USAGE: This register is used to set the internal LED driver's drive strength. Field Name LDC Reserved Address: 0x41-0x44 Rest_mode_configuration Access: Read/Write Address: 0x45 Reset Value: 0x00 7 RM1 0 LDC 1 Reserved 0 Reserved Description Internal LED Driver Current 0 = High current 1 = Low current Reserved Reserved Bit Field 1 Reserved 6 RM0 5 4 Reserved Reserved 3 Reserved 2 Reserved Data Type: Bit field USAGE: Register 0x45 allows the user to change or monitor the rest mode configuration of the sensor. Write operations to RM1 and RM0 forces the sensor into rest mode. Read RM1 and RM0 for the sensor to report which mode it is in. Note: Forced Rest has a long wakeup time and should not be used for power management during normal mouse motion. Field Name RM[1-0] RM[1-0] Reserved 23 Description Write operation: Force rest mode selection 00 = Normal operation 01 = Rest1 10 = Rest2 11 = Rest3 Read operation: Reports which mode the sensor is in. 00 = Run 01 = Rest1 10 = Rest2 11 = Rest3 Reserved Reserved Address: 0x46-0x62 Motion_Burst Access: Read Address: 0x63 Reset Value: 0x00 Bit Field 7 MB7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 Data Type: Various USAGE: Read from this register to activate burst mode. The sensor will return the data in the Delta_X, Delta_Y, Squal, Shutter_Upper, Shutter_Lower, Maximum_Pixel and Pixel_Sum. If the burst is not terminated at this point, the internal address counter stops incrementing and Pixel Sum register's value will be continuously returned. Bursts are terminated when NCS is raised. For product information and a complete list of distributors, go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright (c) 2005-2009 Avago Technologies. All rights reserved. Obsoletes AV01-0096EN AV02-0113EN - December 3, 2009