LM3421,LM3423
LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0 N-Channel Controllers
for Constant Current LED Drivers
Literature Number: SNVS574D
LM3421
LM3421Q1 LM3421Q0
LM3423
LM3423Q1 LM3423Q0
January 21, 2010
N-Channel Controllers for Constant Current LED Drivers
General Description
The LM3421/23 are versatile high voltage N-channel MosFET
controllers for LED drivers . They can be easily configured in
buck, boost, buck-boost and SEPIC topologies. This flexibili-
ty, along with an input voltage rating of 75V, makes the
LM3421/23 ideal for illuminating LEDs in a large family of ap-
plications.
Adjustable high-side current sense voltage allows for tight
regulation of the LED current with the highest efficiency pos-
sible. The LM3421/23 uses Predictive Off-time (PRO) control,
which is a combination of peak current-mode control and a
predictive off-timer. This method of control eases the design
of loop compensation while providing inherent input voltage
feed-forward compensation.
The LM3421/23 devices include a high-voltage startup regu-
lator that operates over a wide input range of 4.5V to 75V. The
internal PWM controller is designed for adjustable switching
frequencies of up to 2.0 MHz, thus enabling compact solu-
tions. Additional features include "zero current" shutdown,
analog dimming, PWM dimming, over-voltage protection, un-
der-voltage lock-out, cycle-by-cycle current limit, and thermal
shutdown.
The LM3423 also includes an LED output status flag, a fault
flag, a programmable fault timer, and a logic input to select
the polarity of the dimming output driver.
The LM3421Q1/23Q1 are AEC-Q100 grade 1 qualified and
LM3421Q0/23Q0 are AEC-Q100 grade 0 qualified.
Features
■LM3421Q1/LM3423Q1 are Automotive Grade products
that are AEC-Q100 grade 1 qualified (-40°C to +125°C
operating junction temperature) and similarly LM3421Q0/
LM3423Q0 are AEC-Q100 grade 0 qualified (-40°C to
+150°C operating junction temperature)
■VIN range from 4.5V to 75V
■High-side adjustable current sense
■2Ω, 1A Peak MosFET gate driver
■Input under-voltage and output over-voltage protection
■PWM and analog dimming
■Cycle-by-cycle current limit
■Programmable switching frequency
■"Zero current" shutdown and thermal shutdown
■LED output status flag (LM3423/23Q1/23Q0 only)
■Fault status flag and timer (LM3423/23Q1/23Q0 only)
Applications
■LED Drivers - Buck, Boost, Buck-Boost, and SEPIC
■Indoor and Outdoor Area SSL
■Automotive
■General Illumination
■Constant-Current Regulators
Typical Boost Application Circuit
300673k9
300673b6
Boost Evaluation Board
9 Series LEDs at 1A
© 2011 National Semiconductor Corporation 300673 www.national.com
LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0 N-Channel Controllers for
Constant Current LED Drivers
Connection Diagrams
Top View
30067304
16-Lead TSSOP EP
NS Package Number MXA16A
Top View
300673a1
20-Lead TSSOP EP
NS Package Number MXA20A
Ordering Information
Order Number Spec. Package Type NSC
Package
Drawing
Supplied As Features
LM3421MH NOPB TSSOP-16 EP MXA16A 92 Units, Rail
LM3421MHX NOPB TSSOP-16 EP MXA16A 2500 Units, Tape and Reel
LM3423MH NOPB TSSOP-20 EP MXA20A 73 Units, Rail
LM3423MHX NOPB TSSOP-20 EP MXA20A 2500 Units, Tape and Reel
LM3421Q1MH NOPB TSSOP-16 EP MXA16A 92 Units, Rail AEC-Q100 Grade 1 qualified.
Automotive Grade Production
Flow*
LM3421Q1MHX NOPB TSSOP-16 EP MXA16A 2500 Units, Tape and Reel
LM3423Q1MH NOPB TSSOP-20 EP MXA20A 73 Units, Rail
LM3423Q1MHX NOPB TSSOP-20 EP MXA20A 2500 Units, Tape and Reel
LM3421Q0MH NOPB TSSOP-16 EP MXA16A 92 Units, Rail AEC-Q100 Grade 0 qualified.
Automotive Grade Production
Flow*
LM3421Q0MHX NOPB TSSOP-16 EP MXA16A 2500 Units, Tape and Reel
LM3423Q0MH NOPB TSSOP-20 EP MXA20A 73 Units, Rail
LM3423Q0MHX NOPB TSSOP-20 EP MXA20A 2500 Units, Tape and Reel
*Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection methodologies.
Reliability qualification is compliant with the requirements and temperature grades defined in the AEC-Q100 standard. Automotive grade products are identified
with the letter Q. For more information go to http://www.national.com/automotive.
www.national.com 2
LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
Pin Descriptions
LM3423 LM3421 Name Description Function
1 1 VIN Input Voltage Bypass with 100 nF capacitor to AGND as close to the
device as possible in the circuit board layout.
2 2 EN Enable Connect to AGND for zero current shutdown or apply >
2.4V to enable device.
3 3 COMP Compensation Connect a capacitor to AGND to set the compensation.
4 4 CSH Current Sense High
Connect a resistor to AGND to set the signal current.
For analog dimming, connect a controlled current
source or a potentiometer to AGND as detailed in the
Analog Dimming section.
5 5 RCT Resistor Capacitor Timing External RC network sets the predictive “off-time” and
thus the switching frequency.
6 6 AGND Analog Ground Connect to PGND through the DAP copper pad to
provide ground return for CSH, COMP, RCT, and TIMR.
7 7 OVP Over-Voltage Protection
Connect to a resistor divider from VO to program output
over-voltage lockout (OVLO). Turn-off threshold is
1.24V and hysteresis for turn-on is provided by 23 µA
current source.
8 8 nDIM Dimming Input /
Under-Voltage Protection
Connect a PWM signal for dimming as detailed in the
PWM Dimming section and/or a resistor divider from
VIN to program input under-voltage lockout (UVLO).
Turn-on threshold is 1.24V and hysteresis for turn-off is
provided by 23 µA current source.
9 - FLT Fault Flag
Connect to pull-up resistor from VIN and N-channel
MosFET open drain output is high when a fault condition
is latched by the timer.
10 - TIMR Fault Timer Connect a capacitor to AGND to set the time delay
before a sensed fault condition is latched.
11 - LRDY LED Ready Flag
Connect to pull-up resistor from VIN and N-channel
MosFET open drain output pulls down when the LED
current is not in regulation.
12 - DPOL Dim Polarity
Connect to AGND if dimming with a series P-channel
MosFET or leave open when dimming with series N-
channel MosFET.
13 9 DDRV Dim Gate Drive Output Connect to the gate of the dimming MosFET.
14 10 PGND Power Ground Connect to AGND through the DAP copper pad to
provide ground return for GATE and DDRV.
15 11 GATE Main Gate Drive Output Connect to the gate of the main switching MosFET.
16 12 VCC Internal Regulator Output Bypass with 2.2 µF–3.3 µF ceramic capacitor to PGND.
17 13 IS Main Switch Current Sense
Connect to the drain of the main N-channel MosFET
switch for RDS-ON sensing or to a sense resistor installed
in the source of the same device.
18 14 RPD Resistor Pull Down
Connect the low side of all external resistor dividers
(VIN UVLO, OVP) to implement “zero-current”
shutdown.
19 15 HSP LED Current Sense Positive Connect through a series resistor to the positive side of
the LED current sense resistor.
20 16 HSN LED Current Sense Negative Connect through a series resistor to the negative side
of the LED current sense resistor.
DAP (21) DAP (17) DAP Thermal PAD on bottom of IC Star ground, connecting AGND and PGND. For thermal
considerations please refer to (Note 2).
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VIN, EN, RPD, nDIM -0.3V to 76.0V
-1 mA continuous
OVP, HSP, HSN, LRDY,
FLT, DPOL
-0.3V to 76.0V
-100 µA continuous
RCT -0.3V to 76.0V
-1 mA to +5 mA continuous
IS -0.3V to 76.0V
-2V for 100 ns
-1mA continuous
VCC -0.3V to 8.0V
TIMR -0.3V to 7.0V
-100µA to +100µA Continuous
COMP, CSH -0.3V to 6.0V
-200 µA to +200 µA
Continuous
GATE, DDRV -0.3V to VCC
-2.5V for 100 ns
VCC+2.5V for 100 ns
-1 mA to +1 mA continuous
PGND -0.3V to 0.3V
-2.5V to 2.5V for 100 ns
Maximum Junction
Temperature
Internally Limited
Storage Temperature
Range
−65°C to +150°C
Maximum Lead
Temperature (Solder and
Reflow) (Note 3)
260°C
Continuous Power
Dissipation
Internally Limited
ESD Susceptibility
(Note 4)
Human Body Model 2 kV
Charge Device Model 500V CSH pin
750V all other pins
Operating Conditions (Note 1)
Operating Junction
Temperature Range
LM3421, LM3421Q1,
LM3423, LM3423Q1 −40°C to +125°C
LM3421Q0, LM3423Q0 −40°C to +150°C
Input Voltage VIN 4.5V to 75V
Electrical Characteristics (Note 1)
Specifications in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating Temperature
Range ( TJ = −40°C to +150°C for LM3421Q0/LM3423Q0, TJ = −40°C to +125°C for all others). Specifications that differ between
the two operating ranges will be identified in the Temp Range column as Q0 for TJ = −40°C to +150°C and as Q1 for TJ = −40°C
to +125°C. If no temperature range is indicated then the specification holds for both Q1 and Q0. Minimum and Maximum limits are
guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = +25°C,
and are provided for reference purposes only. Unless otherwise stated the following condition applies: VIN = +14V.
Symbol Parameter Conditions Temp
Range
Min
(Note 5)
Typ
(Note 6)
Max
(Note 5)Units
STARTUP REGULATOR
VCCREG VCC Regulation ICC = 0 mA 6.30 6.90 7.35 V
ICCLIM VCC Current Limit VCC = 0V 20 25
mA
IQQuiescent Current EN = 3.0V, Static Q1 23
Q0 3.5
ISD Shutdown Current EN = 0V 0.1 1.0 µA
VCC SUPPLY
VCCUV VCC UVLO Threshold VCC Increasing 4.17 4.50
V
VCC Decreasing 3.70 4.08
VCCHYS VCC UVLO Hysteresis 0.1
EN THRESHOLDS
ENST EN Startup Threshold EN Increasing Q1 1.75 2.40
V
Q0 2.75
EN Decreasing 0.80 1.63
ENSTHYS EN Startup Hysteresis 0.1
REN EN Pulldown Resistance EN = 1V Q1 0.45 0.82 1.30 MΩ
Q0 1.80
CSH THRESHOLDS
CSH High Fault CSH Increasing 1.6
V
CSH Low Condition on LRDY
Pin (LM3423)
CSH increasing 1.0
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
Symbol Parameter Conditions Temp
Range
Min
(Note 5)
Typ
(Note 6)
Max
(Note 5)Units
OV THRESHOLDS
OVPCB OVP OVLO Threshold OVP Increasing 1.185 1.240 1.285 V
OVPHYS OVP Hysteresis Source
Current
OVP Active (high) Q1 20 23 25 µA
Q0 26
DPOL THRESHOLDS
DPOLTHRES
H
DPOL Logic Threshold DPOL Increasing 2.0 2.3 2.6 V
RDPOL DPOL Pullup Resistance 500 1200 kΩ
FAULT TIMER
VFLTTH Fault Threshold Q1 1.185 1.240 1.285 V
Q0 1.290
IFLT Fault Pin Source Current Q1 10.0 11.5 13.0 µA
Q0 13.5
ERROR AMPLIFIER
VREF CSH Reference Voltage With Respect to AGND 1.210 1.235 1.260 V
Error Amplifier Input Bias
Current
-0.6 0 0.6
µA
COMP Sink / Source Current Q1 22 30 35
Q0 36
Transconductance 100 µA/V
Linear Input Range (Note 7) ±125 mV
Transconductance Bandwidth -6dB Unloaded Response
(Note 7)0.5 1.0 MHz
OFF TIMER
Minimum Off-time RCT = 1V through
1 kΩ
Q1 35 75 ns
Q0 90
RRCT RCT Reset Pull-down
Resistance
Q1 36 120 Ω
Q0 125
VRCT VIN/25 Reference Voltage VIN = 14V Q1 540 565 585 mV
Q0 590
f Continuous Conduction
Switching Frequency
2.2 nF > CT > 470 pF 25/(CTRT) Hz
PWM COMPARATOR
COMP to PWM Offset 700 800 900 mV
CURRENT LIMIT (IS)
ILIM Current Limit Threshold 215 245 275 mV
ILIM Delay to Output Q1 35 75
nsQ0 90
Leading Edge Blanking Time 115 210 325
HIGH SIDE TRANSCONDUCTANCE AMPLIFIER
Input Bias Current 11.5 µA
Transconductance 20 119 mA/V
Input Offset Current -1.5 01.5 µA
Input Offset Voltage -7 07mV
Transconductance Bandwidth ICSH = 100 µA
(Note 7)250 500 kHz
GATE DRIVER (GATE)
RSRC(GATE) GATE Sourcing Resistance GATE = High 2.0 6.0 Ω
RSNK(GATE) GATE Sinking Resistance GATE = Low 1.3 4.5
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
Symbol Parameter Conditions Temp
Range
Min
(Note 5)
Typ
(Note 6)
Max
(Note 5)Units
DIM DRIVER (DIM, DDRV)
nDIMVTH nDIM / UVLO Threshold 1.185 1.240 1.285 V
nDIMHYS nDIM Hysteresis Current Q1 20 23 25 µA
Q0 26
RSRC(DDRV) DDRV Sourcing Resistance DDRV = High 13.5 30.0 Ω
RSNK(DDRV) DDRV Sinking Resistance DDRV = Low 3.5 10.0
PULL-DOWN N-CHANNEL MosFETS
RRPD RPD Pull-down Resistance Q1 145 300
Ω
Q0 350
RFLT FLT Pull-down Resistance Q1 145 300
Q0 350
RLRDY LRDY Pull-down Resistance Q1 135 300
Q0 350
THERMAL SHUTDOWN
TSD Thermal Shutdown Threshold (Note 7) Q1 165 °C
Q0 210
THYS Thermal Shutdown Hysteresis (Note 7) 25
THERMAL RESISTANCE
θJA Junction to Ambient (Note 2) 16L TSSOP EP 37.4 °C/W
20L TSSOP EP 34.0
θJC Junction to Exposed Pad (EP) 16L TSSOP EP 2.3 °C/W
20L TSSOP EP 2.3
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Operating Ratings is not implied. The recommended Operating Ratings indicate conditions at which the device is functional and the device should not be
operated beyond such conditions. All voltages are with respect to the potential at the AGND pin, unless otherwise specified.
Note 2: Junction-to-ambient thermal resistance is highly board-layout dependent. The numbers listed in the table are given for an reference layout wherein the
16L TSSOP package has its EP pad populated with 9 vias and the 20L TSSOP has its EP pad populated with 12 vias. In applications where high maximum power
dissipation exists, namely driving a large MosFET at high switching frequency from a high input voltage, special care must be paid to thermal dissipation issues
during board design. In high-power dissipation applications, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-
MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C for Q1, or 150°C for Q0), the maximum power dissipation of the device in
the application (PD-MAX), and the junction-to ambient thermal resistance of the package in the application (θJA), as given by the following equation: TA-MAX = TJ-
MAX-OP – (θJA × PD-MAX). In most applications there is little need for the full power dissipation capability of this advanced package. Under these circumstances, no
vias would be required and the thermal resistances would be 104 °C/W for the 16L TSSOP and 86.7 °C/W for the 20L TSSOP. It is possible to conservatively
interpolate between the full via count thermal resistance and the no via count thermal resistance with a straight line to get a thermal resistance for any number
of vias in between these two limits.
Note 3: Refer to National’s packaging website for more detailed information and mounting techniques. http://www.national.com/analog/packaging/
Note 4: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The applicable standard is JESD22-A114C.
Note 5: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100%
production tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used
to calculate Average Outgoing Quality Level (AOQL).
Note 6: Typical numbers are at 25°C and represent the most likely norm.
Note 7: These electrical parameters are guaranteed by design, and are not verified by test.
Note 8: The measurements were made using the standard buck-boost evaluation board from AN-2010.
Note 9: The measurements were made using the standard boost evaluation board from AN-2011.
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
Typical Performance Characteristics TA=+25°C and VIN = 14V unless otherwise specified
Boost Efficiency vs. Input Voltage
VO = 32V (9 LEDs) (Note 9)
300673b6
Buck-Boost Efficiency vs. Input Voltage
VO = 21V (6 LEDs) (Note 8)
300673b5
Boost LED Current vs. Input Voltage
VO = 32V (9 LEDs) (Note 9)
300673b8
Buck-Boost LED Current vs. Input Voltage
VO = 21V (6 LEDs) (Note 8)
300673b7
Analog Dimming
VO = 21V (6 LEDs); VIN = 24V (Note 8)
300673b9
PWM Dimming
VO = 32V (9 LEDs); VIN = 24V (Note 9)
300673c0
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
VCSH vs. Junction Temperature
300673b0
VCC vs. Junction Temperature
300673b1
VRCT vs. Junction Temperature
300673b2
VLIM vs. Junction Temperature
300673b3
tON-MIN vs. Junction Temperature
300673b4
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
Block Diagram
30067303
Theory of Operation
The LM3421/23 are N-channel MosFET (NFET) controllers
for buck, boost and buck-boost current regulators which are
ideal for driving LED loads. The controller has wide input volt-
age range allowing for regulation of a variety of LED loads.
The high-side differential current sense, with low adjustable
threshold voltage, provides an excellent method for regulating
output current while maintaining high system efficiency. The
LM3421/23 uses a Predictive Off-time (PRO) control archi-
tecture that allows the regulator to be operated using minimal
external control loop compensation, while providing an inher-
ent cycle-by-cycle current limit. The adjustable current sense
threshold provides the capability to amplitude (analog) dim
the LED current and the output enable/disable function with
external dimming FET driver allows for fast PWM dimming of
the LED load. When designing, the maximum attainable LED
current is not internally limited because the LM3421/23 is a
controller. Instead it is a function of the system operating
point, component choices, and switching frequency allowing
the LM3421/23 to easily provide constant currents up to 5A.
This controller contains all the features necessary to imple-
ment a high efficiency versatile LED driver.
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
30067398
FIGURE 1. Ideal CCM Regulator Inductor Current iL(t)
CURRENT REGULATORS
Current regulators can be designed to accomplish three basic
functions: buck, boost, and buck-boost. All three topologies
in their most basic form contain a main switching MosFET, a
recirculating diode, an inductor and capacitors. The
LM3421/23 is designed to drive a ground referenced NFET
which is perfect for a standard boost regulator. Buck and
buck-boost regulators, on the other hand, usually have a high-
side switch. When driving an LED load, a ground referenced
load is often not necessary, therefore a ground referenced
switch can be used to drive a floating load instead. The
LM3421/23 can then be used to drive all three basic topolo-
gies as shown in the Basic Topology Schematics section.
Other topologies such as the SEPIC and flyback converter
(both derivatives of the buck-boost) can be implemented as
well.
Looking at the buck-boost design, the basic operation of a
current regulator can be analyzed. During the time that the
NFET (Q1) is turned on (tON), the input voltage source stores
energy in the inductor (L1) while the output capacitor (CO)
provides energy to the LED load. When Q1 is turned off
(tOFF), the re-circulating diode (D1) becomes forward biased
and L1 provides energy to both CO and the LED load. Figure
1 shows the inductor current (iL(t)) waveform for a regulator
operating in CCM.
The average output LED current (ILED) is proportional to the
average inductor current (IL) , therefore if IL is tightly con-
trolled, ILED will be well regulated. As the system changes
input voltage or output voltage, the ideal duty cycle (D) is var-
ied to regulate IL and ultimately ILED. For any current regulator,
D is a function of the conversion ratio:
Buck
Boost
Buck-boost
PREDICTIVE OFF-TIME (PRO) CONTROL
PRO control is used by the LM3421/23 to control ILED. It is a
combination of average peak current control and a one-shot
off-timer that varies with input voltage. The LM3421/23 uses
peak current control to regulate the average LED current
through an array of HBLEDs. This method of control uses a
series resistor in the LED path to sense LED current and can
use either a series resistor in the MosFET path or the MosFET
RDS-ON for both cycle-by-cycle current limit and input voltage
feed forward. D is indirectly controlled by changes in both
tOFF and tON, which vary depending on the operating point.
Even though the off-time control is quasi-hysteretic, the input
voltage proportionality in the off-timer creates an essentially
constant switching frequency over the entire operating range
for boost and buck-boost topologies. The buck topology can
be designed to give constant ripple over either input voltage
or output voltage, however switching frequency is only con-
stant at a specific operating point .
This type of control minimizes the control loop compensation
necessary in many switching regulators, simplifying the de-
sign process. The averaging mechanism in the peak detec-
tion control loop provides extremely accurate LED current
regulation over the entire operating range.
PRO control was designed to mitigate “current mode
instability” (also called “sub-harmonic oscillation”) found in
standard peak current mode control when operating near or
above 50% duty cycles. When using standard peak current
mode control with a fixed switching frequency, this condition
is present, regardless of the topology. However, using a con-
stant off-time approach, current mode instability cannot oc-
cur, enabling easier design and control.
Predictive off-time advantages:
•There is no current mode instability at any duty cycle.
•Higher duty cycles / voltage transformation ratios are
possible, especially in the boost regulator.
The only disadvantage is that synchronization to an external
reference frequency is generally not available.
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
SWITCHING FREQUENCY
An external resistor (RT) connected between the RCT pin and
the switch node (where D1, Q1, and L1 connect), in combi-
nation with a capacitor (CT) between the RCT and AGND pins,
sets the off-time (tOFF) as shown in Figure 2. For boost and
buck-boost topologies, the VIN proportionality ensures a vir-
tually constant switching frequency (fSW).
For a buck topology, RT and CT are also used to set tOFF,
however the VIN proportionality will not ensure a constant
switching frequency. Instead, constant ripple operation can
be achieved. Changing the connection of RT in Figure 2 from
VSW to VIN will provide a constant ripple over varying VIN.
Adding a PNP transistor as shown in Figure 3 will provide
constant ripple over varying VO.
The switching frequency is defined:
Buck (Constant Ripple vs. VIN)
Buck (Constant Ripple vs. VO)
Boost and Buck-boost
For all topologies, the CT capacitor is recommended to be
1 nF and should be located very close to the LM3421/23.
30067399
FIGURE 2. Off-timer Circuitry for Boost and Buck-boost
Regulators
30067301
FIGURE 3. Off-timer Circuitry for Buck Regulators
30067357
FIGURE 4. LED Current Sense Circuitry
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
AVERAGE LED CURRENT
The LM3421/23 uses an external current sense resistor
(RSNS) placed in series with the LED load to convert the LED
current (ILED) into a voltage (VSNS) as shown in Figure 4. The
HSP and HSN pins are the inputs to the high-side sense am-
plifier which are forced to be equal potential (VHSP=VHSN)
through negative feedback. Because of this, the VSNS voltage
is forced across RHSP to generate the signal current (ICSH)
which flows out of the CSH pin and through the RCSH resistor.
The error amplifier will regulate the CSH pin to 1.24V, there-
fore ICSH can be calculated:
This means VSNS will be regulated as follows:
ILED can then be calculated:
The selection of the three resistors (RSNS, RCSH, and RHSP) is
not arbitrary. For matching and noise performance, the sug-
gested signal current ICSH is approximately 100 µA. This
current does not flow in the LEDs and will not affect either the
off-state LED current or the regulated LED current. ICSH can
be above or below this value, but the high-side amplifier offset
characteristics may be affected slightly. In addition, to mini-
mize the effect of the high-side amplifier voltage offset on LED
current accuracy, the minimum VSNS is suggested to be
50 mV. Finally, a resistor (RHSN = RHSP) should be placed in
series with the HSN pin to cancel out the effects of the input
bias current (~10 µA) of both inputs of the high-side sense
amplifier.
The sense resistor (RSNS) can be placed anywhere in the se-
ries string of LEDs as long as the voltage at the HSN and HSP
pins (VHSP and VHSN) satisfies the following conditions.
Typically, for a buck-boost configuration, RSNS is placed at the
bottom of the string (LED-) which allows for greater flexibility
of input and output voltage. However, if there is substantial
input voltage ripple allowed, it can help to place RSNS at the
top of the string (LED+) which limits the output voltage of the
string to:
Note that he CSH pin can also be used as a low-side current
sense input regulated to 1.24V. The high-side sense amplifier
is disabled if HSP and HSN are tied to AGND (or VHSN >
VHSP) .
ANALOG DIMMING
The CSH pin can be used to analog dim the LED current by
adjusting the current sense voltage (VSNS). There are several
different methods to adjust VSNS using the CSH pin:
1. External variable resistance : Adjust a potentiometer
placed in series with RCSH to vary VSNS.
2. External variable current source: Source current (0 µA to
ICSH) into the CSH pin to adjust VSNS.
300673k3
FIGURE 5. Analog Dimming Circuitry
In general, analog dimming applications require a lower
switching frequency to minimize the effect of the leading edge
blanking circuit. As the LED current is reduced, the output
voltage and the duty cycle decreases. Eventually, the mini-
mum on-time is reached. The lower the switching frequency,
the wider the linear dimming range. Figure 5 shows how both
CSH methods are physically implemented.
Method 1 uses an external potentiometer in the CSH path
which is a simple addition to the existing circuitry. However,
the LEDs cannot dim completely because there is always
some resistance causing signal current to flow. This method
is also susceptible to noise coupling at the CSH pin since the
potentiometer increases the size of the signal current loop.
Method 2 provides a complete dimming range and better
noise performance, though it is more complex. It consists of
a PNP current mirror and a bias network consisting of an NPN,
2 resistors and a potentiometer (RADJ), where RADJ controls
the amount of current sourced into the CSH pin. A higher re-
sistance value will source more current into the CSH pin
causing less regulated signal current through RHSP, effective-
ly dimming the LEDs. VREF should be a precise external
voltage reference, while Q7 and Q8 should be a dual pair PNP
for best matching and performance. The additional current
(IADD) sourced into the CSH pin can be calculated:
The corresponding ILED for a specific IADD is:
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
CURRENT SENSE/CURRENT LIMIT
The LM3421/23 achieves peak current mode control using a
comparator that monitors the main MosFET (Q1) transistor
current, comparing it with the COMP pin voltage as shown in
Figure 6. Further, it incorporates a cycle-by-cycle over-current
protection function. Current limit is accomplished by a redun-
dant internal current sense comparator. If the voltage at the
current sense comparator input (IS) exceeds 245 mV (typi-
cal), the on cycle is immediately terminated. The IS input pin
has an internal N-channel MosFET which pulls it down at the
conclusion of every cycle. The discharge device remains on
an additional 210 ns (typical) after the beginning of a new cy-
cle to blank the leading edge spike on the current sense
signal. The leading edge blanking (LEB) determines the min-
imum achievable on-time (tON-MIN).
300673a2
FIGURE 6. Current Sense / Current Limit Circuitry
There are two possible methods to sense the transistor cur-
rent. The RDS-ON of the main power MosFET can be used as
the current sense resistance because the IS pin was designed
to withstand the high voltages present on the drain when the
MosFET is in the off state. Alternatively, a sense resistor lo-
cated in the source of the MosFET may be used for current
sensing, however a low inductance (ESL) type is suggested.
The cycle-by-cycle current limit (ILIM) can be calculated using
either method as the limiting resistance (RLIM):
OVER-CURRENT PROTECTION
The LM3421/23 devices have a secondary method of over-
current protection. Switching action is disabled whenever the
current in the LEDs is more than 30% above the regulation
set point. The dimming MosFET switch driver (DDRV) is not
disabled however as this would immediately remove the fault
condition and cause oscillatory behavior.
ZERO CURRENT SHUTDOWN
The LM3421/23 devices implement "zero current" shutdown
via the EN and RPD pins. When pulled low, the EN pin places
the devices into near-zero current state, where only the leak-
age currents will be observed at the pins (typical 0.1 µA). The
applications circuits, frequently have resistor dividers to set
UVLO, OVLO, or other similar functions. The RPD pin is an
open drain N-channel MosFET that is enabled only when the
device is enabled. Tying the bottom of all resistor dividers to
the RPD pin as shown in Figure 7 allows them to float during
shutdown, thus removing their current paths and providing
true application-wide zero current shutdown.
300673j1
FIGURE 7. Zero Current Shutdown Circuit
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
CONTROL LOOP COMPENSATION
The LM3421/23 control loop is modeled like any current mode
controller. Using a first order approximation, the uncompen-
sated loop can be modeled as a single pole created by the
output capacitor and, in the boost and buck-boost topologies,
a right half plane zero created by the inductor, where both
have a dependence on the LED string dynamic resistance.
There is also a high frequency pole in the model, however it
is near the switching frequency and plays no part in the com-
pensation design process therefore it will be neglected. Since
ceramic capacitance is recommended for use with LED
drivers due to long lifetimes and high ripple current rating, the
ESR of the output capacitor can also be neglected in the loop
analysis. Finally, there is a DC gain of the uncompensated
loop which is dependent on internal controller gains and the
external sensing network.
A buck-boost regulator will be used as an example case. See
the Design Guide section for compensation of all topologies.
The uncompensated loop gain for a buck-boost regulator is
given by the following equation:
Where the uncompensated DC loop gain of the system is de-
scribed as:
And the output pole (ωP1) is approximated:
And the right half plane zero (ωZ1) is:
300673a7
FIGURE 8. Uncompensated Loop Gain Frequency
Response
Figure 8 shows the uncompensated loop gain in a worst-case
scenario when the RHP zero is below the output pole. This
occurs at high duty cycles when the regulator is trying to boost
the output voltage significantly. The RHP zero adds 20dB/
decade of gain while loosing 45°/decade of phase which
places the crossover frequency (when the gain is zero dB)
extremely high because the gain only starts falling again due
to the high frequency pole (not modeled or shown in figure).
The phase will be below -180° at the crossover frequency
which means there is no phase margin (180° + phase at
crossover frequency) causing system instability. Even if the
output pole is below the RHP zero, the phase will still reach
-180° before the crossover frequency in most cases yielding
instability.
300673a3
FIGURE 9. Compensation Circuitry
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
To mitigate this problem, a compensator should be designed
to give adequate phase margin (above 45°) at the crossover
frequency. A simple compensator using a single capacitor at
the COMP pin (CCMP) will add a dominant pole to the system,
which will ensure adequate phase margin if placed low
enough. At high duty cycles (as shown in Figure 8), the RHP
zero places extreme limits on the achievable bandwidth with
this type of compensation. However, because an LED driver
is essentially free of output transients (except catastrophic
failures open or short), the dominant pole approach, even with
reduced bandwidth, is usually the best approach. The domi-
nant compensation pole (ωP2) is determined by CCMP and the
output resistance (RO) of the error amplifier (typically 5 MΩ):
It may also be necessary to add one final pole at least one
decade above the crossover frequency to attenuate switching
noise and, in some cases, provide better gain margin. This
pole can be placed across RSNS to filter the ESL of the sense
resistor at the same time. Figure 9 shows how the compen-
sation is physically implemented in the system.
The high frequency pole (ωP3) can be calculated:
The total system transfer function becomes:
The resulting compensated loop gain frequency response
shown in Figure 10 indicates that the system has adequate
phase margin (above 45°) if the dominant compensation pole
is placed low enough, ensuring stability:
300673a4
FIGURE 10. Compensated Loop Gain Frequency
Response
30067361
FIGURE 11. Start-Up Waveforms
START-UP REGULATOR
The LM3421/23 includes a high voltage, low dropout bias
regulator. When power is applied, the regulator is enabled
and sources current into an external capacitor (CBYP) con-
nected to the VCC pin. The recommended bypass capacitance
for the VCC regulator is 2.2 µF to 3.3 µF. The output of the
VCC regulator is monitored by an internal UVLO circuit that
protects the device from attempting to operate with insuffi-
cient supply voltage and the supply is also internally current
limited. Figure 11 shows the typical start-up waveforms for the
LM3421/23.
First, CBYP is charged to be above VCC UVLO threshold
(~4.2V). The CVCC charging time (tVCC) can be estimated as:
CCMP is then charged to 0.9V over the charging time (tCMP)
which can be estimated as:
Once CCMP = 0.9V, the part starts switching to charge CO until
the LED current is in regulation. The CO charging time (tCO)
can be roughly estimated as:
The system start-up time (tSU) is defined as:
In some configurations, the start-up waveform will overshoot
the steady state COMP pin voltage. In this case, the LED cur-
rent and output voltage will overshoot also, which can trip the
over-voltage or protection, causing a race condition. The eas-
iest way to prevent this is to use a larger compensation
capacitor (CCMP), thereby slowing down the control loop.
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
OVER-VOLTAGE LOCKOUT (OVLO)
30067358
FIGURE 12. Over-Voltage Protection Circuitry
The LM3421/23 can be configured to detect an output (or in-
put) over-voltage condition via the OVP pin. The pin features
a precision 1.24V threshold with 23 µA (typical) of hysteresis
current as shown in Figure 12. When the OVLO threshold is
exceeded, the GATE pin is immediately pulled low and a 23
µA current source provides hysteresis to the lower threshold
of the OVLO hysteretic band.
If the LEDs are referenced to a potential other than ground
(floating), as in the buck-boost and buck configuration, the
output voltage (VO) should be sensed and translated to
ground by using a single PNP as shown in Figure 13.
The over-voltage turn-off threshold (VTURN-OFF) is defined:
Ground Referenced
Floating
In the ground referenced configuration, the voltage across
ROV2 is VO - 1.24V whereas in the floating configuration it is
VO - 620 mV where 620 mV approximates VBE of the PNP.
The over-voltage hysteresis (VHYSO) is defined:
30067359
FIGURE 13. Floating Output OVP Circuitry
The OVLO feature can cause some interesting results if the
OVLO trip-point is set too cose to VO. At turn-on, the converter
has a modest amount of voltage overshoot before the control
loop gains control of ILED. If the overshoot exceeds the OVLO
threshold, the controller shuts down, opening the dimming
MosFET. This isolates the LED load from the converter and
the output capacitance. The voltage will then discharge very
slowly through the HSP and HSN pins until VO drops below
the lower threshold, where the process repeats. This looks
like the LEDs are blinking at around 2 Hz. This mode can be
escaped if the input voltage is reduced.
INPUT UNDER-VOLTAGE LOCKOUT (UVLO)
The nDIM pin is a dual-function input that features an accurate
1.24V threshold with programmable hysteresis as shown in
Figure 14. This pin functions as both the PWM dimming input
for the LEDs and as a VIN UVLO. When the pin voltage rises
and exceeds the 1.24V threshold, 23 µA (typical) of current is
driven out of the nDIM pin into the resistor divider providing
programmable hysteresis.
300673a5
FIGURE 14. UVLO Circuit
When using the nDIM pin for UVLO and PWM dimming con-
currently, the UVLO circuit can have an extra series resistor
to set the hysteresis. This allows the standard resistor divider
to have smaller resistor values minimizing PWM delays due
to a pull-down MosFET at the nDIM pin (see PWM Dimming
section). In general, at least 3V of hysteresis is preferable
when PWM dimming, if operating near the UVLO threshold.
The turn-on threshold (VTURN-ON) is defined as follows:
The hysteresis (VHYS) is defined as follows:
UVLO only
PWM dimming and UVLO
When "zero current" shutdown and UVLO are implemented
together, the EN pin can be used to escape UVLO. The nDIM
pin will pull-up to VIN when EN is pulled low, therefore if VIN is
within the UVLO hysteretic window when EN is pulled high
again, the controller will start-up even though VTURN-ON is not
exceeded.
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
PWM DIMMING
The active low nDIM pin can be driven with a PWM signal
which controls the main NFET and the dimming FET (dim-
FET). The brightness of the LEDs can be varied by modulat-
ing the duty cycle of this signal. LED brightness is approxi-
mately proportional to the PWM signal duty cycle, (i.e. 30%
duty cycle ~ 30% LED brightness). This function can be ig-
nored if PWM dimming is not required by using nDIM solely
as a VIN UVLO input as described in the Input Under-Voltage
Lockout section or by tying it directly to VCC or VIN.
300673a6
FIGURE 15. PWM Dimming Circuit
Figure 15 shows how the PWM signal is applied to nDIM:
1. Connect the dimming MosFET (QDIM) with the drain to
the nDIM pin and the source to AGND. Apply an external
logic-level PWM signal to the gate of QDIM.
2. Connect the anode of a Schottky diode (DDIM) to the
nDIM pin. Apply an inverted external logic-level PWM
signal to the cathode of the same diode.
The DDRV pin is a PWM output that follows the nDIM PWM
input signal. When the nDIM pin rises, the DDRV pin rises and
the PWM latch reset signal is removed allowing the main
MosFET Q1 to turn on at the beginning of the next clock set
pulse. In boost and buck-boost topologies, the DDRV pin is
used to control a N-channel MosFET placed in series with the
LED load, while it would control a P-channel MosFET in par-
allel with the load for a buck topology.
The series dimFET will open the LED load, when nDIM is low,
effectively speeding up the rise and fall times of the LED cur-
rent. Without any dimFET, the rise and fall times are limited
by the inductor slew rate and dimming frequencies above
1 kHz are impractical. Using the series dimFET, dimming fre-
quencies up to 30 kHz are achievable. With a parallel dimFET
(buck topology), even higher dimming frequencies are
achievable.
When using the PWM functionality in a boost regulator, the
PWM signal can drive a ground referenced FET. However,
with buck-boost and buck topologies, level shifting circuitry is
necessary to translate the PWM dim signal to the floating
dimFET as shown in Figure 16 and Figure 17. If high side
dimming is necessary in a boost regulator using the LM3423,
level shifting can be added providing the polarity inverting
DPOL pin is pulled low (see LM3423 ONLY: DPOL, FLT,
TIMR, and LRDY section) as shown in Figure 18.
When using a series dimFET to PWM dim the LED current,
more output capacitance is always better. A general rule of
thumb is to use a minimum of 40 µF when PWM dimming. For
most applications, this will provide adequate energy storage
at the output when the dimFET turns off and opens the LED
load. Then when the dimFET is turned back on, the capaci-
tance helps source current into the load, improving the LED
current rise time.
A minimum on-time must be maintained in order for PWM
dimming to operate in the linear region of its transfer function.
Because the controller is disabled during dimming, the PWM
pulse must be long enough such that the energy intercepted
from the input is greater than or equal to the energy being put
into the LEDs. For boost and buck-boost regulators, the min-
imum dimming pulse length in seconds (tPULSE) is:
Even maintaining a dimming pulse greater than tPULSE, pre-
serving linearity at low dimming duty cycles is difficult.
The second helpful modification is to remove the CFS capac-
itor and RFS resistor, eliminating the high frequency compen-
sation pole. This should not affect stability, but it will speed up
the response of the CSH pin, specifically at the rising edge of
the LED current when PWM dimming, thus improving the
achievable linearity at low dimming duty cycles.
300673a0
FIGURE 16. Buck-boost Level-Shifted PWM Circuit
30067331
FIGURE 17. Buck Level-Shifted PWM Circuit
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300673j5
FIGURE 18. Boost Level-Shifted PWM Circuit
LM3423 ONLY: DPOL, FLT, TIMR, and LRDY
The LM3423 has four additional pins: DPOL, FLT, TIMR, and
LRDY. The DPOL pin is simply used to invert the DDRV po-
larity . If DPOL is left open, then it is internally pulled high and
the polarity is correct for driving a series N-channel dimFET.
If DPOL is pulled low then the polarity is correct for using a
series P-channel dimFET in high-side dimming applications.
For a parallel P-channel dimFET, as used in the buck topol-
ogy, leave DPOL open for proper polarity.
Among the LM3423's other additional pins are TIMR and FLT
which can be used in conjunction with an input disconnect
MosFET switch as shown in Figure 19 to protect the module
from various fault conditions.
A fault is detected and an 11.5 µA (typical) current is sourced
from the TIMR pin whenever any of the following conditions
exist:
1. LED current is above regulation by more than 30%.
2. OVLO has engaged.
3. Thermal shutdown has engaged.
An external capacitor (CTMR) from TIMR to AGND programs
the fault filter time as follows:
When the voltage on the TIMR pin reaches 1.24V, the device
is latched off and the N-channel MosFET open drain FLT pin
transitions to a high impedance state. The TIMR pin will be
immediately pulled to ground (reset) if the fault condition is
removed at any point during the filter period. Otherwise, if the
timer expires, the fault will remain latched until one of three
things occurs:
1. The EN pin is pulled low long enough for the VCC pin to
drop below 4.1V (approximately 200 ms).
2. The TIMR pin is pulled to ground.
3. A complete power cycle occurs.
When using the EN and OVP pins in conjunction with the RPD
pull-down pin, a race condition exists when exiting the dis-
abled (EN low) state. When disabled, the OVP pin is pulled
up to the output voltage because the RPD pull-down is dis-
abled, and this will appear to be a real OVLO condition. The
timer pin will immediately rise and latch the controller to the
fault state. To protect against this behavior, a minimum timer
capacitor (CTMR = 220pF) should be used. If fault latching is
not required, short the TMR pin to AGND which will disable
the FLT flag function.
The LM3423 also includes an LED Ready (LRDY) flag to no-
tify the system that the LEDs are in proper regulation. The N-
channel MosFET open drain LRDY pin is pulled low whenever
any of the following conditions are met:
1. VCC UVLO has engaged.
2. LED current is below regulation by more than 20%.
3. LED current is above regulation by more than 30%.
4. Over-voltage protection has engaged
5. Thermal shutdown has engaged.
6. A fault has latched the device off.
Note that the LRDY pin is pulled low during startup of the de-
vice and remains low until the LED current is in regulation.
300673j4
FIGURE 19. Fault Detection and LED Status Circuit
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
Design Considerations
This section describes the application level considerations
when designing with the LM3421/23. For corresponding cal-
culations, refer to the Design Guide section.
INDUCTOR
The inductor (L1) is the main energy storage device in a
switching regulator. Depending on the topology, energy is
stored in the inductor and transfered to the load in different
ways (as an example, buck-boost operation is detailed in the
Current Regulators section). The size of the inductor, the volt-
age across it, and the length of the switching subinterval
(tON or tOFF) determines the inductor current ripple (ΔiL-PP ). In
the design process, L1 is chosen to provide a desired ΔiL-PP.
For a buck regulator the inductor has a direct connection to
the load, which is good for a current regulator. This requires
little to no output capacitance therefore ΔiL-PP is basically
equal to the LED ripple current ΔiLED-PP. However, for boost
and buck-boost regulators, there is always an output capaci-
tor which reduces ΔiLED-PP, therefore the inductor ripple can
be larger than in the buck regulator case where output ca-
pacitance is minimal or completely absent.
In general, ΔiLED-PP is recommended by manufacturers to be
less than 40% of the average LED current (ILED). Therefore,
for the buck regulator with no output capacitance, ΔiL-PP
should also be less than 40% of ILED. For the boost and buck-
boost topologies, ΔiL-PP can be much higher depending on the
output capacitance value. However, ΔiL-PP is suggested to be
less than 100% of the average inductor current (IL) to limit the
RMS inductor current.
L1 is also suggested to have an RMS current rating at least
25% higher than the calculated minimum allowable RMS in-
ductor current (IL-RMS).
LED DYNAMIC RESISTANCE
When the load is a string of LEDs, the output load resistance
is the LED string dynamic resistance plus RSNS. LEDs are PN
junction diodes, and their dynamic resistance shifts as their
forward current changes. Dividing the forward voltage of a
single LED (VLED) by the forward current (ILED) leads to an
incorrect calculation of the dynamic resistance of a single LED
(rLED). The result can be 5 to 10 times higher than the true
rLED value.
30067374
FIGURE 20. Dynamic Resistance
Obtaining rLED is accomplished by refering to the
manufacturer's LED I-V characteristic. It can be calculated as
the slope at the nominal operating point as shown in Figure
20. For any application with more than 2 series LEDs, RSNS
can be neglected allowing rD to be approximated as the num-
ber of LEDs multiplied by rLED.
OUTPUT CAPACITOR
For boost and buck-boost regulators, the output capacitor
(CO) provides energy to the load when the recirculating diode
(D1) is reverse biased during the first switching subinterval.
An output capacitor in a buck topology will simply reduce the
LED current ripple (ΔiLED-PP) below the inductor current ripple
(ΔiL-PP). In all cases, CO is sized to provide a desired ΔiLED-
PP. As mentioned in the Inductor section, ΔiLED-PP is recom-
mended by manufacturers to be less than 40% of the average
LED current (ILED-PP).
CO should be carefully chosen to account for derating due to
temperature and operating voltage. It must also have the nec-
essary RMS current rating. Ceramic capacitors are the best
choice due to their high ripple current rating, long lifetime, and
good temperature performance. An X7R dieletric rating is
suggested.
INPUT CAPACITORS
The input capacitance (CIN) provides energy during the dis-
continuous portions of the switching period. For buck and
buck-boost regulators, CIN provides energy during tON and
during tOFF, the input voltage source charges up CIN with the
average input current (IIN). For boost regulators, CIN only
needs to provide the ripple current due to the direct connec-
tion to the inductor. CIN is selected given the maximum input
voltage ripple (ΔvIN-PP) which can be tolerated. ΔvIN-PP is sug-
gested to be less than 10% of the input voltage (VIN).
An input capacitance at least 100% greater than the calcu-
lated CIN value is recommended to account for derating due
to temperature and operating voltage. When PWM dimming,
even more capacitance can be helpful to minimize the large
current draw from the input voltage source during the rising
transistion of the LED current waveform.
The chosen input capacitors must also have the necessary
RMS current rating. Ceramic capacitors are again the best
choice due to their high ripple current rating, long lifetime, and
good temperature performance. An X7R dieletric rating is
suggested.
For most applications, it is recommended to bypass the VIN
pin with an 0.1 µF ceramic capacitor placed as close as pos-
sible to the pin. In situations where the bulk input capacitance
may be far from the LM3421/23 device, a 10 Ω series resistor
can be placed between the bulk input capacitance and the
bypass capacitor, creating a 150 kHz filter to eliminate unde-
sired high frequency noise.
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
MAIN MosFET / DIMMING MosFET
The LM3421/23 requires an external NFET (Q1) as the main
power MosFET for the switching regulator. Q1 is recommend-
ed to have a voltage rating at least 15% higher than the
maximum transistor voltage to ensure safe operation during
the ringing of the switch node. In practice, all switching regu-
lators have some ringing at the switch node due to the diode
parasitic capacitance and the lead inductance. The current
rating is recommended to be at least 10% higher than the
average transistor current. The power rating is then verified
by calculating the power loss given the RMS transistor current
and the NFET on-resistance (RDS-ON).
When PWM dimming, the LM3421/23 requires another Mos-
FET (Q2) placed in series (or parallel for a buck regulator)
with the LED load. This MosFET should have a voltage rating
equal to the output voltage (VO) and a current rating at least
10% higher than the nominal LED current (ILED) . The power
rating is simply VO multiplied by ILED, assuming 100% dim-
ming duty cycle (continuous operation) will occur.
In general, the NFETs should be chosen to minimize total gate
charge (Qg) when fSW is high and minimize RDS-ON otherwise.
This will minimize the dominant power losses in the system.
Frequently, higher current NFETs in larger packages are cho-
sen for better thermal performance.
RE-CIRCULATING DIODE
A re-circulating diode (D1) is required to carry the inductor
current during tOFF. The most efficient choice for D1 is a
Schottky diode due to low forward voltage drop and near-zero
reverse recovery time. Similar to Q1, D1 is recommended to
have a voltage rating at least 15% higher than the maximum
transistor voltage to ensure safe operation during the ringing
of the switch node and a current rating at least 10% higher
than the average diode current. The power rating is verified
by calculating the power loss through the diode. This is ac-
complished by checking the typical diode forward voltage
from the I-V curve on the product datasheet and multiplying
by the average diode current. In general, higher current
diodes have a lower forward voltage and come in better per-
forming packages minimizing both power losses and temper-
ature rise.
BOOST INRUSH CURRENT
When configured as a boost converter, there is a “phantom”
power path comprised of the inductor, the output diode, and
the output capacitor. This path will cause two things to happen
when power is applied. First, there will be a very large inrush
of current to charge the output capacitor. Second, the energy
stored in the inductor during this inrush will end up in the out-
put capacitor, charging it to a higher potential than the input
voltage.
Depending on the state of the EN pin, the output capacitor
would be discharged by:
1. EN < 1.3V: no discharge path (leakage only).
2. EN > 1.3V, the OVP divider resistor path, if present, and
10µA into each of the HSP & HSN pins.
In applications using the OVP divider and with EN > 1.3V, the
output capacitor voltage can charge higher than VTURN-OFF. In
this situation, the FLT pin (LM3423 only) is open and the PWM
dimming MosFET is turned off. This condition (the system
appearing disabled) can persist for an undesirably long time.
Possible solutions to this condition are:
•Add an inrush diode from VIN to the output as shown in
Figure 21.
•Add an NTC thermistor in series with the input to prevent
the inrush from overcharging the output capacitor too high.
•Use a current limited source supply.
•Raise the OVP threshold.
300673i9
FIGURE 21. Boost Topology with Inrush Diode
CIRCUIT LAYOUT
The performance of any switching regulator depends as much
upon the layout of the PCB as the component selection. Fol-
lowing a few simple guidelines will maximimize noise rejection
and minimize the generation of EMI within the circuit.
Discontinuous currents are the most likely to generate EMI,
therefore care should be taken when routing these paths. The
main path for discontinuous current in the LM3421/23 buck
regulator contains the input capacitor (CIN), the recirculating
diode (D1), the N-channel MosFET (Q1), and the sense re-
sistor (RLIM). In the LM3421/23 boost regulator, the discon-
tinuous current flows through the output capacitor (CO), D1,
Q1, and RLIM. In the buck-boost regulator both loops are dis-
continuous and should be carefully layed out. These loops
should be kept as small as possible and the connections be-
tween all the components should be short and thick to mini-
mize parasitic inductance. In particular, the switch node
(where L1, D1 and Q1 connect) should be just large enough
to connect the components. To minimize excessive heating,
large copper pours can be placed adjacent to the short current
path of the switch node.
The RT, COMP, CSH, IS, HSP and HSN pins are all high-
impedance inputs which couple external noise easily, there-
fore the loops containing these nodes should be minimized
whenever possible.
In some applications the LED or LED array can be far away
(several inches or more) from the LM3421/23, or on a sepa-
rate PCB connected by a wiring harness. When an output
capacitor is used and the LED array is large or separated from
the rest of the regulator, the output capacitor should be placed
close to the LEDs to reduce the effects of parasitic inductance
on the AC impedance of the capacitor.
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
Basic Topology Schematics
BOOST REGULATOR (VIN < VO)
30067322
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
BUCK REGULATOR (VIN > VO)
30067351
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
BUCK-BOOST REGULATOR
30067350
23 www.national.com
LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
Design Guide
Refer to Basic Topology Schematics section.
SPECIFICATIONS
Number of series LEDs: N
Single LED forward voltage: VLED
Single LED dynamic resistance: rLED
Nominal input voltage: VIN
Input voltage range: VIN-MAX, VIN-MIN
Switching frequency: fSW
Current sense voltage: VSNS
Average LED current: ILED
Inductor current ripple: ΔiL-PP
LED current ripple: ΔiLED-PP
Peak current limit: ILIM
Input voltage ripple: ΔvIN-PP
Output OVLO characteristics: VTURN-OFF, VHYSO
Input UVLO characteristics: VTURN-ON, VHYS
1. OPERATING POINT
Given the number of series LEDs (N), the forward voltage
(VLED) and dynamic resistance (rLED) for a single LED, solve
for the nominal output voltage (VO) and the nominal LED
string dynamic resistance (rD):
Solve for the ideal nominal duty cycle (D):
Buck
Boost
Buck-boost
Using the same equations, find the minimum duty cycle
(DMIN) using maximum input voltage (VIN-MAX) and the maxi-
mum duty cycle (DMAX) using the minimum input voltage (VIN-
MIN). Also, remember that D' = 1 - D.
2. SWITCHING FREQUENCY
Set the switching frequency (fSW) by assuming a CT value of
1 nF and solving for RT:
Buck (Constant Ripple vs. VIN)
Buck (Constant Ripple vs. VO)
Boost and Buck-boost
3. AVERAGE LED CURRENT
For all topologies, set the average LED current (ILED) knowing
the desired current sense voltage (VSNS) and solving for
RSNS:
If the calculated RSNS is too far from a desired standard value,
then VSNS will have to be adjusted to obtain a standard value.
Setup the suggested signal current of 100 µA by assuming
RCSH = 12.4 kΩ and solving for RHSP:
If the calculated RHSP is too far from a desired standard value,
then RCSH can be adjusted to obtain a standard value.
4. INDUCTOR RIPPLE CURRENT
Set the nominal inductor ripple current (ΔiL-PP) by solving for
the appropriate inductor (L1):
Buck
Boost and Buck-boost
To set the worst case inductor ripple current, use VIN-MAX and
DMIN when solving for L1.
The minimum allowable inductor RMS current rating (IL-RMS)
can be calculated as:
Buck
Boost and Buck-boost
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
5. LED RIPPLE CURRENT
Set the nominal LED ripple current (ΔiLED-PP), by solving for
the output capacitance (CO):
Buck
Boost and Buck-boost
To set the worst case LED ripple current, use DMAX when
solving for CO. Remember, when PWM dimming it is recom-
mended to use a minimum of 40 µF of output capacitance to
improve performance.
The minimum allowable RMS output capacitor current rating
(ICO-RMS) can be approximated:
Buck
Boost and Buck-boost
6. PEAK CURRENT LIMIT
Set the peak current limit (ILIM) by solving for the transistor
path sense resistor (RLIM):
7. LOOP COMPENSATION
Using a simple first order peak current mode control model,
neglecting any output capacitor ESR dynamics, the neces-
sary loop compensation can be determined.
First, the uncompensated loop gain (TU) of the regulator can
be approximated:
Buck
Boost and Buck-boost
Where the pole (ωP1) is approximated:
Buck
Boost
Buck-boost
And the RHP zero (ωZ1) is approximated:
Boost
Buck-boost
And the uncompensated DC loop gain (TU0) is approximated:
Buck
Boost
Buck-boost
For all topologies, the primary method of compensation is to
place a low frequency dominant pole (ωP2) which will ensure
that there is ample phase margin at the crossover frequency.
This is accomplished by placing a capacitor (CCMP) from the
COMP pin to AGND, which is calculated according to the low-
er value of the pole and the RHP zero of the system (shown
as a minimizing function):
If analog dimming is used, CCMP should be approximately 4x
larger to maintain stability as the LEDs are dimmed to zero.
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
A high frequency compensation pole (ωP3) can be used to
attenuate switching noise and provide better gain margin. As-
suming RFS = 10Ω, CFS is calculated according to the higher
value of the pole and the RHP zero of the system (shown as
a maximizing function):
The total system loop gain (T) can then be written as:
Buck
Boost and Buck-boost
8. INPUT CAPACITANCE
Set the nominal input voltage ripple (ΔvIN-PP) by solving for
the required capacitance (CIN):
Buck
Boost
Buck-boost
Use DMAX to set the worst case input voltage ripple, when
solving for CIN in a buck-boost regulator and DMID = 0.5 when
solving for CIN in a buck regulator.
The minimum allowable RMS input current rating (ICIN-RMS)
can be approximated:
Buck
Boost
Buck-boost
9. NFET
The NFET voltage rating should be at least 15% higher than
the maximum NFET drain-to-source voltage (VT-MAX):
Buck
Boost
Buck-boost
The current rating should be at least 10% higher than the
maximum average NFET current (IT-MAX):
Buck
Boost and Buck-boost
Approximate the nominal RMS transistor current (IT-RMS) :
Buck
Boost and Buck-boost
Given an NFET with on-resistance (RDS-ON), solve for the
nominal power dissipation (PT):
10. DIODE
The Schottky diode voltage rating should be at least 15%
higher than the maximum blocking voltage (VRD-MAX):
Buck
Boost
Buck-boost
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
The current rating should be at least 10% higher than the
maximum average diode current (ID-MAX):
Buck
Boost and Buck-boost
Replace DMAX with D in the ID-MAX equation to solve for the
average diode current (ID). Given a diode with forward voltage
(VFD), solve for the nominal power dissipation (PD):
11. OUTPUT OVLO
For boost and buck-boost regulators, output OVLO is pro-
grammed with the turn-off threshold voltage (VTURN-OFF) and
the desired hysteresis (VHYSO). To set VHYSO, solve for ROV2:
To set VTURN-OFF, solve for ROV1:
Boost
Buck-boost
A small filter capacitor (COVP = 47 pF) should be added from
the OVP pin to ground to reduce coupled switching noise.
12. INPUT UVLO
For all topologies, input UVLO is programmed with the turn-
on threshold voltage (VTURN-ON) and the desired hysteresis
(VHYS).
Method #1: If no PWM dimming is required, a two resistor
network can be used. To set VHYS, solve for RUV2:
To set VTURN-ON, solve for RUV1:
Method #2: If PWM dimming is required, a three resistor net-
work is suggested. To set VTURN-ON, assume RUV2 = 10 kΩ
and solve for RUV1 as in Method #1. To set VHYS, solve for
RUVH:
13. PWM DIMMING METHOD
PWM dimming can be performed several ways:
Method #1: Connect the dimming MosFET (Q3) with the drain
to the nDIM pin and the source to AGND. Apply an external
PWM signal to the gate of QDIM. A pull down resistor may be
necessary to properly turn off Q3.
Method #2: Connect the anode of a Schottky diode to the
nDIM pin. Apply an external inverted PWM signal to the cath-
ode of the same diode.
The DDRV pin should be connected to the gate of the dimFET
with or without level-shifting circuitry as described in the PWM
Dimming section. The dimFET should be rated to handle the
average LED current and the nominal output voltage.
14. ANALOG DIMMING METHOD
Analog dimming can be performed several ways:
Method #1: Place a potentiometer in series with the RCSH
resistor to dim the LED current from the nominal ILED to near
zero.
Method #2: Connect a controlled current source as detailed
in the Analog Dimming section to the CSH pin. Increasing the
current sourced into the CSH node will decrease the LEDs
from the nominal ILED to zero current in the same manner as
the thermal foldback circuit.
27 www.national.com
LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
Design Example
DESIGN #1 - LM3421 BUCK-BOOST Application
300673i1
SPECIFICATIONS
N = 6
VLED = 3.5V
rLED = 325 mΩ
VIN = 24V
VIN-MIN = 10V
VIN-MAX = 70V
fSW = 500 kHz
VSNS = 100 mV
ILED = 1A
ΔiL-PP = 700 mA
ΔiLED-PP = 12 mA
ΔvIN-PP = 100 mV
ILIM = 6A
VTURN-ON = 10V
VHYS = 3V
VTURN-OFF = 40V
VHYSO = 10V
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
1. OPERATING POINT
Solve for VO and rD:
Solve for D, D', DMAX, and DMIN:
2. SWITCHING FREQUENCY
Assume CT = 1 nF and solve for RT:
The closest standard resistor is 49.9 kΩ therefore fSW is:
The chosen component from step 2 is:
3. AVERAGE LED CURRENT
Solve for RSNS:
Assume RCSH = 12.4 kΩ and solve for RHSP:
The closest standard resistor for RSNS is actually 0.1Ω and for
RHSP is actually 1 kΩ therefore ILED is:
The chosen components from step 3 are:
4. INDUCTOR RIPPLE CURRENT
Solve for L1:
The closest standard inductor is 33 µH therefore ΔiL-PP is:
Determine minimum allowable RMS current rating:
The chosen component from step 4 is:
5. OUTPUT CAPACITANCE
Solve for CO:
The closest capacitance totals 40 µF therefore ΔiLED-PP is:
Determine minimum allowable RMS current rating:
The chosen components from step 5 are:
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
6. PEAK CURRENT LIMIT
Solve for RLIM:
The closest standard resistor is 0.04 Ω therefore ILIM is:
The chosen component from step 6 is:
7. LOOP COMPENSATION
ωP1 is approximated:
ωZ1 is approximated:
TU0 is approximated:
To ensure stability, calculate ωP2:
Solve for CCMP:
To attenuate switching noise, calculate ωP3:
Assume RFS = 10Ω and solve for CFS:
The chosen components from step 7 are:
8. INPUT CAPACITANCE
Solve for the minimum CIN:
To minimize power supply interaction a 200% larger capaci-
tance of approximately 20 µF is used, therefore the actual
ΔvIN-PP is much lower. Since high voltage ceramic capacitor
selection is limited, four 4.7 µF X7R capacitors are chosen.
Determine minimum allowable RMS current rating:
The chosen components from step 8 are:
9. NFET
Determine minimum Q1 voltage rating and current rating:
A 100V NFET is chosen with a current rating of 32A due to
the low RDS-ON = 50 mΩ. Determine IT-RMS and PT:
The chosen component from step 9 is:
10. DIODE
Determine minimum D1 voltage rating and current rating:
A 100V diode is chosen with a current rating of 12A and VD =
600 mV. Determine PD:
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
The chosen component from step 10 is:
11. INPUT UVLO
Solve for RUV2:
The closest standard resistor is 130 kΩ therefore VHYS is:
Solve for RUV1:
The closest standard resistor is 18.2 kΩ making VTURN-ON:
The chosen components from step 11 are:
12. OUTPUT OVLO
Solve for ROV2:
The closest standard resistor is 432 kΩ therefore VHYSO is:
Solve for ROV1:
The closest standard resistor is 13.7 kΩ making VTURN-OFF:
The chosen components from step 12 are:
31 www.national.com
LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
DESIGN #1 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3421 Buck-boost controller NSC LM3421MH
1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L
1 CCMP 0.33 µF X7R 10% 25V MURATA GRM21BR71E334KA01L
1 CFS 0.27 µF X7R 10% 25V MURATA GRM21BR71E274KA01L
4 CIN 4.7 µF X7R 10% 100V TDK C5750X7R2A475K
4 CO10 µF X7R 10% 50V TDK C4532X7R1H106K
1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A
1 CT1000 pF COG/NPO 5% 50V MURATA GRM2165C1H102JA01D
1 D1 Schottky 100V 12A VISHAY 12CWQ10FNPBF
1 L1 33 µH 20% 6.3A COILCRAFT MSS1278-333MLB
1 Q1 NMOS 100V 32A FAIRCHILD FDD3682
1 Q2 PNP 150V 600 mA FAIRCHILD MMBT5401
1 RCSH 12.4 kΩ 1% VISHAY CRCW080512K4FKEA
1 RFS 10Ω 1% VISHAY CRCW080510R0FKEA
2 RHSP, RHSN 1.0 kΩ 1% VISHAY CRCW08051K00FKEA
1 RLIM 0.04Ω 1% 1W VISHAY WSL2512R0400FEA
1 ROV1 13.7 kΩ 1% VISHAY CRCW080513K7FKEA
1 ROV2 432 kΩ 1% VISHAY CRCW0805432KFKEA
1 RSNS 0.1Ω 1% 1W VISHAY WSL2512R1000FEA
1 RT49.9 kΩ 1% VISHAY CRCW080549K9FKEA
1 RUV1 18.2 kΩ 1% VISHAY CRCW080518K2FKEA
1 RUV2 130 kΩ 1% VISHAY CRCW0805130KFKEA
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
Applications Information
The following designs are provided as reference circuits. For a specific design, the steps in the Design Procedure section should
be performed. In all designs, an RC filter (0.1 µF, 10Ω) is recommended at VIN placed as close as possible to the LM3421/23
device. This filter is not shown in the following designs.
DESIGN #2 - LM3421 BOOST Application
300673h5
Features
•Input: 8V to 28V
•Output: 9 LEDs at 1A
•PWM Dimming up to 30kHz
•700 kHz Switching Frequency
33 www.national.com
LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
DESIGN #2 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3421 Boost controller NSC LM3421MH
1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L
1 CCMP 0.1 µF X7R 10% 25V MURATA GRM21BR71E104KA01L
0 CFS DNP
4 CIN 4.7 µF X7R 10% 100V TDK C5750X7R2A475K
4 CO10 µF X7R 10% 50V TDK C4532X7R1H106K
1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A
1 CT1000 pF COG/NPO 5% 50V MURATA GRM2165C1H102JA01D
2 D1, D2 Schottky 60V 5A COMCHIP CDBC560-G
1 L1 33 µH 20% 6.3A COILCRAFT MSS1278-333MLB
2 Q1, Q2 NMOS 60V 8A VISHAY SI4436DY
1 Q3 NMOS 60V 115mA ON-SEMI 2N7002ET1G
2 RCSH, ROV1 12.4 kΩ 1% VISHAY CRCW080512K4FKEA
1 RFS 0Ω 1% VISHAY CRCW08050000Z0EA
2 RHSP, RHSN 1.0 kΩ 1% VISHAY CRCW08051K00FKEA
1 RLIM 0.06Ω 1% 1W VISHAY WSL2512R0600FEA
1 ROV2 499 kΩ 1% VISHAY CRCW0805499KFKEA
1 RSNS 0.1Ω 1% 1W VISHAY WSL2512R1000FEA
1 RUV2 10.0 kΩ 1% VISHAY CRCW080510K0FKEA
1 RT35.7 kΩ 1% VISHAY CRCW080535K7FKEA
1 RUV1 1.82 kΩ 1% VISHAY CRCW08051K82FKEA
1 RUVH 17.8 kΩ 1% VISHAY CRCW080517K8FKEA
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
DESIGN #3 - LM3421 BUCK-BOOST Application
300673h6
Features
•Input: 10V to 30V
•Output: 4 LEDs at 2A
•PWM Dimming up to 10kHz
•Analog Dimming
•600 kHz Switching Frequency
35 www.national.com
LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
DESIGN #3 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3421 Buck-boost controller NSC LM3421MH
1 CB100 pF COG/NPO 5% 50V MURATA GRM2165C1H101JA01D
1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L
3 CCMP, CREF, CSS 1 µF X7R 10% 25V MURATA GRM21BR71E105KA01L
1 CF0.1 µF X7R 10% 25V MURATA GRM21BR71E104KA01L
0 CFS DNP
4 CIN 6.8 µF X7R 10% 50V TDK C5750X7R1H685K
4 CO10 µF X7R 10% 50V TDK C4532X7R1H106K
1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A
1 CT1000 pF COG/NPO 5% 50V MURATA GRM2165C1H102JA01D
1 D1 Schottky 100V 12A VISHAY 12CWQ10FNPBF
1 D2 Zener 10V 500mA ON-SEMI BZX84C10LT1G
1 L1 22 µH 20% 7.2A COILCRAFT MSS1278-223MLB
2 Q1, Q2 NMOS 60V 8A VISHAY SI4436DY
1 Q3 NMOS 60V 260mA ON-SEMI 2N7002ET1G
1 Q4 PNP 40V 200 mA FAIRCHILD MMBT5087
1 Q5 PNP 150V 600 mA FAIRCHILD MMBT5401
1 Q6 NPN 300V 600 mA FAIRCHILD MMBTA42
1 Q7 NPN 40V 200 mA FAIRCHILD MMBT6428
1 RCSH 12.4 kΩ 1% VISHAY CRCW080512K4FKEA
1 RF10Ω 1% VISHAY CRCW080510R0FKEA
1 RFS 0Ω 1% VISHAY CRCW08050000Z0EA
1 RUV2 10.0 kΩ 1% VISHAY CRCW080510K0FKEA
2 RHSP, RHSN 1.0 kΩ 1% VISHAY CRCW08051K00FKEA
1 RLIM 0.04Ω 1% 1W VISHAY WSL2512R0400FEA
1 ROV1 18.2 kΩ 1% VISHAY CRCW080518K2FKEA
1 ROV2 499 kΩ 1% VISHAY CRCW0805499KFKEA
1 RPOT 1 MΩ potentiometer BOURNS 3352P-1-105
1 RPU 4.99 kΩ 1% VISHAY CRCW08054K99FKEA
1 RSER 499Ω 1% VISHAY CRCW0805499RFKEA
1 RSNS 0.05Ω 1% 1W VISHAY WSL2512R0500FEA
1 RT41.2 kΩ 1% VISHAY CRCW080541K2FKEA
1 RUV1 1.43 kΩ 1% VISHAY CRCW08051K43FKEA
1 RUVH 17.4 kΩ 1% VISHAY CRCW080517K4FKEA
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
DESIGN #4 - LM3423 BOOST Application
300673h7
Features
•Input: 18V to 38V
•Output: 12 LEDs at 700mA
•High Side PWM Dimming up to 30 kHz
•Analog Dimming
•Zero Current Shutdown
•700 kHz Switching Frequency
37 www.national.com
LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
DESIGN #4 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3423 Boost controller NSC LM3423MH
1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L
1 CCMP 1 µF X7R 10% 25V MURATA GRM21BR71E105KA01L
1 CFS 0.1 µF X7R 10% 25V MURATA GRM21BR71E104KA01L
4 CIN 4.7 µF X7R 10% 100V TDK C5750X7R2A475K
4 CO10 µF X7R 10% 50V TDK C4532X7R1H106K
1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A
1 CT1000 pF COG/NPO 5% 50V MURATA GRM2165C1H102JA01D
2 D1, D2 Schottky 60V 5A COMCHIP CDBC560-G
1 D3 Zener 10V 500mA ON-SEMI BZX84C10LT1G
1 L1 47 µH 20% 5.3A COILCRAFT MSS1278-473MLB
1 Q1 NMOS 60V 8A VISHAY SI4436DY
1 Q2 PMOS 70V 5.7A ZETEX ZXMP7A17K
1 Q3 NMOS 60V 260mA ON-SEMI 2N7002ET1G
1 Q4, Q5 (dual pack) Dual PNP 40V 200mA FAIRCHILD FFB3906
1 Q6 NPN 300V 600mA FAIRCHILD MMBTA42
1 Q7 NPN 40V 200 mA FAIRCHILD MMBT3904
1 RADJ 100 kΩ potentiometer BOURNS 3352P-1-104
1 RBIAS2 17.4 kΩ 1% VISHAY CRCW080517K4FKEA
2 RCSH, ROV1 12.4 kΩ 1% VISHAY CRCW080512K4FKEA
1 RFS 10Ω 1% VISHAY CRCW080510R0FKEA
3 RHSP, RHSN, RMAX 1.0 kΩ 1% VISHAY CRCW08051K00FKEA
1 RLIM 0.06Ω 1% 1W VISHAY WSL2512R0600FEA
1 ROV2 499 kΩ 1% VISHAY CRCW0805499KFKEA
1 RSNS 0.15Ω 1% 1W VISHAY WSL2512R1500FEA
1 RT35.7 kΩ 1% VISHAY CRCW080535K7FKEA
1 RUV1 1.43 kΩ 1% VISHAY CRCW08051K43FKEA
1 RUV2 10.0 kΩ 1% VISHAY CRCW080510K0FKEA
1 RUVH 16.9 kΩ 1% VISHAY CRCW080516K9FKEA
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
DESIGN #5 - LM3421 BUCK-BOOST Application
300673h9
Features
•Input: 10V to 70V
•Output: 6 LEDs at 500mA
•PWM Dimming up to 10 kHz
•Slow Fade Out
•MosFET RDS-ON Sensing
•700 kHz Switching Frequency
39 www.national.com
LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
DESIGN #5 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3421 Buck-boost controller NSC LM3421MH
1 CB100 pF COG/NPO 5% 50V MURATA GRM2165C1H101JA01D
1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L
1 CCMP 1 µF X7R 10% 25V MURATA GRM21BR71E105KA01L
1 CF0.1 µF X7R 10% 25V MURATA GRM21BR71E104KA01L
0 CFS DNP
4 CIN 4.7 µF X7R 10% 100V TDK C5750X7R2A475K
4 CO10 µF X7R 10% 50V TDK C4532X7R1H106K
1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A
1 CT1000 pF COG/NPO 5% 50V MURATA GRM2165C1H102JA01D
1 D1 Schottky 100V 12A VISHAY 12CWQ10FNPBF
1 D2 Zener 10V 500mA ON-SEMI BZX84C10LT1G
1 L1 68 µH 20% 4.3A COILCRAFT MSS1278-683MLB
2 Q1, Q2 NMOS 100V 32A FAIRCHILD FDD3682
1 Q3 NMOS 60V 260mA ON-SEMI 2N7002ET1G
2 Q4, Q8 PNP 40V 200mA FAIRCHILD MMBT5087
1 Q5 PNP 150V 600 mA FAIRCHILD MMBT5401
1 Q6 NPN 300V 600mA FAIRCHILD MMBTA42
2 Q7, Q9 NPN 40V 200mA FAIRCHILD MMBT6428
1 RCSH 12.4 kΩ 1% VISHAY CRCW080512K4FKEA
1 RFS 0Ω 1% VISHAY CRCW08050000Z0EA
1 RUV2 10.0 kΩ 1% VISHAY CRCW080510K0FKEA
2 RHSP, RHSN 1.0 kΩ 1% VISHAY CRCW08051K00FKEA
1 ROV1 15.8 kΩ 1% VISHAY CRCW080515K8FKEA
1 ROV2 499 kΩ 1% VISHAY CRCW0805499KFKEA
1 RPU 4.99 kΩ 1% VISHAY CRCW08054K99FKEA
1 RSER 499Ω 1% VISHAY CRCW0805499RFKEA
1 RSNS 0.2Ω 1% 1W VISHAY WSL2512R2000FEA
1 RT35.7 kΩ 1% VISHAY CRCW080535K7FKEA
1 RUV1 1.43 kΩ 1% VISHAY CRCW08051K43FKEA
1 RUVH 17.4 kΩ 1% VISHAY CRCW080517K4FKEA
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LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
DESIGN #6 - LM3423 BUCK Application
300673h8
Features
•Input: 15V to 50V
•Output: 3 LEDs at 1.25A
•PWM Dimming up to 50 kHz
•LED Status Indicator
•Zero Current Shutdown
•700 kHz Switching Frequency
41 www.national.com
LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
DESIGN #6 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3423 Buck controller NSC LM3423MH
1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L
2 CCMP, CDIM 0.1 µF X7R 10% 25V MURATA GRM21BR71E104KA01L
0 CFS DNP
4 CIN 4.7 µF X7R 10% 100V TDK C5750X7R2A475K
0 CODNP
1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A
1 CT1000 pF COG/NPO 5% 50V MURATA GRM2165C1H102JA01D
1 D1 Schottky 100V 12A VISHAY 12CWQ10FNPBF
1 D2 Zener 10V 500mA ON-SEMI BZX84C10LT1G
1 L1 22 µH 20% 7.3A COILCRAFT MSS1278-223MLB
1 Q1 NMOS 60V 8A VISHAY SI4436DY
1 Q2 PMOS 30V 6.2A VISHAY SI3483DV
1 Q3 NMOS 60V 115mA ON-SEMI 2N7002ET1G
1 Q4 PNP 150V 600 mA FAIRCHILD MMBT5401
1 RCSH 12.4 kΩ 1% VISHAY CRCW080512K4FKEA
1 RFS 0Ω 1% VISHAY CRCW08050000OZEA
2 RHSP, RHSN 1.0 kΩ 1% VISHAY CRCW08051K00FKEA
1 RLIM 0.04Ω 1% 1W VISHAY WSL2512R0400FEA
1 ROV1 21.5 kΩ 1% VISHAY CRCW080521K5FKEA
1 ROV2 499 kΩ 1% VISHAY CRCW0805499KFKEA
3 RPU, RPU2, RUV2 100 kΩ 1% VISHAY CRCW0805100KFKEA
1 RT35.7 kΩ 1% VISHAY CRCW080535K7FKEA
1 RSNS 0.08Ω 1% 1W VISHAY WSL2512R0800FEA
1 RUV1 11.5 kΩ 1% VISHAY CRCW080511K5FKEA
www.national.com 42
LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
DESIGN #7 - LM3423 BUCK-BOOST Application
300673i0
Features
•Input: 15V to 60V
•Output: 8 LEDs at 2.5A
•Fault Input Disconnect
•Zero Current Shutdown
•500 kHz Switching Frequency
43 www.national.com
LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
DESIGN #7 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3423 Buck-boost controller NSC LM3423MH
1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L
1 CCMP 0.33 µF X7R 10% 25V MURATA GRM21BR71E334KA01L
1 CFS 0.1 µF X7R 10% 25V MURATA GRM21BR71E104KA01L
4 CIN 4.7 µF X7R 10% 100V TDK C5750X7R2A475K
4 CO10 µF X7R 10% 50V TDK C4532X7R1H106K
1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A
1 CT1000 pF COG/NPO 5% 50V MURATA GRM2165C1H102JA01D
1 CTMR 220 pF COG/NPO 5% 50V MURATA GRM2165C1H221JA01D
1 D1 Schottky 100V 12A VISHAY 12CWQ10FNPBF
1 D2 Zener 10V 500mA ON-SEMI BZX84C10LT1G
1 L1 22 µH 20% 7.2A COILCRAFT MSS1278-223MLB
1 Q1 NMOS 100V 32A FAIRCHILD FDD3682
1 Q2 PMOS 70V 5.7A ZETEX ZXMP7A17K
1 Q5 PNP 150V 600 mA FAIRCHILD MMBT5401
2 RCSH, ROV1 12.4 kΩ 1% VISHAY CRCW080512K4FKEA
1 RFS 10Ω 1% VISHAY CRCW080510R0FKEA
2 RFLT, RPU2 100 kΩ 1% VISHAY CRCW0805100KFKEA
2 RHSP, RHSN 1.0 kΩ 1% VISHAY CRCW08051K00FKEA
2 RLIM, RSNS 0.04Ω 1% 1W VISHAY WSL2512R0400FEA
1 ROV1 15.8 kΩ 1% VISHAY CRCW080515K8FKEA
1 ROV2 499 kΩ 1% VISHAY CRCW0805499KFKEA
1 RT49.9 kΩ 1% VISHAY CRCW080549K9FKEA
1 RUV1 13.7 kΩ 1% VISHAY CRCW080513K7FKEA
1 RUV2 150 kΩ 1% VISHAY CRCW0805150KFKEA
www.national.com 44
LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
DESIGN #8 - LM3421 SEPIC Application
300673i8
Features
•Input: 9V to 36V
•Output: 5 LEDs at 750mA
•PWM Dimming up to 30 kHz
•500 kHz Switching Frequency
45 www.national.com
LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
DESIGN #8 Bill of Materials
Qty Part ID Part Value Manufacturer Part Number
1 LM3421 SEPIC controller NSC LM3421MH
1 CBYP 2.2 µF X7R 10% 16V MURATA GRM21BR71C225KA12L
1 CCMP 0.47 µF X7R 10% 25V MURATA GRM21BR71E474KA01L
0 CFS DNP
4 CIN 4.7 µF X7R 10% 100V TDK C5750X7R2A475K
4 CO10 µF X7R 10% 50V TDK C4532X7R1H106K
1 CSEP 1.0 µF X7R 10% 100V TDK C4532X7R2A105K
1 COV 47 pF COG/NPO 5% 50V AVX 08055A470JAT2A
1 CT1000 pF COG/NPO 5% 50V MURATA GRM2165C1H102JA01D
1 D1 Schottky 60V 5A COMCHIP CDBC560-G
2 L1, L2 68 µH 20% 4.3A COILCRAFT DO3340P-683
2 Q1, Q2 NMOS 60V 8A VISHAY SI4436DY
1 Q3 NMOS 60V 115 mA ON-SEMI 2N7002ET1G
1 RCSH 12.4 kΩ 1% VISHAY CRCW080512K4FKEA
1 RFS 0Ω 1% VISHAY CRCW08050000OZEA
2 RHSP, RHSN 750Ω 1% VISHAY CRCW0805750RFKEA
1 RLIM 0.04Ω 1% 1W VISHAY WSL2512R0400FEA
1 ROV1 15.8 kΩ 1% VISHAY CRCW080515K8FKEA
1 ROV2 499 kΩ 1% VISHAY CRCW0805499KFKEA
2 RREF1, RREF2 49.9 kΩ 1% VISHAY CRCW080549K9FKEA
1 RSNS 0.1Ω 1% 1W VISHAY WSL2512R1000FEA
1 RT49.9 kΩ 1% VISHAY CRCW080549K9FKEA
1 RUV1 1.62 kΩ 1% VISHAY CRCW08051K62FKEA
1 RUV2 10.0 kΩ 1% VISHAY CRCW080510K0FKEA
1 RUVH 16.9 kΩ 1% VISHAY CRCW080516K9FKEA
www.national.com 46
LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
Physical Dimensions inches (millimeters) unless otherwise noted
TSSOP-16 Pin EP Package (MXA)
For Ordering, Refer to Ordering Information Table
NS Package Number MXA16A
TSSOP-20 Pin EP Package (MXA)
For Ordering, Refer to Ordering Information Table
NS Package Number MXA20A
47 www.national.com
LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0
Notes
LM3421 LM3421Q1 LM3421Q0 LM3423 LM3423Q1 LM3423Q0 N-Channel Controllers for
Constant Current LED Drivers
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