December 2009
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
SG5842A/SG5842JA • Rev. 1.4.3
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
SG5842A/SG5842JA — Highly Integrated Green-Mode
PWM Controller
Features
Green-Mode PWM Controller
Low Startup Current: 14µA
Low Operating Current: 4mA
Programmable PWM Frequency with Hopping
(SG5842JA)
Peak-Current-Mode Control
Cycle-by-Cycle Current Limiting
Synchronized Slope Compensation
Leading-Edge Blanking (LEB)
Constant Output Power Limit
Totem-Pole Output with Soft Driving
VDD Over-Voltage Protection (OVP)
Programmable Over-Temperature Protection (OTP)
Internal Latch Circuit (OTP, OVP)
Internal Open-Loop Protection
VDD Under-Voltage Lockout (UVLO)
GATE Output Maximum Voltage Clamp: 18V
Applications
General-purpose switch-mode power supplies and
flyback power converters, including:
Notebook Power Adapters
Open-Frame SMPS
Description
The highly integrated SG5842A/JA series of PWM
controllers provides several features to enhance the
performance of flyback converters. To minimize standby
power consumption, a proprietary green-mode function
provides off-time modulation to continuously decrease
the switching frequency at light-load conditions. To
avoid acoustic-noise problems, the minimum PWM
frequency set above 22KHz. This green-mode function
enables the power supply to meet international power
conservation requirements. To further reduce power
consumption, SG5842A/JA is manufactured using the
BiCMOS process. This allows a low startup current,
around 14µA, and an operating current of only 4mA. As
a result, a large startup resistance can be used.
The SG5842A/JA built-in synchronized slope
compensation achieves stable peak-current-mode
control. SG5842JA integrates a frequency-hopping
function that helps reduce EMI emission of a power
supply with minimum line filters.
SG5842A/JA provides many protection functions. In
addition to cycle-by-cycle current limiting, the internal
open-loop protection circuit ensures safety should an
open-loop or output short-circuit failure occur. PWM
output is disabled until VDD drops below the UVLO lower
limit, then the controller starts again. As long as VDD
exceeds about 24V, the internal OVP circuit is triggered.
An external NTC thermistor can be applied for over-
temperature protection.
SG5842A/JA is available in an 8-pin DIP or SOP
package.
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
SG5842A/SG582JA • Rev. 1.4.3 2
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
Ordering Information
Part Number Operating
Temperature
Range
Eco
Status Package OTP
Latch OVP
Latch Frequency
Hopping
SG5842JASZ -40°C to +105°C RoHS 8-Pin Small Outline Package (SOP) Yes Yes Yes
SG5842JADZ -40°C to +105°C RoHS 8-Pin Dual Inline Package (DIP) Yes Yes Yes
SG5842JASY -40°C to +105°C Green 8-Pin Small Outline Package (SOP) Yes Yes Yes
SG5842ASZ
(Preliminary) -40°C to +105°C RoHS 8-Pin Small Outline Package (SOP) Yes Yes No
SG5842ASY
(Preliminary) -40°C to +105°C Green 8-Pin Small Outline Package (SOP) Yes Yes No
For Fairchild’s defini t i on of Eco St atus, pleas e visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Application Diagram
Figure 1. Application Diagram
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
SG5842A/SG582JA • Rev. 1.4.3 3
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
F- Fairchild Logo
Z- Plant Code
X- 1 Digit Year Code
Y- 1 Digit week Code
TT: 2 Digits Die Run Code
T: Package Type (S=SOP, D=DIP)
P: Y: Green Package
M: Manufacture Flow Code
H: J = with Frequency Hopping
Null = without Frequency
Hopping
T: D = DIP, S = SOP
P: Z = Lead Free
Null = Regular Package
XXXXXXXX: Wafer Lot
Y: Year; WW: Week
V: Assembly Location
Block Diagram
Figure 2. Function Block Diagram
Marking Informa ti on
Figure 3. Top Mark
ZXYTT
SG5842HA
TPM
Marking for SG5842JASZ (pb-free)
Marking for SG5842JADZ (pb-free)
Marking for SG5842ASZ (pb-free)
Marking for SG5842ADZ (pb-free)
Marking for SG5842JASY (green-compound)
Marking for SG5842ASY (green-compound)
SG5842HATP
XXXXXXXXYWWV
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
SG5842A/SG582JA • Rev. 1.4.3 4
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
Pin Configuration
Figure 4. Pin Configuration
Pin Definitions
Pin # Name Description
1 GND Ground
2 FB
The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is
determined in response to the signal from this pin and the current-sense signal from Pin 6. If FB
voltage exceeds the threshold, the internal protection circuit disables PWM output after a
predetermined delay time.
3 VIN
For startup, this pin is pulled HIGH to the rectified line input via a resistor. Since the startup
current requirement is very small, a large startup resistance can be used to minimize power loss.
4 RI
A resistor connected from the RI pin to GND provides a constant current source. This determines
the center PWM frequency. Increasing the resistance reduces PWM frequency. Using a 26KΩ
resistor results in a 65KHz center PWM frequency.
5 RT
For over-temperature protection. An external NTC thermistor is connected from this pin to the
GND pin. The impedance of the NTC decreases at high temperatures. Once the voltage of the
RT pin drops below a fixed limit, PWM output is latched off.
6 SENSE
Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle
current limiting.
7 VDD Power supply. The internal protection circuit disables PWM output if VDD is over-voltage.
8 GATE The totem-pole output driver for the power MOSFET, which is internally clamped below 18V.
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
SG5842A/SG582JA • Rev. 1.4.3 5
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol Parameter Min. Max. Unit
VVDD Supply Voltage(1) 30
V
VVIN Input Terminal 30 V
VFB Input Voltage to FB Pin -0.3 7.0 V
VSENSE Input Voltage to SENSE Pin -0.3 7.0 V
VRT Input Voltage to RT Pin -0.3 7.0 V
VRI Input Voltage to RI Pin -0.3 7.0 V
PD Power Dissipation (TA < 50°C ) DIP 800 mW
SOP 400
ΘJA Thermal Resistance (Junction-to-Air) DIP 82.5 °C/W
SOP 141
TJ Operating Junction Temperature -40 +125 °C
TSTG Storage Temperature Range -55 +150 °C
TL Lead Temperature (Wave Soldering or Infrared, 10 Seconds) +260 °C
ESD Electrostatic Discharge Capability
Human Body Model,
JESD22-A114 3
KV
Charged Device
Model, JESD22-C101 1
Notes:
1. All voltage values, except differential voltage, are given with respect to GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol Parameter Min. Max. Unit
TA Operating Ambient Temperature -20 +85 °C
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
SG5842A/SG582JA • Rev. 1.4.3 6
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
Electrical Characteristics
VDD=15V and TJ=TA= -40~125°C, unless otherwise noted.
Symbol Parameter Conditions Min. Typ. Max. Units
VDD Section
VDD-OP Continuously Operating Voltage 20 V
VDD-ON Start Threshold Voltage 15.5 16.5 17.5 V
VDD-OFF Minimum Operation Voltage 9.5 10.5 11.5 V
IDD-ST Startup Current VDD=VDD-ON–0.16V 14 30 µA
IDD-OP Operating Supply Current VDD=15V, RI=26KΩ,
GATE=OPEN 4 5 mA
VDD-OVP V
DD Over-Voltage Protection 23.2 24.2 25.2 V
tD-OVP VDD Over-Voltage Protection
Debounce Time RI=26KΩ 100 µs
IDD-H Holding Current After OVP/OTP
Latchup VDD=5V 40.0 52.5 65.0 µA
RI Section
RINOR R
I Operating Range 15.5 36.0 KΩ
RIMAX Maximum RI Value for Protection 230 KΩ
RIMIN Minimum RI Value for Protection 10 KΩ
Oscillator Section
fOSC Normal PWM
Frequency
Center
Frequency RI=26KΩ 62 65 68
KHz
Hopping Range RI=26KΩ
SG5842JA Only ±3.7 ±4.2 ±4.7
tHOP Hopping Period RI=26KΩ
SG5842JA Only 3.9 4.4 4.9 ms
fOSC-G Green-Mode Minimum Frequency RI=26KΩ 18 22 25 KHz
fDV Frequency Variation vs. VDD
Deviation VDD=11.5V to 20V 5 %
fDT Frequency Variation vs.
Temperature Deviation TA=-20 to 85°C 5 %
Feedback Input Section
AV FB Input to Current Comparator
Attenuation 1/4.5 1/4.0 1/3.5 V/V
ZFB Input Impedance 4 7 KΩ
VFB-OPEN Output High Voltage FB Pin Open 5.5 V
VFB-OLP FB Open-Loop Trigger Level 5.0 5.4 V
tD-OLP FB Open-Loop Protection Delay RI=26KΩ 50 56 62 ms
VFB-N Green-Mode Entry FB Voltage RI=26KΩ 1.9 2.1 2.3 V
VFB-G Green-Mode Ending FB Voltage RI=26KΩ V
FB-N-0.5 V
Continued on the following page…
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
SG5842A/SG582JA • Rev. 1.4.3 7
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
Electrical Characteristics (Continued)
VDD= 15V and TJ=TA= -40~125°C, unless otherwise noted.
Figure 5. VFB vs. PWM Frequency
Symbol Parameter Conditions Min. Typ. Max. Units
Current Sense Section
ZSENSE Input Impedance 12 KΩ
VSTHFL Current Limit Flatten Threshold
Voltage 0.85 0.90 0.95 V
VSTHVA Current Limit Valley Threshold
Voltage VSTHFL–VSTHVA 0.22 V
DCYSAW Duty Cycle of SAW Limit Maximum Duty Cycle 45 %
tPD Propagation Delay to GATE Output RI=26KΩ 150 200 ns
tLEB Leading-Edge Blanking Time RI=26KΩ 200 270 350 ns
GATE Section
DCYMAX Maximum Duty Cycle 60 65 70 %
VGATE-L Output Voltage Low VDD=15V, IO=50mA 1.5 V
VGATE-H Output Voltage High VDD=12.5V, IO=-50mA 7.5 V
tr Rising Time VDD=15V, CL=1nF 150 250 350 ns
tf Falling Time VDD=15V, CL=1nF 30 50 90 ns
IO Peak Output Current VDD=15V, GATE=6V 230 mA
VGATE-
CLAMP Gate Output Clamping Voltage VDD=20V 18 19 V
RT Section
IRT Output Current of RT Pin RI=26KΩ 67 70 73 µA
VRTTH Over-Temperature Protection
Threshold Voltage 1.015 1.050 1.085 V
tD-OTP Over-Temperature Debounce RI=26KΩ 60 100 140 µs
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
SG5842A/SG582JA • Rev. 1.4.3 8
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
Performance Characteristics
10
14
18
22
26
30
-40 -25 -10 5 20 35 50 65 80 95 110 125
I
DD-ST
(µA)
Temperature °C
2.5
3.0
3.5
4.0
4.5
5.0
-40 -25 -10 5 20 35 50 65 80 95 110 125
I
DD-OP
(mA)
Temperature °C
Figure 6. Startup Current (IDD-ST) vs. Temperature Figure 7. Operating Supply Current (IDD-OP)
vs. Temperature
0
3
6
9
12
15
12 13 14 15 16 17 18 19 20 21 22 23 24
V
DD
Voltage (V)
IDD-OP (mA)
GATE=OPE
N
GATE=1000pF
15.5
16.0
16.5
17.0
17.5
-40 -25 -10 5 20 35 50 65 80 95 110 125
V
DD-ON
(V)
Temperature °C
Figure 8. Operation Current (IDD-OP) vs. VDD
Operation Figure 9. Start Threshold (VDD-ON) vs. Temperature
9.5
10.0
10.5
11.0
11.5
-40 -25 -10 5 20 35 50 65 80 95 110 125
V
DD-OFF
(V)
Temperature °C
62
63
64
65
66
67
68
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature °C
fOSC (Khz)
Figure 10. Minimum Operating Voltage (VDD-OFF)
vs. Temperature Figure 11. PWM Frequency (fOSC) vs. Temperature
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
SG5842A/SG582JA • Rev. 1.4.3 9
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
Performance Characteristics (Continued)
60
62
64
66
68
70
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature °C
DCY
max
(%)
1.015
1.025
1.035
1.045
1.055
1.065
1.075
1.085
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature °C
V
RTTH
(V)
Figure 12. Maximum Duty Cycle (DCYmax)
vs. Temperature Figure 13. Trigger Voltage for Over-Temperature
Protection (VRTTH) vs. Temperature
67
68
69
70
71
72
73
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature °C
I
RT
(µA)
Figure 14. Output Current of RT Pin (IRT) vs. Temperature
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
SG5842A/SG582JA • Rev. 1.4.3 10
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
Functional Description
Startup Current
The typical startup current is only 14µA, which allows a
high-resistance, low-wattage startup resistor to be used to
minimize power loss. A 1.5MΩ/0.25W startup resistor and
a 10µF/25V VDD hold-up capacitor are sufficient for an
AC/DC adapter with a universal input range.
Operating Current
The required operating current has been reduced to
4mA. This results in higher efficiency and reduces the
VDD hold-up capacitance requirement.
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to continuously decrease the PWM
frequency under light-load conditions. To avoid acoustic
noise problems, the minimum PWM frequency is set
above 22KHz. This green-mode function dramatically
reduces power consumption under light-load and zero-
load conditions. Power supplies using this controller can
meet even the strictest international standby power
regulations.
Oscillator Operation
A resistor connected from the RI pin to the GND pin
generates a constant current source for the controller.
This current is used to determine the center PWM
frequency. Increasing the resistance reduces PWM
frequency. Using a 26KΩ resistor, RI, results in a
corresponding 65KHz PWM frequency. The relationship
between RI and the switching frequency is:
(KHz)
)(KR
1690
I
PWM
fΩ
= (1)
The range of the PWM oscillation frequency is designed
as 47KHz ~ 109KHz.
SG5842JA also integrates a frequency hopping function
internally. The frequency variation ranges from around
62KHz to 68KHz for a center frequency of 65KHz. The
frequency hopping function helps reduce EMI emission
of a power supply with minimum line filters.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs at the sense resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate drive.
Under-Voltage Lockout ( UVLO )
The turn-on/turn-off thresholds are fixed internally at
16.5V/10.5V. To enable a SG5842A/JA controller during
startup, the hold-up capacitor must first be charged to
16.5V through the startup resistor.
The hold-up capacitor continues to supply VDD before
energy can be delivered from the auxiliary winding of
the main transformer. VDD must not drop below 10.5V
during this startup process. This UVLO hysteresis
window ensures that the hold-up capacitor can
adequately supply VDD during startup.
Gate Output / Soft Driving
The SG5842A/JA BiCMOS output stage is a fast totem-
pole gate driver. Cross-conduction has been avoided to
minimize heat dissipation, increase efficiency, and
enhance reliability. The output driver is clamped by an
internal 18V Zener diode to protect the power MOSFET
transistors from harmful over-voltage gate signals. A
soft-driving waveform is implemented to minimize EMI.
Slope Compensation
The sensed voltage across the current sense resistor is
used for peak-current-mode control and cycle-by-cycle
current limiting. The built-in slope compensation
function improves power supply stability and prevents
peak-current-mode control from causing sub-harmonic
oscillations. Within every switching cycle, the
SG5842A/JA controller produces a positively sloped,
synchronized ramp signal.
Constant Output Power Li mi t
When the SENSE voltage across the sense resistor,
RS, reaches the threshold voltage, around 0.85V; the
output GATE drive is turned off after a small delay, tPD.
This delay introduces additional current proportional to
tPD • VIN / LP. The delay is nearly constant regardless of
the input voltage VIN. Higher input voltage results in a
larger additional current and the output power limit is
higher than under low input line voltage. To compensate
this variation for a wide AC input range, a sawtooth
power-limiter (saw limiter) is designed to solve the
unequal power-limit problem. The saw limiter is
designed as a positive ramp signal (VLIMIT_RAMP) fed to
the inverting input of the OCP comparator. This results
in a lower current limit at high-line inputs than at low-
line inputs.
VDD Over-Voltage Protection (OVP)
VDD over-voltage protection is built in to prevent
damage due to abnormal conditions. Once the VDD
voltage is over the VDD over-voltage protection voltage
(VDD-OVP) and lasts for tD-OVP, the PWM pulse is latched
off. The PWM pulses stay latched off until the power
supply is unplugged from the mains outlet.
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
SG5842A/SG582JA • Rev. 1.4.3 11
SG5842A/SG5842JA — Highly Integrated Green-Mode PWM Controller
Functional Description (Continued)
Limited Power Control
The FB voltage increases every time the output of the
power supply is shorted or overloaded. If the FB voltage
remains higher than a built-in threshold longer than tD-
OLP, PWM output is turned off. As PWM output is turned
off, the supply voltage VDD begins decreasing.
)(K
I
R154.2
(ms)
t
OLP-D Ω×= (2)
When VDD goes below the turn-off threshold (eg.
10.5V), the controller is totally shut down. VDD is
charged up to the turn-on threshold voltage of 16.5V
through the startup resistor until PWM output is
restarted. This protection feature remains activated as
long as the overloading condition persists. This
prevents the power supply from overheating due to
overloading conditions.
Protection Lat ch Ci rcuit
The built-in latch function provides a versatile protection
feature that does not require external components (see
ordering information for a detailed description). To reset
the latch circuit, disconnect the AC line voltage of the
power supply.
Thermal Protection
An external NTC thermistor can be connected from the
RT pin to ground. A fixed current, IRT, is sourced from
the RT pin. Because the impedance of the NTC
decreases at high temperatures, when the voltage of
the RT pin drops below 1.05V, PWM output is latched
off. The RT pin output current is related to the PWM
frequency programming resistor RI.
Noise Immunit y
Noise from the current sense or the control signal may
cause significant pulse width jitter, particularly in
continuous-conduction mode. Slope compensation
helps alleviate this problem. Good placement and
layout practices should be followed. Avoid long PCB
traces and component leads. Compensation and filter
components should be located near the SG5842A/JA.
Increasing the power-MOS gate resistance is advised.
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
SG5842A/SG5842JA • Rev. 1.4.3 12
SG5842A/JA — Highly Integrated Green-Mode PWM Controller
Reference Circuit
1
2
3
CN1
R1
C2
21
+
C4
R2
R5
C3
2
1
3
4
BD1
2 1
D2
1
23
Q2
R8
GND
1
FB
2
VIN
3
RI
4RT 5
SENSE 6
VDD 7
GATE 8
U1
SG5842A/JA
12
43
U2
C6 R4
1
3
2
Q1
21
+C7
21
D4
R9
R16
R13
R15
R14
R11
C10
21
+C9
VZ1 C1
1 2
3 4
L2
C11
R7
T1
R10
THER2
R3
C5
1 2
3 4
L1
R12
21
+C8
2 1
D3
A K
R
U3 VO+
1 2
L3
TR1
D1
R6
Vo+
Figure 15. Reference Circuit
BOM
Reference Component Reference Component
BD1 BD 4A/600V Q2 MOS 7A/600V
C1 XC 0.68µF/300V R1, R2, R5, R7 R 470KΩ 1/4W
C2 XC 0.1µF/300V R3 R 100KΩ 1/2W
C3 CC 0.01µF/500V R4 R 47Ω 1/4W
C4 EC 120µ/400V R6 R 2KΩ 1/8W
C5 YC 222p/250V R8 R 0.3Ω 2W
C6 CC 1000pF/100V R9 R 33KΩ 1/8W
C7 EC 1000µF/25V R10 R 4.7KΩ 1/8W
C8 EC 470µF/25V R11 R 470Ω 1/8W
C9 EC 10µF/50V R12 R 0Ω 1/8W
C10 CC 222pF/50V R13 R 4.7KΩ 1/8W
C11 CC 470pF/50V R14 R 154KΩ 1/8W 1%
D1 LED R15
R 39KΩ 1/8W 1%
D2 Diode BYV95C R16 R 100Ωm 1/8W
D3 TVS P6KE16A THER2 Thermistor TTC104
D4 Diode FR103 T1 Transformer (600µH-PQ2620)
F1 FUSE 4A/250V U1 IC SG5842A/JA
L1 Choke (900µH) U2 IC PC817
L2 Choke (10mH) U3 IC TL431
L3 Inductor (2µH) VZ1 VZ 9G
Q1 Diode 20A/100V
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
SG5842A/SG5842JA • Rev. 1.4.3 13
SG5842A/JA — Highly Integrated Green-Mode PWM Controller
Physical Dimensions
8°
0°
SEE DETAIL A
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
LAND PATTERN RECOMMENDATION
SEATING PLANE
0.10 C
C
GAGE PLANE
x 45°
DETAIL A
SCALE: 2:1
PIN ONE
INDICATOR
4
8
1
C
MBA0.25
B
5
A
5.60
0.65
1.75
1.27
6.20
5.80
3.81
4.00
3.80
5.00
4.80
(0.33)
1.27
0.51
0.33
0.25
0.10
1.75 MAX
0.25
0.19
0.36
0.50
0.25
R0.10
R0.10
0.90
0.406 (1.04)
OPTION A - BEVEL EDGE
OPTION B - NO BEVEL EDGE
Figure 16. 8-Pin, Small Outline Package (SOP)
Pack age drawings are provided as a service to customers consideri ng Fai rchild components . Drawings may c hange i n any manner
without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emiconductor represent ative to v er ify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
SG5842A/SG5842JA • Rev. 1.4.3 14
SG5842A/JA — Highly Integrated Green-Mode PWM Controller
Physical Dimensions (Continued)
5.08 MAX
0.33 MIN
2.54
7.62
0.56
0.355
1.65
1.27
3.683
3.20
3.60
3.00
6.67
6.096
9.83
9.00
7.62
9.957
7.87
0.356
0.20
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5M-1994
8.255
7.61
E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.
(0.56)
Figure 17. 8-Pin, Dual Inline Package (DIP)
Pack age drawings are provided as a service to customers consideri ng Fai rchild components . Drawings may c hange i n any manner
without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emiconductor represent ative to v er ify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com
SG5842A/SG5842JA • Rev. 1.4.3 15
SG5842A/JA — Highly Integrated Green-Mode PWM Controller
