© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 9 1Publication Order Number:
MC14049B/D
MC14049B, MC14050B
Hex Buffer
The MC14049B Hex Inverter/Buffer and MC14050B Noninverting
Hex Buffer are constructed with MOS P−Channel and N−Channel
enhancement mode devices in a single monolithic structure. These
complementary MOS devices find primary use where low power
dissipation and/or high noise immunity is desired. These devices
provide logic level conversion using only one supply voltage, VDD.
The input−signal high level (VIH) can exceed the VDD supply
voltage for logic level conversions. Two TTL/DTL loads can be driven
when the devices are used as a CMOS−to−TTL/DTL converter
(VDD = 5.0 V, VOL ≤ 0.4 V, IOL ≥ 3.2 mA).
Note that pins 13 and 16 are not connected internally on these
devices; consequently connections to these terminals will not affect
circuit operation.
Features
•High Source and Sink Currents
•High−to−Low Level Converter
•Supply Voltage Range = 3.0 V to 18 V
•VIN can exceed VDD
•Meets JEDEC B Specifications
•Improved ESD Protection On All Inputs
•NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol Parameter Value Unit
VDD DC Supply Voltage Range −0.5 to +18.0 V
Vin Input Voltage Range (DC or Transient) −0.5 to +18.0 V
Vout Output Voltage Range (DC or Transient) −0.5 to VDD +
0.5 V
Iin Input Current (DC or Transient) per Pin ±10 mA
Iout Output Current (DC or Transient) per Pin ±45 mA
PDPower Dissipation, per Package (Note 1)
(Plastic)
(SOIC) 825
740
mW
TAAmbient Temperature Range −55 to +125 °C
Tstg Storage Temperature Range −65 to +150 °C
TLLead Temperature (8−Second Soldering) 260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be af fected.
1. Temperature Derating: See Figure 3.
This device contains protection circuitry to protect the inputs against damage
due to high static voltages or electric fields referenced to the VSS pin only. Extra
precautions must be taken to avoid applications of any voltage higher than the
maximum rated voltages to this high−impedance circuit. For proper operation, the
ranges VSS ≤ Vin ≤ 18 V and VSS ≤ Vout ≤ VDD are recommended.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
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MARKING DIAGRAMS
SOIC−16
TSSOP−16
140xxBG
AWLYWW
14
050B
ALYWG
G
xx = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G= Pb−Free Indicator
SOEIAJ−16
MC140xxB
ALYWG
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
1
16
1
16
1
16
(Note: Microdot may be in either location)
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
SOEIAJ−16
F SUFFIX
CASE 966
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
OUTE
NC
INF
OUTF
NC
IND
OUTD
INE
OUTB
INA
OUTA
VDD
VSS
INC
OUTC
INB
MC14049B, MC14050B
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2
LOGIC DIAGRAM
MC14049B
14 15
11
9
7
5
3
12
10
6
4
2
NC = PIN 13, 16
VSS = PIN 8
VDD = PIN 1
MC14050B
14 15
11
9
7
5
3
12
10
6
4
2
NC = PIN 13, 16
VSS = PIN 8
VDD = PIN 1
ORDERING INFORMATION
Device Package Shipping†
MC14049BDG SOIC−16
(Pb−Free) 48 Units / Rail
MC14049BDR2G SOIC−16
(Pb−Free) 2500 Units / Tape & Reel
NLV14049BDR2G* SOIC−16
(Pb−Free) 2500 Units / Tape & Reel
MC14049BFELG SOEIAJ−16
(Pb−Free) 2000 Units / Tape & Reel
MC14050BDG SOIC−16
(Pb−Free) 48 Units / Rail
NLV14050BDG* SOIC−16
(Pb−Free) 48 Units / Rail
MC14050BDR2G SOIC−16
(Pb−Free) 2500 Units / Tape & Reel
NLV14050BDR2G* SOIC−16
(Pb−Free) 2500 Units / Tape & Reel
MC14050BDTG TSSOP−16
(Pb−Free) 96 Units / Rail
NLV14050BDTG* TSSOP−16
(Pb−Free) 96 Units / Rail
MC14050BDTR2G TSSOP−16
(Pb−Free) 2500 Units / Tape & Reel
MC14050BFELG SOEIAJ−16
(Pb−Free) 2000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
MC14049B, MC14050B
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3
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbo
l
VDD
Vdc
–55_C +25_C +125_C
Unit
Min Max Min Typ
(Note 2) Max Min Max
Output Voltage “0” Leve
l
Vin = VDD
“1” Leve
l
Vin = 0
VOL 5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
VOH 5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
Input Voltage “0” Leve
l
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
“1” Leve
l
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)
VIL 5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
Vdc
VIH 5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc) Sin
k
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOH 5.0
10
15
–1.6
–1.6
–4.7
−
−
−
–1.25
–1.30
–3.75
–2.5
–2.6
–10
−
−
−
–1.0
–1.0
–3.0
−
−
−
mAdc
IOL 5.0
10
15
3.75
10
30
−
−
−
3.2
8.0
24
6.0
16
40
−
−
−
2.6
6.6
19
−
−
−
mAdc
Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc
Input Capacitance (Vin = 0) Cin − − − − 10 20 − − pF
Quiescent Current (Per Package) IDD 5.0
10
15
−
−
−
1.0
2.0
4.0
−
−
−
0.002
0.004
0.006
1.0
2.0
4.0
−
−
−
30
60
120
mAdc
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
per package)
(CL = 50 pF on all outputs, all
buffers switching
IT5.0
10
15
IT = (1.8 mA/kHz) f + IDD
IT = (3.5 mA/kHz) f + IDD
IT = (5.3 mA/kHz) f + IDD
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at +25_C
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL − 50) Vfk
Where: IT is in mA (per Package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency and k = 0.002.
MC14049B, MC14050B
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4
AC SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = + 25_C)
Characteristic Symbol VDD
Vdc Min Typ
(Note 6) Max Unit
Output Rise Time
tTLH = (0.7 ns/pF) CL + 65 ns
tTLH = (0.25 ns/pF) CL + 37.5 ns
tTLH = (0.2 ns/pF) CL + 30 ns
tTLH 5.0
10
15
−
−
−
100
50
40
160
80
60
ns
Output Fall Time
tTHL = (0.2 ns/pF) CL + 30 ns
tTHL = (0.06 ns/pF) CL + 17 ns
tTHL = (0.04 ns/pF) CL + 13 ns
tTHL 5.0
10
15
−
−
−
40
20
15
60
40
30
ns
Propagation Delay Time
tPLH = (0.33 ns/pF) CL + 63.5 ns
tPLH = (0.19 ns/pF) CL + 30.5 ns
tPLH = (0.06 ns/pF) CL + 27 ns
tPLH 5.0
10
15
−
−
−
80
40
30
140
80
60
ns
Propagation Delay Time
tPHL = (0.2 ns/pF) CL + 30 ns
tPHL = (0.1 ns/pF) CL + 15 ns
tPHL = (0.05 ns/pF) CL + 12.5 ns
tPHL 5.0
10
15
−
−
−
40
20
15
80
40
30
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Typical Output Source Characteristics Figure 2. Typical Output Sink Characteristics
MC14049B MC14050B MC14049B MC14050B
VDD
VSS
VDD
VSS
1
8
1
8
IOL
IOH VOH VOL
VDS = VOH - VDD
VDD
VSS
1
8
IOL VOL
VDD
VSS
1
8
IOH VOH
VDD = VOL
IOH, OUTPUT SOURCE CURRNT (mAdc)
IOL, OUTPUT SINK CURRENT (mAdc)
-50
-40
-30
-20
-10
0
-10 -8.0 -6.0 -4.0 -2.0 0
VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)
VGS = 5.0 Vdc
VGS = 10 Vdc
MAXIMUM CURRENT LEVEL
VGS = 15 Vdc
160
120
80
40
00 2.0 4.0 6.0 8.0 10
VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)
VGS = 15 Vdc
VGS = 10 Vdc
MAXIMUM CURRENT LEVEL
VGS = 5.0 Vdc
MC14049B, MC14050B
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5
Figure 3. Ambient Temperature Power Derating
PD, MAXIMUM POWER DISSIPATION (mW)
PER PACKAGE
1200
1100
1000
900
825
800
740
700
600
500
400
300
200
100
0175150125100755025
TA, AMBIENT TEMPERATURE (°C)
175 mW (P)
120 mW (D)
(P) PDIP
(D) SOIC
tPHL
Figure 4. Switching Time Test Circuit and Waveforms
PULSE
GENERATOR
VDD
VSS
8
1
CL
Vout
Vin
#
#Invert on MC14049B only
20 ns 20 ns
VDD
VSS
VOH
VOL
VOH
VOL
90%
50%
10%
90%
50%
10%
90%
50%
10%
tPLH
tTLH
tPHL
tTHL
tPHL
tPLH
tTLH tTHL
OUTPUT
MC14049B
OUTPUT
MC14050B
INPUT
MC14049B, MC14050B
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6
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
16
89
8X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
MC14049B, MC14050B
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7
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F
ISSUE B
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
ÇÇÇ
ÇÇÇ
ÇÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
MC14049B, MC14050B
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8
PACKAGE DIMENSIONS
SOEIAJ−16
F SUFFIX
CASE 966
ISSUE A
HE
A1
DIM MIN MAX MIN MAX
INCHES
--- 2.05 --- 0.081
MILLIMETERS
0.05 0.20 0.002 0.008
0.35 0.50 0.014 0.020
0.10 0.20 0.007 0.011
9.90 10.50 0.390 0.413
5.10 5.45 0.201 0.215
1.27 BSC 0.050 BSC
7.40 8.20 0.291 0.323
0.50 0.85 0.020 0.033
1.10 1.50 0.043 0.059
0
0.70 0.90 0.028 0.035
--- 0.78 --- 0.031
A1
HE
Q1
LE
_10 _0
_10 _
LEQ1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005) 0.10 (0.004)
1
16 9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
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P
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Phone: 81−3−5817−1050
MC14049B/D
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