General Description
The MAX9691/MAX9692/MAX9693 are ultra-fast ECL
comparators capable of very short propagation delays.
Their design maintains the excellent DC matching char-
acteristics normally found only in slower comparators.
The MAX9691/MAX9692/MAX9693 have differential
inputs and complementary outputs that are fully com-
patible with ECL-logic levels. Output current levels are
capable of driving 50Ωterminated transmission lines.
The ultra-fast operation makes signal processing possi-
ble at frequencies in excess of 600MHz.
The MAX9692/MAX9693 feature a latch-enable (LE)
function that allows the comparator to be used in a
sample-hold mode. When LE is ECL high, the compara-
tor functions normally. When LE is driven ECL low, the
outputs are forced to an unambiguous ECL-logic state,
dependent on the input conditions at the time of the
latch input transition. If the latch-enable function is not
used on either of the two comparators, the appropriate
LE input must be connected to ground; the companion
LE input must be connected to a high ECL logic level.
These devices are available in SO, QSOP, and tiny
µMAX®packages for added space savings.
________________________Applications
High-Speed Line Receivers
Peak Detectors
Threshold Detectors
High-Speed Triggers
Features
o1.2ns Propagation Delay
o100ps Propagation Delay Skew
o150ps Dispersion
o0.5ns Latch Setup Time
o0.5ns Latch-Enable Pulse Width
oAvailable in µMAX and QSOP Packages
o+5V, -5.2V Power Supplies
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
________________________________________________________________
Maxim Integrated Products
1
IN+
RLRL
IN-
VT
Q OUT
Q OUT
MAX9691
NONINVERTING
INPUT
RLRL
VT
INVERTING
INPUT
NONINVERTING
INPUT
INVERTING
INPUT
Q OUT
Q OUT
RLRL
LATCH ENABLE
THE OUTPUTS ARE OPEN EMITTERS, REQUIRING EXTERNAL PULLDOWN
RESISTORS. THESE RESISTORS MAY BE IN THE RANGE OF 50Ω TO 200Ω
CONNECTED TO -2.0V, OR 240Ω TO 2000Ω CONNECTED TO -5.2V.
MAX9693 MAX9693
LE LE
LATCH ENABLE
LE LE
_________________________________________________________
Functional Diagrams
19-1789; Rev 2; 1/12
Ordering Information
Ordering Information continued at the end of data sheet.
Pin Configurations appear at end of data sheet.
PART TEMP
RANGE PIN-PACKAGE
MAX9691EUA -40°C to +85°C 8 µMAX
MAX9691ESA -40°C to +85°C 8 SO
MAX9691EPA -40°C to +85°C 8 PDIP
Selector Guide
PART COMPARATORS
PER PACKAGE
LATCH
ENABLE
PIN-
PACKAGE
MAX9691 1 No 8 µMAX,
8 SO, 8 PDIP
MAX9692 1 Yes 10 µMAX,
16 SO, 16 PDIP
MAX9693 2 Yes
16 QSOP,
16 SO, 16 PDIP
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Note: Devices are also available in lead(Pb)-free/RoHS-compli-
ant packages. Specify lead-free by adding a “+” after the part
number.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC = +5V, VEE = -5.2V, RL= 50Ωto VT, VT= -2V, LE = 0, TA= TMIN to TMAX, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage (VCC) ...............................................-0.3V to +6V
Supply Voltage (VEE)................................................-6V to +0.3V
Input Voltage....................................(VCC + 0.3V) to (VEE - 0.3V)
Output Short-Circuit Duration ....................................Continuous
Differential Input Voltage ......................................................±5V
Latch Enable ...............................................(VEE - 0.3V) to +0.3V
Output Current ....................................................................50mA
Input Current ....................................................................±25mA
Continuous Power Dissipation (TA= +70°C)
8-Pin µMAX (derate 4.8mW/°C above 70°C)...............387.8mW
8-Pin SO (derate 7.4mW/°C above +70°C)..................588.2mW
8-Pin PDIP (derate 9.1mW/°C above +70°C) ...........727.3mW
10-Pin µMAX (derate 8.8mW/°C above +70°C) ...........707.3mW
16-Pin QSOP (derate 9.6mW/°C above +70°C) .........771.5mW
16-Pin SO (derate 13.3mW/°C above +70°C) ..........1066.7mW
16-Pin PDIP (derate 10.5mW/°C above +70°C) .......842.1mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TA = +25°C -6.5 6.5
Input Offset Voltage VOS TA = TMIN to TMAX -11.5 +11.5 mV
Temperature Coefficient ∆VOS/∆T 10 µV/°C
TA = +25°C 0.2 5
Input Offset Current IOS TA = TMIN to TMAX 8µA
TA = +25°C620
Input Bias Current IBTA = TMIN to TMAX 30 µA
Input Voltage Range VCM Note 1 -2.5 +3.0 V
Common-Mode Rejection Ratio CMRR -2.5V ≤ VCM ≤ +3.0V (Note 1) 60 80 dB
Positive Power-Supply Rejection
Ratio +PSRR 4.5V ≤ VCC ≤ 5.5V 60 dB
Negative Power-Supply
Rejection Ratio -PSRR -5.7V ≤ VEE ≤ -4.7V 60 dB
Open-Loop Gain AOL VCM = 0V 70 dB
Differential Input Resistance RIN -10mV < VIN < 10mV 60 kΩ
Differential Input Clamp Voltage 1.7 V
Input Capacitance CIN 3pF
Latch Enable Input Current High IIH(LE) VIH(LE) = 1.1V 60 120 µA
Latch Enable Input Current Low IIL(LE) VIL(LE) = 1.5V 0.2 10 µA
Latch E nab l e Log i c H i g h V ol tag eV
IH
(
LE
)
-1.1 V
Latch Enable Logic Low Voltage VIL
(
LE
)
-1.5 V
TA = TMIN -1.2 -0.87
TA = TMAX -0.99 -0.70Logic Output High Voltage VOH
TA = +25°C -1.06 -0.76
V
TA = TMIN -1.93 -1.57
TA = TMAX -1.89 -1.51
Logic Output Low Voltage VOL TA = +25°C -1.89 -1.55 V
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5V, VEE = -5.2V, RL= 50Ωto VT, VT= -2V, LE = 0, TA= TMIN to TMAX, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TA = +25°C 34 46
MAX9693 TA = TMIN to TMAX 50
TA = +25°C 18 26
Supply Current ICC MAX9691/
MAX9692 TA = TMIN to TMAX 36
mA
Note 1: Guaranteed by design.
Note 2: VIN = 100mV, VOD = 10mV.
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V, VEE = -5.2V, RL= 50Ωto VT, VT= -2V, LE = 0, TA= TMIN to TMAX, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX9691/MAX9692/MAX9693
TA = +25°C 1.2 1.8
Propagation Delay (Notes 1, 2) t
p
d+, t
p
d- TA = TMIN to TMAX 2.0 ns
Rise/Fall Time tr, tf10% to 90% 500 ps
Propagation Delay Skew ∆PD 100 ps
Dispersion PDSP VOD from 10mV to 100mV 150 ps
MAX9692/MAX9693
TA = +25°C 1.0 1.8
Latch-Enable Time (Note 1) TLE(±) TA = TMIN to TMAX 2.0 ns
Latch- Enab le P ul se Wi d th (N ote 1) t
p
w
(
LE
)
0.5 1.0 ns
Setup Time (Note 1) ts0.5 1.0 ns
Hold Time (Note 1) th0.5 1.0 ns
Channel-to-Channel
Propagation Match tPDM Note 2 (MAX9693 only) 100 ps
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
4 _______________________________________________________________________________________
400
600
800
1000
1200
1400
0405020 3010 60 70 80 90 100
WORST-CASE PROPAGATION DELAY
vs. INPUT OVERDRIVE
MAX9691/3-01
INPUT OVERDRIVE (mV)
PROPAGATION DELAY (ps)
0
3000
2000
1000
4000
5000
6000
0 20015050 100 250 300 350 400 450 500
WORST-CASE PROPAGATION DELAY
vs. SOURCE IMPEDANCE
MAX9691/3-02
SOURCE IMPEDANCE (Ω)
PROPAGATION DELAY (ps)
600
1000
800
1400
1200
1600
1800
0105 152025
WORST-CASE PROPAGATION DELAY
vs. CLOAD
MAX9691/3-03
CLOAD (pF)
PROPAGATION DELAY (ps)
600
700
800
900
1000
1100
1200
1300
1400
-40 -15 10 35 60 85
WORST-CASE PROPAGATION DELAY
vs. TEMPERATURE
MAX9691/3-04
TEMPERATURE (°C)
PROPAGATION DELAY (ps)
VOD = 100mV
-1.1
-1.0
-0.8
-0.9
-0.7
-0.6
-40 10-15 35 60 85
OUTPUT HIGH VOLTAGE
vs. TEMPERATURE
MAX9691/3-05
TEMPERATURE (°C)
VOH (V)
RPULLDOWN = 200Ω
RPULLDOWN = 100Ω
RPULLDOWN = 50Ω
-1.80
-1.74
-1.76
-1.78
-1.72
-1.70
-1.68
-1.66
-1.64
-1.62
-1.60
-40 10-15 35 60 85
OUTPUT LOW VOLTAGE
vs. TEMPERATURE
MAX9691/3-06
TEMPERATURE (°C)
VOL (V)
RPULLDOWN = 200Ω
RPULLDOWN = 100Ω
RPULLDOWN = 50Ω
-2000
-1500
-1000
-500
0
500
1000
1500
2000
-40 -15 10 35 60 85
INPUT OFFSET VOLTAGE
vs. TEMPERATURE
MAX9691/3-08
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE (µV)
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
-40 -15 10 35 60 85
INPUT BIAS CURRENT
vs. TEMPERATURE
MAX9691/3-09
TEMPERATURE (°C)
INPUT BIAS CURRENT (µA)
Typical Operating Characteristics
(VCC = +5V, VEE = -5.2V, RL= 50Ωto VT, VT= -2V, VOD = 10mV, TA= +25°C, unless otherwise noted.)
-5000
-3000
-4000
-1000
-2000
1000
0
2000
4000
3000
5000
-5 -3 -2 -1-4 012 435
INPUT BIAS CURRENT
vs. DIFFERENTIAL INPUT VOLTAGE
MAX9691/3-10
DIFFERENTIAL INPUT VOLTAGE (V)
INPUT BIAS CURRENT (µA)
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
_______________________________________________________________________________________
5
Typical Operating Characteristics (continued)
(VCC = +5V, VEE = -5.2V, RL= 50Ωto VT, VT= -2V, VOD = 10mV, TA= +25°C, unless otherwise noted.)
PROPAGATION DELAY
MAX9691/3-11
VIN
200mV/div
1ns/div
Q OUT - Q OUT
200mV/div
VIN = 100mV
VOD = 10mV
100MHz OUTPUT RESPONSE
MAX9691/3-12
-1.0V
Q OUT
200mV/div
Q OUT
200mV/div
-1.8V
-1.8V
-1.0V
1ns/div
Pin Description
PIN
MAX9691 MAX9692
µMAX
MAX9692
PDIP/SO MAX9693 NAME FUNCTION
11211V
CC Positive Supply. Bypass to GND with a 0.1µF capacitor.
2 2 3 — IN+ Positive Input
3 3 4 — IN- Negative Input
4686V
EE Negative Supply. Bypass to GND with a 0.1µF capacitor.
5 7 11 — Q OUT Output
6 8 12 — Q OUT Complimentary Output
7 9 16 — GND2 Device Ground
8 10 1 — GND1 Device Ground
—4
5, 7, 9, 10,
13, 14, 15 — N.C. No Connection. Not internally connected.
— 5 6 — LE Latch Enable Input
— — — 1 Q OUTA Channel A Output
——— 2Q OUTA Channel A Complementary Output
— — — 3, 14 GND Device Ground
— — — 4 LEA Channel A Latch Enable Input
——— 5LEA Channel A Latch Enable Complementary Input
— — — 7 INA- Channel A Negative Input
— — — 8 INA+ Channel A Positive Input
— — — 9 INB+ Channel B Positive Input
— — — 10 INB- Channel B Negative Input
———12LEB Channel B Latch Enable Complementary Input
— — — 13 LEB Channel B Latch Enable Input
———15Q OUTB Channel B Complementary Output
— — — 16 Q OUTB Channel B Output
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
6 _______________________________________________________________________________________
__________ Applications Information
Layout
Because of the MAX9691/MAX9692/MAX9693s’ large
gain-bandwidth characteristic, special precautions
must be taken to use them. A PC board with a ground
plane is mandatory. Mount 0.01µF ceramic decoupling
capacitors as close to the power-supply pins as possi-
ble, and process the ECL outputs in microstrip fashion,
consistent with the load termination of 50Ωto 200Ω(for
VT = -2V). For low-impedance applications, microstrip
layout and terminations at the input may also be help-
ful. Pay close attention to the bandwidth of the decou-
pling and terminating components. Chip components
can be used to minimize lead inductance. Connect
GND1 and GND2 together to a solid copper ground
plane for the MAX9691/MAX9692. GND1 biases the
input gain stages, while GND2 biases the ECL output
stage. If the LE function is not used, connect the LE pin
to GND (MAX9692/MAX9693) and the complementary
LE to ECL logic high level (MAX9693 only). Do not
leave the inputs of an unused comparator floating for
the MAX9693.
Input Slew-Rate Requirements
As with all high-speed comparators, the high gain-
bandwidth product of these devices creates oscillation
problems when the input goes through the linear
region. For clean switching without oscillation or steps
in the output waveform, the input must meet certain
minimum slew-rate requirements. The tendency of the
part to oscillate is a function of the layout and source
impedance of the circuit employed. Poor layout and
larger source impedance will increase the minimum
slew-rate requirement.
Figure 1 shows a high-speed receiver application with
50Ωinput and output termination. With this configura-
tion, in which a ground plane and microstrip PC board
are used, the minimum slew rate for clean output
switching is 1V/µs.
In many applications, adding regenerative feedback
will assist the input signal through the linear region,
which will lower the minimum slew-rate requirement
considerably. For example, with the addition of positive
feedback components, Rf = 1kΩand Cf = 10pF, the
minimum slew-rate requirement can be reduced by a
factor of four.
As high-speed receivers, the MAX9691/MAX9692/
MAX9693 are capable of processing signals in excess
of 600MHz. Figure 2 is a 100MHz example with an
input signal level of 14mVRMS.
VIN
-2V
50Ω
Cf
Rf50Ω
50Ω
50Ω
Q
Q
LE
Figure 1. Regenerative Feedback—High-Speed Receiver with
50
Ω
Input and Output Termination
0V
-0.9V
-1.7V
OUTPUT
500mV/div
INPUT
20mV/div
2ns/div
Figure 2. Signal Processed at 100MHz with Input Signal Level
of 14mVRMS
MAX9691/MAX9692/MAX9693
The timing diagram (Figure 3) illustrates the series of
events that complete the compare function, under
worst-case conditions. The top line of the diagram illus-
trates two latch-enable pulses. Each pulse is high for
the compare function and low for the latch function. The
first pulse demonstrates the compare function; part of
the input action takes place during the compare mode.
The second pulse demonstrates a compare function
interval during which there is no change in the input.
The leading edge of the input signal (illustrated as a
large-amplitude, small-overdrive pulse) switches the
comparator after time interval tpd. Output Q and Qtran-
sistors are similar in timing. The input signal must occur
at time tsbefore the latch falling edge, and must be
maintained for time thafter the edge to be acquired.
After th, the output is no longer affected by the input sta-
tus until the latch is again strobed. A minimum latch
pulse width of tpw(LE) is needed for the strobe opera-
tion, and the output transitions occur after a time tLE(±).
The MAX9691/MAX9692/MAX9693 will not false trip
(i.e., output invert) if one of the inputs is in the valid
common-mode range while the other input is outside
the common-mode range.
LATCH
ENABLE
DIFFERENTIAL
INPUT
VOLTAGE
Q
Q
LATCH
COMPARE
ts
th
VOD
VIN
tLE(+)
VOS
50%
50%
50%
tpw(LE)
tpd
Figure 3. Timing Diagram
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
_______________________________________________________________________________________ 7
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
8 _______________________________________________________________________________________
Definition of Terms
VOS Input Offset Voltage. The voltage required
between the input terminals to obtain 0V dif-
ferential at the output.
VIN Input Voltage Pulse Amplitude
VOD Input Voltage Overdrive
tpd+ Input to Output High Delay. The propagation
delay measured from the time the input signal
crosses the input offset voltage to the 50%
point of an output low-to-high transition.
tpd- Input to Output Low Delay. The propagation
delay measured from the time the input signal
crosses the input offset voltage to the 50%
point of an output high-to-low transition.
tLE(+) Latch-Enable to Output High Delay. The prop-
agation delay measured from the 50% point of
the latch-enable signal low-to-high transition
to the 50% point of an output low-to-high tran-
sition.
tLE(-) Latch-Enable to Output Low Delay. The prop-
agation delay measured from the 50% point of
the latch-enable signal low-to-high transition
to the 50% point of an output high-to-low tran-
sition.
tpw(LE) Latch-Enable Pulse Width. The minimum time
the latch-enable signal must be high to acquire
and hold an input signal.
tsSetup Time. The minimum time before the
negative transition of the latch-enable pulse
that an input signal must be present to be ac-
quired and held at the outputs.
thHold Time. The minimum time after the nega-
tive transition of the latch-enable signal that
an input signal must remain unchanged to be
acquired and held at the output.
∆pd Propagation Delay Skew. The difference in
propagation delay between the Q and Qout-
puts crossing each other in both directions.
PDSP Propagation Delay Dispersion. The change in
propagation delay as a result of the overdrive
of the input signal varying.
tpdm Propagation Delay Match (MAX9693 only).
The difference in propagation delay between
two separate channels.
PART TEMP
RANGE
PIN-PACKAGE
MAX9692EUB -40°C to +85°C 10 µMAX
MAX9692ESE -40°C to +85°C 16 Narrow SO
MAX9692EPE -40°C to +85°C 16 PDIP
MAX9693ESE -40°C to +85°C 16 Narrow SO
MAX9693EEE -40°C to +85°C 16 QSOP
MAX9693EPE -40°C to +85°C 16 PDIP
Ordering Information (continued)Chip Information
PROCESS: BiCMOS
Note: Devices are also available in lead(Pb)-free/RoHS-compli-
ant packages. Specify lead-free by adding a “+” after the part
number.
MAX9691/MAX9692/MAX9693
Pin Configurations
DIP/SO/µMAX
MAX9691
Q OUT
Q OUTVEE
1
2
8
7
GND1
GND2IN+
IN-
VCC
3
4
6
5
TOP VIEW
µMAX
MAX9692
1
2
3
4
5
10
9
8
7
6
GND1
GND2
Q OUT
Q OUTN.C.
IN-
IN+
VCC
VEE
LE
PDIP/SO
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
GND1 GND2
N.C.
N.C.
N.C.
Q OUT
N.C.
N.C.
VCC
IN+
LE
IN-
N.C.
N.C.
VEE
MAX9692 MAX9693
DIP/SO/QSOP
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Q OUTA Q OUTB
Q OUTB
GND
LEB
LEB
VCC
INB-
INB+
Q OUTA
GND
VEE
LEA
LEA
INA-
INA+
Q OUT
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
_______________________________________________________________________________________ 9
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or
"-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND
PATTERN NO.
8 µMAX U8+1 21-0036 90-0092
8 SO S8+2 21-0041 90-0096
8 PDIP P8+5 21-0043 —
10 µMAX U10+2 21-0061 90-0330
16 QSOP E16+1 21-0055 90-0167
16 SO S16+3 21-0041 90-0097
16 PDIP P16+1 21-0043 —
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
10 ______________________________________________________________________________________
α
α
D
D
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or
"-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
MAX9691/MAX9692/MAX9693
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or
"-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
______________________________________________________________________________________ 11
MAX9691/MAX9692/MAX9693
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
12
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 8/00 Initial release —
1 10/02 Updated Ordering Information. 7
2 1/12 Revised Ordering Information, Absolute Maximum Ratings, and Pin Description. 1, 2, 5, 7
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Maxim Integrated:
MAX9692EPE+ MAX9691EPA+ MAX9691ESA+ MAX9691ESA+T MAX9691EUA+ MAX9691EUA+T
MAX9692EPE MAX9692ESE MAX9692ESE+ MAX9692ESE+T MAX9692EUB+ MAX9692EUB+T MAX9693EEE+
MAX9693EEE+T MAX9693EPE MAX9693EPE+ MAX9693ESE MAX9693ESE+ MAX9693ESE+T MAX9691EPA
MAX9691ESA MAX9691ESA-T MAX9691EUA MAX9691EUA-T MAX9692ESE-T MAX9693EEE MAX9693EEE-T
MAX9693ESE-T
