Intel® IXF1104 4-Port Gigabit Ethernet
Media Access Controller
Datasheet
The Intel® IXF1104 4-Port Giga bit Ethernet Media Ac cess Controller (hereafter referred to as
the IXF1104 MAC) supp orts IEEE 802.3* 10/100/1000 Mbps a pplications. The IXF1104 MAC
supports a System Packet Interface Phase 3 (SPI3) syste m interface to a network processor or
ASIC, and concurrently support s c opper and fib er physical layer devic es (P HYs).
The copper PHY interface supports the standard and reduc ed pin-count Gigabit Media
Indepen dent Interface (GMII and RGMII) for high -port-cou nt app lic atio ns. For fiber
applications the in tegr ated Serializer/Deserializer (S erDes) on each port sup p o rts di rect
connec tion to optical modules to reduce PCB ar ea requirements and system cost .
Produ ct Features
Applications
Four Independe nt Ethernet MAC Ports fo r
Copper or Fiber Physical layer con nectivity.
—IEEE 802.3 compliant
—Independent Enable/Disable of any po rt
Copper Mode:
—RGMII for 10/100/1000 Mbps li nks
—GMII for 1000 Mbps full-duplex links
—IEEE 802.3 MDIO interface
Fiber Mode:
—In tegrated SerDes int erface for direct
connection to 1000BASE-X optica l modules
—IEEE 802.3 auto-negotiation or forced mode
—Supports SFP MSA-compatible transceivers
SPI3 interface supports data transfers up to
4 Gbps in both modes:
—32-bit Multi-PHY mode (133 MHz)
—4 x 8-bit Single-PHY mode (125 MHz)
IEEE 802.3-compliant Flow Control
—Loss-less up to 9.6 KB packets and 5 km links
—Jumbo frame support for 9.6 KB packets
Internal per-channel FIFOs: 32 KB Rx, 10 KB Tx
Flexible 32/16/ 8-bit CPU interface
Programmable Packet handling
—Filter b roadcast, multicast, uni cast, VLAN
and errored packets
—Automaticall y pad undersized Tx packets
—Rem ove CRC fr om Rx packets
Performance Monitoring and Diagnosti cs
— RMON Statistics
—CRC ca lculation and error det ection
—Dete ction of length error, ru nt, or overly
large packets
—Count ers for dropped and errored pac k ets
—Loopback modes
—JTAG boundary scan
.18 μ CMOS process technology
— 1.8 V core, 2.5 V RGMII, GMII, OMI, and
3.3 V SPI3 and CPU
Ope rat ing Te m p eratur e Ran ge s:
—Copper Mode: -40°C to +85°C
—Fiber Mode: 0°C to +70°C
Pac kag e O p tio n s:
—552-ball Ceramic BG A (standard)
—
552-ball Ceramic BGA
(RoHS-c o m p liant)
—552-ball Pl astic FC-BG A
(contact your Intel
Sales Representative)
Load Bal ancing Systems
MultiService Switches
Web Caching Appliances
Intelligent Backplane Interfaces
Edge Routers
Redundant Line Cards
Base Station Controll ers and Transceivers
Serving GPRS Support Nodes (SGSN)
Gate way GPRS Sup por t Nodes (GGSN)
Packe t Data Serving Nodes (PDSN)
DSL Access Multiplexers (DSLAM)
Cable Mo dem Termination Systems (CMTS)
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
2Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHA TSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULA R PURPOSE , MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or sa f et y sy ste ms, or
in nuclear facility appl icatio ns.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The IXF1104 MAC Media Access Controller may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2005, Intel Corporation
Contents
Datasheet 3
Document Number: 278757
Re vision N umber: 009
Re vision D ate: 27-Oct-2005
Contents
1.0 Introduction..................................................................................................................................20
1.1 What You Will Find in This Document................................................................................20
1.2 Related Documents............................................................................................................20
2.0 General Description ....................................................................................................................21
3.0 Ball Assignments and Ball List Tables......................................................................................23
3.1 Ball Assignments ................................................................................................................23
3.2 Ball List Tables ...................................................................................................................24
3.2.1 Balls Listed in Alphabetic Order by Signal Name ............... ......... ....... ............ .......24
3.2.2 Balls Listed in Alphabetic Order by Ball Location ................. ....... ................... .......30
4.0 Ball Assignm ents and Sign al Descrip tions ..............................................................................37
4.1 Naming Conventions ..........................................................................................................37
4.1.1 Signal Name Conventions ................................. ....... ............ ....... ....... ............ .......37
4.1.2 Regi ste r Ad d r es s Conve n tions .......... ............ ....... ....... ....................... ........ ....... ....37
4.2 Interface Signal Groups. .. ......... ............ ....... ............ ............ ............ ......... ....... ............ .......38
4.3 Signal Description Tables............................ ............ ....... ............ ............ ......... ............ .......39
4.4 Ball Usage Summary..........................................................................................................57
4.5 Multiplexed B all Connection s..............................................................................................58
4.5.1 GMII/RGMII/SerDes/OMI Multiplexed Ball Connections.............. ....... .......... .........58
4.5.2 SPI3 MPHY/SPHY Ball Connect ions.....................................................................59
4.6 Ball State During Reset ......................................................................................................61
4.7 Power Su p ply Se q uen cing.... ............ ....... ....... ....................... ........ ....... ........... ........ ....... ....63
4.7.1 Power-Up Sequence......... ....... ....... ..... ....... ....... ..... ....... ....... ....... ..... ....... ....... .......63
4.7.2 Power-Down Sequence.........................................................................................63
4.8 Pull-Up/Pull-Down Ball Guide li n e s. ....................................................................... ....... .......64
4.9 Analog Power Filterin g........................................................................................................64
5.0 Functional Descriptions..............................................................................................................66
5.1 Media Access Controller (MAC) .........................................................................................66
5.1.1 Features for Fiber and Copper Mode ....... ....... .. ....... ..... ....... ....... ..... ....... ....... ..... ..67
5.1.1.1 Paddi ng of Undersized Frames on Trans m it ........................ .................67
5.1.1.2 Automa tic CRC Generation ...................................................................67
5.1.1.3 Fil te r i n g of Rece ive Packets .......... ....................... ....... ....... ........ ...........67
5.1.1.4 CRC Error Detecti on..............................................................................69
5.1.2 Flow Contr o l........ ............ ....... ....... ....... ............ ....... ....... ....... ............ ....... ....... .......69
5.1.2.1 802.3x Flo w Control (Full-Duplex Op eration) .........................................70
5.1.3 Mixed- Mode Oper a tion .......... ........................ ....... ....... ....................... ........ ....... ....75
5.1.3.1 Configuration..........................................................................................75
5.1.3.2 Key Configu ra tion Register s....... ....... ........................ ....... ....... ..............75
5.1.4 Fiber Mo d e................... ........ ....... ............ ....... ....... ............ ....... ....... .......................76
5.1.4.1 Fiber Auto-Negotiatio n...........................................................................77
5.1.4.2 Determ ining If Link Is Established in Auto-Negotiation Mode. ...............77
5.1.4.3 Fiber Forced Mode.................................................................................77
5.1.4.4 Determination of Link Establishment in Forced Mode ...... ....... ............ ..77
5.1.5 Copper Mode.. .......................................................................................................77
Contents
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Revision Number: 009
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5.1.5.1 Speed.....................................................................................................78
5.1.5.2 Duplex....................................................................................................78
5.1.5. 3 Copper A uto -Negot iation .......................................................................78
5.1.6 Jumbo P ack et Support ..........................................................................................78
5.1.6 .1 R x Sta tis tics.............. ....... ....... .................................... ....... ....... .............79
5.1.6.2 TX Statistics...........................................................................................79
5.1.6 .3 L o ss- l e ss Fl o w Contro l... ....................... ....... ........ ....... ........... ........ ....... .79
5.1.7 Packet Bu ffer Dimensions... ....... ....... ........ ........... ....... ........ ....... ....................... ....80
5.1.7. 1 TX and RX FIFO Operat ion ...................................................................80
5.1.8 RMON Stat istics Support... ....... ....... .................................... ....... ....... ....................80
5.1.8.1 Conventions...........................................................................................82
5.1.8.2 Advantages............................................................................................83
5.2 SPI3 Inte r face.. ....... ....... ........................ ....... ....... ............ ....... ....... ........................ .............83
5.2.1 MPHY Opera ti o n ........... ....... ....... ........................ ....... ....... ............ ....... ....... ...........84
5.2.1.1 SPI3 RX Round Robin Data Transmi ssion............................................84
5.2.2 MPHY Logica l Timi ng... ........................ ....... ....... ....... ............ ....... ....... ..................84
5.2.2 .1 Transmit Ti mi n g........ ....... ............ ....... ....... ........................ ....... ....... ......85
5.2.2.2 Receive Timin g......................................................................................85
5.2.2 .3 C l o ck Rates............. ....... ....... ................................... ....... ....... ................87
5.2.2.4 Parity......................................................................................................87
5.2.2.5 SPHY Mode...........................................................................................87
5.2.2. 6 S PHY Logical Timing.............................................................................88
5.2.2 .7 Transmit Ti mi n g (SPHY).. ....... ....... ............ ....... ....... ............ ....... ....... ....88
5.2.2.8 Receive Timin g (SPHY).........................................................................88
5.2.2.9 SPI3 Flow Control..................................................................................91
5.2.3 Pre-Pending Function...................... ....... ....... ....... ....... ............ ....... ....... .......... ......93
5.3 Gigabit Media Independ ent Inte rface (GMII) ......................................................................93
5.3.1 GMII Si g nal Mu ltiplexin g.... ....... ....... ........................ ....... ....... ............ ....... ....... ......94
5.3.2 GMII Interface Signal Definiti on..................... ....... ....... .......... .. ....... ....... ............ ....94
5.4 Reduced Gigabit Media Independent Interface (RGMII) ............................. ................... ....96
5.4.1 Mul tiplexing of Data and Control............................................................................96
5.4.2 Timing Specifics.....................................................................................................97
5.4.3 TX_ER and RX_ER Codi n g........ ....... .................................... ....... ....... ....... ...........97
5.4.3 .1 In-Band Status.......... ....... ............ ....... ....... ............ ....... ....... ..................99
5.4.4 10/ 1 00 Mbp s Func tionality. ........................ ....... ....... ............ ....... ....... ....................99
5.5 MDIO Control and Interface ................................................................................................99
5.5.1 MDIO Address.....................................................................................................100
5.5.2 MDIO Register Descriptions................................................................................100
5.5.3 C lear When Done................................................................................................100
5.5.4 MDC Generation..................................................................................................100
5.5.4.1 MDC High-Frequency Operation ............................. ....... ....... ............ ..100
5.5.4.2 MDC Low-Frequency Operation......... ......... ............ ............ .............. ..100
5.5.5 Management Frames...........................................................................................101
5.5.6 Single MDI Command Operation.........................................................................101
5.5.7 MDI State Machi n e......... ........ ....... ............ ....... ....... ................................... ....... ..101
5.5.8 Autoscan Operation.............................................................................................103
5.6 SerDes In terface ...............................................................................................................103
5.6.1 Features...............................................................................................................103
5.6.2 Functional Description.... ............ ............ ............ ......... ............ ....... ............ .........103
5.6.2.1 Transmitter Operational Overview.......................................................104
5.6.2.2 Transmitter Programmable Driver-Power Levels.................................104
Contents
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5.6.2.3 Recei ver Op erational Overview . ..........................................................1 05
5.6.2.4 Selective Power-Down.........................................................................105
5.6.2.5 Receiver Jitter Tolerance.....................................................................1 05
5.6.2.6 Transmit Jitter ......................................................................................1 06
5.6.2.7 Rece ive Jitter ......... ........................ ....... ....... ................................... .....106
5.7 Optical Module Interface...................................................................................................107
5.7.1 Intel® IXF1104 MAC-Supported Optical Module Interface Signals .....................1 07
5.7.2 Functional Descr i pt ions ..................... ....... ....... ................................... ........ ....... ..108
5.7.2.1 High-Sp eed Serial Interface.................................................................1 08
5.7.2.2 Low-Spee d Status Signaling Interface. ................................................108
5.7.3 I²C Module Configuration Interface......................................................................110
5.7.3.1 I2C Control and Data Registers............................................................1 10
5.7.3.2 I2C Read Ope ration. .............................................................................110
5.7.3.3 I2C Write Operation..............................................................................111
5.7.3.4 I²C Pro to c o l Sp ec ifics......... ....... ....... ............ ....... ....... ............ ....... .......112
5.7.3.5 Port Protocol Operation .......................................................................1 13
5.7.3.6 Clock and Data Transitions. .................................................................1 13
5.8 LED Inte r face..... ....... ....... ............ ....... ....... ........................ ....... ....... ............ ....... ....... .......115
5.8.1 Modes of Ope r a ti o n............... ....... ....... ............ ....... ....... ............ ....... ....... ............115
5.8.2 LED Interface Signal Description..................... .. ..... ....... ..... ....... .. ....... ..... ....... .....116
5.8.3 Mode 0: Detailed Operation.................................................................................1 16
5.8.4 Mode 1: Detailed Operation.................................................................................1 17
5.8.5 Power-O n , Res et , In itializa tion ..... ....... ....... ....... ............ ....... ....... ....... ............ .....118
5.8.6 LED DATA Decodes......... ....... ....... .................................... ....... ....... ....... ............118
5.8.6.1 LED Signali ng Behav ior. ......................................................................119
5.9 CPU Inter face . ........ ....... ........... ........ ....... ............ ....... ....... ....................... ....... ........ .........120
5.9.1 Functional Descr i pt ion.... ....... ....... ........................ ....... ....... .................................121
5.9.1.1 Rea d Access.................................. ....... ....... ....................... ........ ....... ..121
5.9.1.2 Write Access........................................................................................121
5.9.1.3 CPU Timing Parameters......................................................................1 22
5.9.2 Endian..................................................................................................................122
5.10 TAP In te rface (JTAG)........ ....... ............ ....... ........ ....................... ....... ....... ............ ....... .....123
5.10 .1 TAP Sta te Machi n e................ ....... ....... ........................ ....... ....... ............ ....... .......123
5.10.2 I nstruction Register and Supported Instructions.......................... ................... .....124
5.10.3 ID Register...........................................................................................................1 25
5.10.4 B oundary Scan Register......................................................................................1 25
5.10.5 Bypass Register ...................................................................................................125
5.11 Loopbac k Modes ..............................................................................................................125
5.11.1 S PI3 Interface Loopbac k . ....................................................................................1 25
5.11.2 Line S ide Interface Loopba ck . .............................................................................126
5.12 Clocks...............................................................................................................................127
5.12.1 System Interface Reference Clocks.....................................................................1 27
5.12.1.1 CLK125................................................................................................128
5.12.2 S PI3 Receive and Transm it Clocks .. ...................................................................1 28
5.12.3 RGMII Clocks.......................................................................................................128
5.12 .4 MDC Cloc k............................... ....... ........ ....................... ....... ....... ........................128
5.12.5 JTAG Clock..........................................................................................................1 29
5.12.6 I2C Clock............. ....... ....... ....... ............ ....... ....... ....... ............ ....... ....... ........ .........129
5.12 .7 LED Clock.... ........................ ....... ....... ....................... ........ ....... ....................... .....129
Contents
6Datasheet
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Revision Number: 009
Revision Date: 27-Oct-2005
6.0 Applications...............................................................................................................................130
6.1 Change Port Mode Initialization Sequenc e.......................................................................130
6.2 Disable and Enable Port Sequen ces................................................................................131
6.2.1 D isable Port Sequence........................................................................................131
6.2.2 Ena ble Port Sequenc e.........................................................................................131
7.0 Electrical Specifications...........................................................................................................132
7.1 DC Specifications........ ....... ............ ....... ....... ........................ ....... ....... ............................ ..133
7.1.1 Undershoot / Overshoot Specifications ................ ....... ............ ............ ............ ....135
7.1.2 RGMII Electr ical Characte ristics. ....... ........ ....................... ....... ....... .....................135
7.2 SPI3 AC Timi ng Spe c i fication s......... ....... ............ ....... ....... ........................ ....... ....... .........137
7.2.1 Recei ve In te rfac e Tim ing... ....... ....... ............ ....... ....... ........................ ....... ....... ....137
7.2.2 Transmit Interface Timing....................................................................................139
7.3 RGMII AC Timi ng Sp e cificatio n........ ............ ....... ....... ........................ ....... ....... ............ ....141
7.4 GMII AC Timi n g Specificati o n.... ....... ....... ............ ....... ....... ........................ ....... ....... .........142
7.4.1 1000 Ba se -T Operation .......................................................................................142
7.4.1. 1 1000 B A SE-T Transmit Interfa ce.........................................................142
7.4.1.2 1000BASE-T Receiv e In te rface........................ ....... ....... ............ ....... ..143
7.5 SerDes AC Timing Specification.......................................................................................144
7.6 MDIO AC Timing Specifi catio n.........................................................................................145
7.6.1 MDC High-Speed Operation Timing....................................................................145
7.6.2 MDC Low-Speed Operation Timing.....................................................................145
7.6.3 MDIO AC T iming..................................................................................................146
7.7 Optical Module and I2C AC Timi ng Spe c i fication ..... ....... ....... ..........................................147
7.7.1 I2C Interface Tim ing.............................................................................................147
7.8 CPU AC Timing Specificati on...........................................................................................149
7.8.1 CPU Interface Read Cycle AC Timing.................................................................149
7.8.2 CPU Interface Write Cycle AC Timing.................................................................149
7.9 Transmit Pause Contro l AC Ti ming Specification.............................................................151
7.10 JTAG AC Timing Sp e cificatio n......... ............ ....... ....... ........................ ....... ....... ................152
7.11 System AC Timing Specification.......................................................................................153
7.12 LED AC Timing Specificati on............................................................................................154
8.0 R egister Se t................................................................................................................................155
8.1 Document Structure ..........................................................................................................155
8.2 Graphical Representation................. ....... ....... ............ ....... ..... ....... ....... ....... ....... .......... ....155
8.3 Per Port Registers............................................................................................................156
8.4 Registe r Map....................................................................................................................156
8.4.1 MAC Contro l Registers........................................................................................163
8.4.2 MAC RX Statistics Register Overview.................................................................174
8.4.3 MAC TX Statistics Register Overvie w .................................................................178
8.4.4 PHY Autoscan Registers.....................................................................................181
8.4.5 Globa l Status and Configura tion Register Overview ...........................................188
8.4.6 RX FIFO Register Overview................................................................................193
8.4.7 TX FIFO Regi ste r Overview........ ............ ....... ....... ........................ ....... ....... ....... ..203
8.4.8 MDIO Register Overview.....................................................................................211
8.4.9 SPI3 Regi ster Ove r view.............. ....... ........ ....... ........... ........ ....... ....... ............ ......213
8.4.10 SerDes Register Overview ..................................................................................220
8.4.11 Optical Module Register O verview ......................................................................222
Contents
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9.0 Mechanical Specifications........................................................................................................224
9.1 Overview...........................................................................................................................224
9.1.1 Features...............................................................................................................224
9.2 Package Sp e cifics .. ....... ....................... ....... ........ ........... ....... ........ ....................... ....... .....224
9.3 Package In fo rmat i on........ ....... ....... ........................ ....... ....... ............ ....... ....... ...................225
9.3.1 CBGA Package Diagrams ..... ....... .. ............ ..... ....... ....... ....... ....... ..... ....... ....... .....225
9.3.2 Flip Chi p -Plastic Bal l Gr id Arr a y Pa cka g e Diagra m.............................................227
9.3.3 Top Label Mar king Example.... ....... ........................ ....... ....... ........................ .......229
10.0 Product Ord eri ng Informatio n..................................................................................................230
Figures
1 Block Diagram ............................................................................................................................21
2 Internal Architecture....................................................................................................................22
3 552-B all CBGA Assignments (Top View) ...................................................................................23
4 Interface Signals ........................................................................................................................38
5 Power Su pply Sequenc ing ..........................................................................................................63
6 Analo g Power Supply Filter Network. .........................................................................................65
7 Packet Buffering F IFO................................................................................................................71
8 Ethern e t Frame For ma t ......... ....... ....... ........................ ....... ....... ............ ....... ....... .......................71
9 PAUSE Frame Format................................................................................................................72
10 Transm it Pause Control Interface................................ ....... ....... ....... ............ ....... ....... ....... ....... ..74
11 M P HY Transmit Logical Timing ..................................................................................................85
12 M P HY Receive Logical Timing...................................................................................................86
13 MPHY 32-Bit Interface................................................................................................................86
14 SPHY Transmit Logical Timing............................................... ................... .............. ................. ..88
15 SPHY Receive Logica l Timi n g. ....... ....... ............ ....... ....... .................................... ....... ....... .........89
16 SPHY Connection for Two Intel® IXF1104 M AC Ports (8-Bit Interface).....................................90
17 MAC GMII Int erconnect.................... ........ ....... ....... ............ ....... ....... ....................... ........ ...........94
18 RGMII Interface ..........................................................................................................................96
19 T X_C TL B ehavior.......................................................................................................................98
20 RX_CTL Be h av ior........ ....... ....... ............ ....... ....... ........................ ....... ....... ............ ....... ..............98
21 M anagement Frame Structure (Single-Frame Format) ............................................................101
22 MDI Sta te..................................................................................................................................1 02
23 SerDe s Recei v e r Jitter Toler a n ce.................................... ....... ....... ........ ........... ....... ........ ....... ..106
24 I2C Random Read Transac tion.................................................................................................111
25 Data Va lidity T iming..................................................................................................................113
26 S tart and Stop Definition Timing...............................................................................................113
27 Acknowledge Timin g.. ....... ....... ........................ ....... ....... ............ ....... ....... ........................ .........114
28 Random Read...........................................................................................................................115
29 Mode 0 Timing..........................................................................................................................116
30 Mode 1 Timing..........................................................................................................................118
31 Read Timing Diagram - Asynchronous Interface......................................................................1 21
32 Writ e Timing Diagra m - Asyn ch r o n ous Interface.... ............ ....... ....... ....... .................................122
33 S PI3 Interface Loopback Path..................................................................................................126
34 Line Side Interface Loopback Path.................................. ....... ....... ............ ....... ............ ....... .....127
35 SPI3 Receive Interface Timing.................................................................................................137
36 SPI3 Transmit Interfa ce Timing................................................................................................139
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37 RGMII Interface T iming ............................................................................................................141
38 1000BASE-T Transmit Interface Timing...................................................................................142
39 1000BASE- T Rec eive In te r face Timing......... ....... ............ ....... ....... ............ ....... ....... ............ ....143
40 SerDes Timi n g Diag r a m.... ....... ....... ....................... ........ ....... ....... ............ ....... ....... ..................144
41 M DC High-Speed Operation Timing.... ..... ....... ..... .. .......... .. ....... ..... ....... ..... ....... .. ..... ....... ..... ....145
42 MDC Low-Speed Oper a tion Tim ing........ ............ ....... ....... ................................... ....... ........ ......145
43 MDIO Write Timing Diagra m ........ ....... ........................ ....... ....... ........................ ....... ....... ....... ..146
44 MDIO Read Timing Diag r a m.... ....... ....... ............ ....... ....... ........................ ....... ....... ....... ...........146
45 Bus Timing Dia g ra m..... ....... ........................ ....... ....... ....... ............ ....... ....... ........................ ......147
46 Write Cycle Diagram.................................................................................................................147
47 CPU I nterface Read Cycle AC Timing......................................................................................149
48 CPU Interface Write Cycle AC Timing......................................................................................149
49 Pause Cont ro l Inte r face Timi ng.............. ....... ....... .................................... ....... ....... ..................151
50 JTAG AC Timing.......................................................................................................................152
51 System Reset AC Timing .........................................................................................................153
52 LED AC Int e rfa c e Ti mi n g... ....... ....... ....................... ........ ....... ....... ............ ....... ....... ..................154
53 Memory Overview Diagram......................................................................................................155
54 Register Overview Dia g r a m.................................... ........ ....... ....... ............ ....... ....... ....... ...........156
55 CBGA Package Diagram..................... ..... ....... ....... ..... ....... ....... ..... ....... ....... ..... ....... .. .......... .. ..225
56 CBGA Package Side View Diagram.........................................................................................226
57 FC-PBGA Packa g e (T op a nd Bottom Vie ws)..... ....... ....................... ........ ....... ........... ........ ......227
58 FC-PBGA Mech a nica l Speci ficati ons..... ............ ....... ....... ............ ....... ....... ........................ ......228
59 Package Mar king Example..................... ....... ....... ........................ ....... ....... ............ ....... ....... ....229
60 Ordering Info rmat i on – Sample .... ....... ............ ....... ........ ....................... ....... ....... ............ ....... ..230
Tables
1 Ball List in Alphanumeric Order by Signal Name.............................. .......... ......... ....... .......... ......24
2 Ball List in Alph anu mer ic Orde r b y Ball Location.... ........ ........... ....... ........ ........... ....... ........ ........30
3 S PI3 Interface Signal Descriptions.............................................................................................39
4 SerDes Interface Signal Descriptions.............. ..... ....... ..... ....... .. ....... .......... .. ....... ....... ..... ....... ....47
5 GMII Interface Signal Descriptio ns.............................................................................................48
6 RGMII Interface Signal Descriptions ..........................................................................................50
7 CPU Interface Signal Descriptions ......................... ..... ....... ....... ....... .......... ....... .. ....... .......... ......51
8 Transmit Pause Control Interface Signal Descriptions...............................................................53
9 Optical Module Interface Signal Descriptions. ............................................................................53
10 MD IO Interface Signal Descript ions ...........................................................................................54
11 LED Interface Signal Descriptions................... ..... ....... ..... ....... .. ....... ..... ....... ..... ....... .. .......... .. ....55
12 JTAG Interface Signal Descriptions............................................................................................55
13 Sy stem Interface Signal Descriptions................... ....... ....... ............ ....... ....... ....... ....... ............ ....55
14 Power Supply Signal Descriptions..... ............ ....... ....... ....... ............ ....... ....... ....... .......................56
15 Ball Usage Summary..................................................................................................................57
16 Line Side Interface Mul tiplexed Balls..........................................................................................58
17 SPI3 MPHY/SPHY Interface .......................................................................................................59
18 Definition of Output and Bi-directional Balls During Hardware Reset . ........................................61
19 Power Supply Sequencing .................. .......... ....... ....... ....... ..... ....... ....... ....... ....... ....... ..... ....... ....64
20 Pull-Up /Pu ll-Down and Unused Ball Guid e li n e s... ...................................................... ................64
21 Analog Power Ba lls ....................................................................................................................65
22 CRC Errored P ackets Drop Enable Behavior. ............................................. ...............................69
23 Valid Decodes fo r TXPAUSEADD[2:0].......................................................................................74
24 Operation al Mode Configurati on Registers ................................................................................76
Contents
Datasheet 9
Document Number: 278757
Re vision N umber: 009
Re vision D ate: 27-Oct-2005
25 RMON Additional Statistics.........................................................................................................81
26 G MII Interface Signal Definitions. ...............................................................................................95
27 RG MII Signal Definitions .............................................................................................................97
28 T X_ER and RX_E R Coding Description.....................................................................................97
29 SerDes Driver TX Power Levels...............................................................................................1 04
30 Intel® IXF1104 MAC-to-SFP Optical Module Interface Connections..................... ....... ....... .....107
31 LED Interface Signal Descriptions............................................................................................116
32 M ode 0 Clock Cycle to Data Bit Relationship. ..........................................................................1 17
33 M ode 1 Clock Cycle to Data Bit Relationship. ..........................................................................1 18
34 LED_DATA# Decodes..............................................................................................................119
35 LE D Behav ior (Fiber Mode). .....................................................................................................119
36 LE D Behav ior (Copper Mode) ..................................................................................................1 20
37 B yte Swapper B ehavior ............................................................................................................123
38 Instruction Register Descrip tion................................................................................................124
39 Absolute Maximum Ratings......................................................................................................132
40 Rec om m ended Op erating C onditions.......................................................................................133
41 DC Specifications .....................................................................................................................134
42 SerDes Transmit Characteristics..............................................................................................134
43 SerDes Receive Characteristics...............................................................................................135
44 Undersho ot / O vershoot Limits.................................................................................................135
45 RGMII Power............................................................................................................................136
46 S PI3 Receive Interface Signal Param eters ..............................................................................138
47 SPI3 Transmit Interfa ce Signal Parameters .............................................................................140
48 RGMII Interface Tim ing Parameters.........................................................................................141
49 GMII 1000BASE-T Tra n smit Signal Pa r a me te r s ......... ....... ........... ........ ........... ....... ............ .....142
50 GMII 1000BASE-T Receive Signal Parameters .......................................................................143
51 SerDes Timing Parameters ......................................................................................................144
52 MDIO Timi n g Parame ters........ ....... ....... ........................ ....... ....... ............ ....... ....... ...................146
53 I2C AC Timing Characteristics..................................................................................................147
54 CPU Interface Write Cycle AC Signal Parameters...................................................................150
55 Transm it Pause Control Interface Timing Parameter s.................................... ....... ....... ....... .....151
56 JTAG AC Timing Parameters...................................................................................................152
57 System Reset AC Timing Parameters......................................................................................153
58 LED Interface AC Timing Parameters ......................................................................................1 54
59 MAC Control Registers ($ Port Index + Offset) ........ ....... ..... .. ..... ....... ..... .. ..... .. ....... ..... ..... .. .....156
60 MAC RX Statistics Registers ($ Port In dex + Offset)................................................................157
61 MAC TX Statistics Registers ($ Port Index + Offset)....... ....... ....... ............ ....... ....... ..... ....... .....158
62 PHY Autoscan Registers ($ Port Index + Offset)......................................................................159
63 G lobal Sta tus and Configuration Registers ($ 0x500 - 0 X50C) ................................................1 59
64 RX FIFO Registers ($ 0x580 - 0x5 BF)......................................................................................1 59
65 TX FIFO Register s ($ 0x 600 - 0x63E)........ ....... ............ ....... ....... ....... ............ ....... ....... ....... .....160
66 MDIO Registers ($ 0x680 - 0x683)............... ....... ..... ....... ....... ..... ....... ....... ..... ....... .. .......... .......161
67 S PI3 Registers ($ 0x700 - 0x716) .............................................................................................161
68 S erDes Regist ers ($ 0x780 - 0x798) .. ......................................................................................1 62
69 Optical Module Register s ($ 0x799 - 0x79F) ........................ .. ....... .......... ....... ....... ....... ....... .....162
70 Stat ion Add r e ss ($ Port_ Inde x +0x0 0 – +0x 01)... ........ ....................... ....... ....... ........................163
71 Desired Duplex ($ Port_Index + 0x02) .....................................................................................163
72 FD FC Type ($ Port_In d ex + 0x03) .......... ....... ............ ....... ....... ............ ....... ....... ............ ....... ..163
73 Collision Distance ($ Port_Index + 0x05) .................................................................................164
74 Collision Thres hold ($ Por t_ Index + 0x0 6) ........ ....... ....... ............ ....... ....... ...............................164
Contents
10 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
75 FC TX Timer Va lue ($ Port_In dex + 0x07)...............................................................................164
76 FD FC Addres s ($ Port_Index + 0x08 – + 0x09) ......................................................................164
77 I PG Receive Time 1 ($ Port_Index + 0x0A) .... ....... ............ ............ ....... ............ ......... .......... ....165
78 I PG Receive Time 2 ($ Port_Index + 0x0B) .... ....... ............ ............ ....... ............ ......... .......... ....165
79 IPG Transmit Time ($ Port_ Inde x + 0x0 C )......... ....... ....... ............ ....... ....... ............ ....... ....... ....165
80 Pause Thres hold ($ Port_Index + 0x0E) ..................................................................................166
81 M ax Frame Size (Addr: Port_Index + 0x0F)................ ....... ....... ....... ............ ..... ....... ....... ....... ..166
82 M AC IF Mode and RGMII Speed ($ Port_Index + 0x10).............................. ....... ....... ............ ..167
83 Flush TX ($ Port_Index + 0x11). ...............................................................................................167
84 FC Enable ($ Po rt_Index + 0x 12).............................................................................................168
85 FC Bac k Pressure Length ($ Port_Index + 0x13).....................................................................168
86 Short Runts Threshold ($ Port_Index + 0x1 4)..........................................................................169
87 Discard U nknown Contro l Frame ($ Port_Index + 0x15)..........................................................169
88 RX Config Word ($ Port_Index + 0x16)....................... ....... ....... ....... .......... .. ....... ....... .......... ....169
89 TX Config Word ($ Port_Index + 0x17) ....................................................................................170
90 Di verse Config Write ($ Port_Index + 0x18)........... .......... ....... ....... ............ ....... ....... ....... ....... ..171
91 RX Packet Filter Control ($ Port_Index + 0x19) .......... ....... ....... ....... .......... ....... .. ....... .......... ....172
92 Port Multicast Addres s ($ Port_Index +0x1A – +0x1B) ............................................................173
93 MAC RX Statistics ($ Port_Index + 0x20 – + 0x39)..................................................................174
94 MAC TX Statistics ($ Port_Index +0x40 – +0x58)....................................................................178
95 PHY Control ($ P ort Index + 0x60)...........................................................................................181
96 PHY Status ($ Port Index + 0x6 1) . ...........................................................................................182
97 PHY Identification 1 ($ Po rt Index + 0x62) ...............................................................................183
98 PHY Identification 2 ($ Po rt Index + 0x63) ...............................................................................184
99 Auto-Negotiation Advertisement ($ Port In dex + 0x64)............................................................184
100 Auto-Negotiation Link Partner Base Page Ability ($ Port Index + 0x6 5) . . .................................185
101 Auto-Negotiation Expan sion ($ Port Index + 0 x66) . . ................................................................186
102 Auto-Negotiation Next Pa ge Transmit ($ Port Index + 0x67) ...................................................187
103 Port Enable ($0x500)... .............................................................................................................188
104 I nt e rfa ce Mo d e ($0 x5 0 1) ..... ............ ....... ....... ............ ....... ....... ........................ ....... ....... ...........188
105 Link LED Enable ($0x502)........................................................................................................189
106 MAC Soft Reset ($0x505). ........................................................................................................189
107 MDIO Soft Reset ($ 0 x5 0 6).... ....... ........................ ....... ....... .................................... ....... ....... ....190
108 CPU Interface ($0x508)......... ....... ....... ............ ..... ....... ....... ....... ....... .......... ....... ....... ....... .........190
109 LED Cont r o l ($0 x 5 0 9)..... ....... ....... ........................ ....... ....... ........................ ....... ....... ................190
110 LED Fla sh Rate ($ 0 x5 0A ).... ....... .................................... ....... ....... ....................... ....... ........ ......191
111 LED Fault Disable ($0x50B).....................................................................................................191
112 JTAG ID ($0x50C)....................................................................................................................192
113 RX FIFO High Watermark Port 0 ($0x580)...............................................................................193
114 RX FIFO High Watermark Port 1 ($0x581)...............................................................................193
115 RX FIFO High Watermark Port 2 ($0x582)...............................................................................193
116 RX FIFO High Watermark Port 3 ($0x583)...............................................................................194
117 RX FIFO Low Watermark Port 0 ($0x58A)...............................................................................194
118 RX FIFO Low Watermark Port 1 ($0x58B)...............................................................................194
119 RX FIFO Low Watermark Port 2 ($0x58C)...............................................................................195
120 RX FIFO Low Watermark Port 3 ($0x58D)...............................................................................195
121 RX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($ 0x 594 – 0x597)....................................195
122 RX FIFO Po rt Reset ($0x59E)..................................................................................................196
123 RX FIFO Errored Frame Drop Enable ($0x59F ).......................................................................196
124 RX FIFO Overfl ow Event ($ 0x5A0) ..........................................................................................197
Contents
Datasheet 11
Document Number: 278757
Re vision N umber: 009
Re vision D ate: 27-Oct-2005
125 RX FIFO Erro red Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5)......................................198
126 RX FIFO SPI3 Loopb ack Enable for Ports 0 - 3 ($0x5B2). .......................................................1 99
127 RX FIFO Padding and CRC Strip Enable ($0x5B3) ........ ....... ..... ....... ....... ..... ....... .. .......... .......200
128 RX FIFO Transfer Threshold Port 0 ($0x5B8)..........................................................................2 01
129 RX FIFO Transfer Threshold Port 1 ($0x5B9)..........................................................................2 01
130 RX FIFO Transfer Threshold Port 2 ($0x5BA)..........................................................................202
131 RX FIFO Transfer Threshold Port 3 ($0x5BB)..........................................................................202
132 TX FIFO High Watermark Ports 0 - 3 ($0x600 – 0x603) ..........................................................203
133 TX FIFO Low Water mar k Register Port s 0 - 3 ($0 x6 0 A – 0x6 0 D)......... ...................................204
134 TX FIFO MAC Threshold Register Ports 0 - 3 ($ 0x 614 – 0x617).............................................205
135 TX FIFO Overflow/Un derflow/Out of Sequence Eve n t ( $ 0x 61E)... ............ ....... ....... ............ .....206
136 Loop RX Data to TX FIFO (Line-S ide Loopb ack) Ports 0 - 3 ($0 x61F) ...................................207
137 TX FIFO Port Reset ($0x620)................ ..... ....... .. ..... ....... ..... .. ....... ..... ....... ..... .. ....... ..... ..... .......207
138 TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624) ..... ....... ....... .......... .. .....208
139 TX FIFO Errored Frame Drop Count er Ports 0 - 3 ($0x625 – 0x629) .. ....................................2 09
140 TX FIFO Occu pancy Counter for Ports 0 - 3 ($0x62D – 0x630)...............................................2 10
141 TX FIFO Port Drop Enable ($0x63D).......... .. ..... .. ..... ....... ..... .. ..... ....... ..... .. ..... ....... .. ..... ..... .. .....210
142 MDIO Si ngl e Comma nd ($ 0x 680). ....... ............ ....... ....... ....... ............ ....... ....... ........................ ..211
143 MDIO Single Read and Write Data ($0x681).. ..........................................................................211
144 Autos can PHY Add ress Enable ($0x682).................................................................................212
145 MDIO Cont r o l ($0 x 6 83).......... ....... ............ ....... ....... ................................... ....... ....... .................212
146 SPI3 Tran smit and Glob al Configurat ion ($0x700)...................................................................213
147 SPI3 Receive Configuration ($0x701) ......................................................................................215
148 Addre ss Pa r ity Error Packe t Dr op Counter ($0x7 0 A)......... ....... ....................... ....... ........ ....... ..219
149 TX Driver Power Level Ports 0 - 3 ($0x 784)... ..........................................................................2 20
150 TX and RX Power-Dow n ($0x787) ...........................................................................................220
151 RX Signal Detect Level Ports 0 - 3 ($ 0x 793)............................................................................220
152 Clock and Interface Mode Change Enable Ports 0 - 3 ($0x 794) ..............................................2 21
153 Optical Modul e Status Ports 0-3 ($0x799). ...............................................................................2 22
154 Optical Module Control Ports 0 - 3 ($0x79A)..... .. .......... ....... .. ....... ..... ....... ....... ..... ....... ....... .....222
155 I2C Con tro l Ports 0 - 3 ($0 x7 9 B)... ....... ....... ....... ............ ....... ....... ....... ........................ ....... .......223
156 I2C Data Ports 0 - 3 ($0x79F)...................................................................................................223
157 Product Inform ation ..................................................................................................................230
Contents
12 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Revision History
Revision Number: 00 9
Revision Date: 27-Oct-2005
Page # Description
71 Modified Figure 8 “Ethernet Frame Format” [cha nged Pream b le byte cou nt to 7 byte s].
136 Section 45, “RGMII Power” [c ha ng ed VCC to VDD in IIH and IIL]
110 Added b ullet t o Section 5.7.3, “I²C Module Configuration Interface”: The I2C interface only
supports ra ndom single-byte reads and does no t guarantee coher ency when reading two-byte
registers.
227 Replaced Figure 57 “FC-PBGA Package (Top and Bottom Views)” on page 227.
215 Modified Table 147 “SPI3 Receive Configuration ($0x701)”.
222 Modified Table 154 “Opti c al Module Control Ports 0 - 3 ($0x79A)”: chan ged de fault val ues.
223 Modified Table 155 “I2C Control Ports 0 - 3 ($0x79B)”.
249 Modified Table 208 “I2C Data Ports 0 - 9 ($0x79F)” (changed address from $0x79C to $0x79 F).
229 A dded Section 9.3.3, “Top Label Marking Example”.
230 Modifed Table 157 “Product Information” and F igure 60 “Ordering Information – Sample” under
Section 10.0, “Product Ordering Information”.
Revision Number: 00 8
Revision Dat e: August 1, 2005 (Sheet 1 of 2)
Page # Description
1Added 552-ball Ceramic Ball Grid Ar ray (CBG A) c ompliant w ith RoHS and Produc t Ordering
Number information.
55 Modified Ta bl e 12 “ JTAG In t erf ace Si gna l Desc rip t io ns”: changed S tandard to 3.3 V LVTTL from
2.5 V CMOS.
72 Modified Figure 9 “PAUSE Frame Format” [changed Pr eamble by te count to 7 bytes].
85 Modified Figure 11 “MPHY Transm it Logical Timing” [updated TDAT[31:0]].
86 Modified Figure 12 “MPHY Receive Logical Timing” [updated RDAT[31:0]].
88 Modified Figure 14 “SP HY Transmit Lo gical Timing” [updated TDAT[7:0]].
89 Modified Figure 15 “SPHY Receiv e Logical Timing” [updated RDAT[7:0] and RPR TY].
121 Modified F igure 31 “Read T iming Diagram - Asynchronous Interface”: changed uPx_ADD[12:0]
to uPx_ADD[10:0].
125 Ad ded paragraphs two and three unde r Section 5.11, “Loopback Mode s”.
129 Changed 3.3 V CMOS to 2.5 V CMOS under Section 5.12.5, “JTAG Clock” on page 129.
131 A dded Section 6.2, “Disable and Enable Port Sequences”.
136 Modified Table 45 “RGMII Power” [c hanged V OH, VOL, VIH, VIL minimum conditi ons to VDD and
changed VIN value to VDD + .3].
138 Modified Tabl e 46 “SP I3 Re ce iv e In ter f ac e Signa l P ara m et e rs ” [changed RFCLK duty cycle to
45 mi n an d 55 ma x; Ch an ge d Min for RF CLK fre q uenc y to 90 ] .
140 Modified Table 47 “SPI3 Transmit Interface Signal Parameters” [cha nged TF CLK duty cycle to
4 5 mi n an d 55 max ].
146 Changed MDC to MDIO Output delay max for t3 for 2.5 MHz from 200 to 300 in Tabl e 52 “ MD IO
Timing Parameters” on page 146.
Contents
Datasheet 13
Document Number: 278757
Re vision N umber: 009
Re vision D ate: 27-Oct-2005
170 Modified Table 89 “TX Config Word ($ Port_Index + 0x17)” [c hanged default va lue for the
register from “0x0001A0” to “0x000001A 0” and c hanged default value for bit 6 (Half Duplex)
from 1 to 0].
181 Modified Table 95 “PHY Co ntrol ($ Port Index + 0x 60)” [added “Need one-sentence
descriptions of register” and reg ister defaul t value] .
182 Modified Table 96 “ PHY St atus ( $ Port Index + 0x6 1)” [add ed “Nee d one- se nte nce desc rip t io ns
of register” and register default val ue].
183 Modified Table 97 “PHY Identification 1 ($ Port Index + 0x62)” [added “Need one-sentence
descriptions of register” and reg ister defaul t value] .
184 Modified Table 98 “PHY Identification 2 ($ Port Index + 0x63)” [added “Need one-sentence
descriptions of register” and reg ister defaul t value] .
184 Modified Table 99 “Auto-N egoti ation Advertisemen t ($ Port Index + 0x64)” [added “Need one-
sentence descriptions of register” and register default value].
185 Modified Table 100 “Auto-Negotiation Link Partner Base Page Ability ($ Port Index + 0x65)”
[added “Need one-sentence descriptions of register” and register default value].
186 Modified Table 101 “Auto-Negotiation Expansion ($ Port Index + 0x66)” [added “Need one-
sentence descriptions of register” and register default value].
187 Modified Table 102 “ Aut o-N e goti at i on Nex t Page T ra ns mit ($ Po r t Inde x + 0x6 7) ” [a dd ed “Nee d
one-sentence des c riptions of register” and register defaul t value].
211 Modified Table 143 “MDIO Single Read and Write Data ($0x681)” [changed MDIO write data to
“MDIO write data to external device”].
213 Modified Tabl e 14 6 “ SP I3 Tra ns m it and Gl ob al Co nfi gu r at io n ($0x7 00 )” [changed defaul t value
for bits 3:0 from “0” to “1” and changed default value for entire register from “0x0020000F” to
“0x00200000”].
215 Modified Table 147 “SPI3 Receive Configuration ($0x701)” [changed default value for bits 11:8
from “0xF” to “0x1”].
222 Modified Table 154 “Optical Module Control Port s 0 - 3 ($0x79A)” [changed default value for
bits 16:13 from “0xF” to “0x1”].
227 Added Figure 57 “FC-PBGA Package (Top and Bottom Views)” on page 227 and Figure 58
“FC-PBGA Mechanical Specifications” on page 228.
229 Replaced Figure 59 “Package Marking Example”.
229 Added Section 9.4, “RoHS Compliance” on page 229.
230 Added CBGA RoHS-compliant and FC-PBGA ordering information under Table 157 “Product
Information”.
Revision Number: 008
Revision Date: August 1, 2005 (Sheet 2 of 2)
Page # Description
Contents
14 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Revision Number: 007
Revision Date: March 24, 2004
(Sh eet 1 of 5)
Page # Description
All Globally replaced GBIC with Optical Module Interface.
All Globally edited signal names.
All
Globally chan ged SerD es and PLL a nalog power ball names as follows:
TXAVTT and RX AVTT change d to AVDD1P8_2
TXAV25 and RXAV2 5 changed to AVD D2P5_2
PLL 1_ V DD A and PLL2_ V DD A chan ge d t o AVD D1P8_1
PLL3_VDDA c hanged to AVDD2P5 _1
PLL1_GNDA, PLL2_GNDA, and PLL3_GNDA changed to GND
1Reworded and rearranged the Product Features section on page one
Changed Jumbo frame support from “10 kbytes” to “9.6 KB”.
21 Changed heading to Section 2.0, “G eneral Descriptio n” [was Se ction 2. 0, “Block Diagram”] .
23/37 Reversed sections as follows:
Section 3.0, “B all Assignments and Ball List Tables”
Section 4.0, “Ball Assignments and Signal Descriptions”
24
M odifi ed Table 1 “Ball List in Alphanumeric Order by Signal Name”:
Changed A10 from VCC to VDD
Changed C12 from VCC to VDD
Changed D11 from VCC to VDD
Chan ged J20 f rom GND t o VDD
Changed Ball A1 from NC to No Pad.
Changed Balls A2, A3, A22, A23, A24, B1, B2, B23, B24, C1, C24, AB1, AB24, AC1, AC2, AC23,
AC24, AD1, AD2, AD3, AD22, AD23, AD24 from NC to No Ball.
30
M odifi ed Table 2 “Ball List in Alphanumer ic Order by Ball Location ”
Changed A10 from VCC to VDD
Changed C12 form VCC to VDD
Changed D11 from VCC to VDD
Chan ged J20 f rom GND t o VDD
Changed Ball A1 from NC to No Pad.
Changed Balls A2, A3, A22, A23, A24, B1, B2, B23, B24, C1, C24, AB1, AB24, AC1, AC2, AC23,
AC24, AD1, AD2, AD3, AD22, AD23, AD24 from NC to No Ball.
38 Updated Figure 4 “Interface Signals” [modified SPI3 interface signals a nd added MPH Y and SPHY
c ategories; modifie d signal names].
39 Broke old Table 1, “IXF1104 Signal Descriptions” into the following:
Table 3 “SPI3 Interface Signal Descriptions” on page 39 thro ugh Table 14 “Power Supply S ignal
Descriptions” on page 56
39 M odifi ed Table 3 “SPI3 Interface Signal Descriptions” on page 39 [edited de scription fo r DTPA;
added text to TFCLK description; added text to RFCLK description].
50 Modified Table 6 “RGMII Interface Signal Descriptions” [Added Ball Designators; added notes
under descriptions].
51 Modified Table 7 “CPU Interface Signal Descriptions” [UPX_DATA[16]: deleted J10, added M10].
53 M odified Table 9 “Optical Module Interface Signal Descriptions” [added Ball Designators].
54 Modified Table 10 “MDIO Interface Signal Descriptions” [moved note from MDC to MDIO].
56 M odifi ed Table 14 “Po wer Supply Signal Descriptions” [added Ball Designators A4, A21, and AD21
to GND; added AVDD1P8_1, AVDD1P8_2, AVDD2P5_1, and AVDD2P5_2].
Contents
Datasheet 15
Document Number: 278757
Re vision N umber: 009
Re vision D ate: 27-Oct-2005
39 Modifie d Section 4.3, “Si gnal Descrip tion Tables” [changed heading from “Signal Naming
Conventions; added new headings Section 4.1.1, “Signal Name Conventions” and Section 4.1.2,
“R egister Ad dress Conventions”; and added/enhanced material under headings.
58 Added new S ection 4.5, “Multiplexed Bal l Connection s” with Table 16 “Line Side Interface
Multipl exed Ba lls” and Tabl e 17 “ SP I3 MPHY/SPHY Interf ace”.
63 Modi f ie d Se ct io n 4.7 , “Po wer Su pp ly Sequ en ci ng ” [cha ng ed la ngua ge un de r th i s se ctio n and a dde d
Section 4.7.1, “Power-Up Sequence” and Section 4.7.2, “Power-Down Sequence”].
63 Modifie d Table 5 “Power Su pply Sequencing” [deleted 3.3 V Supplies Stable; changed Apply 1.8 V
to VDD, AVDD1P8_1, and AVDD1P8_2; changed Apply 2.5 V to AVDD2P5_1 and AVDD2P5_2].
61 Modified Table 18 “Definition of Output and Bi-directional Balls Dur ing Hardwar e Res et” [changed
comment s for Optical Modules ].
64 Modi f ie d Table 20 “P u ll- Up/ P ull- Do w n and U nus ed B a ll Gui d elin es ” [c hang ed TRS T _L t o p ul l-d ow n;
added MDIO, UPX_RDY_L, I2C_DATA_3:0, and TX_DISABLE_3:0].
64 Added new Sec tion 4. 9, “Analog Power Filtering” [including Figure 6 “Analog Power Supply Filter
Network” on page 65 and Table 21 “Analog Powe r Balls” on page 65].
66 Modifie d/edited text under Section 5.1, “Media Access Controller (MAC)” [rearranged and created
new bullets].
67 Modified first paragraph under Section 5.1.1.1, “Padding of Un dersi z ed Frames on Transmit ”.
67 Modifie d entire Section 5.1.1.3, “Filtering of Receive Packets”.
68 Added new Sectio n 5.1.1.3.6, “Filter CRC Error Packets”.
69 Added note under Table 22 “CRC Errored Packets Drop Enable Behavior”.
69 Added new Section 5.1.2, “Flow Control” including Figure 7 “Packet Buffering FIFO”, Figure 8
“Ethernet Frame Format”, and Figure 9 “PAUSE Frame Format”.
73 Rep l aced S ec tion 5. 1.2. 1 .5 , “T r an smi t Pau se Cont rol In ter face ” [add ed Table 23 “Vali d Deco de s for
TX PAUS EA DD [ 2: 0 ]” an d mo di fied Ta ble 1 0 “ Tra ns mi t P au se Cont r ol I n terfac e”.
74 Modified Figure 10 “Transmit Pause Control Interface”
75 Added note under Section 5.1.3.1, “Configuration”.
76 Ad de d table no te t o Ta bl e 24 “Ope r a tio nal Mo de Co nfi gu r at io n Re g is t ers ”.
77 Added note under Section 5.1.4.3, “Fiber Forced Mode”.
79 Modifie d Section 5.1.6.2, “TX Statistics ” [added text to third sentenc e in first paragraph].
79 Modifie d Section 5.1.6.3, “Loss -less Flow Control” [changed “two kilometers” to “fiv e kilometers” in
last sentence.
80 Modifie d Section 5.1.7.1.2, “RX FIFO” [c hanged 10 KB to 9.6 KB; added text to last paragraph].
83 Rewrote/replaced Section 5.2, “SPI3 Interface”.
86 Edited signal names in Figure 13 “MPHY 32- Bit Interface”.
90 Edited signal names in Figure 16 “ SPHY Connection for Two Intel® IXF1104 MAC Ports (8-Bit
Interface)”.
91 Added new Sec tion 5. 2.2.9 , “S PI3 Flow Control”.
[Removed old “Packet-Level and Byte-Level Transfers” section.}
94 Modifie d Figure 17 “MAC G MII Inter connect” [edited signal names].
NA Removed old Section 5.3.3 Electrical Requirements and Table 27 “Electrical Requirements” –
changed Input high curre nt Max from 40 to 15 and Input lo w cur rent M in from -600 to -15.
96 Added a note under Sectio n 5.4, “Reduced Gigabit Med ia Independent Interfac e (RGMII)”.
96 Modifie d Figure 18 “RGMII Interface ” [edited sign al names].
Revision Number: 00 7
Revision Date: March 24, 2004
(Sheet 2 of 5)
Page # Description
Contents
16 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
98 Modifi ed Figure 19 “TX_CTL Behavior” [changed signal names].
98 Modified Figure 20 “RX_CTL Behavior” [changed signal names].
99 Modified Section 5.5, “MDIO Control and Interface” [changed 3.3 us to 3.3 ms in fourth paragraph,
thi rd sent ence ] .
103 Mod ified /replaced all text under Sectio n 5.6, “SerD es Interface” on pa ge 103 [added Table 29
“SerDes Driver TX Power Levels”].
NA Remo ved old Section 5.6.2.4 AC/DC Coupling.
NA Removed old Section 5.6.2.9 System Jitte r.
107 Modified Table 30 “Intel® IXF1104 MAC-to-SFP Optical Module Interface Connections” [edited
signal names].
107 Modified/replaced text and deleted old “Figure 19. Typical GBIC Module Functional Diagram” under
Section 5.7, “Optical Module Interface”].
108 Modifie d sec on d se ntenc e unde r S ectio n 5.7.2 . 2 .1, “M O D_D E F _0 :3 ”.
109 Modifie d sec on d se ntenc e unde r S ectio n 5.7.2 . 2 .3, “RX _ LO S_ 0:3” .
109 Removed third paragraph under Section 5.7.2.2.7, “RX_LOS_INT”.
110 Mo di fied first an d seco nd par ag r a ph s un de r Sectio n 5.7.3, “I²C Mo d ule Co nf iguratio n I nt erfac e”.
111 Modified Section 5.7.3.3, “I2C Write Operation” [edited portions of text].
116 Modif ied Table 31 “LED Int erface Signal D escri ption s” [changed 0.5 MHz to 720 H z for LED_CLK
under Signal Description].
119 Modified Table 35 “LED Behavior (Fiber Mode)” [changed links under Description to “Link LED
Enable ($0x502)”].
NA Removed old Figure 30 “CPU – External and Internal Connections”.
123 Modified Table 37 “Byte Swapper Behavior” [edited/added new values].
123 Modified second parag raph under Section 5 .10, “TAP Int erface (JTAG) ”
126 Modified Fig ure 33 “S PI3 Interface Loop back Path”.
126 Added not e under Section 5.11.2, “Line Side Interf ace Loopback”.
127 Modified Figure 34 “Line Side Interface Loopback Path”.
127 Changed Section 5.12, “Clocks” [from GBIC output clock to I2C Clock].
129 Changed Section 5.12.6, “I2C Clock” [from GBIC Clock to I2C Clock].
130 Added new Section 6.0, “Applications”.
132 Modified Table 39 “Absolute Maximum Ratings” [changed SerDes analog power to AVDD1P8_2
and AVDD2P5_2; changed “PLL1_ VDDA and PLL2_VDDA to AVDD1P8_1; chan ged PLL 3_VDDA
to AVDD2P5_ 1.
133 Mod ified Table 40 “Rec ommended Oper ating Conditions” [c hanged S erDes analog power to
AVDD1P8_2 an d AVDD2P5_2; changed “PLL1_VDDA and PLL2_VDDA to AVDD1P 8_1; ch anged
PLL3_VDDA to AVDD2P5_1.
134 Mod ified Table 42 “SerDes Transmit Characteristics” [included SerDes power dr iver level
information].
142 Modified Table 49 “GMII 1000 BASE-T Transmit Signal Parameters” (changed Min values for t1 an d
t2.
143 Modified Table 50 “GMII 1000BASE-T Receive Signal Parameters” (changed Min values for t1 and
t2.
146 Replac ed old MDIO Timing diagram and table with Figure 43 “MDIO W rite Ti ming Diagram”, Figure
44 “MDIO Read Timing Diagram”, and Table 52 “MDIO Timing Parameters”.
Revision Number: 007
Revision Date: March 24, 2004
(Sh eet 3 of 5)
Page # Description
Contents
Datasheet 17
Document Number: 278757
Re vision N umber: 009
Re vision D ate: 27-Oct-2005
156
Brok e up the old Register Map into Table 59 “MAC Control Registers ($ Port Index + Of fset )”,
Table 60 “MAC RX Statistics Registers ($ Port Ind ex + O ffset)”, Table 61 “MAC TX Statis tics
Registers ($ Port Index + Of f set)”, Table 62 “PHY Autoscan Registers ($ Port Index + Offset)”,
Table 63 “Global Status and Configuration Regi sters ($ 0x500 - 0X5 0C)”, Table 64 “RX FIFO
Registers ($ 0x580 - 0x5BF)”, Table 65 “TX FI FO Registers ($ 0x 600 - 0x6 3E)”, Table 66 “MDIO
Registers ($ 0x680 - 0x683)”, Table 67 “SPI3 Registers ($ 0x700 - 0x716)”, Table 68 “ SerDes
Registers ($ 0x780 - 0x798)”, and Table 69 “Optical Module Registers ($ 0x799 - 0x79F)”.
159 Edited Table 63 “Global Status and Configuration Registers ($ 0x500 - 0X50C)” [no offset].
159 Edited Table 64 “RX FIFO Registers ($ 0x580 - 0x5BF) ” [no offset].
160 Edited Table 65 “TX FIFO Registers ($ 0x600 - 0x63E)” [no offset].
161 Edited Table 66 “MDIO Regis ters ($ 0x680 - 0x683)” [n o offset].
161 Edited Table 67 “SPI3 Registers ($ 0x700 - 0x716)” [no offset].
162 Edited Table 68 “SerD es Registers ($ 0x 780 - 0x7 98)” [no of fset].
162 Edited Table 69 “Optical Module Registers ($ 0x799 - 0x79F)” [no offset].
163 Modified Table 71 “Desired Duplex ($ Port_Index + 0x0 2)” [changed 100 Mbps to 1000 Mbps in
register description .
167 Modified Table 82 “MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)” [Added text to register
description.]
168 Modified Table 84 “FC Enable ($ Port_Index + 0x12)” [changed description for bits 1:0].
169 Modified Table 88 “RX C onfig Word ($ Port_Index + 0x1 6)” [edited Re gister Des c ription tex t;
changed description and type for bits 13:12].
170 Modified Table 89 “TX Config Word ($ Por t_In dex + 0x17)” [edite d descr iption and type fo r bits 14,
13:12.
171 Modified Table 90 “Diverse Config Write ($ Por t_Ind ex + 0x18)” [edited descr iption and type for bits
18: 8 ; cha n ged bits 3:1 to R es er v e d; ad de d ta bl e no te 2] .
172 Renamed/modified Table 91 “RX Packet Filter Control ($ Port_Index + 0x19)” [old register name -
added RX to head ing; added table note 2].
174 Modified Table 93 “MAC RX Statistics ($ Port_Index + 0x20 – + 0x39)” [added note to
RxPauseMacControlReceivedCounter description; edited note 3 and added note 4].
178 Modified Table 94 “MAC TX S tatistics ($ Port_Index +0x40 – +0x58)” [changed “1526-max” to “1523
- max frame size ” fo r Txpkts1519 toMaxOct ets description].
193 Modified Table 113 “ RX FIFO High Watermark Port 0 ($0x 580)”, Table 114 “RX FIF O High
Watermark Port 1 ($0x581) ”, Table 115 “RX FIFO High Watermark Port 2 ($0x5 82)”, and Table 116
“RX FIFO High Watermark Port 3 ($0x583)” [changed bits 11:0 description].
195
Renamed and modified Table 121 “RX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x594 –
0x597)”
[old register name: RX FIFO Number of Frames Removed Ports 0 to 3; renamed bit names to
match register names; removed “This register gets updated after one cycle of sw reset is applied”
under Description].
196 Modified Table 123 “RX FIFO Er rored Fr ame Drop Enable ($0x59F)” [renamed bit names to matc h
register name].
198 Renamed/modified Table 125 “RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5)”
on page 198 [older register name: RX FIFO Dropped Packet Counter for Ports 0 to 3; renamed bit
names to match register name].
199 Modified Table 126 “RX FI FO SPI3 Loopback Enable for Ports 0 - 3 ($0x5B2)” [renamed heading
and bit na me; changed descri ption and type fo r bits 7:0].
201 Renamed Table 128 “RX FIFO Transfer Threshold Port 0 ($0x5B8)” on page 201 [from “RX FIFO
Jumbo Pack et Si ze; changed bit names and edited/added text under description] .
Revision Number: 00 7
Revision Date: March 24, 2004
(Sheet 4 of 5)
Page # Description
Contents
18 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
207 Mod ified Table 136 “Loop RX Da ta to TX FIFO (Line-Side Loo pback) Ports 0 - 3 ($0x6 1F)”
[renam ed heading and bit name].
208 Mod ified Table 138 “TX FIFO Overflow Frame Drop Counter P orts 0 - 3 ($ 0x621 – 0x624)”
[renamed from TX FIF O Number of Frames Removed Ports 3 - 0].
209 Modified Table 139 “TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 – 0x629)” [renamed
from TX FIFO Number of Dropped Packets Ports 0- 3 and text under the description].
210 Modified Table 141 “TX FIFO Port Drop Enable ($0x63D)” [changed description for bits 3:0].
211 Modified Table 142 “MDIO Si ngle Command ($0x680) ” [cha nged def ault; changed description and
default for bits 9:8; changed default for bits 4:0].
212 Modified Table 144 “Autoscan PHY Address Enable ($0x682)” [added note to register description].
213 Mod ified Table 146 “SPI3 Transmit and Global Configuration ($0x 700)” [broke out bits 19:16, 7:4,
and 3:0 and c hanged desc ription text].
215 Modified Table 147 “SPI3 Receive Configuration ($0x701)” [broke out bits and modified all text
adding SPHY and MPHY modes].
221 Mod ified Table 152 “Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794)” [deleted
second paragraph of the Register Description; renamed bits to match caption; changed text under
Description].
222 Added note under Section 8.4.11, “Optical Module Register Overview”.
222 Modified Table 153 “ Optical Module Status Ports 0-3 ($0x799)” [edited register description].
222 Modified Table 154 “Optical Module Control Ports 0 - 3 ($0x79A)” [changed register description].
NA Removed/Reserved Table 190 “TX and RX AC/DC Coupling Selection ($7x780)”.
NA Deleted old Figure 19, “T ypical GBIC Module Functional Diagram” under Section 5.7, “Optical
Module Interface”.
NA Removed old Section 5.1.1.5, “Pause Command Fr ames.”
180(old) Re mo ved ol d Ta ble 1 3. TX FI FO Mini F r ame S ize for MAC and Padd in g Ena bl e Por t 0 to 3 R egi st er
(Addr: 0x63E) and replaced with Reserved.
Revision Number: 00 6
Revision Date: August 21, 2003
(Sheet 1 of 2)
Page # Description
19 Modified Table 1 “Intel® IXF1 104 Signal Descriptions”
53 Modified Sectio n 5.1.1.1, “Padding of Undersized Frames on Transmit”.
60 Modified text for et herSta tsCollision in Table 9 “RMON Additional Stat istics”.
87 Mo difie d Ta bl e 17 “ In tel® IXF1104-to-Optical Module Interfac e Connec tions”
65 Modified first paragraph under Section 5.3.1.2, “C lock Rates”.
87 Modified Section 5.8.2.1, “High- Sp eed Serial Interface” .
100 Modified Figure 27 “Microprocessor — External and Internal Connections”.
110 Changed PECL to LVDS under Section 6.1, “DC Specifications”.
113 Modified table note 4 in Table 32 “SPI3 Receive Interface Signal Parameters”.
11 9 Modif ie d Ta ble 3 7 “ SerD es Timing Pa ram e t er s” .
125 M o difie d Ta bl e 40 “Mi c r op r oc es s or Interfac e Wr ite Cy cl e AC Si gn al Par am e ter s ”.
Revision Number: 007
Revision Date: March 24, 2004
(Sh eet 5 of 5)
Page # Description
Contents
Datasheet 19
Document Number: 278757
Re vision N umber: 009
Re vision D ate: 27-Oct-2005
140 Modified Table 53 “IPG Re ceive and Transmi t Ti me Register (Addr: Por t_Ind ex + 0x0A – +
0x0C)”.
143 M odifi ed Tab le 60 “ Short Runts Threshold Register (A ddr: Port_I ndex + 0x14)”.
143 M odified Table 61 “Discard Unknown Control Frame Re gister (Addr: Por t_In dex + 0x15)”.
143 M odified Table 62 “RX Config Word Register Bi t Definit ion (Addr: Port_In dex + 0x16)”.
145 M odified Table 64 “DiverseConfigWrite Register (Addr: Port _Index + 0x18)”.
148 M odified Table 67 “RX Stat istics Registers (Addr: Port_Index + 0x 20 – + 0x39)”.
163 M odified Table 82 “Microproc essor I nterface Register (Addr: 0x 508)”.
164 M odified Table 84 “LED Flash Rate Register (A ddr: 0x 50A)”.
169 Modified Table 93 “RX FIFO Errored Frame Drop Enable Register (Addr: 0x59F)”.
170 M odifi ed Tab le 96 “ RX FIFO Loopback En able for Po rts 0 - 3 Register (Addr : 0x5B2)”.
171 Added Table 98 “RX FIFO Jumbo Packet Size 0-3 Regis ter (Ad dr: 0x5B8 – 0x5 BB ”.
172 Added Table 99 “RX FIFO Ju mbo Pack et Si ze Port 0 Register B it Definitions (Addr: 0 x 5B8)”.
172 Added Table 100 “RX FIFO Jumbo Packet Size Port 1 Register Bit Definitions (Addr: 0x5B9)”.
172 Added Table 101 “RX FIFO Jumbo Packet Size Port 2 Register Bit Definitions (Addr: 0x5BA)”.
172 Added Table 102 “RX FIFO Jumbo Packet Size Port 3 Register Bit Definitions (Addr: 0x5BB)”.
178 Modified Table 110 “TX FIFO Number of Dropped Packets Register Ports 0-3 (Addr: 0x625 –
0x629)”.
177 Modified Table 108 “TX FIFO Port Reset Register (Addr: 0x620)”.
177 Modified Table 108 “TX FIFO Port Reset Register (Addr: 0x620)”.
177 Modified Table 107 “Loop RX Data to TX FIFO Register Ports 0 - 3 (Addr: 0x61F)”.
179 Adde d Table 111 “ TX FIFO Occupancy Counter fo r Po rts 0 - 3 Regist ers (Add r: 0x62D –
0x630)”.
180 Added Table 112 “TX FIFO Port Drop Enable Register (Addr: 0x63D)”.
181 M odified Table 114 “MDI Single Comman d Reg ister (Addr: 0x6 80)”.
186 Added Table 122 “Tx and Rx P ower-Down Reg ister (Addr: 0x 787)”.
19 4 R ep la ced Fig ure 53 “ Intel ® IXF1104 Exa m ple Pac k age Mar king” .
Revision 005
Revision Date: April 30, 2003
Page # Description
Init ia l ex te rna l r ele as e .
Revisions 001 through 004
Revision Date: April 2001 – December 2002
Page # Description
Internal releases.
Revision Number: 006
Revision Date: A ugust 21, 2003
(Sheet 2 of 2)
Page # Description
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 20
Document Number: 278757
Re vision N umber: 009
Re vision D ate: 27-Oct-2005
1.0 Introduction
This document contains info rmation on the IXF1104 MAC, a four-port Giga bit Media Acce ss
Controller that supports IEEE 802.3 10/100/1000 Mbps applications.
1.1 What You Will Find in This Document
This document contains the f ollowing secti ons:
•Section 2.0 , “Ge neral Description” on page 21 provide s the block dia gram system
architecture.
•Section 3.0 , “B all Assignment s and Ball List Tabl es ” on page 23 shows the signal na ming
methodology and signal de scriptions.
•Section 4.0 , “B all Assignments and Si gnal Descriptions” on page 37 illustrates and lists the
IXF1104 ball gri d diagram with two ball list tables ( by si gnal name an d ball loc ation)
•Section 5.0 , “Functi onal Descriptions” on page 66 gives de tailed information abou t the
operatio n of the IXF1104 inc luding general features, and interface types and desc riptions.
•Sectio n 7.0, “E l ectr ical S p ecif icatio ns” on pa ge 13 2 provides information on the pr oduct-
operating parameters , el ectrica l specifi cations , and timing parameters .
•Section 8.0 , “R egister Set” on pa ge 155 illustrates and lists the memory map, detailed
des criptions, defaul t values for the register set, and detailed information on each regis ter.
•Section 9.0 , “Me chani cal Specifications” on page 224 illustrates the packaging information.
•Section 10.0, “Product Ordering Infor mation” on page 230 provides ordering informati on.
1.2 Related Document s
Document Document
Number
Intel® IXF1104 Media Access Cont roller Design and Layout Guide 278696
Intel® IXF1104 Media Access Controller Thermal Design Considerations 278751
Intel® IXF1104 Media Access Controller D evelop m ent Kit Manual 278785
Intel® IXF1104 Media Access Controller Specificat ion Update 278756
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
21 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
2.0 General Descr ipti on
The IXF1104 MAC provides up to a 4.0 Gbps interface to f our individual 10/100/1000 Mbps full-
duplex or 10/100 Mbps half- duplex-capabl e Ethernet Media Access Controllers (MACs). The
network proc es s or is supported through a System Pac ket Interface Phase 3 (SP I3) me dia int erface.
The following P HY interfaces are select ed on a per-port basis:
•Serializer/De ser iali zer (SerDes) with Optica l Module Interface sup port
•Gigabit Media Independent Interfa ce (GMII)
•Reduced Gigabit Media Independent Interface (RGMII).
Figure 1 illustrates the IXF1104 MAC block diagram.
Figure 1. Block Diag ram
For wardin g Engine/N etw or k Proc es sor
CPU
Intel
®
I XF1 104 M AC
S e rD e s /RGMII/GM I I In t e rfa c e
MDIO
SPI3
u P IF
PHY 1 De v ic e
PHY 2 De v ic e
PHY 3 De v ic e
PHY 4 De v ic e
B3175-0
1
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 22
Document Number: 278757
Re vision N umber: 009
Re vision D ate: 27-Oct-2005
Figure 2 illustrates the IXF1104 MAC internal architecture.
Figure 2. I nternal Arch itec ture
SPI3 Interface
CPU Interfa ce RMON Statistics
Packet
TX
Buffer
RX
Packet
Buffer
Packet
Buffer
Packet
Buffer
Clock Cont rol Block Clock Register Block
PLLs MDIO OMI
TX
TX
TX
RX
RX
RX
10/100/1000 MAC
10/100/1000 MAC
10/100/1000 MAC
10/100/1000 MAC
R G MII/GMII Inter face
R G MII/GMII Inter face
R G MII/GMII Inter face
R G MII/GMII Inter face
PMA Lay er SerDes
PMA Lay er SerDes
PMA Lay er SerDes
PMA Lay er SerDes
B3176-0
1
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
23 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
3.0 Ball Assignment s and Ball List Tables
3.1 Ball Assignments
See Figure 3, Table 1 “Ba ll List in Alphanumeric Or der by Signal Name” on page 24, and Table 2
“Ball List in Alphanumeric Order by Ball L ocation” on page 30 for the IXF1104 MAC ball
assignments.
Figure 3. 552-Bal l CBGA Assign ments (Top View)
B1458-01
1AD AC AB AA Y W V U T R P N M L K J H G F E D C B A
AD AC AB AA Y W V U T R P N M L K J H G F E D C B A
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V7 U7 T7 R7 P7 N7 M7 L7 K7 J7 H7 G7 F7 E7 D7 G7 B7 A7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V
17
V18
V19
V20
V21
V22
V23
V24
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
N8
N9
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N121
N22
N23
N24
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
B28
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
= No Ball (A2, A3, A22, A23, A24, B1, B2, B23, B24, C1, C24, AB1, AB24, AC1, AC2, AC23, AC24, AD1, AD2, AD3,
AD22, AD23, AD24)
= No Pad (A1)
W24Y24AA24AB24AC24AD24
W23Y23AA23AB23AC23AD23
W22
Y22
AA22AB22AC22AD22
W21Y21AA21AB21AC21AD21
W20Y20AA20AB20AC20AD20
W19Y19AA19AB19AC19AD19
W18Y18AA18AB18AC18AD18
W17Y17AA17AB17AC17AD17
W16Y16AA16AB16AC16AD16
W15Y15AA15AB15AC15AD15
W14Y14AA14AB14AC14AD14
W13Y13AA13AB13AC13AD13
W12Y12AA12AB12AC12AD12
W11Y11AA11AB11AC11AD11
W10Y10AA10AB10AC10AD10
W9Y9AA9AB9AC9AD9
W8Y8AA8AB8AC8
AD8
W7Y7AA7AB7AC7AD7
A6B6C6D6F6F6G6H6J6K6L6M6N6P6R6T6U6V6W6Y6AA6AB6AC6AD6
A5B5C5D5E5F5G5H5J5K5L5M5N5P5R5T5U5V5W5Y5AA4AB5AC5AD5
A4B4C4D4E4F4G4H4J4K4L4M4N4P4R4T4U4V4W4Y4AA4AB4AC4AD4
A3B3C3D3E3F3G3H3J3K3L3M3N3P13R3T3U3V3W3Y3AA3AB3
AC3AD3
A2B2C2D2E2F2G2H2J2K2L2M2N2P2R2T2U2V2W2Y2AA2AB2AD2
B1C1D1E1F1G1H1J1K1L1M1N1P1R1T1U1V1W1Y1AA1AB1AC1
AC2
A1
AD1
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
24 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
3.2 Ball List Tables
3.2.1 Balls Listed in Alphabet ic Order by Signal Name
Table 1 shows the ba ll loca tions and signal names arranged in alphanumeric order by signal name.
The following table notes relate to Table 1 and Table 2:
1. GMII Ball Connection:
See Ta ble 16 for connection in RGMII or fiber mode.
2. SPI3 Ball Connection:
See Ta ble 17 for proper SPHY and MPHY connection.
3. Fiber Mode Ball Connection:
See Ta ble 16 for use in RGMII and GMII (coppe r mode).
Table 1. Ball Li s t in Alp hanum eric Or der by Signal Na me
Signal Name Ball
Location
AVDD1P8_1 A5
AVDD1P8_1 A20
AVDD1P8_2 T23
AVDD1P8_2 AB16
AVDD2P5_1 AD20
AVDD2P5_2 R18
AVDD2P5_2 U14
CLK125 AD19
COL_01AB6
COL_11AB10
COL_21AD15
COL_31AB17
CRS_01AA5
CRS_11AA9
CRS_21AB15
CRS_31AC16
DTPA_02D3
DTPA_12L1
DTPA_22A9
DTPA_32J7
GND B6
GND B10
GND B15
GND B19
GND D4
GND D8
GND D12
GND D13
GND D17
GND D21
GND F2
GND F6
GND F10
GND F15
GND F19
GND F23
GND H4
GND H8
GND H12
GND H13
GND H17
GND H21
GND J10
GND J15
GND K2
GND K6
GND K9
GND K11
Signal Name Ball
Location
GND K14
GND K16
GND K19
GND K23
GND L10
GND L12
GND L13
GND L15
GND M4
GND M8
GND M11
GND M14
GND M17
GND M21
GND N4
GND N8
GND N11
GND N14
GND N17
GND N21
GND P10
GND P12
GND P13
GND P15
Signal Name Ball
Location
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 25
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
GND R2
GND R6
GND R9
GND R11
GND R14
GND R16
GND R19
GND R23
GND T10
GND T15
GND U4
GND U8
GND U12
GND U13
GND U17
GND U21
GND W2
GND W6
GND W10
GND W15
GND W19
GND W23
GND AA4
GND AA8
GND AA12
GND AA13
GND AA17
GND AA21
GND AC6
GND AC10
GND AC15
GND AC19
GND AC14
GND L20
GND L5
GND R7
GND AB12
GND A4
Signal Name Ball
Location
GND A21
GND AD21
I2C_CLK L23
I2C_DATA_03L24
I2C_DATA_13M24
I2C_DATA_23N24
I2C_DATA_33P24
LED_CLK K24
LED_DATA M22
LED_LATCH L22
MDC4W24
MDIO4V21
MOD_DEF_INT N22
NC D24
NC E12
NC F11
NC G15
NC H7
NC H18
NC J21
NC K7
NC K18
NC K20
NC K22
NC L18
NC L19
NC L21
NC M7
NC M18
NC M20
NC N3
NC N18
NC P2
NC P4
NC P6
NC P7
NC P8
NC P17
Signal Name Ball
Location
NC P18
NC R5
NC R10
NC R12
NC R13
NC R15
NC R20
NC T6
NC T7
NC T8
NC T9
NC T21
NC T22
NC U5
NC U7
NC U9
NC U11
NC U18
NC V9
NC V10
NC V11
NC V13
NC AB18
NC AD4
NC AD5
No Ball A2
No Ball A3
No Ball A22
No Ball A23
No Ball A24
No Ball B1
No Ball B2
No Ball B23
No Ball B24
No Ball C1
No Ball C24
No Ball AB1
No Ball AB24
Signal Name Ball
Location
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
26 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
No Ball AC1
No Ball AC2
No Ball AC23
No Ball AC24
No Ball AD1
No Ball AD2
No Ball AD3
No Ball AD22
No Ball AD23
No Ball AD24
No Pad A1
PTPA2B11
RDAT_02A15
RDAT_12A14
RDAT_22B14
RDAT_32C14
RDAT_42C13
RDAT_52D14
RDAT_62E14
RDAT_72F14
RDAT_82A17
RDAT_92C17
RDAT_102D16
RDAT_112E16
RDAT_122F16
RDAT_132E17
RDAT_142E18
RDAT_152F18
RDAT_162B20
RDAT_172B22
RDAT_182C20
RDAT_192C21
RDAT_202C22
RDAT_212D22
RDAT_222E22
RDAT_232E21
RDAT_242G18
RDAT_252G19
Signal Name Ball
Location
RDAT_262G20
RDAT_272G21
RDAT_282G22
RDAT_292G23
RDAT_302G24
RDAT_312F24
RENB_02A13
RENB_12A18
RENB_22C19
RENB_32E24
REOP_02C16
REOP_12D18
REOP_22C23
REOP_32J19
RERR_02A16
RERR_12G17
RERR_22D20
RERR_32H20
RFCLK2A19
RMOD02G14
RMOD12G13
RPRTY_02E15
RPRTY_12G16
RPRTY_22E20
RPRTY_32F20
RSOP_02B16
RSOP_12C18
RSOP_22E23
RSOP_32J18
RSX2E13
RVAL_02C15
RVAL_12B18
RVAL_22E19
RVAL_32F22
RX_DV_01V5
RX_DV_11AB11
RX_DV_21Y24
RX_DV_31V18
Signal Name Ball
Location
RX_ER_01W5
RX_ER_11Y12
RX_ER_21AA22
RX_ER_31U20
RX_LOS_INT3P19
RX_N_03R22
RX_N_13U22
RX_N_23R24
RX_N_33V24
RX_P_03P22
RX_P_13V22
RX_P_23T24
RX_P_33U24
RXC_01V4
RXC_11AD11
RXC_21AA24
RXC_31V23
RXD0_01V8
RXD0_11Y9
RXD0_21Y20
RXD0_31Y17
RXD1_01V7
RXD1_11Y11
RXD1_21Y21
RXD1_31Y18
RXD2_01W7
RXD2_11W11
RXD2_21Y22
RXD2_31Y19
RXD3_01Y7
RXD3_11W9
RXD3_21Y23
RXD3_31W18
RXD4_01Y6
RXD4_11AD10
RXD4_21W22
RXD4_31T16
RXD5_01Y5
Signal Name Ball
Location
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 27
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
RXD5_11AC11
RXD5_21V20
RXD5_31T17
RXD6_01AB5
RXD6_11AA11
RXD6_21V19
RXD6_31T18
RXD7_01AC5
RXD7_11Y10
RXD7_21W20
RXD7_31T19
STPA2C11
SYS_RST_L AD12
TADR02A11
TADR12A12
TCLK J22
TDAT02B3
TDAT12C2
TDAT22C3
TDAT32D1
TDAT42C4
TDAT52C5
TDAT62B5
TDAT72C6
TDAT82F1
TDAT92G1
TDAT102G2
TDAT112H1
TDAT122J1
TDAT132J2
TDAT142J3
TDAT152H3
TDAT162E5
TDAT172E6
TDAT182E7
TDAT192E8
TDAT202E9
TDAT212E10
Signal Name Ball
Location
TDAT222F9
TDAT232C8
TDAT242G4
TDAT252G5
TDAT262G6
TDAT272G7
TDAT282G8
TDAT292G9
TDAT302F5
TDAT312F7
TDI J24
TDO H24
TENB_02B7
TENB_12E2
TENB_22C9
TENB_32J4
TEOP_02A7
TEOP_12F3
TEOP_22E4
TEOP_32H5
TERR_02A8
TERR_12K1
TERR_22E11
TERR_32J8
TFCLK2D7
TMOD02A6
TMOD12D9
TMS H22
TPRTY_02D5
TPRTY_12G3
TPRTY_22B9
TPRTY_32J6
TRST_L J23
TSOP_02C7
TSOP_12E3
TSOP_22C10
TSOP_32J5
TSX E1
Signal Name Ball
Location
TX_EN_01AB2
TX_EN_11Y8
TX_EN_21AC22
TX_EN_31V12
TX_ER_01W1
TX_ER_11AD6
TX_ER_21AD17
TX_ER_31AB13
TX_FAULT_INT3P23
TX_N_03Y14
TX_N_13AD14
TX_N_23Y16
TX_N_33AD18
TX_P_03Y13
TX_P_13AD13
TX_P_23W16
TX_P_33AC18
TXC_01AA1
TXC_11AD7
TXC_21AC20
TXC_31AB14
TXD0_01Y1
TXD0_11AC7
TXD0_21AB20
TXD0_31V14
TXD1_01Y2
TXD1_11AB7
TXD1_21AB21
TXD1_31V15
TXD2_01Y3
TXD2_11AB9
TXD2_21AB22
TXD2_31V16
TXD3_01AA3
TXD3_11AD9
TXD3_21AB23
TXD3_31V17
TXD4_01AB3
Signal Name Ball
Location
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
28 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
TXD4_11AA7
TXD4_21AD16
TXD4_31AA14
TXD5_01AC3
TXD5_11AB8
TXD5_21AB19
TXD5_31Y15
TXD6_01AB4
TXD6_11AD8
TXD6_21AA20
TXD6_31AA16
TXD7_01Y4
TXD7_11AC9
TXD7_21AA18
TXD7_31W14
TXPAUSE_ADD0 N20
TXPAUSE_ADD1 P20
TXPAUSE_ADD2 P21
TXPAUSEFR T20
UPX_ADD0 P3
UPX_ADD1 N1
UPX_ADD2 P1
UPX_ADD3 R1
UPX_ADD4 T1
UPX_ADD5 U1
UPX_ADD6 V1
UPX_ADD7 V2
UPX_ADD8 V3
UPX_ADD9 U3
UPX_ADD10 T3
UPX_BADD0 T2
UPX_BADD1 W3
UPX_CS_L R3
UPX_DATA0 L2
UPX_DATA1 K3
UPX_DATA2 L3
UPX_DATA3 M3
UPX_DATA4 L4
Signal Name Ball
Location
UPX_DATA5 N5
UPX_DATA6 M5
UPX_DATA7 K5
UPX_DATA8 P5
UPX_DATA9 L6
UPX_DATA10 L7
UPX_DATA11 N7
UPX_DATA12 L8
UPX_DATA13 H9
UPX_DATA14 J9
UPX_DATA15 N10
UPX_DATA16 M10
UPX_DATA17 K10
UPX_DATA18 G10
UPX_DATA19 H11
UPX_DATA20 G11
UPX_DATA21 K12
UPX_DATA22 G12
UPX_DATA23 K13
UPX_DATA24 H14
UPX_DATA25 K15
UPX_DATA26 N15
UPX_DATA27 M15
UPX_DATA28 J16
UPX_DATA29 H16
UPX_DATA30 J17
UPX_DATA31 L17
UPX_RD_L V6
UPX_RDY_L M1
UPX_WIDTH0 U16
UPX_WIDTH1 T5
UPX_WR_L T4
VDD D6
VDD D10
VDD D15
VDD D19
VDD F4
VDD F21
Signal Name Ball
Location
VDD H10
VDD H15
VDD J11
VDD J14
VDD K4
VDD K8
VDD K17
VDD K21
VDD L9
VDD L11
VDD L14
VDD L16
VDD P9
VDD P11
VDD P14
VDD P16
VDD R4
VDD R8
VDD R17
VDD R21
VDD T11
VDD T14
VDD U10
VDD U15
VDD W4
VDD W21
VDD AA6
VDD AA10
VDD AA15
VDD AA19
VDD C12
VDD D11
VDD J20
VDD A10
VDD2 B4
VDD2 B8
VDD2 B12
VDD2 D2
Signal Name Ball
Location
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 29
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
VDD2 F8
VDD2 F12
VDD2 H2
VDD2 H6
VDD2 J12
VDD2 M2
VDD2 M6
VDD2 M9
VDD2 M12
VDD3 B13
VDD3 B17
VDD3 B21
VDD3 D23
VDD3 F13
VDD3 F17
VDD3 H19
VDD3 H23
VDD3 J13
VDD3 M13
VDD3 M16
VDD3 M19
VDD3 M23
VDD4 N13
VDD4 N16
VDD4 N19
VDD4 N23
VDD4 T13
VDD4 U19
VDD4 U23
VDD4 W13
VDD4 W17
VDD4 AA23
VDD4 AC13
VDD4 AC17
VDD4 AC21
VDD5 N2
VDD5 N6
VDD5 N9
Signal Name Ball
Location
VDD5 N12
VDD5 T12
VDD5 U2
VDD5 U6
VDD5 W8
VDD5 W12
VDD5 AA2
VDD5 AC4
VDD5 AC8
VDD5 AC12
Signal Name Ball
Location
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
30 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
3.2.2 Balls Listed in Alphabetic Order by Ball Location
Table 2 shows the ba ll loca tions and signal names arranged in order by ball lo ca tion.
Tab le 2. Ball List in Alphanumeric Order by Ball Location
Ball
Location Signal Name
A1 No Pad
A2 No Ball
A3 No Ball
A4 GND
A5 AVDD1P8_1
A6 TMOD02
A7 TEOP_02
A8 TERR_02
A9 DTPA_22
A10 VDD
A11 TADR02
A12 TADR12
A13 RENB_02
A14 RDAT_12
A15 RDAT_02
A16 RERR_02
A17 RDAT_82
A18 RENB_12
A19 RFCLK2
A20 AVDD1P8_1
A21 GND
A22 No Ball
A23 No Ball
A24 No Ball
B1 No Ball
B2 No Ball
B3 TDAT02
B4 VDD2
B5 TDAT62
B6 GND
B7 TENB_02
B8 VDD2
B9 TPRTY_22
B10 GND
B11 PTPA2
B12 VDD2
B13 VDD3
B14 RDAT_22
B15 GND
B16 RSOP_02
B17 VDD3
B18 RVAL_12
B19 GND
B20 RDAT_162
B21 VDD3
B22 RDAT_172
B23 No Ball
B24 No Ball
C1 No Ball
C2 TDAT12
C3 TDAT22
C4 TDAT42
C5 TDAT52
C6 TDAT72
C7 TSOP_02
C8 TDAT232
C9 TENB_22
C10 TSOP_22
C11 STPA2
C12 VDD
C13 RDAT_42
C14 RDAT_32
C15 RVAL_02
C16 REOP_02
C17 RDAT_92
C18 RSOP_12
C19 RENB_22
Ball
Location S igna l N ame
C20 RDAT_182
C21 RDAT_192
C22 RDAT_202
C23 REOP_22
C24 No Ball
D1 TDAT32
D2 VDD2
D3 DTPA_02
D4 GND
D5 TPRTY_02
D6 VDD
D7 TFCLK2
D8 GND
D9 TMOD12
D10 VDD
D11 VDD
D12 GND
D13 GND
D14 RDAT_52
D15 VDD
D16 RDAT_102
D17 GND
D18 REOP_12
D19 VDD
D20 RERR_22
D21 GND
D22 RDAT_212
D23 VDD3
D24 NC
E1 TSX
E2 TENB_12
E3 TSOP_12
E4 TEOP_22
E5 TDAT162
Ball
Location Signal Name
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 31
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
E6 TDAT172
E7 TDAT182
E8 TDAT192
E9 TDAT202
E10 TDAT212
E11 TERR_22
E12 NC
E13 RSX2
E14 RDAT_62
E15 RPRTY_02
E16 RDAT_112
E17 RDAT_132
E18 RDAT_142
E19 RVAL_22
E20 RPRTY_22
E21 RDAT_232
E22 RDAT_222
E23 RSOP_22
E24 RENB_32
F1 TDAT82
F2 GND
F3 TEOP_12
F4 VDD
F5 TDAT302
F6 GND
F7 TDAT312
F8 VDD2
F9 TDAT222
F10 GND
F11 NC
F12 VDD2
F13 VDD3
F14 RDAT_72
F15 GND
F16 RDAT_122
F17 VDD3
F18 RDAT_152
F19 GND
Ball
Location Signal Name
F20 RPRTY_32
F21 VDD
F22 RVAL_32
F23 GND
F24 RDAT_312
G1 TDAT92
G2 TDAT102
G3 TPRTY_12
G4 TDAT242
G5 TDAT252
G6 TDAT262
G7 TDAT272
G8 TDAT282
G9 TDAT292
G10 UPX_DATA18
G11 UPX_DATA20
G12 UPX_DATA22
G13 RMOD12
G14 RMOD02
G15 NC
G16 RPRTY_12
G17 RERR_12
G18 RDAT_242
G19 RDAT_252
G20 RDAT_262
G21 RDAT_272
G22 RDAT_282
G23 RDAT_292
G24 RDAT_302
H1 TDAT112
H2 VDD2
H3 TDAT152
H4 GND
H5 TEOP_32
H6 VDD2
H7 NC
H8 GND
H9 UPX_DATA13
Ball
Location Signal Name
H10 VDD
H11 UPX_DATA19
H12 GND
H13 GND
H14 UPX_DATA24
H15 VDD
H16 UPX_DATA29
H17 GND
H18 NC
H19 VDD3
H20 RERR_32
H21 GND
H22 TMS
H23 VDD3
H24 TDO
J1 TDAT122
J2 TDAT132
J3 TDAT142
J4 TENB_32
J5 TSOP_32
J6 TPRTY_32
J7 DTPA_32
J8 TERR_32
J9 UPX_DATA14
J10 GND
J11 VDD
J12 VDD2
J13 VDD3
J14 VDD
J15 GND
J16 UPX_DATA28
J17 UPX_DATA30
J18 RSOP_32
J19 REOP_32
J20 VDD
J21 NC
J22 TCLK
J23 TRST_L
Ball
Location Signal Name
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
32 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
J24 TDI
K1 TERR_12
K2 GND
K3 UPX_DATA1
K4 VDD
K5 UPX_DATA7
K6 GND
K7 NC
K8 VDD
K9 GND
K10 UPX_DATA17
K11 GND
K12 UPX_DATA21
K13 UPX_DATA23
K14 GND
K15 UPX_DATA25
K16 GND
K17 VDD
K18 NC
K19 GND
K20 NC
K21 VDD
K22 NC
K23 GND
K24 LED_CLK
L1 DTPA_12
L2 UPX_DATA0
L3 UPX_DATA2
L4 UPX_DATA4
L5 GND
L6 UPX_DATA9
L7 UPX_DATA10
L8 UPX_DATA12
L9 VDD
L10 GND
L11 VDD
L12 GND
L13 GND
Ball
Location Signal Name
L14 VDD
L15 GND
L16 VDD
L17 UPX_DATA31
L18 NC
L19 NC
L20 GND
L21 NC
L22 LED_LATCH
L23 I2C_CLK
L24 I2C_DATA_03
M1 UPX_RDY_L
M2 VDD2
M3 UPX_DATA3
M4 GND
M5 UPX_DATA6
M6 VDD2
M7 NC
M8 GND
M9 VDD2
M10 UPX_DATA16
M11 GND
M12 VDD2
M13 VDD3
M14 GND
M15 UPX_DATA27
M16 VDD3
M17 GND
M18 NC
M19 VDD3
M20 NC
M21 GND
M22 LED_DATA
M23 VDD3
M24 I2C_DATA_13
N1 UPX_ADD1
N2 VDD5
N3 NC
Ball
Location S igna l N ame
N4 GND
N5 UPX_DATA5
N6 VDD5
N7 UPX_DATA11
N8 GND
N9 VDD5
N10 UPX_DATA15
N11 GND
N12 VDD5
N13 VDD4
N14 GND
N15 UPX_DATA26
N16 VDD4
N17 GND
N18 NC
N19 VDD4
N20 TXPAUSE_ADD0
N21 GND
N22 MOD_DEF_INT
N23 VDD4
N24 I2C_DATA_23
P1 UPX_ADD2
P2 NC
P3 UPX_ADD0
P4 NC
P5 UPX_DATA8
P6 NC
P7 NC
P8 NC
P9 VDD
P10 GND
P11 VDD
P12 GND
P13 GND
P14 VDD
P15 GND
P16 VDD
P17 NC
Ball
Location Signal Name
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 33
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
P18 NC
P19 RX_LOS_INT3
P20 TXPAUSE_ADD1
P21 TXPAUSE_ADD2
P22 RX_P_03
P23 TX_FAULT_INT3
P24 I2C_DATA_33
R1 UPX_ADD3
R2 GND
R3 UPX_CS_L
R4 VDD
R5 NC
R6 GND
R7 GND
R8 VDD
R9 GND
R10 NC
R11 GND
R12 NC
R13 NC
R14 GND
R15 NC
R16 GND
R17 VDD
R18 AVDD2P5_2
R19 GND
R20 NC
R21 VDD
R22 RX_N_03
R23 GND
R24 RX_N_23
T1 UPX_ADD4
T2 UPX_BADD0
T3 UPX_ADD10
T4 UPX_WR_L
T5 UPX_WIDTH1
T6 NC
T7 NC
Ball
Location Signal Name
T8 NC
T9 NC
T10 GND
T11 VDD
T12 VDD5
T13 VDD4
T14 VDD
T15 GND
T16 RXD4_31
T17 RXD5_31
T18 RXD6_31
T19 RXD7_31
T20 TXPAUSEFR
T21 NC
T22 NC
T23 AVDD1P8_2
T24 RX_P_23
U1 UPX_ADD5
U2 VDD5
U3 UPX_ADD9
U4 GND
U5 NC
U6 VDD5
U7 NC
U8 GND
U9 NC
U10 VDD
U11 NC
U12 GND
U13 GND
U14 AVDD2P5_2
U15 VDD
U16 UPX_WIDTH0
U17 GND
U18 NC
U19 VDD4
U20 RX_ER_31
U21 GND
Ball
Location Signal Name
U22 RX_N_13
U23 VDD4
U24 RX_P_33
V1 UPX_ADD6
V2 UPX_ADD7
V3 UPX_ADD8
V4 RXC_01
V5 RX_DV_01
V6 UPX_RD_L
V7 RXD1_01
V8 RXD0_01
V9 NC
V10 NC
V11 NC
V12 TX_EN_31
V13 NC
V14 TXD0_31
V15 TXD1_31
V16 TXD2_31
V17 TXD3_31
V18 RX_DV_31
V19 RXD6_21
V20 RXD5_21
V21 MDIO4
V22 RX_P_13
V23 RXC_31
V24 RX_N_33
W1 TX_ER_01
W2 GND
W3 UPX_BADD1
W4 VDD
W5 RX_ER_01
W6 GND
W7 RXD2_01
W8 VDD5
W9 RXD3_11
W10 GND
W11 RXD2_11
Ball
Location Signal Name
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
34 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
W12 VDD5
W13 VDD4
W14 TXD7_31
W15 GND
W16 TX_P_23
W17 VDD4
W18 RXD3_31
W19 GND
W20 RXD7_21
W21 VDD
W22 RXD4_21
W23 GND
W24 MDC4
Y1 TXD0_01
Y2 TXD1_01
Y3 TXD2_01
Y4 TXD7_01
Y5 RXD5_01
Y6 RXD4_01
Y7 RXD3_01
Y8 TX_EN_11
Y9 RXD0_11
Y10 RXD7_11
Y11 RXD1_11
Y12 RX_ER_11
Y13 TX_P_03
Y14 TX_N_03
Y15 TXD5_31
Y16 TX_N_23
Y17 RXD0_31
Y18 RXD1_31
Y19 RXD2_31
Y20 RXD0_21
Y21 RXD1_21
Y22 RXD2_21
Y23 RXD3_21
Y24 RX_DV_21
AA1 TXC_01
Ball
Location Signal Name
AA2 VDD5
AA3 TXD3_01
AA4 GND
AA5 CRS_01
AA6 VDD
AA7 TXD4_11
AA8 GND
AA9 CRS_11
AA10 VDD
AA11 RXD6_11
AA12 GND
AA13 GND
AA14 TXD4_31
AA15 VDD
AA16 TXD6_31
AA17 GND
AA18 TXD7_21
AA19 VDD
AA20 TXD6_21
AA21 GND
AA22 RX_ER_21
AA23 VDD4
AA24 RXC_21
AB1 No Ball
AB2 TX_EN_01
AB3 TXD4_01
AB4 TXD6_01
AB5 RXD6_01
AB6 COL_01
AB7 TXD1_11
AB8 TXD5_11
AB9 TXD2_11
AB10 COL_11
AB11 RX_DV_11
AB12 GND
AB13 TX_ER_31
AB14 TXC_31
AB15 CRS_21
Ball
Location S igna l N ame
AB16 AVDD1P8_2
AB17 COL_31
AB18 NC
AB19 TXD5_21
AB20 TXD0_21
AB21 TXD1_21
AB22 TXD2_21
AB23 TXD3_21
AB24 No Ball
AC1 No Ball
AC2 No Ball
AC3 TXD5_01
AC4 VDD5
AC5 RXD7_01
AC6 GND
AC7 TXD0_11
AC8 VDD5
AC9 TXD7_11
AC10 GND
AC11 RXD5_11
AC12 VDD5
AC13 VDD4
AC14 GND
AC15 GND
AC16 CRS_31
AC17 VDD4
AC18 TX_P_33
AC19 GND
AC20 TXC_21
AC21 VDD4
AC22 TX_EN_21
AC23 No Ball
AC24 No Ball
AD1 No Ball
AD2 No Ball
AD3 No Ball
AD4 NC
AD5 NC
Ball
Location Signal Name
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 35
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
AD6 TX_ER_11
AD7 TXC_11
AD8 TXD6_11
AD9 TXD3_11
AD10 RXD4_11
AD11 RXC_11
AD12 SYS_RST_L
AD13 TX_P_13
AD14 TX_N_13
AD15 COL_21
AD16 TXD4_21
AD17 TX_ER_21
AD18 TX_N_33
AD19 CLK125
AD20 AVDD2P5_1
AD21 GND
AD22 No Ball
AD23 No Ball
AD24 No Ball
Ball
Location Signal Name
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
36 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
37 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
4.0 Ball Assignments and Signal Descriptions
4.1 Namin g Con ve nt io ns
4.1.1 Signal Name Conventions
Si gnal names begin with a Signal Mnemonic, and can also contain one or more of the followi ng
designations: a differential pair designation, a serial designation, a port designation (RGMII
interface), and an active low designation. Signal naming conventions are a s fol lows :
Dif f erential Pair + Port Designation. The p ositive and negative componen ts of differ ential pairs
tied to a spec ific port are designated by the Signal Mnemonic, immediatel y f ollowed by an
unders core and either P (positive component) or N (negative component), and an unde rscore
f ollowed by the port designation. For e xample, SerDes interface sig nals for port 0 are i dentified as
TX_P_0 and TX_N_0.
Serial Designation. A set of signals that are not tied to any specific port are designated by the
Si gnal Mnemonic, followed by a bracketed serial designation. For example, the set of 11 CPU
Address Bus signals is id entified as UPX_ADD[10:0 ] .
Port Designation. Individual signals that apply to a particular port are designated by the Signal
Mnemonic, immediately followed by an underscore and the Port Desi gnation. For example,
RGMII Transmit Control signals are identified as TX_CTL_0, TX_CTL_1, TX_CTL_2, and so on.
Port Bu s Design ati on. A set of bus signals tha t apply to a particular port are designated by the
Signal Mne monic, immediately followed by a brackete d bus designation, followed by an
underscore and the port designation. For example, RGMII tra ns mit data bus signals are identified
as TD[3:0]_0, TD[3:0]_1, TD[3:0]_2, and so on.
Active Low Designation. A control input or indicat or output that is active Low is designated by a
f inal suf fi x c onsisti ng of an underscore followe d by an uppe r case “ L”. For example , the CPU c ycle
complete identifier is shown as UP X_ RDY_L.
4.1.2 Register Ad dress Conventi ons
Registers loca ted in on-ch ip mem ory are access ed using a registe r address, which is provided in
Hex notation. A Registe r Address is indicated by the dol lar sign ($), followed by the memory
location in Hex .
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 38
Document Number: 278757
Re vision N umber: 009
Re vision D ate: 27-Oct-2005
4.2 Interface Signal Groups
This section d escribes th e IXF1104 M A C signals in groups acco rding to the ass o ciated inter face or
function. Figure 4 shows the various interface s availab le on the IXF1104 MAC.
Figure 4. Interface Signals
TDAT[31:0]
TFCLK
TENB_0
TERR_0
TPRTY_0
TMOD[1:0]
TSX
TSOP_0
TEOP_0
TADR[1:0]
DTPA_0:3
STPA
PTPA
RDAT[31:0]
RFCLK
RENB_0
RVAL_0
RERR_0
RPRTY_0
RMOD[1:0]
RSX
RSOP_0
REOP_0
TMS
TDI
TDO
TCLK
MDIO
MDC
TXPAUSEADD[2:0]
TXPAUSEFR
UPX_WIDTH[1:0]
UPX_D AT A[ 31:0]
UPX_ADD[10:0]
UPX_BADD[1:0]
UPX_WR_L
UPX_RD_L
UPX_CS_L
UPX_RDY_L
LED_CLK
LED_DATA
LED_LATCH
SYS_RES_L
CLK125
MOD_DEF_0:3
TX_D ISABLE_0:3
TX_F AU LT_0:3
RX_LOS_0:3
TX_F AU LT_IN T
RX_LOS_IN T
MOD_DEF_INT
I
2
C_CLK
I
2
C_DATA_0:3
SPI3
Interface
JTA G
Interface
MDIO
Interface
Pause
Control
Interface
CPU
Interface
LED
Interface
System
In terface
GMII RGMII
GMII an d
RGMII
In terfaces*
* D ata an d clock ba ll s are sha red for
GMII and RG MII Interfaces
SerDes
In terface
Optical
Module
In terface
Si gnals*
*
** Thes e optic a l modu l e si gna ls
ar e m ulti plex ed on t he G M I I balls .
RX_P/N_0:3
TX_P/N_0:3
TRST_L
Intel
®
IXF1104
Media Acc ess
Controller
B3181-01
MPHYSPHY
TFCLK
TENB_0:3
TERR_0:3
TPRTY_0:3
TSOP_0:3
TEOP_0:3
TDAT[7:0]_0:3
TADR[1:0]
DTPA_0:3
PTPA
RDAT[7:0]_0:3
RFCLK
RENB_0:3
RVAL_0:3
RERR_0:3
RPRTY_0:3
RSOP_0:3
REOP_0:3
TXC_0:3
TXD[7:0]_3
TXC_0: 3
TD[3:0]_3
TXD[7:0]_2 TD[3:0]_2
TXD[7:0]_1 TD[3:0]_1
TXD[7:0]_0 TD[3:0]_0
TX_EN_0:3
TX_ER_0:3 TX_C TL_0:3
RXC_0:3 RXC _0:3
RXD[7:0]_3
RD[3:0]_3
RXD[7:0]_2 RD[3:0]_2RXD[7:0]_1 RD[3:0]_1
RXD[7:0]_0
RD[3:0]_0
RX_D V_0:3
RX_ER_0:3
CRS_0:3
COL_0:3
RX_CTL_0:3
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
39 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
4.3 Signal D escription Tables
The I/ O signals , power supplie s, or ground retur ns associa ted with eac h IXF1 104 MAC connec tion
ball are described in Table 3 thr ough Table 14.
Tab le 3. SPI3 Interface Signal Descript ions (Sheet 1 of 8)
Signal Name Ball
Designator Type Standard Description
MPHY SPHY
TDAT31
TDAT30
TDAT29
TDAT28
TDAT27
TDAT26
TDAT25
TDAT24
TDAT7_3
TDAT6_3
TDAT5_3
TDAT4_3
TDAT3_3
TDAT2_3
TDAT1_3
TDAT0_3
F7
F5
G9
G8
G7
G6
G5
G4
Input 3.3 V
LVTTL
Transmit D ata Bu s.
Carries payload data to the IXF1104 MAC
egress pat h.
Mode
32-bit Multi-PHY
4 x 8 Single-P HY
Bits
[31:24]
[7:0] for port 3
TDAT23
TDAT22
TDAT21
TDAT20
TDAT19
TDAT18
TDAT17
TDAT16
TDAT7_2
TDAT6_2
TDAT5_2
TDAT4_2
TDAT3_2
TDAT2_2
TDAT1_2
TDAT0_2
C8
F9
E10
E9
E8
E7
E6
E5
Input 3.3 V
LVTTL
Transmit D ata Bu s.
Carries payload data to the IXF1104 MAC
egress pat h.
Mode
32-bit Multi-PHY
4 x 8 Single-P HY
Bits
[23:16]
[7:0] for port 2
TDAT15
TDAT14
TDAT13
TDAT12
TDAT11
TDAT10
TDAT9
TDAT8
TDAT7_1
TDAT6_1
TDAT5_1
TDAT4_1
TDAT3_1
TDAT2_1
TDAT1_1
TDAT0_1
H3
J3
J2
J1
H1
G2
G1
F1
Input 3.3 V
LVTTL
Transmit D ata Bu s.
Carries payload data to the IXF1104 MAC
egress pat h.
Mode
32-bit Multi-PHY
4 x 8 Single-P HY
Bits
[15:8]
[7:0] for port 1
TDAT7
TDAT6
TDAT5
TDAT4
TDAT3
TDAT2
TDAT1
TDAT0
TDAT7_0
TDAT6_0
TDAT5_0
TDAT4_0
TDAT3_0
TDAT2_0
TDAT1_0
TDAT0_0
C6
B5
C5
C4
D1
C3
C2
B3
Input 3.3 V
LVTTL
Transmit D ata Bu s.
Carries payload data to the IXF1104 MAC
egress pat h.
Mode
32-bit Multi-PHY
4 x 8 Single-P HY
Bits
7:0]
[7:0] for port 0
TFCLK TFCLK D7 Input 3.3 V
LVTTL
Transmit C lock.
TFCLK is the clock associated w ith al l
transm it sign als. Data and cont rol lines are
samp le d on th e ris ing edg e of TFC LK
(frequency operation range 90 - 133 MHz).
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 40
Document Number: 278757
Re vision N umber: 009
Re vision D ate: 27-Oct-2005
TPRTY_0 TPRTY_0
TPRTY_1
TPRTY_2
TPRTY_3
D5
G3
B9
J6
Input 3.3 V
LVTTL
Transmit Parity.
TPRTY in dica te s odd parit y for the TD AT
bus. TPR TY i s valid only when a channel
asserts either TENB or TSX. Odd parity is
the default configuration; however, even
parity can be selected (see Tabl e 146 “SPI3
Transmit and Global Configuration
($0 x 70 0) ” on page 21 3).
3 2 -bit Multi- PHY mode: TPRTY_0 is the
par ity bit co ve r in g al l 32 bit s .
4 x 8 Single-PHY mode: TPRTY_0:3 bits
correspond to the respective TDAT[3:0]_n
channels.
TENB_0 TENB_0
TENB_1
TENB_2
TENB_3
B7
E2
C9
J4
Input 3.3 V
LVTTL
Transmit Write Enable.
TENB_ 0:3 asserted causes an att ached
PHY to proces s TDAT[n], TM OD , TSOP,
TEO P and TE RR si gnal s.
3 2 -bit Multi- PHY mode: TENB_0 is the
enable bit f or al l 32 bits .
4 x 8 Single-PHY mode: TENB_0:3 bits
correspond to the respective TDAT[3:0]_n
c hannels and their assoc iated control and
sta tus si gn als.
TERR_0 TERR_0
TERR_1
TERR_2
TERR_3
A8
K1
E11
J8
Input 3.3 V
LVTTL
Transmit Error.
TERR indicates that there is an error in the
current packet. TERR is valid when
s imult aneously a sserted with TEOP and
TENB.
3 2 -bit Multi- PHY mode: TERR_0 is the bi t
asserted for all 32 bits.
4 x 8 Single-PHY mode: Each bit of
TERR_0:3 corresponds to the respective
TDAT[3:0]_n channel.
TSOP_0 TSOP_0
TSOP_1
TSOP_2
TSOP_3
C7
E3
C10
J5
Input 3.3 V
LVTTL
Transmit Start-of -Packet.
TSO P indi ca t e s the start of a pac ke t an d is
valid when asserted simultaneously with
TENB.
3 2 -bit Multi- PHY mode: TSOP_0 is the bit
asserted for all 32 bits.
4 x 8 Single-PHY mode: Each bit of
TSOP_0:3 corresponds to the respective
TDAT[3:0]_n channel.
TEOP_0 TEOP_0
TEOP_1
TEOP_2
TEOP_3
A7
F3
E4
H5
Input 3.3 V
LVTTL
Transmit End-of-Packet.
TEOP indicates the end of a packet and is
valid when asserted simultaneously with
TENB.
3 2 -bit Multi- PHY mode: TEOP_0 is the bit
asserted for all 32 bits.
4 x 8 Single-PHY mode: Each bit of
TEOP_0:3 corresponds to the respective
TDAT[3:0]_n channel.
Table 3. SPI3 Interface Sig nal Description s (Sheet 2 of 8)
Signal Name Ball
Designator Type Standard Description
MPHY SPHY
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
41 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
TMOD1
TMOD0 NA D9
A6 Input 3.3 V
LVTTL
TMOD[1:0] Transmit Word Modulo.
32 -bit Mu lti- P HY mod e: TMOD[1:0]
indi cate s th e vali d data by tes of TDAT[31: 0].
During transmission, TMOD[1:0] should
always be “00” until the last double word is
transferred on TDAT[31:0]. TMOD[1:0]
specifies the valid bytes of TDAT when
TEO P is ass erted:
TMOD[1:0] – Valid Bytes of TDAT
00 =4 bytes [31:0]
01 =3 bytes [31:8]
10 =2 bytes [31:16]
11 =1 by te [31 :24]
TENB must be asserted simul taneous ly for
TM O D[1: 0] to be valid .
4 x 8 Sing le-PH Y mod e: MO D [1: 0] is not
required.
TSX NA E1 Input 3.3 V
LVTTL
Transmit Start of Transfer.
32-bit Multi-PHY mode: TSX asserted with
TENB = 1 indicates that the PHY address is
present on TDAT[7:0]. The valid values on
T DAT[7:0 ] are 3, 2, 1, an d 0. Wh en
TENB = 0, TSX is not used by the PHY
device.
NOTE: Only TDAT[1:0] are relevant; all
other bits are “Don’t Care”.
4 x 8 Sing le-PH Y mod e: TSX is no t used.
TADR1
TADR0 TADR1
TADR0 A12
A11 Input 3.3 V
LVTTL
TADR[1:0] T ransmit PHY Address.
The value on TADR[1:0] s elects one of the
PHY ports that drives the PTPA signal after
the rising edge of TFCLK.
Tab le 3. SPI3 Interface Signal Descript ions (Sheet 3 of 8)
Signal Name Ball
Designator Type Standard Description
MPHY SPHY
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 42
Document Number: 278757
Re vision N umber: 009
Re vision D ate: 27-Oct-2005
DTPA_0
DTPA_1
DTPA_2
DTPA_3
DTPA_0
DTPA_1
DTPA_2
DTPA_3
D3
L1
A9
J7
Output 3.3 V
LVTTL
DTPA_0:3 Di rect Transmit Packet
Available.
A direct status indication for transmit FI FOs
of ports 0:3.
Whe n High, DTPA indi cate s th at the amo unt
of data in the TX FIFO is below the TX FIFO
High watermark. When the High watermark
is crossed, DTP A transitions Low to indicate
that the TX FIFO is almost full. It stays Low
until the amount of data in the TX FIFO
goes back below the TX FIFO Low
watermark. At this point, DTPA transitions
High to indicate that the programmed
number of bytes are now available for data
transfers.
NOTE: For more information, see
Table 132 “TX FIFO High
Wate rmark Ports 0 - 3 ($0x600 –
0x603)” on page 203 and Table 133
“TX FIFO Low Watermark Register
Ports 0 - 3 ($0x60A – 0x60D)” on
page 204.
DTPA is updated on the rising edge of
TFCLK.
STPA NA C11 Output 3.3 V
LVTTL
Se lec t ed - PH Y Tra nsmit Packet Avai lable.
STPA is only me an in gful in a 32 - bi t mu l ti-
PHY mode.
STP A is a direct status indication for
transmit FIFOs of po rts 0:3.
Whe n Hi gh , STPA in di ca tes t h at t he a mou nt
of data in the TX FIFO, specified by the
latest in-band ad dress, is below the
TX FIFO High watermark. When the High
wa ter mark i s cr os sed, ST PA tran si ti ons Lo w
to indicate the TX FIFO is almost full. It
s tays Low until the amount of data in the
TX FIFO goes back below the TX FIFO Low
watermark. At this point, STPA transitions
High to indicate that the programmed
number of bytes are now available for data
transfers.
NOTE: For more information, see
Table 132 “TX FIFO High
Wate rmark Ports 0 - 3 ($0x600 –
0x603)” on page 203 and Table 133
“TX FIFO Low Watermark Register
Ports 0 - 3 ($0x60A – 0x60D)” on
page 204.
STP A provides the status indication for the
s electe d port to avoid FIFO overflows while
polling is performed. The port reported by
STPA is upd ate d on the follo w in g ris ing
edge of TFC LK after TSX is sampled as
asserted. STPA i s update d on the rising
edge of TFCLK.
Table 3. SPI3 Interface Sig nal Description s (Sheet 4 of 8)
Signal Name Ball
Designator Type Standard Description
MPHY SPHY
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
43 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
PTPA PTPA B11 Output 3.3 V
LVTTL
Polled-PHY Transmit Packet Available.
PTPA allows the polling of the port sele cted
by the TADR address bus .
When High, PTP A indicates that the amount
of da t a i n the TX FIF O i s be lo w th e T X FI F O
High watermark. When the High w atermark
is crossed, PTP A transitions Low to indicate
that the TX FIFO is almost full. It stays Low
until the amount data in the TX FIFO goes
bac k belo w the TX F IFO Low wat erm ar k. At
thi s po in t, PTPA tran siti on s Hig h to indic at e
that the programmed number of by tes are
now ava ila bl e for da ta t ran sfers .
NOTE: For more information, see
Table 132 “TX FIFO High
Watermark Ports 0 - 3 ($0x600 –
0x603)” on page 203 and Table 133
“TX FI FO Low Watermark Register
Ports 0 - 3 ($0x60A – 0x60D)” on
page 204.
The port reported by PTPA is updated on
the following rising edge of TFCLK after the
port address o n TADR is sampled by the
PHY device.
PTPA i s updated on the rising ed ge of
TFCLK.
RDAT31
RDAT30
RDAT29
RDAT28
RDAT27
RDAT26
RDAT25
RDAT24
RDAT7_3
RDAT6_3
RDAT5_3
RDAT4_3
RDAT3_3
RDAT2_3
RDAT1_3
RDAT0_3
F24
G24
G23
G22
G21
G20
G19
G18
Output 3.3 V
LVTTL
Receive Data Bus.
RDAT carries payload data and in-band
addresses from the IXF1104 MAC.
Mode
32-bit Multi-PHY
4 x 8 Single-P HY
Bits
[31:24]
[7:0] for port 3
RDAT23
RDAT22
RDAT21
RDAT20
RDAT19
RDAT18
RDAT17
RDAT16
RDAT7_2
RDAT6_2
RDAT5_2
RDAT4_2
RDAT3_2
RDAT2_2
RDAT1_2
RDAT0_2
E21
E22
D22
C22
C21
C20
B22
B20
Output 3.3 V
LVTTL
Receive Data Bus.
RDAT carries payload data and in-band
addresses from the IXF1104 MAC.
Mode
32-bit Multi-PHY
4 x 8 Single-P HY
Bits
[23:16]
[7:0] for port 2
RDAT15
RDAT14
RDAT13
RDAT12
RDAT11
RDAT10
RDAT9
RDAT8
RDAT7_1
RDAT6_1
RDAT5_1
RDAT4_1
RDAT3_1
RDAT2_1
RDAT1_1
RDAT0_1
F18
E18
E17
F16
E16
D16
C17
A17
Output 3.3 V
LVTTL
Receive Data Bus.
RDAT carries payload data and in-band
addresses from the IXF1104 MAC.
Mode
32-bit Multi-PHY
4 x 8 Single-P HY
Bits
[15:8]
[7:0] for port 1
Tab le 3. SPI3 Interface Signal Descript ions (Sheet 5 of 8)
Signal Name Ball
Designator Type Standard Description
MPHY SPHY
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 44
Document Number: 278757
Re vision N umber: 009
Re vision D ate: 27-Oct-2005
RDAT7
RDAT6
RDAT5
RDAT4
RDAT3
RDAT2
RDAT1
RDAT0
RDAT7_0
RDAT6_0
RDAT5_0
RDAT4_0
RDAT3_0
RDAT2_0
RDAT1_0
RDAT0_0
F14
E14
D14
C13
C14
B14
A14
A15
Output 3.3 V
LVTTL
Receive Data Bus.
RDAT carries payload da ta and in-ban d
address es from the IXF1104 MAC.
Mode
32-bit Multi-PHY
4 x 8 Sing le - PH Y
Bits
[7:0]
[7:0] for port 0
RFCLK RFCLK A19 Input 3.3 V
LVTTL
Receive Clock.
RF CLK is the clock associated with all
rec e iv e si gn als . Data and co ntrols are
driven on the rising edge of RFCLK
(frequency operation range 90 - 133 MHz).
RPRTY_0 RPRTY_0
RPRTY_1
RPRTY_2
RPRTY_3
E15
G16
E20
F20
Output 3.3 V
LVTTL
Receive Parity.
RP RTY in dicate s odd parity f or th e RDAT
bus. RPRTY is valid only when a channel
asserts RENB or RSX. Odd parity is the
default configuration; however, even parity
c an be selected (see Table 147 on
page 215).
3 2 -bit Multi- PHY mode: RPRT Y_0 is the
parity bit for al l 32 bits.
4 x 8 Single-PHY mode: Each bit of
RPRTY_0:3 corresponds to the respective
RDAT[3:0]_n channel.
RENB_0 RENB_0
RENB_1
RENB_2
RENB_3
A13
A18
C19
E24
Input 3.3 V
LVTTL
Receive Read Enable.
The RENB signal c ontrols the f low o f data
from the receive FIFO s. During data
transfer , RVAL must be monitored as it
indicates if the RDAT[31:0], RPRTY,
RMOD[1:0], RSOP, REOP, RERR, and RSX
are valid. The sy stem may de-assert RENB
at any time if it is unable to accept data from
the IXF1104 MAC. When RENB is sampled
Low, a read is performed from the receive
FIFO and the RDAT[31:0], RPRTY,
RMOD[1:0], RSOP, REOP, RERR, RSX and
RVAL signals are updated on the following
rising edge of RFCLK.
When RENB is sampled High by the PHY
device, a read is not performed, and the
RDA T[31:0], RPRTY, RMOD[1:0], RSOP,
REOP, RERR, RSX, and RVAL signals
remain unchanged on the following rising
edge of RFCLK.
3 2-bit Mul ti- PHY Mode : RENB_0 covers all
receive bits.
4 x 8 Single-PHY Mode: The RENB_0:3
bits correspond to the per-port data and
c ontrol signal s.
Table 3. SPI3 Interface Sig nal Description s (Sheet 6 of 8)
Signal Name Ball
Designator Type Standard Description
MPHY SPHY
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
45 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
RERR_0 RERR_0
RERR_1
RERR_2
RERR_3
A16
G17
D20
H20
Output 3.3 V
LVTTL
Receive Error.
RERR indicates that the current packet is in
error . RERR is only asserte d when REOP is
ass erted. Conditions that can cause RERR
to be set include FIFO overflow, CRC error,
code error, and runt or giant packets.
NOTE: RERR can only be set fo r these
conditions if bit 0 in the “SPI3
Receive Configuration ($0x 701) ” is
set to 1.
RERR is considered valid only when RVAL
is asserted.
32 -bit Mu lti- P HY mod e: RERR_0 covers
all 32 bits.
4 x 8 Sing le-PH Y mod e: The RERR_0:3
bits correspond to the RDAT[7:0]_n
channels.
(n = 0, 1, 2, or 3)
RVAL_0 RVAL_0
RVAL_1
RVAL_2
RVAL_3
C15
B18
E19
F22
Output 3.3 V
LVTTL
R ec eive D ata Vali d.
RVAL indicates the validity of the receive
data signals. RVAL is L ow betw een
transfers and assertion of RSX. It is also
Low when the IXF1104 MAC pauses a
t ran s f er du e to an emp ty receiv e FIF O.
When a tr ans fe r is p aused by hold ing R ENB
H igh , RVA L ho ld s its valu e unch an ged,
although no new data is pre s ent on
RDAT[31:0] until the transfer resumes .
When RVAL is High, the RDAT[ 31:0] ,
RMOD[1:0], RSOP, REOP, and RERR
signals are valid. When RVAL is Low, the
RDAT[31:0], RMOD[1:0], RSOP, REOP, and
RERR signals are invalid and mu st be
disregarded.
The RSX si gnal is valid on ly when RVAL is
Low.
32-bit Multi-PHY mode: RV AL_0 covers all
receive bi ts.
4 x 8 Sing le-PH Y mod e: The RVAL_0:3
bits correspond to the per-por t data and
control si gnal s.
RSOP_0 RSOP_0
RSOP_1
RSOP_2
RSOP_3
B16
C18
E23
J18
Output 3.3 V
LVTTL
Receive Start of Packet.
RSOP indicates the start of a packet when
asserted with RVAL.
32 -bit Mu lti- P HY mod e: RSOP_0 covers
all 32 bits.
4 x 8 Sing le-PH Y mod e: The RSOP_0:3
bits correspond to the RDAT[7:0]_n
channels.
Tab le 3. SPI3 Interface Signal Descript ions (Sheet 7 of 8)
Signal Name Ball
Designator Type Standard Description
MPHY SPHY
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
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REOP_0 REOP_0
REOP_1
REOP_2
REOP_3
C16
D18
C23
J19
Output 3.3 V
LVTTL
Receive End of Packet.
RE O P indicates the end of a packet when
asserted with RVAL.
3 2 -bit Multi- PHY mode: REOP_0 co vers
all 32 bit s.
4 x 8 Single-PHY mode: The REOP_0 :3
bits correspond to the RDAT[7:0]_n
channels.
RMOD1
RMOD0 NA G13
G14 Output 3.3 V
LVTTL
Rece ive Word Modulo:
3 2 -bit Multi- PHY mode: RMOD [1: 0]
indicates the valid bytes of data in
RDAT[31:0]. During transmission, RMOD is
always “00”, except when the last double-
word is transferred on RDAT[31:0].
RMOD[1:0] specifies the valid packet data
bytes on RDAT[31:0] when REOP is
asserted.
RMO D [1: 0] Valid Byte s of RDAT
00 =4 bytes [31:0]
01 =3 bytes [31:8]
10 =2 bytes [31:16]
11 = 1 byte [31:24]
4 x 8 Single-PHY mode: RMOD[1:0] is not
required.
RMOD is considered valid only when RVAL
is simultaneously asserted.
RENB must be asserted for RMOD[1:0] to
be valid.
RSX NA E13 Output 3.3 V
LVTTL
Receive Start of Transfer.
3 2 -bit Multi- PHY mode: RSX indicates
wh en the in - band po rt add r ess i s p rese nt o n
the RDAT bus. When RSX is High and
RVAL = 0, the value of RDAT[7:0] is the
address of the receive FIFO to be selected.
Subsequent data transfers on RDAT are
from the FIFO speci fied by this in-ban d
addr e s s. Val ue s of 0, 1, 2, an d 3 sel ec t the
corresponding port. RSX is ignored when
RVAL is de-a sserted.
4 x 8 Single-PHY mode: RSX is ignored.
Table 3. SPI3 Interface Sig nal Description s (Sheet 8 of 8)
Signal Name Ball
Designator Type Standard Description
MPHY SPHY
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
47 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Tab le 4. SerDes Interface Sig nal Descriptions
Signa l N ame B a ll Des ign ato r Typ e Stan da rd Descriptio n
TX_P_0
TX_P_1
TX_P_2
TX_P_3
Y13
AD13
W16
AC18
Output SerDes Transmit Differential Output, Positive.
TX_N_0
TX_N_1
TX_N_2
TX_N_3
Y14
AD14
Y16
AD18
Output SerDes Transmit Differential Output, Negative.
RX_P_0
RX_P_1
RX_P_2
RX_P_3
P22
V22
T24
U24
Input SerDes Receive Differential Input, Positive.1
RX_N_0
RX_N_1
RX_N_2
RX_N_3
R22
U22
R24
V24
Input SerDes Receive Differential Input, Negative.1
1. Internally terminated differentially with 100 Ω.
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Table 5. GMII Interface Signal Descriptions (Sheet 1 of 2)
Signal Name Ball Designator Type Sta ndard Description
TXD7_0
TXD6_0
TXD5_0
TXD4_0
TXD3_0
TXD2_0
TXD1_0
TXD0_0
TXD7_1
TXD6_1
TXD5_1
TXD4_1
TXD3_1
TXD2_1
TXD1_1
TXD0_1
TXD7_2
TXD6_2
TXD5_2
TXD4_2
TXD3_2
TXD2_2
TXD1_2
TXD0_2
TXD7_3
TXD6_3
TXD5_3
TXD4_3
TXD3_3
TXD2_3
TXD1_3
TXD0_3
Y4
AB4
AC3
AB3
AA3
Y3
Y2
Y1
AC9
AD8
AB8
AA7
AD9
AB9
AB7
AC7
AA18
AA20
AB19
AD16
AB23
AB22
AB21
AB20
W14
AA16
Y15
AA14
V17
V16
V15
V14
Output 2.5 V
CMOS
Transmit D ata .
Each bus carries eight data bits [7:0] of
the transmitted data stream to the PHY
device.
RGMII Mode: When a port is
configu red in copper mode and the
RGMII interface is selected, only bits
TXD[3:0]_n a re used. The data is
transmitted on both ed ges of TXC_0 :3.
Fiber Mode : The follo w in g si gnal s
have multiplexed functions when a port
is configured in fiber mode:
TXD4_n: TX_ DISA BLE_0 :3
TX_EN_0
TX_EN_1
TX_EN_2
TX_EN_3
AB2
Y8
AC22
V12
Output 2.5 V
CMOS
Transmit Enable.
TX_EN indicates that valid data is
being drive n on the corr es p on ding
T ransmit Data : TXD_0, TXD_1, T XD_2,
and TXD_3.
TX_ER_0
TX_ER_1
TX_ER_2
TX_ER_3
W1
AD6
AD17
AB13
Output 2.5 V
CMOS
Transmit Error:
TX_ER indicates a transmit error in the
corresponding Transmit Data: TXD _0,
TXD_1, TXD_2, and TXD_3.
TXC_0
TXC_1
TXC_2
TXC_3
AA1
AD7
AC20
AB14
Output 2.5 V
CMOS
Source Synchronous Transmit
Clock.
This clock is supplie d synchr onous t o
the transmit data bus in either RGMII or
GMII mode.
NOTE: Sha res t h e same b al l s as RXC
on the RGMII interface.
NOTE: R efer to th e RGMI I interfa c e for shared data and clock signals.
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
49 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
RXD7_0
RXD6_0
RXD5_0
RXD4_0
RXD3_0
RXD2_0
RXD1_0
RXD0_0
RXD7_1
RXD6_1
RXD5_1
RXD4_1
RXD3_1
RXD2_1
RXD1_1
RXD0_1
RXD7_2
RXD6_2
RXD5_2
RXD4_2
RXD3_2
RXD2_2
RXD1_2
RXD0_2
RXD7_3
RXD6_3
RXD5_3
RXD4_3
RXD3_3
RXD2_3
RXD1_3
RXD0_3
AC5
AB5
Y5
Y6
Y7
W7
V7
V8
Y10
AA11
AC11
AD10
W9
W11
Y11
Y9
W20
V19
V20
W22
Y23
Y22
Y21
Y20
T19
T18
T17
T16
W18
Y19
Y18
Y17
Input 2.5 V
CMOS
Receive Data:
Each bus carries eight data bits [7:0] of
the received data str eam.
RGMII Mode: When a port ID is
configured in copper mode and the
RGMII interface is selected, only bits
RXD[3:0]_n are used to receive data.
Fiber Mode: T he following signals
hav e mul t ip lexe d fu nc tion s w hen a port
is confi gured in fiber mode:
RXD4_n: MOD_DEF_0:3
RXD5_n: TX_FAULT_0:3
RXD6_n: RX_LOS_0:3
RX_DV_0
RX_DV_1
RX_DV_2
RX_DV_3
V5
AB11
Y24
V18
Input 2.5 V
CMOS
Receive Data Vali d.
RX_DV indicates that valid data is
being driven on Receive D ata:
RXD[7:0]_n.
RX_ER_0
RX_ER_1
RX_ER_2
RX_ER_3
W5
Y12
AA22
U20
Input 2.5 V
CMOS
Receive Error.
RX_ER indicates an error in Receive
Data: RXD[7: 0]_n.
CRS_0
CRS_1
CRS_2
CRS_3
AA5
AA9
AB15
AC16
Input 2.5 V
CMOS
Carrier Sense.
CRS indicates the PHY device has
det ec te d a ca r rie r.
RXC_0
RXC_1
RXC_2
RXC_3
V4
AD11
AA24
V23
Input 2.5 V
CMOS
Receiver Refere nce Clock.
RX C operates at:
125 MHz for 1 G igabit
NOTE: S h ares th e s ame ba ll s a s RXC
on the RGMII interface.
Table 5. GM II Interface Signal Descriptions (Sheet 2 of 2)
Signal Name Bal l Designator Ty pe Standard Description
NOTE: Refer to the RGMII interface for shared data and clock si gnals.
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Table 6. RGMI I Interface Signal Descripti ons (Sheet 1 of 2)
Signal Name Ball
Designator Type Standard Description
TXC_0
TXC_1
TXC_2
TXC_3
AA1
AD7
AC20
AB14
Output 2.5 V
CMOS
Source Synchronous Transmit Clock.
Thi s cl oc k is sup plie d sy nch r on ou s to th e tr an sm it
data bus in either RGMII or GMII mode.
TD3_0
TD2_0
TD1_0
TD0_0
TD3_1
TD2_1
TD1_1
TD0_1
TD3_2
TD2_2
TD1_2
TD0_2
TD3_3
TD2_3
TD1_3
TD0_3
AA3
Y3
Y2
Y1
AD9
AB9
AB7
AC7
AB23
AB22
AB21
AB20
V17
V16
V15
V14
Output 2.5 V
CMOS
Transmit Data.
Bits [3:0] are clocked on the rising edge of TXC.
Bits [7:4] are clocked on the falling edge of TXC.
NOTE: Shares da ta signals TXD[ 3:0]_n with the
GMII interface.
TX_CTL_0
TX_CTL_1
TX_CTL_2
TX_CTL_3
AB2
Y8
AC22
V12
Output 2.5 V
CMOS
Tra nsm it C ont rol.
TX _CT L is T X_E N on t he r is in g ed ge of T XC an d a
logical derivativ e of TX_EN and TX_ER on the
falling edg e of TXC.
NOTE: TX_CTL multiplexes with TX_EN_n o n the
GMII interface.
RXC_0
RXC_1
RXC_2
RXC_3
V4
AD11
AA24
V23
Input 2. 5 V
CMOS
Receiver Reference Clock.
Operates at:
125 MHz for 1 G igabit
25 MHz for 10 0 Mb ps
2.5 MHz for 10 Mbps
NOTE: Shares the same balls as RXC on the
GMII interface.
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
51 Datasheet
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Revision Number: 009
Revision Date: 27-Oct-2005
RD3_0
RD2_0
RD1_0
RD0_0
RD3_1
RD2_1
RD1_1
RD0_1
RD3_2
RD2_2
RD1_2
RD0_2
RD3_3
RD2_3
RD1_3
RD0_3
Y7
W7
V7
V8
W9
W11
Y11
Y9
Y23
Y22
Y21
Y20
W18
Y19
Y18
Y17
Input 2.5 V
CMOS
Receive Data.
Bits [3:0] are cloc ked on th e risin g edge of RXC.
Bits [7:4] are cloc ked on th e falli ng edge of RXC.
NOTE: Shares balls with RXD[3:0]_0 on the GMII
interface.
RX_CTL_0
RX_CTL_1
RX_CTL_2
RX_CTL_3
V5
AB11
Y24
V18
Input 2.5 V
CMOS
Receive Control.
RX_CTL is RX_DV on the rising edge of RXC and
a logic al de r iv at iv e of R X_D V and R ER R on the
falling edge of RXC.
NOTE: RX_C TL shar es the sa me bal ls as RX _DV
on the GMII int er f ac e.
Table 7. CPU Interface Signal Descript ions (Sheet 1 of 2)
Signa l N ame Ball
Designator Type Standard Description
UPX_ADD10
UPX_ADD9
UPX_ADD8
UPX_ADD7
UPX_ADD6
UPX_ADD5
UPX_ADD4
UPX_ADD3
UPX_ADD2
UPX_ADD1
UPX_ADD0
T3
U3
V3
V2
V1
U1
T1
R1
P1
N1
P3
Input 3.3 V LVTTL UPX_ADD is the address bus from the
microprocessor.
UPX_BADD1
UPX_BADD0 W3
T2 Input 3.3 V LVTTL
16-bit mode: Th e data word select uses
UPX_BADD1.
8-bit mode: UPX_BADD[ 1:0] s elect s t he indivi dual
bytes.
Tab le 6. RGMII Interface Signal Descri ptions (Sheet 2 of 2)
Signa l N ame Ball
Designator Type Standard Description
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
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UPX_DATA31
UPX_DATA30
UPX_DATA29
UPX_DATA28
UPX_DATA27
UPX_DATA26
UPX_DATA25
UPX_DATA24
UPX_DATA23
UPX_DATA22
UPX_DATA21
UPX_DATA20
UPX_DATA19
UPX_DATA18
UPX_DATA17
UPX_DATA16
UPX_DATA15
UPX_DATA14
UPX_DATA13
UPX_DATA12
UPX_DATA11
UPX_DATA10
UPX_DATA9
UPX_DATA8
UPX_DATA7
UPX_DATA6
UPX_DATA5
UPX_DATA4
UPX_DATA3
UPX_DATA2
UPX_DATA1
UPX_DATA0
L17
J17
H16
J16
M15
N15
K15
H14
K13
G12
K12
G11
H11
G10
K10
M10
N10
J9
H9
L8
N7
L7
L6
P5
K5
M5
N5
L4
M3
L3
K3
L2
Input/
Output 3.3 V LV TTL
Data bus.
32- bit mo de: Uses [31:0]
16- bit mo de: Uses [15:0]
8-bit mode: Use s [7:0]
UPX_CS_L R3 Input 3.3 V LV TTL Chip Select. Active Low.
UPX_WR_L T4 Input 3.3 V LVTTL Write Strobe. Active Low .
UPX_R D_L V 6 In p ut 3.3 V LVTTL Read Strobe. Active Low.
UPX_RDY_L M1 Open
Drain
Output* 3 .3 V LVTTL
Cyc le co mp lete indic at or.
Active Low.
NOTE: An external pull-up resistor is required for
proper operation.
NOTE: *D ua l-m od e I/O
Norm al ope rati on: Op en drai n output
Boundary Scan Mode: Standard CMOS
output
UPX_WIDTH1
UPX_WIDTH0 T5
U16 Input 3.3 V LVTTL
Data bus width select.
UPX_WIDTH[1:0] specifies the CPU bus width.
UPX_WIDTH[1:0]
00
01
1x
Mode
8-bit
16-bit
32-bit
Table 7. CPU Interface Signal Descript ions (Sheet 2 of 2)
Signal Name Ball
Designator Type Standard Description
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
53 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Tab le 8. Transm it Pause Control Interface S ignal Descri ptions
Signa l N ame Ball
Designator Type Standard Description
TXPAUSEADD2
TXPAUSEADD1
TXPAUSEADD0
P21
P20
N20 Input 2.5 V
CMOS TXPAUSEADD[2:0] is the port selection address
for pause frame insertion.
TXPAUSEFR T20 Input 2.5 V
CMOS TX Pause Interface Strobe.
Tab le 9. Optical Module Interface S ignal Descripti ons (Sheet 1 of 2)
Signa l N ame Ball
Designator Type Standard Description
TX_DISABLE_0
TX_DISABLE_1
TX_DISABLE_2
TX_DISABLE_3
AB3
AA7
AD16
AA14
Open
Drain
Output*
2. 5 V
CMOS
Transmit D isa b l e:
TX_DISABLE_0:3 output s disable the Optical
Module Interface transmitter. An external pull-up
resistor usua lly resident in an optical module is
required for proper operation.
NOTE: These signals are m ultip lexed with the
TXD[4]_n bits of the GMII Interface
NOTE: *Dual-mode I/O
Normal operation: Open drain output
Boundary Scan Mod e: Standard CMOS
output
MOD_DEF_0
MOD_DEF_1
MOD_DEF_2
MOD_DEF_3
Y6
AD10
W22
T16
Input 2. 5 V
CMOS
MOD_D EF_0:3 inputs determine when an
Optical Module Interface is present.
NOTE: These signals are m ultip lexed with the
RXD[4]_n bits of the GMII interface.
RX_LOS_0
RX_LOS_1
RX_LOS_2
RX_LOS_3
AB5
AA11
V19
T18
Input 2. 5 V
CMOS
RX_LOS_0:3 inputs determine when the Optical
Module Interface receiver loses synchronization.
NOTE: These signals are m ultip lexed with the
RXD[6]_n bits of the GMII interface.
TX_FAULT_0
TX_FAULT_1
TX_FAULT_2
TX_FAULT_3
Y5
AC11
V20
T17
Input 2. 5 V
CMOS
TX_FAULT_0:3 inputs determine an Optical
Module Interface transmitter fault.
NOTE: These signals are m ultip lexed with the
RXD[5]_n bits of the GMII Interface.
RX_LOS_INT P19 Open
Drain
Output*
2. 5 V
CMOS
Re c eiver Los s of Signa l Inte rr upt .
RX_LOS_INT is an open drain interrupt output to
sig nal an RX_ LO S co nd itio n.
NOTE: An external pull-up resistor is required
for proper operation.
NOTE: *Dual-mode I/O
Normal operation: Open drain output
Boundary Scan Mod e: Standard CMOS
output
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TX_FAULT_INT P23 Open
Drain
Output*
2.5 V
CMOS
Transmitter Fault Interrupt.
TX_FAULT_INT is an open dr ain interr upt output
th at si gnal s a TX _FAULT con di tion.
NOTE: An external pull-up resistor is
required for proper operation.
NOTE: *Dual-mode I/O
Normal operation: Open drain output
Boundary Scan Mode: Standard CMOS
output
MOD_DEF_INT N22 Open
Drain
Output*
2.5 V
CMOS
Modu le Definiti on Int e rrupt.
MOD_DEF_INT is an open drain interrupt output
th at si gnal s a MO D_D EF cond ition .
NOTE: An external pull-up resistor is
required for proper operation.
NOTE: *Dual-mode I/O
Normal operation: Open drain output
Boundary Scan Mode: Standard CMOS
output
I2C_CLK L23 Output 2.5 V
CMOS I2C_CLK is the clock used for the I2C bus
interface.
I2C DATA_0
I2C DATA_1
I2C DATA_2
I2C DATA_3
L24
M24
N24
P24
Input/
Open
Drain
Output*
2.5 V
CMOS
I2C Data Bus.
I2C DATA_0:3 are the data I/Os for the I2C bus
interface.
NOTE: An external pull-up resistor is
required for proper operation.
NOTE: *Dual-mode I/O
Normal operation: Input/ open dr ain
output
Boundary Scan Mode: Standard CMOS
output
Table 10. MDIO Interface Signal Descriptions
Signal Name Ball
Designator Type Standard Description
MDIO V21 Input/
Output 2.5 V
CMOS
MDIO is the management data input and output.
NOTE: An external pull-up resistor is required for
pr op er op era t i on .
MDC W24 Output 2.5 V
CMOS MD C is the mana gement cl ock to ex ternal devices.
Table 9. Op tical Modu le Interface Signa l Descrip tions (Sheet 2 of 2)
Signal Name Ball
Designator Type Standard Description
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
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Revision Date: 27-Oct-2005
Tab le 11. LED Interface Signal Descriptions
Signa l N ame Ball
Designator Type Standard Description
LED_CLK K24 Output 2.5 V
CMOS LED_CLK is the clock output for the LED block.
LED_DATA M22 Output 2.5 V
CMOS LED_DATA is the data output for the LED block.
LED_LATCH L22 Output 2.5 V
CMOS LED_LATCH is the latch enable for the LED block.
Table 12. JTAG Interface Signal Descriptions
Signa l N ame Ball
Designator Type Standard Description
TCLK J22 Input 3.3 V
LVTTL JTAG Test Clock
TMS H22 Input 3.3 V
LVTTL Test Mode Select
TDI J24 Input 3.3 V
LVTTL Test Data Input
TDO H24 Output 3.3 V
LVTTL Test Data Output
TRST_L J23 Input 3.3 V
LVTTL Te s t Rese t; rese t inp ut for JTAG test
Table 13. System Interface Signal Descriptions
Signa l N ame Ball
Designator Type Standard Description
CLK125 AD19 Input 2.5 V
CMOS CLK125 is the input clock to PLL; 125 MHz +/-
50 ppm
SYS_RES_L AD12 Input 2.5 V
CMOS SYS_RES_L is the system hard reset (active Low).
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Table 14. Power Supply Signal Descriptions
Signal Name Ball Designator Ty pe Standard Description
GND
A4
B15
D12
F2
F19
H12
J10
K9
K19
L12
M4
M17
N11
P10
R2
R11
R23
U8
U21
W15
AA8
AA21
AC14
A21
B19
D13
F6
F23
H13
J15
K11
K23
L13
M8
M21
N14
P12
R6
R14
T10
U12
W2
W19
AA12
AB12
AC15
B6
D4
D17
F10
H4
H17
K2
K14
L5
L15
M11
N4
N17
P13
R7
R16
T15
U13
W6
W23
AA13
AC6
AC19
B10
D8
D21
F15
H8
H21
K6
K16
L10
L20
M14
N8
N21
P15
R9
R19
U4
U17
W10
AA4
AA17
AC10
AD21
Input – Digi tal ground
AVDD1P8_1 A5 A20 Input 1.8 V Analog 1.8 V supply
AVDD1P8_2 AB16 T23 Input 1.8 V Analog 1.8 V supply
AVDD2P5_1 AD20 Input 2.5 V Analog 2.5 V supply
AVDD2P5_2 U14 R18 Input 2.5 V Analog 2.5 V supply
VDD
A10
D11
F21
J14
K17
L14
P14
R17
U10
AA6
C12
D15
H10
J20
K21
L16
P16
R21
U15
AA10
D6
D19
H15
K4
L9
P9
R4
T11
W4
AA15
D10
F4
J11
K8
L11
P11
R8
T14
W21
AA19
Input 1.8 V Di gital 1.8 V supply
VDD2
B4
F8
J12
M12
B8
F12
M2
B12
H2
M6
D2
H6
M9 Input 3.3 V Di gital 3.3 V supply
VDD3
B13
F13
J13
M23
B17
F17
M13
B21
H19
M16
D23
H23
M19 Input 3.3 V Di gital 3.3 V supply
VDD4
N13
T13
W17
AC21
N16
U19
AA23
N19
U23
AC13
N23
W13
AC17 Inpu t 2.5 V Digital 2.5 V supply
VDD5
N2
T12
W12
AC12
N6
U2
AA2
N9
U6
AC4
N12
W8
AC8 Input 2.5 V Digital 2.5 V supply
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4.4 Ball Usage Summary
Table 15. Ball Usage Summa ry
Type Quantity
Inputs 158
Outputs 126
Bi-directional 37
Total Signals 321
Power 75
Ground 82
No Connects 74
Total 552
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4.5 Multiplexed Ball Connections
4.5.1 GMII/RGMII/SerDes/OMI Multiplexed Ball Connections
Table 16 lists the balls us ed for the line- si de i nterfaces (GMII, RGMII, SerDes/OMI) a nd provides
a guide to connect these balls. Some of these bal ls are multiplexed depend ing on the mod e of
operatio n select ed for that port.
Note: Do not connect any ball s marked as unused (NC).
Table 16. Line Side Interface Multiplexed Balls ( Sheet 1 of 2)
Copper Mode Fiber Mode
Unused Port Ball Designator
GMII Signal RGMII Signal Optical Module/
SerDes Sig nal
TXC_0:3 TXC_0:3 NC NC AA1 AD7 AC20 AB14
TXD[3:0]_0
TXD[3:0]_1
TXD[3:0]_2
TXD[3:0]_3
TD[3:0]_0
TD[3:0]_1
TD[3:0]_2
TD[3:0]_3
NC NC
AA3
AD9
AB23
V17
Y3
AB9
AB22
V16
Y2
AB7
AB21
V15
Y1
AC7
AB20
V14
TXD4_0:3 NC TX_DISABLE_0:32NC AB3 AA7 AD16 AA14
TXD[7:5]_0
TXD[7:5]_1
TXD[7:5]_2
TXD[7:5]_3
NC NC NC
Y4
AC9
AA18
W14
AB4
AD8
AA20
AA16
AC3
AB8
AB19
Y15
TX_EN_0:3 TX_CTL_0:3 NC NC AB2 Y8 AC22 V12
TX_ER_0:3 NC NC NC W1 AD6 AD17 AB13
RXC_0:3 RXC_0:3 GND GND V4 AD11 AA24 V23
RXD[3:0]_0
RXD[3:0]_1
RXD[3:0]_2
RXD[3:0]_3
RD[3:0]_0
RD[3:0]_1
RD[3:0]_2
RD[3:0]_3
GND GND
Y7
W9
Y23
W18
W7
W11
Y22
Y19
V7
Y11
Y21
Y18
V8
Y9
Y20
Y17
RXD4_0:3 GND MOD_DEF_0:31GND Y6 AD10 W22 T16
RXD5_0:3 GND TX_FAULT_0:31GND Y5 AC11 V20 T17
RXD6_0:3 GND RX_LOS_0:31GND AB5 AA11 V19 T18
RXD7_0:3 GND GND GND AC5 Y10 W20 T19
RX_DV_0:3 RX_CTL_0:3 GND GND V5 AB11 Y24 V18
RX_ER_0:3 GND GND GND W5 Y12 AA22 U20
CRS_0:3 GND GND GND AA5 AA9 AB15 AC16
COL_0:3 GND GND GND AB6 AB10 AD15 AB17
GND GND RX_P_0:3 GND P22 V22 T24 U24
GND GND RX_N_0:3 GND R22 U22 R24 V24
NC NC TX_P_0:3 NC Y13 AD13 W16 AC18
NC NC TX_N_0:3 NC Y14 AD14 Y16 AD18
1. An external pull-up resistor is required with most optical modules.
2. An open drain I/O, external 4.7 k Ω pull-up re sistor is required.
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
59 Datasheet
Document Number: 278757
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4.5.2 SPI3 MPHY/SPHY Ball Connections
Table 17 lists the balls used for the SPI3 Interface and provides a guide to connect these balls in
MPHY and SPHY mode.
NC NC TX_FAULT_INT2NC P23
NC NC RX_LOS_INT2NC P19
NC NC MOD_DEF_INT2NC N22
MDC MDC NC NC W24
MDIO2MDIO2NC NC V21
NC NC I2C_CLK NC L23
NC NC I2C_DATA_0:32NC L24 M24 N24 P24
Table 16. Line Side Interface Multiplexed Balls (Sheet 2 of 2)
Copper M ode Fiber Mode
Unused Port Ball Designator
GM II Sig nal R GMII Signa l O pti ca l Modu l e/
SerDes Signal
1. An external pull-up resistor is required with most optical modules.
2. An open drain I/O, ext ernal 4.7 k Ω pull-up resistor is required.
Table 17. SPI3 MPHY/SPHY Interf ace (Sheet 1 of 3)
SP I3 Signal s Ball Number Comments
MPHY SPHY
TDAT[31:24] TDAT[7:0]_3 F7
G7 F5
G6 G9
G5 G8
G4
MPHY: Co nsists of a single 32-bit data
bus
SPHY: Separate 8-bit data bus for each
Ethernet port
TDAT[23:16] TDAT[7:0]_2 C8
E8 F9
E7 E10
E6 E9
E5
TDAT[15:8] TDAT[7:0]_1 H3
H1 J3
G2 J2
G1 J1
F1
TDAT[7:0] TDAT[7:0]_0 C6
D1 B5
C3 C5
C2 C4
B3
TFCLK TFCLK D7
To achi eve maximum bandwidth, set
TFCLK as follows:
MPHY: 13 3 MHz
SPHY: 125 MHz.
TPRTY_0 TPRTY_0 D5 MPHY: Use TPRTY_0 as the TPRTY
signal.
SPHY: Each port has its own dedicated
TPRTY_n si gn al.
GND TPRTY_1 G3
GND TPRTY_2 B9
GND TPRTY_3 J6
TENB_0 TENB_0 B7 MPHY: Use TENB_0 as the TENB
signal.
SPHY: Each port has its own dedicated
TENB_n signal.
VDD2 TENB_1 E2
VDD2 TENB_2 C9
VDD2 TENB_3 J4
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TERR_0 TERR_0 A8 MPHY: U s e TE RR _ 0 as the T ER R
signal.
SPHY: Each port has its own dedicated
TERR_n signal
GND TERR_1 K1
GND TERR_2 E11
GND TERR_3 J8
TSOP_0 TSOP_0 C7 MPHY: Use TS O P_ 0 as the T SO P
signal.
SPHY: Each port has a dedicated
TSOP_n signal.
GND TSOP_1 E3
GND TSOP_2 C10
GND TSOP_3 J5
TEOP_0 TEOP_0 A7 MPHY: U s e TE OP _ 0 as the TE O P
signal.
SPHY: Each port has a dedicated
TEOP_n signal.
GND TEOP_1 F3
GND TEOP_2 E4
GND TEOP_3 H5
TMOD[1:0] GND D9 A6 TSX a nd TM OD[1 : 0] ar e on ly app lic abl e
in MPHY mode.
TSX GND E1
TADR[1:0] TADR[1:0] A12 A11 Used to address port for PTPA signal.
PTPA PTPA B11 PTPA can be use d in MPHY and SPH Y
modes.
DTPA_0:3 DTPA_0:3 D3 L1 A9 J7 DTPA is available on a per-port basis in
both MPHY and SPHY modes.
STPA NC C11 STPA is only applicable in MP HY mode.
RDAT[31:24] RDAT[7:0]_3 F24
G21 G24
G20 G23
G19 G22
G18
MPHY: Consists of a single 32 bit data
bus.
SPHY: Separate 8-bit data bus for each
Ethernet port.
RDAT[23:16] RDAT[7:0]_2 E21
C21 E22
C20 D22
B22 C22
B20
RDAT[15:8] RDAT[7:0]_1 F18
E16 E18
D16 E17
C17 F16
A17
RDAT[7:0] RDAT[7:0]_0 F14
C14 E14
B14 D14
A15 C13
A14,
RFCLK RFCLK A19
To achieve maximum bandwidth, set
RFCLK as follows:
MPHY: 133 MH z.
SPHY: 12 5 M H z .
RPRTY_0 RPRTY_0 E15 MPHY: U s e RP RTY_0 as the RPRTY
signal.
SPHY: Each port has a dedicated
RPRTY_n sign al .
NC RPRTY_1 G16
NC RPRTY_2 E20
NC RPRTY_3 F20
RENB_0 RENB_0 A13 MPHY: Use RENB_0 as the RENB
signal.
SPHY: Each port has a dedicated
RENB_n signal
VDD2 RENB_1 A18
VDD2 RENB_2 C19
VDD2 RENB_3 E24
Table 17. SPI3 MPHY/SPHY Interface (Sheet 2 of 3)
SPI3 Signals Ball Number Comment s
MPHY SPHY
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Document Number: 278757
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4.6 Ball State During Rese t
RERR_0 RERR_0 A16 MPHY : Use RERR_0 as the RERR
signal.
SPHY: Each port has a dedic ated
RERR_n signal
NC RERR_1 G17
NC RERR_2 D20
NC RERR_3 H20
RVAL_0 RVAL_0 C15 MPHY: Use RVAL_0 as the RVAL
signal.
SPHY: Each port has a dedic ated
RVAL_n signal.
NC RVAL_1 B18
NC RVAL_2 E19
NC RVAL_3 F22
RSOP_0 RSOP_0 B16 MPHY: Us e TSOP_0 as the TSOP
signal.
SPHY: Each port has a dedic ated
TSOP_n signal .
NC RSOP_1 C18
NC RSOP_2 E23
NC RSOP_3 J18
REOP_0 REOP_0 C16 MPHY: Use TEOP_ 0 as the TEOP
signal.
SPHY: Each port has a dedic ated
TEOP_n signal .
NC REOP_1 D18
NC REOP_2 C23
NC REOP_3 J19
RMOD[1:0] NC G13 G14 RS X and RMOD[1:0] are appl icable
only in MPHY mode.
RSX NC E13
Table 18. Definition of Output and Bi-directional Balls During Hardware Reset (Sheet 1 of 2)
Interface Ball Name Ball Reset State Comment
SPI3
DTPA_0:3 0x0 –
STPA 0x0 –
PTPA 0x0 –
RDAT[31:0] 0x00000000 –
RVAL_0:3 0x0 –
RERR_0:3 0x0 –
RPRTY_0:3 0x0 –
RMOD[1:0] 0x0 –
RSX 0x0 –
RSOP_0:3 0x0 –
REOP_0:3 0x0 –
NOTE: Z = High impedance.
Table 17. SPI3 MPHY/SPHY Interf ace (Sheet 3 of 3)
SP I3 Signal s Ball Number Comments
MPHY SPHY
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JTAG TDO 0x0 –
MDIO MDIO High Z Bi-directional
MDC 0x0 –
CPU UPX_DATA[31:0] High Z Bi-directional
UPX_RDY_L 0X1 Open-drain output, requires an external pull-up
LED
LED_CLK 0x0 –
LED_DATA 0x0 –
LED_LATCH 0x0 –
GMII/RGMII
TXC_0:3 High Z Fiber mode is the default. Copper interfaces are
disabled.
TXD[7:0]_0 High Z Fiber mode is the default.
Bit 4 is driven by the optical modu le as MOD_ DEF_0.
TXD[7:0]_1 High Z Fiber mode is the default.
Bit 4 is driven by the optical modu le as MOD_ DEF_1.
TXD[7:0]_2 High Z Fiber mode is the default.
Bit 4 is driven by the optical modu le as MOD_ DEF_2.
TXD[7:0]_3 High Z Fiber mode is the default.
Bit 4 is driven by the optical modu le as MOD_ DEF_3.
TX_EN_0:3 High Z Fiber mode is the default.
Co pp er in ter f ac es ar e di sa bl ed.
TX_ER_0:3 High Z Fiber mode is the default.
Co pp er in ter f ac es ar e di sa bl ed.
RGMII TX_CTL_0:3 High Z Fiber mode is the default.
Co pp er in ter f ac es ar e di sa bl ed.
SerDes TX_P_0:3 0x0 –
TX_N_0:3 0x0 –
Optical Module
TX_FAULT_INT High Z Open- drai n output, requires external pull- up.
RX _LOS_INT High Z Open-drain ou tput, requi res external pul l-up.
MOD_DEF_I NT High Z Open-drain output, requires ex ternal pull-up.
I2C_CLK 0x1 –
I2C_DATA_0:3 0xF Open-drain output, requires external pull-up.
Table 18. Defi nition of Output and Bi-directional Balls During Hardware Rese t (Sheet 2 of 2)
Interface Ball Name Ball Reset State Comment
NOTE: Z = High impedance.
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4.7 Power Supply Sequencing
Fol low the power -up and power-down sequ enc es described in this se cti on to ensure correct
I XF1104 MAC operat ion. The sequence des cribed in Section 4.7 covers all IXF1104 MAC digital
an d analog supplies.
Caution: Failure to follow the sequence described in this se ction might damage the IXF1104 MAC.
4.7.1 Power-Up Sequence
Ensure that the 1.8 V analog a nd digital supplies are applied and stable prior to application of the
2.5 V ana log and digital suppli es.
4.7.2 Power-Down Sequence
Remove the 2. 5 V suppli es pri or to removi ng t he 1.8 V po wer supp lies (the re verse of t he power -up
sequence).
Caution: Damage can occur to the ESD struc tures within the analog I/Os if th e 2.5 V digital and analog
supplies exceed the 1.8 V digital and analog supplies by more than 2.0 V during power-up or
power-down.
Figure 5 a nd Table 19 provide the IXF1104 MAC power supply se quencing.
Figu re 5. Power Sup pl y Seque nc i ng
Time
t=0
1.8 V Supplies Stable 2.5 V Supplies S table
Sys_Res
Apply VDD, AVDD1P8_1, and
AVDD1P8_2 Apply VDD4, VDD5,
AVDD2P5_1 and AVDD2P5_2
NOTE: The 3.3 V sup ply (VD D2 and VDD3) can be applied at any po int during th is s equence.
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4.8 Pull-Up/Pull-Down Ball Guidelines
The signals shown in Table 20 require the addition of a pull-up or pull-down resis tor to the board
des ign for norm al operation. Any balls marked as unused (NC) sho uld be unconn ected.
4.9 Analog Power Filtering
Figure 21 illustrates an analog power supply filt er network and Table 21 lists th e an al o g po wer
balls.
Tab le 19. Power Supply Seq uencing
P ower Sup ply Power -Up Ord er Time Delt a to
Next Supply1Notes
VDD, AVDD1P8_1,
AVDD1P8_2 First 0 1.8 V supplies
VDD4, VDD5,
AVDD2P5_1,
AVDD2P5_2 Second 10 µs 2.5 V supplies
1. The value of 10 µs given is a nominal value only. The exact time difference between the application of the 2.5 V analog
supply is determined by a number of factors, depending on the power management method used.
NOTE: To avoi d damage to the IXF1104 MAC, the TXAV25 supply must not excee d the VDD supply by more
than 2 V at any time during the power-up or power-down sequence.
NOTE: The 3.3 V supply (VDD2 and VDD3) can be applied at any point during this sequence.
Table 20. Pull-Up/Pull-Down and Unused Ball Guidelines
Pin Name Pull-Up/ Pull - Down C om m en ts
TX_FAU LT_I N T P ull- up 4.7 k Ω to 2.5 V. Optical module signal with open-drain I/O.
RX_LOS_INT P ull-up 4.7 k Ω to 2.5 V. Optical module signal with open-drain I/O.
MOD _ D EF _ IN T P ull-up 4.7 k Ω to 2.5 V. Optical module signal with open-drain I/O.
TDI Pull-up 10 k Ω to 3.3 V. JTAG test pin.
TDO Pull-up 10 k Ω to 3.3 V. JTAG test pin.
TMS Pull-up 10 k Ω to 3.3 V. JTAG test pin.
TCLK Pull-up 10 k Ω to 3.3 V. JTAG te st pin.
TRST_L Pull-down 10 k Ω to 3.3 V. JTAG te st pin.
MDIO Pull-up 4.7 k Ω to 2.5 V
UPX_RDY_L Pull-up 4.7 k Ω to 3.3 V
I2C_DATA_0:3 Pull-up 4 .7 k Ω to 2.5 V
TX_DISAB LE_0:3 Pull-up 4.7 k Ω to 2.5 V
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Figu re 6. Anal og Po we r S up pl y Fil ter Ne twork
Tab le 21. Anal og Po wer Balls
Signa l N ame Ball
Designator Comments
AVDD1P8_1 A5 A20 Need to provide a filt er (see Fi g ure 6).
R: AV DD1P8_1 and AVDD2 P5_1 = 5.6 Ω resistor.
AVDD2P5_1 AD20
AVDD1P8_2 AB16 T23 Need to p rovide a filt er (see Fi g ure 6).
R: AV DD1P8_2 and AVDD2 P5_2 = 1.0 Ω resistor.
AVDD2P5_2 U14 R18
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5.0 Functional Descriptions
5.1 Media Access Controller (MAC)
The IXF1104 MAC main functional block consists of four independent 10/100/1000 Mbps
Ethe rnet MACs, which support inte rfac es for fiber an d copper connec tivity.
•Copp er Mode:
— RGMII for 10/100/1000 Mbps full-duplex o perati on and 10/100 Mbps half-dup lex
operation
— GMII for 1000 Mbps full-du plex operation
•Fib er Mode :
— Integrated SerDes/OMI interface for direct connection to optical mod ules
— 100 0 Mbps ful l-duplex operation in fi ber mode
The following features supp ort copper and fiber modes:
•Progra mmable Options:
— Automati c pa dding of trans mitted pack ets that are less than the minimum frame size
— B r oa d ca s t, m u lt ic as t , an d un i ca s t addres s filtering on fra m e s re ceiv e d
— Filter and drop pac kets with errors
— Pre -padded RX frame s wit h two bytes (aligns the Ethernet payload on SPI3 and in
network processor memories)
— Remove CRC fro m RX f rames
— Append CRC to transmitted f r ames
•Per formance Moni toring and Diagnostics:
— Loopbac k modes
— Detection of runt and overly large packets
— Cyclic Redundancy Check ( CRC) calculation and erro r detection
— RMON statistics for dropped packets, pack ets with errors, etc.
•Complia nt with IEEE Spec 802.3x standard for flow contr ol
— Rece ive and execute PAUSE Command Frames
•Suppo rt for non-standard packe t s izes up to 10 KB incl uding loss-less flow control
Note: T he IXF1104 MAC does not support 10/100 Mbps operation when configured in GMII mode.
The IXF1104 MAC is fully integra ted, de signed for use with E thernet 802.3 frame types, and
compliant to all of the IEEE 802.3 MAC requirem ents.
The IXF1104 MAC adds pre amble and Start-of-Frame Delim iter (S FD) to all fram es sent to it
(t ransmit path) and removes preamble and SFD on a ll frames r eceived by it (receive path ) . A CRC
check is also applied to all transmit and r ecei ve packets. CR C is optio nally appended to transmit
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p ackets. CRC is r emoved optionally from receive packets after validation, and is not f o r w arded to
SPI3. Packets wit h a bad CRC are marked, counted in the statist ics block, and may be optionally
dr opped. A bad packe t m ay be signale d with RERR on the SP I 3 interfa ce if it is not dropped.
The IXF1104 MAC operat es only in full-duplex mode at 1000 Mbps rates on both S erDes and
GMII interface connect ions. The IXF 1104 MAC is c apa ble of ope ration at 1000 Mbps, full-duplex
in RGMII mod e, and at full-duplex and half-duplex operat ion for 10/100 Mbps links.
5.1.1 Features for Fiber and Copper Mode
Section 5.1.1.1 through Sectio n 5.1 . 1 .4 cover IXF 1104 MAC func tions t hat are indepen dent of the
line -s ide interface.
5.1.1.1 Padding of Undersized Frames on Transmit
The padding feature allows Etherne t frames smal ler than 64 byt es to be transferred from the SPI3
interface to the TX MAC and padded up to 64 bytes automatically by the MAC. This feature is
enabled by setting bit 7 of the “Divers e Config Write ($ Port_Index + 0x18)".
Note: When the user selects the padding function, the MAC core adds an autom atically calculated CRC
to the end of the transmitted packet.
5.1.1.2 Automatic CRC Generation
Autom atic CRC Generation is use d i n conjunc tion wit h the paddi ng feature to genera te and a ppend
a cor rect CRC to a ny tra nsmi t fram e. Thi s feat ure is enab led by se tti ng bit 6 of the “D iverse Config
Write ($ Port_Index + 0 x18)" .
5.1.1.3 Filte r ing o f R eceive Pa ckets
This feature allows the I X F1104 MAC to filter receive packets under vari ous conditions and dro p
the packets through an interacti on wi th the Re ceive FIFO control.
5.1.1. 3.1 Filter on U n i cast P acket Ma tch
This feature is ena bled when bit 0 of the “RX Pa cke t F ilte r Control ($ Port_Index + 0x19)" = 1.
Any fram e recei ved in t his m ode tha t do es not matc h th e S tati on Addres s (MAC add ress) i s mar ked
by the IXF1104 MAC to be drop ped. The fram e is dropped if the appropriat e bit in the “RX FIFO
Errored Frame Drop Ena ble ($0x59F)" = 1 . Otherwi se, the frame is sent out the SPI3 i nterface and
ma y optionally be s ignaled with an RERR (see bit 0 in “SPI3 R eceive Configurat ion ($0x701)” on
page 215).
When bit 0 of the “RX Pac ket Filter Control ($ Port_I ndex + 0x19)" = 0, all u nicas t fra mes are sent
o ut the SPI3 interface.
Note: The VLAN filter ov errides the unic as t filter. The refore, a VLAN frame c annot be filte red base d on
the unicast address.
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5. 1.1. 3. 2 Filter on M u l ticast Pack et Ma tch
Thi s featu re is en ab l ed w he n bit 1 o f the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1.
Any frame received in this mode that does not match the Port Multicast Addr ess (reserved
mult icast address recognized by IXF1104 MAC) is marked by the MAC to be dropped. The frame
is dropped if the appropri ate bit in the “RX FIFO Errored Fram e Drop Enable ($0x59F)" = 1.
Otherwise, the frame is sent out the SPI3 interface and may opti onally be signal ed with an RERR
(se e bit 0 in “SPI3 Receiv e Configuration ($0x701)” on page 215).
When bit 1 of the “RX Packet Filter C ontrol ($ Port_Index + 0x19)" = 0, all mu lticast f r ames are
sent out th e SPI3 interface.
5.1.1.3.3 Filter Broadcast Packets
Thi s featu re is en ab l ed w he n bit 2 o f the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1.
Any broadcast frame received in this mode is marked by the MAC to be dropped. The fr ame is
dropped if the appropriate bit in the “RX FIFO Errored Frame Drop Enable ($0x59F) " = 1.
Otherwise, the frame is sent out the SPI3 interface and may opti onally be signal ed with an RERR
(se e bit 0 in “SPI3 Receiv e Configuration ($0x701)” on page 215).
When bit 2 of the “RX Packet Filter C ontrol ($ Port_Index + 0x19)" = 0, all broadc as t frames are
sent out th e SPI3 interface.
5.1.1.3.4 Filter VLAN Packets
Thi s featu re is en ab l ed w he n bit 3 o f the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1.
VLAN frames rec eived in this mod e are marked by the MAC to be dropped. The frame is dropped
if the appropriate bit in the “RX FIFO Errored Frame Drop Enable ($0x59F )" = 1. Otherwise, the
VLAN frame is s ent out t he SPI3 in te rface and ma y optiona ll y be signal ed with a n RERR (see bit 0
in “SPI 3 Rec eive Configuration ($0x701)” on page 215).
When bit 3 of th e “RX P ac ket Filter Control ($ Port_Index + 0x19)" = 0, all VLAN frames are s ent
out the SPI3 interface.
5.1.1.3.5 Filter Pause Packets
Thi s featu re is en ab l ed w he n bit 4 o f the “RX Packet Filter Control ($ Port_Index + 0x19)" = 0.
Pause frames receive d in t his mode are ma rked by the MAC t o be droppe d. The frame is dropped if
the appropriate bit in the “RX FIFO E rrored Frame Drop Enable ($0x59F)" = 1. Otherwis e, the
paus e frame is sent out the SPI 3 interface and may optionall y be signaled with an RERR (see bit 0
in “SPI 3 Rec eive Configuration ($0x701)” on page 215).
When bit 4 of the “RX Packet Filter C ontrol ($ Port_Index + 0x19)" = 1, all pause frames are sent
out the SPI3 interface.
Note: Paus e packets are not filtered if flow control is disabled in the “FC Enable ($ Port_Inde x + 0x12)”.
5.1.1.3.6 Filter CRC Error Packets
Thi s featu re is en ab l ed w he n bit 5 o f the “RX Packet Filter Control ($ Port_Index + 0x19)” = 0.
Fra me s received with an errored CRC are marked as bad frames and may optionally be dropped in
the RX FIFO. Otherwise, the frames are sent to the S PI3 interface and may be optionally signaled
with an RERR (see Table 22 “CRC Error ed P ackets Drop Enable Behavior” on page 69).
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Whe n the CRC Error Pass Filter bit = 0 (“RX Packet Filter Control ($ Port_Index + 0x19)” ), it
takes prec edence over the other fi lter bits. Any packet (Pause, Unicast, Multicast or Broadcast
p acket) wi th a CRC err o r w i ll be marke d as a bad frame when the CRC Error Pass Filter bit = 0.
5.1 .1. 4 CRC Error Detect ion
Frames re ce i ve d by the MAC ar e che ck e d fo r a co r rect C R C. W h e n an inco r r ec t C RC is d et ec te d
o n a recei ved f r ame, the RX FCSEr r or RMON statistic c ounter is increm ented for each CRC
errored f r ame. Rece ived frames with CRC errors may optionally be dropped in the RX FI FO (refer
to Sec tion 5.1.1.3.6, “Filter CRC Er ror P ackets” on page 68). Othe rwis e, the frames are sent to the
SPI3 interface and may be dropped by the switch or system controlle r.
Fr am es tr a ns m i tt ed by the M A C are als o ch e ck ed f or co rr ect CR C . W h en an inco r r ect C RC is
det ected on a transmi tted frame , the TX CRCE rror R MON statis tic count er is in cremente d for each
inc orrect fra me.
5.1.2 Flow Control
Flow Control is an IEEE 802.3x-defined mechanism for one network node to request tha t its link
partne r take a temporary “Pause” in packet transmission. This allows the requesting network node
to prevent FIFO overruns and dropped packets, by managing incoming traffic to fit its ava ilable
me mory. The temporary pause allows the device to proce ss packets already rec eived or in transit,
thus freei ng up the FIFO space allocated to those packets.
Table 22. CRC Errore d Packets Drop Enable Behavior
CRC Error
Pass1RX FIFO Errored-
Frame Drop
Enable2RERR
Enable3Actions
1xx
When CRC Errored P ASS = 1, CRC errored pa ck ets
are not filtered and are passed to the SPI3 interfac e.
They are not marked as bad, cannot be dropped, and
cannot be signaled with RERR.
001
Packets are marke d as bad but not dropped in the
RX FIFO. These packets are sent to the SPI3
interface, and are signaled with an RE RR to the
switch or Network Processor.
000
Packets are marke d as bad but not dropped in the
RX FIFO. These packets are sent to the SPI3
interface, an d are not signaled with an RERR.
01x
CRC errored packets are marked as bad, dropped in
the RX FIFO, and never appear at the SPI3 interface.
NOTE: Packet sizes above the RX FIFO Transfer
Threshold (see Table 128 through Ta ble 13 1)
cannot be dropped i n the RX FIFO and are
passed to the SPI3 interface. These packets
can optio nally be signaled wit h RER R on t he
SPI3 interface if the RERR Enable bit = 1.
1. See Table 91 “RX Packet Filter Control ($ Port_Index + 0x19)” on page 172.
2. See Table 123 “RX FIFO Errored Frame Drop Enable ($0x59F)” on page 196.
3. See Table 147 “SPI3 Receive Configuration ($0x701)” on page 215.
NOTE: x = “DON’T CARE”
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The IXF1104 MAC imple ments the IEEE 802.3x sta ndard RX FIFO thr eshol d-ba sed Flow Cont rol
in copper and fiber modes. When appropriately programmed, the MAC can both generate and
res pond to IEEE st andard p aus e frames in full-duplex operation. T he IXF1104 MAC als o supp orts
externally triggered flow control through the Transmit Pause Control interface.
In half-duplex operat ion, the MAC ge nerat es collisions ins tead of sending pause fram es to manage
the incoming traf fic from the link partner
5.1.2.1 802.3x Flow Control (Full-Duplex Operation)
The IEEE 802.3x standa rd identifies four options related to s ystem flow control:
•No Pause
•Symmetri c Pause (both directi ons )
•Asymmetric Pause (Receive direction only)
•Asymmetric Pause (Transmit direc tion only)
The I XF1 104 support s al l fo ur option s on a per -p ort bas is. Bit s 2:0 of t he “FC E nable ($ Port_Inde x
+ 0x12)” on page 168 provide progr ammable cont rol for enabl ing or disa bling flow cont rol in eac h
direction independently.
The IEEE 802.3x flow control mechani s m is accomp lished withi n the MAC sublaye r, and is based
on RX FIFO thresholds cal led watermarks. The RX FIFO level rises and falls as pac kets are
receiv ed and processed. When the RX FIFO r eaches a watermark (e ither exceeding a High or
dropping below a Low a fter exceeding a High), the IXF1104 contro l sublayer signals an inte rnal
state ma ch ine to t r ansmit a PAUSE frame. The FIFOs automat i cally generate PAUSE frames ( also
ca ll e d co nt ro l fr ames) to in i ti a t e th e fo ll o w in g :
•Halt the link part ner when the High waterm ark is rea ched.
•Restar t the link partner when the data stored in the FI F O falls below the Low watermark.
Figure 7 illustrates the IE EE 802.3 FIFO flow co ntrol functions.
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5.1.2. 1.1 Pause F r ame For mat
PAUSE frames are MAC con trol frames that are padde d to the minim um size (64 bytes). Figure 8
and Figure 9 illu s t r ate th e frame for m a t and co n te nts.
Figure 7. Packet Buffering FIFO
MDI
High Watermark Data Flow
M
AC Transfer Threshold
Low Watermark
High Watermark Data Flow
Low Watermark
RX FIFO High
TXPAUSEFR (External
Strobe) 802.3x Pause Frame Generation
TX FIFO TX Side
MAC
RX FIFO
802.3 Flow
Control
RX Side
MAC
SPI3 Interface
B3231-01
Figure 8. Eth e rne t Frame Fo rm at
Number of bytes
Note:
!""# $ % !&"#
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An IEEE 802.3 MAC PAUSE frame is identified by det ectin g all of the following:
•OpCode of 00-01
•Lengt h/Type f iel d of 88-08
•DA matching the unique multicast address (01-80-C2-00-00-01)
XOFF. A PAUSE frame inf orms the link partner to ha lt transmi ssion for a spec ified le ngth of time.
The PauseLength octets specify the duration of the no-transmit period. If this time is greater tha n
zero, the link partner must stop sending any further packets until this time has elapsed. This is
referr ed to as XOFF.
XON. The MAC continues to transmit PAUSE frames with the specified Pause Length as long as
the FI F O leve l exceeds the threshold. If the FIFO level falls below the threshold be fore the Pause
Lengt h time expires, the MAC sends another PAUSE frame with the Pause Lengt h time spe cified
as zero. Thi s is referred to as XON and informs the link partner to resume normal transmiss ion of
packets.
5.1.2.1.2 Pause Settings
The MAC must send PAUSE frames repe atedly to maintain t he link partner in a Pause state. The
following two inter- related variab les control this process:
•Pau se Length is th e amount of tim e, measured in multiples of 512 bit times, that the MAC
requests the li nk partner to halt transmi ssion for .
•Pause Threshold is the amount of time, mea sured in multiples of 512 bit times, prior to the
expiration of the Paus e Length that the MAC transm its another Pause fra me to maintain t he
link partner in the pause state.
The tra nsmitted Pause Le ngth in the IXF1104 MAC is set by the “FC TX Timer Value ($
Port _Index + 0x07)” on page 164.
The IXF1104 PAUSE frame trans mi s si on interval is set by the “Pause Threshold ($ Port_Inde x +
0x0E)” on page 166.
Figure 9. PAUS E Frame For mat
!
"#$%&
'(%& !
)%
*# %& *#%+*, &(%%- %& ., / 0 %& 1 % %&( %& %(% 2
3 .& 4, (#%0 0 %& 1 '( %&( %& %(% %& 1 2
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5.1.2. 1. 3 R es ponse to Recei ved PAUS E C o mm a nd Frames
When Flow Control is enable d in the receive di recti on ( bit 0 in the “FC E nable ($ Port_Index +
0x12)"), the IXF1104 responds to PAUSE Command fr ames rec eived from the link partn er as
follows:
1. The IXF1104 checks the en tire frame to verify tha t it is a valid PAUSE control f rame
addresse d to the Multicast Address 01-80-C2-00-00-01 (a s specified in IEEE 802.3, Annex
31B) or has a Destinations Address matching the address programmed in the “Stati on Address
( $ Port_Index +0x00 – +0x01)".
2. I f the PAUSE frame is valid, the transmit si de of the IXF1 104 paus es for the required number
of PAUSE Quanta , as sp ecified in IE EE 802.3, Cl ause 31.
3. PAUSE does not begin until completion of the frame c urrently being transmit ted.
The IXF1104 respons e to va lid received PAUSE frames is independent of the PAUSE frame filter
setti ngs. Re fer to Section 5.1.1.3.5, “Filte r Pause Packets” on page 68 for additional detai ls.
Note: Pause pa ckets are not filtered if flow control is disabled in bit 0 of the “ F C Enabl e ($ Port_Index +
0x12)”.
5.1.2. 1.4 Half-Du p l ex Operati o n
Transmit flow control is implemented onl y in half-duplex opera tion. Upon entering the flo w
control state, the MAC generates a col lision for all subsequent receiv e packets until exiting the
f low control sta te. Any rece ive packet in progr es s when the MAC enters the flow control state wi ll
no t be c o llided with but could be lost due if the r e is insufficient FIFO depth to complete packet
r eception. Bit 2 of the “F C Enable ($ Port_Index + 0x12)" enables the transmit flow control
function.
5.1.2. 1.5 Tr an smit Pause C o n tr o l In terface
The Transmit Pause Control interface allows an exte rnal device to trigger the generation of pause
f r ames . The Transmit Pause Control interfa ce is comple tely asynchron ous. It consists of three
addre ss signals (TXPAUSEADD[2:0]) and a strobe si gnal (TXPAUSEFR). The requi red address
f or this interface ope ration is pla ce d on the TXPAUSEADD[2:0] sig nals and the TXPAUSEFR is
pulsed High and return ed Low. Refer to Fi gure 10 “ Trans mi t Pause Control Inte rface” on page 74
and Table 55 “Transmit Pause Control Interface Timing Paramete rs” on page 151. Tabl e 23 shows
the valid decodes for the TXPAUSEADD[2: 0] si gnals. Figure 10 illustrates the transmit pause
control interfac e.
Note: Flow cont rol m ust be enabled in the “FC E nable ($ Port_Index + 0x12)” for Transmit Pause
Control interface oper ation.
Note: There are two additi onal dec odes provided tha t allow the user to generat e either an XOFF frame or
XON frame from all ports simultan eously.
The d efault pause qua nta for each port i s held b y the “FC TX T i mer Value ($ Port _Index + 0x0 7)").
The default value of this register is 0x05E after reset is applied.
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Table 23. Valid Decodes for TXPAUSEADD[2:0]
TXPAUSEADD_ 2:0 Operati on of TX Pause Control Interface
0x0 Transmits a PAUSE frame on every port with a pause_time = ZERO (XON)
(Cancels all previous pause commands).
0x1 Transmits a PAUSE frame on port 0 with pause_time equal to the value programmed
in the port 0 “FC TX Timer Valu e ($ Port_Inde x + 0x07)" (XOFF).
0x2 Transmits a PAUSE frame on port 1 with pause_time equal to the value programmed
in the port 1 “FC TX Timer Valu e ($ Port_Inde x + 0x07)" (XOFF).
0x3 Transmits a PAUSE frame on port 2 with pause_time equal to the value programmed
in the port 2 “FC TX Timer Valu e ($ Port_Inde x + 0x07)" (XOFF).
0x4 Transmits a PAUSE frame on port 3 with pause_time equal to the value programmed
in the port 3 “FC TX Timer Valu e ($ Port_Inde x + 0x07)" (XOFF).
0x5 to 0x6 R eserv ed. Do not use these addre s ses. T he TX Pause Contr ol interfac e will not
operate under these conditions.
0x7 Transmits a PAUSE frame on every port with pause_time equal to the value
programmed in the “FC TX Timer Value ($ Port_Index + 0x07)" for each port (XOFF).
Figure 10. Transmit Pause Con trol Interface
B3234-01
TXPAUSEFR
TXPAUSEADD0
TXPAUSEADD1
TXPAUSEADD2
This example shows the following conditions:
Strobe 1:
Port 0: Transmit Pause Packet (XOFF)
Strobe 2:
All Ports: Transmit Pause Packet with pause_time = 0 (XON)
Strobe 3:
Port 3: Transmit Pause Packet (XOFF)
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5.1.3 Mixed-Mode Operation
The IXF1 104 MAC gives the user t he option of confi guri ng each por t for 10/100 Mbps h alf-dup le x
copper, 10/100/1000 Mbps full-duplex coppe r, or 1000 Mbps full-duplex fiber opera tion. This
gives the IXF1104 MAC the ability to support both copper and fiber operation line-side int erfa ces
o p erat ing at th e same time with in a single dev ice. (Refer to Figure 16 “Line Side Inte rface
Multiplexed Balls” on page 58.)
The IXF1104 MAC provides complete flexibility in line-side connect ivity by offe ring RGMII,
int eg r at ed S er D e s , an d GMI I .
5.1.3.1 Configuration
The memory maps (Table 59 “MAC Control Registers ($ Port Index + Offset)” on page 156
through Table 69 “Optical Module Registers ($ 0x799 - 0x79F)” on page 162) ar e logical ly spli t
into the fol lowing two distinct regi ons:
•Per -Port Registers
•Global Registers
To achieve a desire d configuration for a giv en port, the relevant per-port regist ers mu st be
configured correctly by the user. Th e Ta ble 59 through Table 69 also con tain registers that affect
the operation of all ports, such as the SPI3 interface configuration.
See Section 8.0, “Register Set” on page 155 for a co mpl ete desc ription of IXF1104 MAC
configuration and status registers . Th e Register Maps (Ta ble 59 through Tabl e 69) present a
summ ary of important configuration registers.
Note: The initializa tion sequence provided in Section 6.1, “Change Po rt Mode Initializ ation Sequence”
on page 1 30 must be followed for proper configurat ion of the IXF1104 MAC.
5.1 .3. 2 Key Configurati on Registers
The following key regi sters select the op erational mode of a given port:
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5.1.4 Fiber Mode
When the IXF1104 MAC i s configure d for f iber mode, the TX Data pat h from the MAC is an
internal
10- bit inte rface as des cribed in the IEEE 802. 3z speci ficat ion. It is connec ted dire ctly t o an intern al
SerD es block for serialization/deserializa tion and transmission/reception on the fiber medium to
and from the link partner.
The MAC cont ai ns all of t he PCS (8B /10B encodi ng and 10B/ 8B decod ing) require d to e ncode a nd
decode the data. The MAC also supports auto-negotiation per the I EEE 802.3z specification via
access to the “TX Confi g Word ($ Port _Ind ex + 0x17)", “RX Co nfig Word ($ Port_Inde x + 0x16) ",
and “ Diverse Config Write ($ Port _Index + 0x18 )".
Table 24. Operational Mode Configuration Registers
Reg ist er N a me Register
Address Description
“Desi red Du plex
($ Port_Index +
0x02)"
0x002 – Port 0
0x082 – Port 1
0x102 – Port 2
0x182 – Port 3
The “Desired Duplex ($ Port_Index + 0x02)” on page 163 def in es
whether a port is to be configured for full-duplex or half-duple x
operation.
NOTE: Half - dupl ex op erat i on is o nl y v al id for 10/ 1 00 sp eeds w h ere t he
RG M II lin e inter f ac e ha s been sel ec ted.
“MAC IF Mode
and RGMII
Sp eed ($
Port_I ndex +
0x10)"
0x010 – Port 0
0x090 – Port 1
0x11 0 – Po rt 2
0x190 – Port 3
The “MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)” on
page 167 determines the MAC operational f requency and mode for a
given port.
NOTE: Set the “Clock and Interface Mode Change Enable Por ts 0 - 3
($0x794)” on page 221 to 0x0 prior to any change in the
register value. This ensures that a change in the MAC clock
frequency is controlled correctly. If the “Clo c k an d I nte rf a c e
Mode Change Enable Ports 0 - 3 ($0x7 94)" is not us ed
corre c tly, the IXF11 0 4 MAC may not be conf ig ure d to the
pr op er mo de .
“Port Enable
($0x500)"
0x500
Bit 0 – Port 0
Bit 1 – Port 1
Bit 2 – Port 2
Bit 3 – Port 3
Each “P or t En ab le ($0 x50 0)" bit relates to a port. Set the appropriate bit
to 0x1 to enable a port. This should be the last step in the configuration
process for a port.
“Int er f ac e Mo de
($0x501)"
0x501
Bit 0 – Port 0
Bit 1 – Port 1
Bit 2 – Port 2
Bit 3 – Port 3
The “Inter face Mode ($0x501)" selects whether a port operates with a
copper (RGMI I or GMII) line-side interface an integ rated SerDes fiber
line-side interface.
For copper op eration for a given port, set the relevant bit to 0x1.
For fi ber operation for a given port, set the relevant bit to 0x0.
NOTE: All ports are config ured for fiber operation in the IXF1104 MAC
default mode of operation.
“C lock and
Int er f ac e Mo de
Change Enable
Ports 0 - 3
($0x794)"
0x794
Bit 0 – Port 0
Bit 1 – Port 1
Bit 2 – Port 2
Bit 3 – Port 3
The “Clock and Int erface Mode Change En able Ports 0 - 3 ($0x794)"
indicates to an internal clock generator when to sample the new value
of the “MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)" and the
“Interf ace Mode ($ 0x501)" (copper/fiber).
When any of the s e two configuration values are changed for a port, the
corresponding bits mu st be kept in this regist er under reset by writing
0x 0 to the releva nt bit.
NOTE: The initializ ation sequence provided in Section 6.1, “Change Port Mode Initialization Sequence” on
page 130 must be followed for p roper configuration of the IXF1104 MAC .
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When configured for fiber mode, the full s et of Optical Mod ule interfac e contr ol and status signals
is pr esented through re-use of GMII signals on a per-p ort basis (see Table 4.5 “Multiplexed Ball
Connections” on page 58). Fiber mode supports onl y full-duplex Gigabi t operat ion.
5.1.4.1 Fiber Auto-Negotiation
Auto-negot ia tion is pe rformed by using t he “TX Co nfig Word ($ Port _Index + 0 x17)", “RX Co nfig
Word ($ Port_Index + 0x16)", and “Diverse Config Write ( $ Port_Index + 0x18 )". When
autoneg_enable (“Divers e Config Writ e ($ Port_Index + 0x18) " ) is set, the IXF1104 MAC
performs hardware -defined aut o-negotiation with the “TX Con fig Word ($ Port_ Index + 0x17)"
used as an “Auto-Negotia tion Advertisement ($ Port Index + 0x64)" and the “RX Config Word ($
Port_Index + 0x16)" used as an “Aut o-Negotiation L ink Partner Base Page Ability ($ Port Index +
0x65)".
Note: While the MAC supports auto-negotia tion functions, the IXF1104 MAC does not aut omati ca lly
configure t he MAC or other dev ice blocks t o be consistent with the auto-negotiation results. This
configuration is done by the user an d system software .
5.1.4.2 Determining If Link Is Establishe d in Auto-Negotiation Mode
A valid link is establis hed when the AN_comple te bit is set and the RX_Syn c bit reports that
syn chroniz ation has occurred. Bot h regist er bits ar e l ocate d in t he “RX Config W ord ($ Port _Index
+ 0x16)".
I f the link goes down af ter auto-negotiation is completed, RX_S ync indicates that a loss of
synchro nizat ion occurred. The IXF1104 MAC restarts auto -negotiation a nd attempts to reestablish
a link. Once a link is reest ablished, the AN_complete bit is set and the RX_Sync bit s hows that
synchro nizat ion has occurred.
To manually resta r t auto-negotiation, bit 5 of the “Diverse Config Write ($ Port_Inde x + 0x18)”
(AN_enable) must be de-asserted, then re-asserted.
5.1 .4. 3 Fiber Forced Mode
The MAC fiber opera tion c a n b e forced to o perate at 1000 Mbps fu ll- duplex wit hout completio n of
th e auto-negotiation f unction. In this mode, the MAC RX path must achieve synchroni zation with
the link pa rtner. Once achieved, the MAC TX pat h is enable d to allow dat a transmission. This
f orced mode is limited to operation with a link pa rtner that operates with a full-duplex link at
1000 Mbps.
5.1.4.4 Determination of Link Es tablishm ent in Forced Mode
When the IXF1104 MAC is in forc ed mode operation, the “RX Config Word ($ Port_I ndex +
0x16)” bit 20 RX Sync indicates when synchronization occ urs and a va lid link establishe s.
Note: The RX Sync bit indicates a loss of synchronization when the link is down.
5.1.5 Copper Mode
In copper mode, the IXF1104 MAC trans mits data on the egress path of the RGMII or GMII
interface, depending on the port confi guration defined by the user. The copper MAC receives data
on the ingress path of the RGMII or GMII interf ace, depending on the port configuration de fined
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by the user. The RGMII interface supports ope ration a t 10/100/100 0 Mbps when a full-duplex link
is establ ished, an d supports 10/100 Mbps when a half-duplex lin k is establis hed. The GMII
interfac e only supports a 1000 Mbps full-duplex link.
5.1.5.1 Speed
The copper MAC supports 10 Mbps, 100 Mbps, and 1000 Mbps . All requi red speed adjustments,
clocks, etc., are supplied by the MAC. The opera ting spe ed of the MAC is programmable through
the “MAC IF Mode and R GMII Speed ($ Port _Index + 0x10)" (MAC_ IF_Mode). The IXF1104
MAC speed s etti ng must be pro grammed by t he system soft ware to m atch the spe ed of the a ttach ed
PHY for proper IXF1104 MAC operation.
Note: When the IXF1104 MAC is confi gured to use the GMII interface, the only mode of ope ration th at
is supported is 1000 Mbps ful l-duplex.
If 10/100 Mbps operation is required in either full-duplex or half-duplex, the IXF1104 MAC must
be confi gured to use the R GMII interface.
5.1.5.2 Duplex
The MAC supports full-duplex or half-duplex depending on the line-s ide interfac e tha t is
configured by the “MAC IF Mode and RGMII Spee d ($ Port_Index + 0x10)" (MAC_IF_Mode).
The duplex of the MAC is se t in the “Desired Duplex ($ Port_Index + 0x02)” on page 163. The
IXF1104 MAC duplex setting must be programm ed by the system softwar e to match the attac hed
PHY duplex for proper IXF1104 MAC operation.
5.1.5.3 Copper Auto-Negotiation
In the c oppe r MAC, auto-negotiation a nd all other controls of the PHY devic es are achieved
through the MDIO interface , and are independent of the MAC controller. See Section 5.5, “MDIO
Control and Int erface” on page 99 for further operation detail s.
Note: In co pper mode, au to-negotiation is accomplished by the attached PHY, not the IXF1104 MAC.
Thus, the IXF1104 MAC does not automatically configur e the MAC or other blocks in the device
to be c onsi stent with at tach ed PHY a uto-negot ia tion re sult s. T his mus t be acco mplis hed by t he use r
and system sof tware.
5.1.6 Jumbo Packet Support
The IXF1104 MAC supports jumbo frames. The jumbo fra me length is dependent on the
application and the IXF1 104 MAC des ign is optimized for a 9.6 KB j umbo frame le ngth. Larger
lengths can be progra mmed, but limit ed system perf ormance may le ad to data loss during certain
flow-control conditions
The value programmed in to the“Max Frame Size (Addr: Port_Index + 0x0F)" dete r mines the
maximu m leng th f rame si ze th e MAC ca n receive or trans mit wi thout a ctiva ti ng any e rror coun ter s,
and without trun cation.
The“Max Frame Si ze (Addr: Port_I ndex + 0 x0F )" bits 13:0 set the frame length. The defaul t value
programm ed into thi s regist er is 0x05E E (1518). The value is interna lly adj usted by +4 if th e frame
has a VLAN tag. The overall programmable maximum is 0x3FFF or 16383 bytes.
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The regis ter should be programmed to 0x2667 for the 9.6 KB length jumbo fra me , optimiz ed for
the IXF1104 MAC. The RMON counte rs are al s o imp lemented for jumbo frame support as
follows:
5.1.6.1 Rx Statistic s
•RxOctetsTotalOK (Addr: Por t_Index + 0x20)
•RxPkts1519toMaxOctets (Addr: Port_Index + 0x2B)
•RxFCSErrors (Addr: Port_Index + 0x2C)
•RxDatatError (Addr: Port_Index = 0x02E)
•RxAlignErrors (Addr: P ort_Index + 0x2F)
•RxLongErrors (Addr: Port_Index + 0x30)
•RxJabberErrors (Addr: Port_Index + 0x31)
•RxVeryLongErrors (Addr: Port_Index + 0x34)
5.1.6.2 TX Statistic s
•OctetsTransmittedOK (Addr: Port_Index + 0x40)
•TxPkts1 519toMaxOctets (Addr: P ort_Index + 0x4B)
•TxExce ssiveLength Drop (Addr: Port_Index + 0x53)
•TxCRCError (Addr: Port_Index + 0x56)
The IXF1104 MAC checks the CRC for all le gal-length jum bo frames (frames between 1519 and
the Max Frame Size ). On transmi s sion, the MAC can be programmed to append the CRC to t he
f r ame or che ck the CRC and incremen t the appro priate counter. On reception, the MAC trans mits
t h ese frames across t h e SPI3 i n terface ( j u mbo frames above the set ting in th e “RX FIFO Trans fer
Threshold Port 0 ($0x5B8)” with a bad CRC cannot be dropped and are sent across the SPI3
in terface). If the receive frame h as a bad CRC, the appropriate counter is incremented and the
RxERR fl a g is ass er t ed on th e SP I 3 re ce iv e inte rf ace .
Jumbo frames also impact flow control. The maxim um frame siz e needs to be ta ken into account
when det ermining the FIF O watermarks. The cu rrent transmissi on must be completed before a
Pause frame is transmitted (needed when the receiver FIFO High watermark is exceeded). If the
current transmis sion is a jumbo frame, the delay may be significant and inc r ea se data loss due to
i nsufficient a vailable FIFO sp ace.
5.1.6.3 Loss-less Flow Control
The IXF 1104 MAC supports loss-less flow control when the size of a Jumbo packet is r estricted to
9.6 k bytes. If this condition is met, the IXF1104 MAC has sufficient memory resources alloc ated
to ea ch MAC port to ensure that, if both the IXF1104 MAC and link partne r are required to send
Pause pac kets simult aneously during jumbo packe t transfers acro ss a medium of five kilometers of
fiber, no packet data should be lost due to F IFO overflows .
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5.1.7 Packet Buffer Dimensions
5.1.7.1 TX and RX FIFO Operation
5.1.7.1.1 TX FIFO
The IXF1104 MAC TX FIFOs are implemented wi th 10 KB for each chann el. This provides
enough s pace for at le as t one maximum size (10 KB) packe t per-port storage and ens ures t hat no
under-run condi tions o ccur , ass uming that the sending dev ice can sup ply data at the required data
rate.
A trans fer to MAC Threshold paramete r, whic h is user -programmable, determine s when the FIFO
signals to the MAC that it has data to send. This is configured for spe cific block sizes, and the user
must ensure that an under-run does not occur. Also, the th reshold can be se t above th e maxim um
siz e of a normal Ethernet packe t. This c aus es th e FI FO to sen d on ly data t o the MAC when this
threshold is exceeded or when the End-of-Packet marke r is received. This second condition
eliminates t h e pos sibility of under- r u n, except when the controlling sw itch dev ice fails. It can,
however, cause idle times on the media .
5. 1.7. 1. 2 RX FIF O
The IXF1104 MAC RX FIFOs are provisioned so that e ach port has it s own 32 KB of memory
spa ce . Thi s is enough memory to e nsure th at there is never an over-run on any channel while
trans f erring n o rmal Ethern et fram e size data.
The FIFO s au tom atically generate Paus e control f ram es to halt the link part ner when the High
water mar k is re ac hed an d to r esta rt t he lin k par tner whe n the data stor ed in t he FIFO f alls bel ow th e
low-watermark. The RX and TX FIFOs have been s ized to supp ort lossless flow control with
9.6 KB packet s. The RX FIFO has a progr amma ble transfer threshold that se ts the threshold at
which packets bec ome “cut through” and starts transitioning to the SPI3 interface before the EOP
is r eceived. Packets sizes belo w th is threshold ar e treated as “store an d forward. ” Once a pa ck et
siz e exceeds th e RX FIF O transfe r thr eshol d, it ca n no longer be dropped by the RX FIFO e ven if it
is marked to be dropped by the MAC.
5.1.8 RMON Statistics Support
The IXF1104 MAC supplies RMON stat istics through the CPU inte rface. These statistics are
avail ab l e in th e f orm of co un t er va lu es th at can be a cc es s ed a t sp ec if i c ad dres ses in th e r eg i s te r
maps (Table 59 through Table 69). Once read, these counters automatically r eset and begin
counting from zero. A separat e set of RMON st atistics is available for each MAC device in the
IXF1104 MAC.
Imple mentation of the RMON Statistics bl ock is similar to th e functionality provi ded by existing
Intel switch and rout er products. This implement ation allows the IXF1104 MAC to pr ovide al l of
the RMON Statistics group as de fined by RF C2819. The IXF1104 MAC s upports the RMON
RFC2819 Group 1 stat istics counters. Ta ble 25 notes the differenc es and additional statistics
regis ters supported by the IXF1104 MAC that are outside the scope of the RMON RFC2819
document.
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Tab le 25. RMO N Additional Sta tistics (Sheet 1 of 2)
R MON Ethe rne t Statisti cs
Group 1 Statistics Type IXF1104 MAC- Equiv alent
Statistics Type
Definition of RMON
Versus
I XF110 4 MAC
Documentation
etherSt atsinde x Integ er 32 NA NA NA
etherStatsDataSource Object
identifier NA NA NA
etherStatsDropEvents Counter
32
RX Num ber of Frames
Removed/
TX Number of Frames
Removed
Counter 32 See table note 1
etherStatsOctets Co un ter
32
RxOctetsTotalOK
RxOctetsBad
OctetsTransmittedOK
OctetsTransmittedBad
Counter 32
The IXF1104 MAC
has two counters for
receive and transmit
th at us e diffe r e nt
naming conventions
for the total Octet s
and Oc tets Bad .
These counters must
be combined to meet
the RMON definition
for this statistic.
etherStatsPkts Counter32 RxUCPkts/TxUCPkts
RxBCPkts/TxBCPkts
RxMCPkts/TxMCPkts Counter 32
The I XF1104 MAC
has three counters
for the etherStatsPkts
that mu st be
c ombined to give the
total packets as
defined by the
RMON specification.
etherStatsBroadcastPkts Counter32 RxBCPkts/TxBCPkts Counter 32 Same as RMON
specification
etherStatsMul ticastPkts Counter32 RxMCPkt s/TxMCPkts Counter 32 See table note 2
etherStatsCRCAlignErrors Counter32 RxAlignErrors
RxFCSErrors
TxCRCError Counter 32
The I XF1104 MAC
has two counters for
the alignm ent and
CRC errors for the
RX side only.
The I XF1104 MAC
has a CRC Error
counter for the TX
side.
etherStatsUndersizedPkts Counter32 RxRuntErrors
RxShortErrors
Rx Statis tic s ONLY Counter 32
The I XF1104 MAC
has two counte rs ,
one for Runt errors
and one for
ShortErrors.
NOTE: The RMO N sp eci fic at io n req ui r es t hat thi s is, “ Th e tot a l nu mber of even ts w he re p ac ket s we re dr o pp ed
by the p rob e d ue to a l a ck o f re so urce s. Thi s n umb er i s n ot ne ce ssa ril y t he nu mb er o f p a cke ts d r oppe d;
it is the number of times this condition is detected. " The “RX FIFO Overflow Frame Drop Counter Ports
0 - 3 ($0x594 – 0x597)" and “TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624)" in
the IXF1104 MAC support this and increment when either an RX FIFO or TX FIFO overflows. If any
IXF1104 MAC programmabl e packet filtering is enable d, the “RX FIFO Er rored Frame D rop Counter
Por ts 0 - 3 ( $0x 5A 2 - 0 x5A 5 )" an d “T X FI FO Er r ore d F ram e Dr op Cou nt er P orts 0 - 3 ( $0x 625 – 0x6 29 ) "
incremen t wi th every fram e removed in addition to the existing frames counte d due to FIFO over flow.
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5.1.8.1 Conventions
The fol lowing conventions are used throughout the RMON Management Information Base (MIB)
and its companion documents.
•Good Packets: Error-free packe ts tha t have a valid frame length. For example, on Ethernet,
good packets are error-free pac kets that are between 64 and 1518 octets long. The y follow the
form def ined in IEEE 802.3, Section 3. 2.
•Bad P acke ts : Bad pa ckets a re pa ckets t hat hav e pro per framing a nd re cogniz ed as pac kets , but
contain errors within the packet or have an invalid length. For example, on Ethernet, bad
etherStatsOversizePkts Counter32 RxLongErrors
TxExcessiveL ength Drop Counter 32 Same as RMON
specification
etherStatsFragments Counter32 RuntErrors Counter 32 Same as RMON
specification
etherStatsJabbers Counter3 2 JabberErrors Counter 32 Same as RMON
specification
etherStatsCollisions Counter32
TxSingleCollision
TxMultipleCollision
TxLateCollision
TxTotalCollision
Counter 32
T h e Tx To tal C ol lis io n
count value is
equivalent to the
RMON specification
minus the
TxLateCollision
etherStatsPkts64Octets Counter32 RxPkts64Octets/
TxPkts64Octets Counter 32 Same as RMON
specification
etherStatsPkts65to127Octets Counter32 RxPkts65to127Octets/
TxPkts65to127Octets Counter 32 Same a RMON
specification
etherStatsPkts128to255Octets Counter32 RxPkts128to255Octets/
TxPkts128to255Octets Counter32 Same a RMON
specification
etherStatsPkts256to511Octets Counter32 RxPkts256to511Octets/
TxPkts256to511Octets Counter32 Same a RMON
specification
etherStatsPkts512to1023Octets Counter32 RxPkts512to1023Octets/
TxPkts512to1023Octets Counter32 Same a RMON
specification
etherStatsPkts1023to1518Octets Counter32 RxPkts1023to1518Octets/
TxPkts1023to1518Octets Counter32 Same as RMON
specification
etherStatOwner Owner
String NA NA NA
etherStatsStatus Entry
Status NA NA NA
Table 25. RM ON Add itional Statistics (Sheet 2 of 2)
RMON Ethernet Statistics
Group 1 Statistics Type IXF1104 MAC-Equivalent
Statistics Type
De f i ni ti on of RM O N
Versus
IXF1104 MAC
Documentation
NOTE: The RM ON spe ci fi ca t ion re qu i res th at th is i s , “T h e tot al num be r of ev en t s whe re pa ck ets were dr op pe d
by th e p robe du e t o a lac k of r esou r ce s. This numbe r is not nec es sar il y t he nu mber of pac ke t s d ropp ed ;
it is th e number of times this condit ion is de tected." The “RX FIFO Overflow Frame Drop Counter Ports
0 - 3 ($0x594 – 0x597)" and “TX F IFO Overflow Frame Drop Counter P orts 0 - 3 ($0x 621 – 0x624)" in
the IXF1104 MAC support th is a nd increment when either an RX FIFO or TX FIFO overflows. If any
IXF1104 MAC programmable packet filtering i s enabled, the “RX FIFO Errored Frame Drop Counter
Ports 0 - 3 ($0x5A2 - 0x5A5)" and “TX F IF O Er ror e d F rame Dr op Co un t er P ort s 0 - 3 ( $ 0x 625 – 0x 629 )"
incremen t with every fra m e removed in addition to the ex isting frames counted due to FIFO ove rflow.
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packet s ha ve a valid prea mble and SFD, but have a bad CRC, or are either sho r ter than 64
octets or longer than 1518 oc tets.
5.1.8.2 Advantages
The follow ing lists additional IXF1104 MAC re gisters that support fea tures not documented in
RMON:
•MAC (flow) control frames
•VLAN Tagged
•Sequenc e Errors
•Symbol Errors
•CRC Erro r
The se additional counters allow for differenti ation beyond standard RMON probes.
Note: In fibe r mode, a packet tran s f er with an invalid 10-bit symbol does not alwa ys upda te the sta tistics
registers correc tly.
•Behavior: The IXF 1104 MAC 8B10B decoder su bstitutes a va lid code word octet in its p lace.
The packet transf er is aborted a nd marked as bad. The new internal length of the packet is
equal to the byte position where the inva lid symbol was. No pac ket fragments are see n at the
next packet transfer.
•Issue: If the invalid 10-bit code is inserted in a byte position of 64 or greater, expected RX
statis tics are reported. However , if the inva lid code is insert ed in a byte position of les s than
64, exp e ct ed RX st at is t i cs ar e n o t sto r ed.
5.2 SPI3 Interface
The IXF1104 MAC SPI3 Interface is im plemented to th e System Pac ket Interface Level 3 (SPI3)
Phy si cal Layer Interface standard. The interface function all ows the IXF1104 MAC blocks to
interface to higher-layer network processors or switch fabric.
The IXF 1104 MAC t r ansm it interf ac e a llows data fl ows from a net work processor or s witch fabric
device to the IXF1 104 MAC. The rece ive interface allows data to flow from the IXF1104 MAC to
the network processor or switch fabric de vice.
This interface receive s a nd transmi ts data betw ee n the MAC and the Network Proce ssor with
com pliant S PI3 in terfaces . The SPI3 interface operation is de fined in the OIF- S P I 3-01.0 (available
f rom the Optical Internet Worki ng Fo rum [www.oiforum. com]). The OIF specification defi nes
operation for the transfer of data at data rates of up to 3.2 Gbps when opera ting at a freque ncy of
104 MHz. The IXF1104 MAC d efines operation for the tran sfer of data at data rates of up to 4.256
Gbps when ope rating at a maximum frequency of 133 MHz in MPHY mode and 125 MHz in
SPHY Mode.
The r e is no guarant ee of the number of bytes avail able since the size of packet s is varia ble. An
I XF1104 MAC port-transm it pac ket available status is provided on signals DTPA, STPA or PTPA,
indicating the TX FIFO is nearly full.
I n the receive direct ion, RVAL indica tes if valid data is availa ble on the re ce ive data bus and is
defined so that data transfers can be ali gned with packet boundaries.
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The SPI3 interface supports the following two modes of operation:
•MPHY or 32 bit m ode (one 32-bit data bus)
•SPHY or 4 x 8 mode (four individual 8-bit data buses)
5.2.1 MPHY Operation
The MPHY o perati on mode is s ele cted wh en bit 21 of the “SPI3 T r ansm it and Glob al Confi gura tion
($0x700)” is se t to 0 and bit 7 of the “SPI3 Receive Configuration ($0x701)" is set to 1.
Data Path
The IXF1104 MAC SPI3 interface has a single 32-bit data path in the MPHY configuration m ode
(see Figure 13). The bus interface is point-to-point (one output driving only one input load), so a
32-bit data bus would s upport only one IXF1104 MAC.
To supp ort variable-le ngth pac kets, the RMOD[1:0]/TMOD[1 :0] s ignals are defined t o specify
valid bytes in the 32-bit data bus structure. Each double-w ord must contain four va lid bytes of
packe t data until the last double-w ord of the packet transf er , which is mar ked with the e nd of
packe t REOP/TEOP signal. This last double-word of the trans f er conta ins up to fou r valid bytes
specified by the RMOD[1:0]/TMOD[1:0] signals.
The IXF1104 MAC port sel ec tion is pe rformed us ing in-band addressing. In the transmit directi on,
the net w ork process or device selects an IXF1104 MAC port by sending the address on the
TDAT[1:0] bus marked with the T SX signa l active and TENB signal inactive. All subse quent
TD AT[1:0] bus operations mar ked with the TSX s i g nal inactive and th e TENB active are packet
data for the specified port.
In the rec eive direction, the IXF1104 MAC specifies the selected port by sending the address on
the RDAT[1:0] bus marked with the R SX signa l acti ve and RVAL signal inactive. All subse quent
RDAT[1:0] bus ope rations marked with RSX ina ctive and RVAL ac tive ar e packet data from the
specified port.
Note: See Table 17 “S PI3 MPHY/SPHY Interface” on pa ge 59 for a comp lete list of the MP HY mode
signals. The control signals wit h the port designat or for P ort 0 are the only one s used in MPHY
mode and they apply to all 4 ports. Table 3 “SPI3 Interface Signal Descriptions” on page 39
provides a comprehensive lis t of SPI3 signal descriptions.
5.2.1.1 SPI3 RX Round Robin Data Transmission
The IXF1104 MAC uses a round-ro bin protocol to serv ice each of the 4 ports dependent upon the
enabl e s tatus of the port and if there is dat a ava ilabl e to be taken from the RX FIFO. The round
robin order goes from port 0, port 1, port 2, port 3, and back to port 0. A port is skipped and the
next port is se rviced if it has no available transm it data. The data tran s f er burs ts are use r-
configurable burst lengths of 64, 128, or 256 byt es. The IXF1104 MAC als o has a configurable
paus e interv al between da ta transfer bursts on the receive side of the interface. The RX SPI3 burst
lengths and the pause interval can be set in the “SPI3 Receive Configuration ($0x701)").
5.2.2 MPHY Logical Timing
The SPI3 interface AC timing for MPHY can be found in Sec tion 7.2, “SPI3 AC Timing
Specifications” on page 137. Logical timing in the following diagrams illustrates all signals
as so ci at ed w it h MPH Y mo d e.
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5.2.2.1 Transmit Timing
I n MPHY mode a packe t transmi ssion st arts wi th the TSX signal indicati ng port address
information is on the data bus. The next clock cycle TENB a nd TSOP indicate present data on the
bus is the first word in th e pa cket and all subsequ ent cl ock s will contai n vali d data as lon g as TENB
is active or until TEOP is asserted. Dat a tra nsmis sion can be temp orally halted when TENB goes
high then resum ed when TENB is low. The valid byt es in the final word, du ring an active TEOP,
are in d i ca ted by st at e o f TMO D [ 1 :0 ] .
5.2.2.2 Receive Timing
A packe t is rec eived when RSX indicat es port addre ss information on the data bus followed by
RSOP to indicate the data bus contains the first word of a packet. All su bsequent dat a is valid only
while RVAL is High and until REOP is asserted. Receive data can be temporarily halted when
RENB is de-ass erted and starts agai n on the second ri sing edge of RFCL K following the assert ion
of RENB. RMOD indicat es the number of valid byt es in the last transfer when RE OP i s ass erted.
Figure 11 . MP HY Tra n s m it Lo gical Timing
B3216-02
TFCLK
TENB
TSOP
TEOP
TMOD
[1:0]
TERR
TSX
TDAT
[31:0]
TPRTY
0000 B0-B3 B4-B7 B48-B51B44-B47 B52-B55 B60-B64B56-B59 0001 B0-B3 B4-B7
1. Appl ies to al l tr ansmit packet available sign als (STPA, PTPA, DTPA_0:3).
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Figure 12. MPHY Receive Logical Timing
Figure 13. M P HY 32-Bit Interface
B3217-02
RFCLK
RENB
RSX
RSOP
RSX
RERR
RMOD
[1:0]
RDAT
[31:0]
RPRTY
RVAL
0000
B1-B3
B1-B3
B48-B51 B52-B55
B56-B59 B60-B63 00001
B4-B7
B0-B3
B0660-02
TFCLK
TENB
TDAT[31:0]
TPRTY
TERR
TSX
TSOP
TEOP
Network Processor SPI3 Bus IXF1104 MPHY
Mode
Transceiver
TFCLK
TENB_0
TDAT[31:0]
TPRTY_0
TMOD[1:0] TMOD[1:0]
RMOD[1:0] RMOD[1:0]
TERR_0
TSX
TSOP_0
TEOP_0
RFCLK
RENB
RDAT[31:0]
RPRTY RPRTY
RVAL
RERR
RSX
RSOP
REOP
RPRTY_0
RFCLK
RENB_0
RDAT[31:0]
RVAL_0
RERR_0
RSX
RSOP_0
REOP_0
DTPA_0:3
STPA
PTPA
TADR[1:0]
DTPA_0:3
STPA
PTPA
TADR[1:0]
Transceiver
Transceiver
Transceiver
Line-Side Interface
Port 0
Port 1
Port 3
Port 2
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5.2.2.3 Cloc k R ates
I n MPHY mode, the TFC LK and RFCL K can be i ndepen dent of each other . TFCL K and RFCLK
should be commo n to the IXF1104 MAC and the Ne twork P r ocess or. The IXF1104 MAC requires
a single cl ock s ource for the transmi t path and a single clock source for the receive path.
To allow all four IXF1104 MAC po rts to operate at 1 Gbps , the I XF1 104 MAC is designed to allo w
this interfac e to be overclocked. This allows operati on for data transfer at dat a ra tes of up to 4.256
Gbps whe n opera ting at an overclocke d frequency of 133 MHz.
Note: MPHY mode operates a t a maximum clock frequency of 133 MHz (TFCLK and RFCL K).
5.2.2.4 Parity
The IXF1104 MAC can be odd or even (the IXF1 104 MAC is odd by defaul t) when calculating
parity on the d ata bus. This can be change d to ac com m odate even pa rity if des ired, and can be set
f or transmit and rece ive independently. The RX Pari ty is set in bit 12 of the “SPI3 Receive
Configuration ($0x701)” and the TX Parity is set in bit 4 of the “SPI3 Transmit and Global
Configuration ($0x700)”.
5.2.2.5 SPH Y M o d e
The SPHY operation mode is se lected when bit 21 of the Table 146 “SPI3 Transmit and G lobal
Configuration ($0x700)” on page 213 is set to 1. The SPHY mode is the default operation for the
IXF11 04 MAC SPI3 interface.
5.2.2.5.1 Data Path
The IXF 1104 MAC SPI3 interface has four 8-bit data paths that ca n support four ind epende nt 8-bi t
point-to-point conn ec tions i n SPHY mode (see Figure 16). Since each MAC port has its own
dedic ated 8-bit SPI3 data bus, each port has it own s tatus signal (unlike MPHY). See the For a
deta iled list of all the signals refer to the SPI3 pin multiple xing table....
Furthermore since each port has it own dedic ated bus the in band port address ing is not nee ded.
The 8 bit data bus eli minates the need to have separat e control signals determine the number of
valid bytes on an EOP.There fore TSX, RS X, TMOD[1:0] RMOD[1:0] a r e not used in SPHY mode.
Note: See Table 17 “S P I3 MPHY/ S PHY Interface” on page 59 for a complete list of the SPHY mode
signals . Unlike MPHY mode, e ac h port has a dedic ated control signal ass ociat ed with each of the
per-port 8-bit data bus es . Tab le 3 “SPI3 Interface Signa l Des criptions” on page 39 provides signal
descriptions for all SPI3 signals.
5.2.2.5.2 Receive Data Transmission
Packets are transmitted on each port as they become available from the RX FIFO. The burst length
is determined by the setting of per port burst size and th e B2B pause settings in the “SPI3 Receive
Configuration ($0x701)". If the B2B pause setting is zero pause cycles inserted, then the entire
packet will be burst with out any pause s unless the Network Process or de-asserts RENB. If the
B 2B_Pa us e set tin g ca ll s fo r the ins er tio n of two pau se c ycl es o n a p ort , th ese a re i n sert ed a fte r ea ch
data burst for that port. The data bursts are user configurable for each port in the “SPI3 Receive
Configuration ($0x701)".
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5.2. 2.6 SPHY Logical Timing
SPI3 interface AC timing for SPHY can be found in Section 7.2 , “SPI3 AC Timing Spe cific ations ”
on page 137. Logical timi ng in the following diagr am s illustrates all signals a ssociated with SPHY
mode . SPHY mode is simila r to MP HY mode except the followin g signals are not used:
•TMOD[1:0]
•RMOD[1:0]
•TSX
•RSX
•Address Data appearing on the data bus
5.2. 2.7 Transmit Timing (SPHY)
Packet transmiss ion star ts when TE NB and TSOP indicate present d ata on the bus is the first word
in the packet. All subsequent clocks will contai n valid dat a as long as TENB is active or until
TEOP is ass erted . Data tr ansmis sion can be tempor ally ha lted when TENB goes hig h then resum ed
wh en T ENB is lo w.
5.2.2.8 Receive Timing (SPHY)
A packet is re ceived w h en RSOP is a ssert ed to indic ate the data bus contains the f irst word of the
packet. All subsequent data is valid only while RVAL is high and until RE OP is asserted. Receive
data can be tempora r ily halted when RENB is de-asserted and sta r ts again on the second ris ing
edge of RFCLK following the a ssertion of RENB. When REOP is asserted RMOD indicates the
number of valid bytes in the last transfer.
Figure 14. SP HY Transmit Logic al Timing
B3249-02
TFCLK
TENB
TSOP
TEOP
TERR
TDAT
[7:0]
TPRTY
B0 B1 B60B59 B61 B63B62 B0 B1 B2
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
89 Datasheet
Document Number: 278757
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Revision Date: 27-Oct-2005
Figure 15. SPH Y Receive Logical Timing
L
K
N
B
O
P
O
P
R
A
T
0
]
T
Y
A
L
B0 B2
B1 B62 B63 B0 B1
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 90
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5. 2.2. 8. 1 Clock Rates
The TFCLK and RFCLK can be i ndepen dent of each other in SPHY mode operation. T FC LK and
RFCLK should be common to all the Network Processor devic es. The IXF1104 MAC requires an
individual single clock source for the device tra nsmit path and a single clock source for the device
receive pa th.
The I XF110 4 MAC allows th is in terfac e to be over cl ocke d s o t hat al l fou r IX F1 1 04 MA C po rts can
operate at 1 Gbps. This allows data tra nsfer at data rates of up to 4.0 Gbps when operating at a n
overclocked frequency of 125 MHz.
Note: SPHY operates at a maximum frequency of 125 MHz.
Fig ure 16 . S P H Y Connect i on f or Two Intel ® IXF1104 MA C Ports (8-Bit Interface)
B0659-02
TFCLK
TENB[0]
TDAT[7:0][0]
TPRTY[0]
TERR[0]
TSOP[0]
TEOP[0]
Network Processor SPI3 Bus Intel
®
IXF1104
Port 0
TFCLK
TENB_0
TDAT[7:0]_0
TPRTY_0
TERR_0
TSOP_0
TEOP_0
RFCLK
RENB[0]
RDAT[7:0][0]
RPRTY[0] RPRTY_0
RVAL[0]
RERR[0]
RSOP[0]
REOP[0]
RFCLK
RENB_0
RDAT[7:0]_0
RVAL_0
RERR_0
RSOP_0
REOP_0
DTPA[0]
TFCLK
TENB[1]
TDAT[7:0][1]
TPRTY[1]
TERR[1]
TSOP[1]
TEOP[1]
RFCLK
RENB[1]
RDAT[7:0][1]
RPRTY[1] RPRTY_1
RVAL[1]
RERR[1]
RSOP[1]
REOP[1]
DTPA[1]
DTPA_0
Transceiver
Port 1
SPI3
Flow Control
TFCLK
TENB_1
TDAT[7:0]_1
TPRTY_1
TERR_1
TSOP_1
TEOP_1
RFCLK
RENB_1
RDAT[7:0]_1
RVAL_1
RERR_1
RSOP_1
REOP_1
DTPA_1
Transceiver
Port 0
Port 1
Line-Side
Interface
Line-Side
Interface
PTPA
TADR[1:0] PTPA
TADR[1:0]
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5.2.2.8.2 Parity
The IXF1104 MAC can be odd or even (the IXF1 104 MAC defaults to odd) when ca lculating
parity on the d ata bus. This can be change d to ac com m odate even parity if des ired, and can be set
f or transmit and receive ports independently. The RX and TX parity sense bits have a direct
relationship to the port parity in SPHY mode.
Th e p er po r t R X par i ty is set in th e “SPI3 Rec eive Configuration ($0x701)" and t he per po rt TX
Parity is set in the “SP I 3 Transmit and Globa l Configuration ($0x700)".
5.2.2.9 SPI3 Flow Control
The SPI3 pack et interfa ce sup ports t ransmit and receive data t ransfe rs at clock rate s indep endent of
the line bit rat e. As a result, the IXF1104 MAC supports packet rate dec oupling using internal
FIFOs. These FIFOs are 10 KB per port in the transmit direction (egress from the IXF1104 MAC
to the line interfaces) and 32 KB per port in the rece ive direction (i ngress to the IXF1104 MAC
from the line interfaces ) .
Contr ol s ignals ar e provi ded to the network proc essor a nd the I XF1 104 MAC to a llow ei ther one t o
exercise flow control . Since th e bus interface is point - to-point, the receive in terface of the
I XF1 104 MAC pushes dat a to the link-l ayer devi ce. For the transmit int er face, the packet ava ilabl e
status granulari ty is byte-based.
5.2.2.9.1 RX SPI3 Flow Control
In the receive direction, whe n the IXF1104 MAC has stored an end-of-packet (a comple te small
packet or the end of a larger pac ket) or some prede f ined number of bytes in its receive FIFO, it
se nds the in-ba nd address followed by FIF O data to the link-lay er dev ice (in MPHY mode). The
data on the interface bus is marked with the valid s ignal (RVAL) asserted. The network processor
device can pause the data flow by de-as serting the Receive Read Ena ble (RENB) sign al.
RENB_0:3
RENB_ 0:3 control s the flow of data from the IXF1 1 04 MAC RX FIFOs. In SPHY mode, there is a
dedicated RENB for each port. In MPHY mode, RENB_0 is used as the global signal covering all
ports. When RENB is sampled Low, the network process or ca n accept data. A read is performed
from the RX FIF O and t he RD AT, RPRTY, RMOD[1:0], RS O P, REOP, RERR, RSX, and RVAL
signals are updated on the following rising edg e of RFCLK.
RENB c an be assert ed High by th e Network P rocess or at any t ime if it is unable to acc ept any more
data . When the RENB is sampled High by the IXF1104 MAC, a read of the RX FIFO is not
p er f ormed, and the RDAT, RPRTY, RMOD[ 1:0], RSOP, REOP, RERR, RSX and RVAL signals
remain unchanged on the following rising edge of RFCLK.
5.2.2. 9.2 T X SPI 3 F l ow C o n tr o l
I n the transm it direction, when the IXF1104 MAC has space for some pred efined number of bytes
in its transmit FIFO, it inform s the Net work P r ocessor device by asserting one of the T r ansmi t
Packe t Availa ble (T PA) signa ls. The Networ k Pr ocess or devi ce writ es t he in- band address follo wed
by pac ket da ta to th e IXF1104 MAC usi ng an ena ble s ignal (T ENB). The networ k process or devi ce
monitors the TPA signals for a High-to-Low tra nsition, which indicates that the tra nsmit FIFO is
almost ful l (the number of bytes left in the FIFO is user-sel ec table by setting the “TX FIFO Hi gh
Watermark Ports 0 - 3 ($0x600 – 0x603)", and suspends data transfer to avoid an overflow. The
Network Processor device can pause the da ta flow by de-asserti ng the enable signal (TENB).
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The IXF1104 MAC provid es the following three types of TPA signals:
•Dedicated per port Direct Transmit Packet Available (DTPA)
•Selected-PHY Transmit Packet Available (STPA), which is based on the current in-band port
address in MPHY mode.
•Po ll e d- P HY Trans mit pa ck et Ava il a b l e ( PT PA), w h ich p rov i d es FI F O in f ormat io n on th e p or t
se le cted by th e TAD R [ 1 :0 ] si g n al s .
The fol lowing three TPA signals (DTPA_0: 3, STPA, and PTPA) provide flow co ntrol based on the
programmable TX FIFO High and Low watermarks. Refer to Table 13 2 “TX FIFO High
Watermark Ports 0 - 3 ($0x600 – 0x603)” on page 203 and Table 133 “TX FIFO Low Watermark
Register Ports 0 - 3 ($0x60A – 0x60D)” on page 204 for more information.
DTPA_0:3:
A direct status indicat ion for the TX FIFOs of port s [0:3]. When DTPA is High, it indicates th e
amou nt of data in the TX F IFO is be low the TX FIFO High watermark. When the High watermark
is crossed, DTPA transitions Low to indicate the TX FIFO is alm ost full. It s tays low until the
amou nt data in the TX FIFO goes back below the TX FIFO Low watermark. At this point, DTPA
tr ansitions High to indica te the pro grammed number of bytes are now available for data trans f ers.
DTPA_0:3 is updated on the rising edge of the TFCLK.
STPA:
STPA provides TX FIF O st atus for the cu rrently selecte d port in MPHY mode. When High, STPA
indicates that the amount of data i n the T X FIFO f or the port s elected, spec ified by the latest in-
band address, is be low the TX FIF O High watermark. When th e High watermark is crossed, STPA
tr ans itions Low to indicate t he T X FIFO is a lm ost full. It s tays Low until the amount of d ata in the
TX FIFO goes bac k below the TX FIFO Low watermark. At this point, STPA transitions High to
indicate the progra mmed number of byte s are now availab le for data transfer s.
The port r eported by STPA is updated on the rising edge of TFCLK after TSX is sa mpl ed as
asserted. STPA is updated on the rising edge of TFCL K.
Note: STPA is only used when the IXF1104 MAC is configured for MPHY mode of operatio n.
PTPA:
PTPA provides status of the TX FIFO based on the port selected by the TADR[1:0] address bus.
When High, PTPA indicates that the amount of data in the TX FIFO for the port selected is below
the T X FIFO High watermark. W hen the High wate rmark is crossed, PTPA trans itions Low to
in dicate the TX FIFO is al mos t fu ll. It stays Low until the amou nt of data in the TX FI FO goes
back below the TX F IF O Low wat ermark. PTPA then trans itions High to indicate the pro grammed
numbe r of bytes are now availabl e for da ta transfers.
The port reported by PTPA is updated on the rising edge of TFC LK aft er the TADR{1:0] po rt
address is sa mp led.
PTPA is update d on the rising edge of TFCLK.
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5.2 .3 Pre- Pending Function
The IXF1104 MAC i m plements a pre-pending f eature to allow 1518-byte Etherne t pac kets to be
pre-padded with two additional bytes of data so that the packet becomes low-word aligne d. The
2-byte pre-pend value is all zeros and is ins erted before the destinati on address of the packet being
pr e-pended. This val ue is fixed a nd cannot be chan ged.
This function is enabled by wr iting the appr opriate data to the “RX F I FO Padding and CRC Strip
Enable ($0x5B3)" for each port.
A standard 1518-byte Ethernet packet occupies 379 long words (four bytes) with two additional
bytes left over (1518 /4 = 379. 5). To eliminate the memory-manage me nt proble ms for a net work
pr oce ssor or switch fabric, the two remaining bytes are dealt with by the ad dition of two bytes to
the start of a packet. T his resul ts in a standard 1518-byte Ethernet packet rece ived by the IXF1 104
MAC being forwarded to the higher-layer device as a 380-long-word packet. The upper-layer
devic e is responsible for stripping the additional two bytes.
This feature was added to the IXF1104 MAC to ass is t in the design of higher-laye r memory
ma nagement . T he addition of the two ext ra bytes is not the default oper ation of the IXF 1104 MAC
and m ust b e enabled by th e use r . The de fault oper ation of the IXF1 1 04 MAC SPI3 re ceiv e inte rface
forwards data exactly as it is received by the IXF1104 MA C line interface.
5.3 Gigabit Media Independent Interface (GMII)
The IXF1104 MAC supports a subset of the GMII interface s tandard as defined in IEEE 802. 3
2000 Editi on for 1 Gbps operation only. This subset is lim ited to operation at 1000 Mbps full-
duplex.
The GMII Interface operates as a source synchronous interface only and does not accept a TXC
clock provi ded by a PHY device when operat ing at 10/100 Mbps speed s.
Note: The RGMII interfac e must be used for applic ations that require 10/100/1000 Mbps operation.
The IXF1104 MAC does NOT suppor t 10/100 Mb ps copper PHY devices that are implemented
using the MII Interface.
Note: MII operation is n ot supported by the IXF1104 MAC.
The use r can select GMII, RGMII, or Opti cal Module/SerDe s func tionality on a per- port basis.
This mode of operation is controlled through a co nfiguration register.
While IEEE 802.3 specifi es 3.3 V operation of GMII devices, most PHYs use 2.5 V signaling. The
IX F1104 MAC provides a 2.5 V drive and is 3.3 V-tolerant on inputs .
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Datasheet 94
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5.3.1 GMII Signal Multiplexing
The GMII balls are reassigned when using the RGMII mode or fiber mode. Table 16 “Line Side
Interface Multipl exed Balls” on page 58 specifies the multiple xing of GMII ba lls in these modes.
See Section 5.1.3, “Mixed-Mode Ope ration ” on page 75 for proper conf iguration of the IXF1104
MAC in GMII mo de.
5.3.2 GMII Interface Signal Definition
Table 26 “GMII Interface Signal Definitions” on page 95 provide s the GMII interface signal
definitions. For information on 1000BASE-T GMII transmit and receive timing diagrams and
tabl es, please refer to Ta ble 49 “GMII 1000B ASE-T Transmit Signal Par ameters” on page 142,
Fig ure 38 “1 000BAS E-T Transmit Inte rface Timing” on page 142, Figure 39 “1000BASE-T
Rece ive Interface Timing” on page 143, and Tabl e 50 “GMII 1000BASE-T Rec eive Signal
Parameters” on page 143
Figure 17. MAC GM II Interconnect
TXC_3:0
TX_EN_3:0
TX_ER_3:0
RXC_3:0
TXD[7:0]_0
TXD[7:0]_3
TXD[7:0]_2
TXD[7:0]_1
RX_EN_3:0
RX_ER_3:0
RXD[7:0]_0
RXD[7:0]_3
RXD[7:0]_2
RXD[7:0]_1
COL_3:0
CRS_3:0
Intel® IX F1104
Media Access Controller
TXC_3:0
TX_EN_3:0
TX_ER_3:0
TXD[7:0]_0
TXD[7:0]_3
TXD[7:0]_2
TXD[7:0]_1
RXC_3:0
RX_EN_3:0
RX_ER_3:0
RXD[7:0]_0
RXD[7:0]_3
RXD[7:0]_2
RXD[7:0]_1
COL_3:0
CRS_3:0
Quad PHY Device
B3203-0
1
Intel® I XF1104 4-Port Gigab it Ethern et Media Acces s Controller
95 Datasheet
Document Number: 278757
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Tab le 26. GM II Interface Signal Definitions
IXF1104 MAC
Signal GMII Standard
Signal Source Description
TXC_0
TXC_1
TXC_2
TXC_3
GTX_CLK IXF1104
MAC
Transmit Reference Clock:
125 MHz for Gigabit operation.
MII operation for 10/100 Mbps operation is not
supported.
TXD[7:0]_0
TXD[7:0]_1
TXD[7:0]_2
TXD[7:0]_3
TXD[7:0] IXF1104
MAC
Transmit Data Bus:
Width of this syn c hronous output bus vari es with the
speed/mode of operation. In 1000 M bps mode, a ll 8
bits ar e used.
TX_EN_0
TX_EN_1
TX_EN_2
TX_EN_3
TX_EN IXF1104
MAC
Transmit Enable:
Synchronous inp ut that indicates Valid data is being
driven on the TXD[7:0] data bus.
TX_ER_0
TX_ER_1
TX_ER_2
TX_ER_3
TX_ER IXF1104
MAC
Transmit Error:
Synchronous input to PHY causes the transmission of
err or symb ols in 1000 Mbps links.
RXC_0
RXC_1
RXC_2
RXC_3
RX_CLK PHY Receive Clock:
Continuous reference clock is 125 MHz +/– 100 ppm.
RXD[7:0]_0
RXD[7:0]_1
RXD[7:0]_2
RXD[7:0]_3
RXD<3:0> PHY
Receive Data Bus:
Width of the bus v aries with the spee d and mode of
operation. In 1000 Mbps mode, all 8 bit s are driven by
the PHY device.
Note: MII opera tion at 10/100 Mbps i s not supported.
RX_DV_0
RX_DV_1
RX_DV_2
RX_DV_3
RX_DV PHY Receive Data Valid:
This signal is asserted w hen valid data is present on
the corresponding RXD bus.
RX_ER_0
RX_ER_1
RX_ER_2
RX_ER_3
RX_ER PHY
Receive Error:
In 1000 Mbp s mode, as serted w hen error symbols or
carrier extension symbols are received.
Always synchronous to R X_CLK.
CRS_0
CRS_1
CRS_2
CRS_3
CRS PHY Carrier Sense:
Asserted when valid activity is detected at the line-
sid e inter f ac e.
COL_0
COL_1
COL_2
COL_3
COL PHY
Collision:
As s erted wh en a coll is ion is de tecte d and rem ains
asserted for the duration of the collision event. In full-
duplex mode, the PHY should force this signal Low.
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5.4 Reduced Gi gabit Media Independe n t Interface (RGMII)
The IXF1104 MAC supports the RGMII int erfa ce standard as defined in the RGMII Ver si on 1.2
sp ec i fi c a t io n . Th e R G MII in ter f ac e is a n al te r n at ive to th e IEEE 8 02 . 3u M I I in t er f ace.
The RGMII in terf ace is intended as an alternative to the IEEE 802.3u MII and th e IEEE 802 .3z
GMII. The principle obj ective of the RGMII is to reduc e the num ber of balls (from a maximum of
28 balls to 12 balls) required to interconnect the MAC and the PHY. Th is reduction is both co st-
effectiv e and technology-independent. To acc omplish this o bject ive, the data paths and all
associated control signals are red u ce d, control signals are multiplexed toget her, and both edge s of
th e clock are used .
•1000 Mbps operation – clocks ope rate at 125 MHz
•100 Mbps operation – clocks operate at 25 MHz
•10 Mbps ope ration – clocks operat e at 2.5 MHz.
Note: The IXF1104 MAC RGMII interface is multiplexed with signals from the GMII interface. See
Table 16 “Line Side Interface Mult iplexed Balls” on pa ge 58 for detailed information.
5.4.1 Multiplexing of Data and Control
Multiplexing of data and control information is achi eved by utilizing both ed ges of the refer ence
cloc ks and se ndin g the lowe r four bits on th e rising ed ge and the upper four b its on the fa lling e dge.
Control si gnals are multiplexed into a single clock cycle us ing the same technique. For further
information on timing paramet ers , see F igure 37 “RGMII Interface Timing” on pa ge 141 and
Table 48 “RGMII Interface Timing Parameters” on page 141.
Figure 18. RGMII Interface
TXC_3:0
TX_CTL_3:0
TXD[3:0]_3
TXD[3:0]_0
TXD[3:0]_1
TXD[3:0]_2
Intel® IXF1104
M edia Ac cess Controller
TXC_3:0
Quad PHY Device
B3203-0
1
TX_CTL_3:0
TXD[3:0]_3
TXD[3:0]_0
TXD[3:0]_1
TXD[3:0]_2
RXC_3:0
RX_CTL_3:0
RXD[3:0]_3
RXD[3:0]_0
RXD[3:0]_1
RXD[3:0]_2
RXC_3:0
RX_CTL_3:0
RXD[3:0]_3
RXD[3:0]_0
RXD[3:0]_1
RXD[3:0]_2
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5. 4.2 T iming S p ecifi cs
The IXF1104 MAC RGMII complies wit h RGMII Rev1. 2a requirements. Table 27 provides the
tim i n g s p ec if i c s .
5.4.3 TX_ER and RX_ER Coding
To reduce interface power, the tra ns mi t error condition (TX_ER) and the receive error condition
( RX_ER) are encoded on the RGMII interface to minimiz e tra nsitions during norm al net work
opera tion (ref er to Table 28 on page 97 for the encoding method). Table 27 provides signal
definitions for RGMII.
The value of RGMII_TX_ER and RGMII_T X _EN ar e val id at the rising edge of the clock while
TX_ER is presented on the fallin g edge of the clock. RX_ER coding behaves in the same way (see
Table 28, F igure 19, and Figure 20).
Tab le 27. RGM II Signal Definitions
IXF 1104
MAC Signal
RGMII
Standard
Signal Source Description
TXC_0:3 TXC MAC Depending on speed, the transmit reference clock is 125 MHz, 25
MHz, or 2.5 MHz +/– 50ppm.
TD[3:0]_nTD<3:0> MAC Contains register bits 3:0 on the rising edge of TXC and register bits
7:4 on the falling edge of TXC.
TX_EN TX_CTL MAC T XEN is on t he leading e dge of TXC.
TX_EN xor TX_ER i s on the f alling ed ge of TX C.
RXC_0:3 RXC PHY Con tinuous refe rence c lock is 125 MHz, 25 MHz, or 2.5 MHz +/– 50
ppm.
RD[3:0]_nRD<3:0> PHY Contains register bits 3:0 on the leading edge of RXC and register bits
7:4 on the trailing edge of RXC.
RX_DV RX_CTL PHY RX_DV is on the le ading edge of RX C.
RX_DV or RXERR is the falling edge of RXC.
Table 28. TX_ER and RX_ER Coding Description
Condition Description
Receiving valid frame,
no errors RX _D V = t rue
Logic High on rising edge of RXC RX_ER = false
Logic High on the falling edge of RXC
Receiving valid frame,
with errors RX _D V = t rue
Logic High on rising edge of RXC RX_ER = true
Logic Low on the falling edge of RXC
Receiving invalid frame
(or no frame) RX_DV = false
Logic Low on rising edge of R XC RX_ER = false
Logic Low on the falling edge of RXC
Transmitting valid frame,
no errors TX_EN = true
Logic High on risin g edge of TXC TX_ER =fa ls e
Logic High on the falling edge of TXC
Tran sm ittin g vali d fr am e
with errors TX_EN = true
Logic High on risin g edge of TXC TX_ ER = true
Logic Low on the falling edge of TXC
Tran sm it ting inv a lid
f ram e ( o r no fra m e) TX_ EN = false
Logic Low on rising edge of TXC TX_ER = fals e
Logic low on the fallin g edge of T XC
NOTE: Refer to Fi gure 19 for TX_CTL behavior, and Figure 20 for RX_CTL behavior.
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
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Figure 19. T X _CTL Behavior
Figure 20. RX _CT L Beh avior
B0616-02
TXC_0:3
(at Transmitter)
TD[3:0]_0:3
TX_CTL_0:3 End-of-Frame
TD[3:0] TD[7:4]
TX_EN=True TX_ER=False TX_EN=False TX_ER=False
TXC_0:3
(at Transmitter)
TD[3:0]_0:3
TX_CTL_0:3
End-of-Frame
TD[3:0] TD[7:4]
TX_EN=True TX_ER=False TX_EN=False TX_ER=False
Valid Frame
Frame with Error
B3237-01
RXC_0:3
(at PHY)
RD[3:0]_0:3
RX_CTL_0:3
End-of-Frame
RD[3:0] RD[7:4]
RX_DV=True RX_ER=False RX_DV=False RX_ER=False
RXC_0:3
(at PHY)
RD[3:0]_0:3
RX_CTL_0:3
End-of-Frame
RD[3:0] RD[7:4]
RX_DV=True RX_ER=True RX_DV=False RX_ER=False
Valid Frame
Frame with Error
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5.4.3.1 In-Band Status
Carrier Sense (CRS) is generated by the PHY when a packet is received from the network
in terface. CRS is indi cated when:
•RXDV = true.
•RXDV = fals e, RXERR = true, and a value of FF exis ts on the RXD[ 7:0] bits simultaneously.
•Carri er Exte nd, Carrier Exte nd Error, or False Carrier occurs (please reference the Hewlett-
Packard* Version 1. 2a RGMII Spec ification for details.).
Carrier Extend and Carrier Extend Error are applicable to Gigabit speeds only. C ollision is
determined at the MAC by the assertion of TXEN being true whi le eith er CRS or RXDV are tr ue.
The PHY will not assert CRS as a result of TXEN being true.
5.4.4 10/100 Mbps Functionality
The RGMII interface impleme nts the 10/100 Mbps E thernet Media Independen t Interface (MII) by
r educ ing the clock rate t o 25 MHz for 100 Mbps operati on and 2.5 MHz for 10 Mbps. The TXC is
generated by the MAC and the RXC is genera ted by th e PHY. During packet reception, the RXC is
stretched on either the positive or neg ative pul se to accommoda te transiti on from the free-running
clock to a data-synch r onous clock do ma in. When the speed of the PHY chang es, a similar
st retchi ng of the po siti ve or negati ve puls es is a llo wed. No gli tching of the clock s is all owed during
speed tran siti ons.
This interface operates at 10 Mbps and 100 Mbps spee ds in the same manner as 1000 Mbps speed,
although the data may be duplicated on the falling edge of the appropriate clock. The MAC holds
TX_CT L L ow until it is operat ing at the same speed as the PHY.
Note: The IXF1104 MAC does not support 10/100 Mbps operation when configured in GMII mode
5.5 MDIO Control and Interface
The IXF1104 MAC supports the IEEE 802.3 MII Management Interface, also known as the
Management Data Input/Output (MDIO) Interface. T his interface allows the IXF1104 MAC to
moni tor and cont rol each of the PHY devices th at are connec ted to the four ports of IXF1 104 MAC
when those por t s ar e in copp er mo d e.
The MDIO Master Interfac e block is implemented once in the IXF1104 MAC. The MDIO
I nterface block contains the logi c through which the user accesses the regis ters in PHY devic es
connected to the MDIO/MDC interface, which is controlled by e ach port.
The MDIO Master Interface bloc k sup ports the management frame format, specif ied by IEEE
802.3, cl ause 22.2.4.5. This block al so supports singl e MDI ac ce ss through the CPU interface and
an aut oscan mode. Aut oscan all ows the IXF1 10 4 MAC MDIO master to read all 32 regis ters of the
per-port copper PHYs and store the contents in the IXF1104 MAC. This provides external-CPU-
r eady acce ss to the PHY regi ster conte nts th rough a si ngle CPU read wi thout the latenc y of waitin g
on th e low -spe ed s er i al MDI O da ta bus f or ea ch re g is t er ac ce s s.
Scan of a single register with low-frequency operation takes approximately 25.6 µs. Scan of a 32-
register block ta kes approximately 820 µs, or 3.3 m s for all four ports. Autoscan data is not valid
until approximately 19.2 µs after enabl ing scan. These numbers sc ale by 7/50 f or high-frequency
operation.
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5.5.1 MDIO Address
The 5-bi t P HY addre ss for the MDIO transact ions can be set in the “MDIO Single Command
($0x680)". Bits 5:2 of the PHY ad dres s are fixed to a value of 0. Bits 1 and 0 are programmable in
bits 9 and 8 of “MDIO Single Command ($0x680)".
5.5.2 MDIO Register Descriptions
For complete info rmation on the MDI registers, re fer to the Table 142 “MDIO Single Command
($0x680)” on page 211, Table 143 “ MDIO Single Read and Write Data ($0x681)” on page 211,
Table 144 “Autoscan PHY Addres s Enable ($0x6 82)” on page 212, and Table 145 “MDIO Control
($0x683)” on page 212.
5.5.3 Clear When Done
The MDI Command re giste r bit, i n the “MDIO Singl e Command ($0x680)" , cl ears upon command
comp letion and is se t by the user to start the requested single MDIO Read or Write ope ration. This
bit is cleared automatically upon ope ration comple tion.
5.5.4 MDC Generation
The MDC clock is used for t he MDIO/MDC interface. The freque ncy of the MDC cl ock is
sel ec table by setting bit 0, MDC S peed, in an IXF1104 MAC configuration register (see Table 145
“MDIO Control ($0x683)” on page 212).
5.5.4.1 MDC High-Frequency Operation
The high-frequency MDC is 18 MHz, derived from the 125-MHz syste m clock by dividing the
frequency by 7.
The duty cycle is as follows :
•MDC High dur ation: 3 x (1/125 MHz) = 3 x 8 ns = 24 ns
•MDC Low duration: 4 x (1/125 MHz) = 4 x 8 ns = 32 ns
•MDC runs con tinuously after reset
Refer to Figure 41 “MDC High-Speed Operation Timing” on page 145 for the high-frequency
MDC timi ng diagram.
5.5.4.2 MDC Low-Frequency Operation
The low-frequency MDC is 2.5 MHz, which is derived from the 125- MHz syst em clock by
dividing the frequ enc y by 50.
The duty cycle is as follows :
•MDC High dur ation: 25 x (1/125 MHz) = 25 x 8 ns = 200 ns
•MDC Low duration: 25 x (1/125 MHz) = 25 x 8 ns = 200 ns
•MDC runs con tinuously after reset
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Refer to Figure 42 “MDC Low-S peed Operati on Tim ing” on page 14 5 for the low freque ncy MDC
timing dia gram.
5.5.5 Management Frames
The M an a ge m e n t Interf ace ser ia li zes th e ex t er n al re gis t er ac cess in f ormat io n in to th e f ormat
spe cified by IEEE 802.3, Section 22.2.4. 5 (se e Figure 21).
5.5.6 Single MDI Command Operation
The Management Data Interface is accessed through the “MDIO Single Command ($0x680)" and
the “MDIO Single Re ad and Write Data ($0x681)". A single manage ment frame is se nt by setting
Register 0, bit 20 to logic 1, and is automatically c leared when the frame is compl eted.
The W r ite dat a is first set up in Reg iste r 1 , bits 15:0 for Write opera tion. Register 0 is init ialized
with the appro priate c ontrol inf ormati on (sta rt, op code, etc.) and Regi ste r 0, bit 20 is set to logic 1.
Register 0, bit 20 is reset to logic 0 when the frame is complete.
The steps are identical for Read operation except that in Register 1, bits 15:0, the data is ignored.
The data recei ved from the MDIO is read by the CPU int erface from Register 1, bit s 31: 16.
5.5.7 MDI State Machine
The MDI S tate Machine sequences th e in f o r mation sent to it by t h e MDIO con trol re g i sters an d
keeps tra ck of the current sequence bit count, ena bling or dis abling the MDIO driver output (s ee
Figure 22.
Figure 21. Mana gement Frame Structure (Single -Frame Fo rmat)
Preamble
32 Bits Start
2 Bits Op Cod e
2 Bits PHY Addr
5 Bits Turnaround
2 Bits Data
16 Bits
First Bit Transmitted Last Bit Transmitted
REG Addr
5 Bits
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Figure 22. MDI State
Idle
Preamble
Go = 1
Cnt = 32
Cnt < 32
Start Bits
Cnt = 2
Cnt < 2
Cnt > 32
Cnt > 2
Cnt > 2
Op Code
Phy Addr
Cnt = 2
Cnt < 2
Cnt > 5 Cnt < 5
Reg Addr
Cnt = 5
Cnt = 5
Cnt < 5
Cnt > 5
Turn Arou nd
Cnt > 2 Cnt < 2
Cnt = 2
Data
Cnt < 16
Cnt > 16
Cnt = 16 And Go = 1
or (Cnt = 16 and
Go = 0)
MDOE = 0
MDO = 0
MDC_EN = 0
MDOE = 1
MDO = 1
MDC_EN = 1
MDOE = 1
MDO = Reg_Bit_St(Cnt)
MDC_EN = 1
MDOE = 1
MDO = Reg_Bit_Op(Cnt)
MDC_EN = 0
MDOE = 1
MDO = Reg_Bit_PA(Cnt)
MDC_EN = 1
MDOE = 1
MDO = Reg_Bi t_RA (Cnt)
MDC_EN = 1
MDOE = Wr_Op
MDO = Reg_Bit_WO(Cnt)
MDC_EN = 1
MDOE = Wr_Op
MDO = Data(C nt)
MDC_EN = 1
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5.5.8 Autoscan Operation
The au t osca n fu nc tio n all o ws th e 32 re g is ters in each ex t er nal PHY (u p to f our ) to be st ored
internally in the IXF1104 MAC. Autoscan is enabled by setting bit 1 of the MDI Control register.
When enabled, autoscan runs conti nuously, reading each PHY register. When a PHY register
acc es s is instigated through the CPU interface , the current autoscan regist er Read is completed
b efo re the CPU regis t er acce ss starts. Upon comp letion of the CPU-induced access, the autosc an
f unctionality restarts from the la s t autoscan register acc es s.
The“Autoscan PHY Addre ss En able ($0x6 82)" determines which PHY address es are bei ng
occupied for ea ch IXF1104 MAC port. The least significant bit (LSB) t hat is set in the regi ster is
Port 0, th e next si gnificant bit that is s et is assumed to be port 1, and s o on. If more than four bits
are set, the bits beyond the fourt h bit are ignored. If less than four bits are set, th e round-robin
process returns to the port identified by the LSB being set.
5.6 SerDe s Interface
The IXF1104 MAC integr ate s four integrated Seriali ze r /Deserializ er (SerDe s) devices that allow
dire ct conne ction to optic al modules and remove the requ irement for ex te rnal SerDes dev ices. This
increases integration, which re duce s the siz e of the PCB area required to implement th is funct ion,
r educ es total power, reduces silicon and manufacturing costs, and improves reliability. Each
Se rDes interface is i d entica l and f u lly compl i ant with the relevant IEEE 802 .3 S p ecificati ons,
including auto-ne gotiation. Each port is also compliant with and suppor ts the requi rem ents of the
Small Form Factor Pluggable (SFP) Multi-Source Agreement (MSA), see S ect ion 5.7, “Opti cal
Module Interface” on page 107.
The following secti ons describe the operat ions suppor ted by each inte rface, the con figurable
options, and the regis ter bits that control these options. A full list of the re gister addresses and full
bit definitions are found in the register maps (Table 59 through Table 69).
5.6.1 Features
The SerDes core s are designed to operate in poi nt-to-point data tr ansmiss ion applications. While
the core can be use d acro ss various media types, such as PCB or ba ckplanes , it is configured
spe cifically for use in 1000BASE - X Ethernet fiber applic ations in the IXF11 04 MAC. Th e
f ollowing features are supported.
•10-bit data path, which connects to the out put/input of the 8B/10B encoder/decoder PCS that
resides in the MAC controller
•Data frequency of 1.25 GHz
•Low powe r: < 200 mW per SerDes port
•Async hronous clock data re cove ry
5.6.2 Functional Description
The SerDes transmit interface sends serialized data at 1.25 GHz. The interface is differential with
two signals for transmit opera tion. The transmit interface is designed to operate in a 100 Ω
d i fferential environment and all th e terminations ar e includ ed on the device. The outputs are high-
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spe ed SerDe s and are capabl e of operat ing in either an AC- or DC-coupl ed en vironment. AC
coupling is recommende d for this interface to en su re that th e correct input bias current is supplied
at the receiver.
The S erDe s rece ive int erfa ce rec ei ves seri ali ze d dat a at 1.25 GHz . The int erf ace is dif f er ent ia l with
two signals for the receive operation. The equalizer receives a differential signal that is equalized
for the assumed media channel. The Ser Des tran sm it and receive in terfac es are desi g n ed to o pera t e
within a 100 Ω differential environment and al l termi nations are included on the device . The
Ser Des is capable of opera ting in either AC- or DC-coupled envi ronmen ts .
5.6.2.1 Transmitter Operational Overview
The t ransmit sectio n of the IXF1104 MAC has to ser ializ e the Ten Bit I nterface ( TBI) data fro m the
IXF1104 MAC MA C section a nd outputs this da ta at 1.25 GHz differentia l signal leve ls. The
1.25 GHz diffe ren ti al SerDes signals are compliant with the Small Form Factor Pluggable (SFP)
Multi-Source Agreement (MSA).
The transmitter sec tion takes the content s of the data register within the MAC and synchr onously
transfers the data out, ten bits at a time – Least Significant Bit (LSB) first, followed by the next
Most Significant Bit (MSB). Whe n the se te n bits have bee n serialized and transm itted, the next
word of 10-bit da ta from the MAC is ready to be serialize d for tra nsmission.
The data is trans mitted by the high-speed current mode differential SerDe s output sta ge using an
interna l 1. 25 GHz clock generated from the 125 MHz cloc k input.
5.6.2.2 Transmitter Programmable Driver-Power Levels
The IXF1104 MAC SerDes core has programmable transmitter power levels to enhance us abili ty
in any given app licat ion.The SerDes Registers are programmable to al low adjustment of the
transmit core driver output power. When driving a 100 Ω differential t erminated network, these
output power settings effectively establish the differential voltage swings at the driver output.
The “TX Driver Power Level Ports 0 - 3 ($0x784)" allows the sel ection of four dis cret e powe r
set tings . The sele ct ed power se tt ing of the se i nputs i s appl ied to e a ch of the trans mit core drive rs on
a per- port basis. Table 29 “SerDes Driver TX Power Levels” lists the norm alized power sett ings of
the transmit drivers as a function of the Driver Power Control inputs. The normalized current
setting is 10 mA, whic h corresponds to the normalized power setting of 1.0. This is the default
setting of the IXF1104 MAC SerDes interface. Other values listed in the Normalized Driver Power
Setting column are mult iples of 10 mA. For exam ple, wit h inputs at 1110, the driver power is the
following:
.5 x 10 mA = 5 mA.
Table 29. SerDes Dri ver TX P ower Levels
DRVPWRx[3] DRVPWRx[2] DRVPWRx[1] DRVPWRx[0] Normalized
Driver Power
Setting Driver Power
0 0 1 1 1.33 13.3 mA
NOTE: All other values are reserved.
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5.6.2.3 Rec ei ver Op er ational Overvi ew
The receiver structure performs Clock and Data Rec overy (CDR) on the incoming seria l data
st rea m. The quality of this operation is a dominant fa ctor for the Bit Error Rate (BER) s ystem
performance. Feed forward and feedback controls are combined in one receiver architecture for
enhanced performance. The data is over-sampled and a digital circuit detects the edge position in
the data stream. A signal is not generated if an edge is not found. A fee dback loop takes care of
low-frequency jitter phe nom enon of unli mited amplitude, while a feed forwa r d s ection suppresses
high-frequenc y jitter having limi ted amplitude. The stat ic edge position is hel d at a constant
position in the over- sa mpled by a constant adjust ment of the sampling phas es with the early and
late signals.
5.6.2.4 Selective Power-Down
The IXF 1104 MAC offers t he abi lity to se lect ively power-down any of the SerDes TX or RX ports
that are not being used. This is done via “TX and RX Power-Down ($0x787)” on page 220.
5.6.2.5 Rec ei ver Jit ter Toleran ce
The SerDes rec eiver architecture is de si gned to tra ck fre quency mismatch, reco ver pha se, and is
tolerant of low-frequency data jitter. Figure 23 specifies the SerDes core receiver sinusoidal jitter
tr acking capabi lities.
1 0 1 1 2.0 20 mA
1 1 0 1 1.0 10 mA
1110 0.5 5 mA
Table 29. SerDes Driver TX Po wer Le vels
DRVPWRx[3] DRVPWRx[2] DRVPWRx[1] DRVPWRx[0] Normalized
Driver Power
Setting Driver Power
NOTE: A ll ot h er va lues are r es erve d.
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5. 6.2.6 Tran smit Ji tter
The S erDes c ore total transmit jitter, including contributions from th e intermediate freque ncy PLL,
is co mpri sed of the following tw o components:
•A determin istic com po nent at tributed t o t h e SerDes core’s arc h itectural characteristics
•A random compo nent attr ibuted to random th erm al noise ef fects
Since the thermal noise component is random and statistica l in nature , the SerDe s core total
tr ansmit jitter must be specifi ed as a function of BER.
5.6.2.7 Receive Jitter
The Ser D es core total receiver jitter, including contributions from the interm ediate f r equency PLL,
is co mpri sed of the following two components:
•A deterministic component attributed to the SerDes core architectural characteristics
•A random compo nent attr ibuted to random th erm al noise ef fects.
Figure 23. SerDes Recei ver Jitter To le ranc e
Note: UI = Unit interval.
B0745-02
10-1
0
10+1
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
Frequency
Sinusoidal Jitter Mask
Peak-to-Peak Amplitude (UI)
16 ui 375 Hz 16 ui
22.5836 kHz 8.5 ui
1.9195 MHz 0.1 ui
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5.7 Optical Module Interface
This section describes the co nnection of the IXF1104 MAC ports to an Optic al Module Interfa ce
and details the minimal connection s t hat are supported for correc t operation. The registers used for
write control and read status information are documented.
The Optical Module Interface allows the IX F1104 MAC a seam less connection to the Small Form
Factor Optical Module s (SFP) that form the system’s phys ical media connecti on, eli minating the
need for any F PGAs or CPUs to pr oce ss data. All requir ed optical module information is available
to the syste m CPU through the I XF1104 MAC CPU int erfa ce, leading to a more integrated,
reli able, and co st-effective system.
The IXF1104 MAC supports all the functions required for the Small Form Factor pluggable Multi -
So u rce A g re em en t (MS A) .
The re a r e spe ci fic mecha nic al and ele ct ric al requ ire me nts f or t he s i ze, f orm fa cto r , and conn ec tio ns
supported on all Opti cal Module Interface s. The re are also specific requirements for each Optical
Module Interface that supports a particular media requ irement or interface con f iguration. These
r equireme nts are detailed in the relevant specifications or manufact urers’ d ata sheets .IXF1104
MAC
5.7.1 Intel® IXF1104 MAC-Supported Optical Module Interface Signals
To describe the Optic al Module Interface operat ion, three supported s ignal subgroups are requi red,
allowing a more explicit definition of each function and implement ation. The three subgroups ar e
as follows:
•High-S peed Ser ial Interface
•Low-Speed Status Signaling Interface
•I ²C Module Configuration Interface
Table 30 provides descriptions for IXF 1104 MAC-to-SFP optical module connection signals.
Table 30. Intel® IXF1104 MAC-to-SFP Op tical Module Interface Connections (S heet 1 of 2 )
IXF1104 MAC
Signal Names S FP Sign al
Names Description Notes
TX_P_0:3 TD+ Transmit Data, Differential LVDS Output from the IXF1 104 MAC
TX_N_0:3 TD- Transmit Data, Differential LVDS Output from the IXF1104 MAC
RX_P_0:3 RD+ Receive Data, Differential LVDS Input to the IXF1104 MAC
RX_N_0:3 RD- Receive Data, Differential LVDS In put to the IXF1104 MAC
I2C_CLK MOD-DEF1 I2C_ CLK ou tp ut from the
IXF 1104 MA C (SCL ) Output from the IXF1104 MAC
I2C_DATA_0:3 MOD-DEF2 I2C_DATA I/O (SDA) Input/Output
MOD_DEF_0:3 MOD-DEF0 MOD_DEF_0 is TTL Low level
during normal operation. Input to the IXF1104 MAC
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5.7.2 Functional Descriptions
5. 7.2.1 High -Speed Ser i al In te r face
These sig n als are responsible fo r tran sfer of the actual data at 1 .25 Gbps. Table 41 “ DC
Specifications” on page 134 shows the data is 8B/10B encoded and transmitted differentially.
The following signals are required to implement the high-speed serial interface:
•TX_P_0:3
•TX_N_0:3
•RX_P_0:3
•RX_N_0:3
5.7.2.2 Low-Speed Status Signaling Interface
The following Low-Speed signals indica te the state of the line through the Optical Module
Interface:
•MOD_DEF_0:3
•TX_FAULT_0:3
•RX_LOS_0:3
•TX_DISABLE_0:3
•MOD_DEF_INT
•TX_FAULT_INT
•RX_LOS_INT
5.7.2.2.1 MOD_DEF_0:3
MOD_DEF_0:3 are dire ct input s to the IXF1104 MAC and are pulled to a logic Low leve l during
nor mal operation, indicating that a module is pres ent for each channel re spectivel y. If a module is
not pr esent, a logic High is received, which is achieved by an external pull-up resistor at the
IXF1104 MAC device pad.
The sta tus of ea ch bit (one for each port) is found in bits [3: 0] of the “Optical Modu l e Status Ports
0-3 ($0x799) ” on page 222). Any change in the state of these bits causes a logic Low level on the
MOD_DEF_INT output if this operation is enabled.
TX_DISABLE_0: 3 TX D ISAB LE Tra n sm itter di sa ble, lo gi c Hi g h,
open collector compatible Output from the IXF1104 MAC
TX_FAULT_0:3 TX FAULT Transmitter f ault, logic High, op en
collector compatible Input to the IXF1104 MAC
RX_LOS_0:3 LOS Receiver los s-of-signal, logi c High,
open collector compatible Input to the IXF1104 MAC
Table 30. Intel® IXF1104 MAC-to-SFP Optical Module Interface Connections (Sheet 2 of 2)
IXF 1104 MAC
Signal Names SFP Signal
Names Description Notes
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5.7.2.2.2 TX_FAULT_0:3
TX_FAULT_0:3 are inputs t o the IXF1104 MAC. These s ignals are pulled to a logic Low level by
the optical module during normal operation. A logic Low level on these signals indicates no fault
condition exists. If a fault is pr es ent, a logic High is r eceived through t he use of an external pull-up
r es is tor at the IXF1104 MAC pad.
The st atus of each bit (one for ea ch port) ca n be found in bi ts [13: 10] of th e “Optic al Modul e St atus
Ports 0-3 ($0x799)” on page 222. Any change in the state of these bits causes a logic Low level on
the TX_FAULT_ INT output if this operation is enabled.
5.7.2.2.3 RX_LOS_0:3
RX_LOS_0: 3 are i nputs to the IXF1 104 MAC. Thes e signals are pull ed to a logic Low level by the
optical module during norma l operat ion, which indicates that no loss-of-signa l exists. If a loss-of-
signal occurs, a logic High is r ec eived on these inputs through the use of an external pull-up
r es is tor at the IXF1104 MAC device pad.
The status of each bit (one for each port) is found in “Opt ical Module Status Ports 0-3 ($0x7 99)"
bits [23:20]. Any change in the state of these bits causes a logic Low level on the RX_L OS_INT
output if this operation is enabled.
5.7.2.2.4 TX_DISABLE_0:3
TX_DISABLE_0 :3 are outpu ts from the IXF1104 MAC. These signals are driven to a logic Low
level by the IXF1 104 MAC during normal oper ation. This indicates that the optica l module
tr ansmit te r is e nabled . If the o pti cal m odule tr ansm it ter is disa bled, this s ig nal is switc hed to a log ic
High level. On the IXF1104 MAC, t hese outputs are open drain types and pulled up by the 4 .7 k to
10 k pull-up res is tor at the Optical Module Interface. Each of these s ignals is controlled through
bits 3:0 respec tively of t he “Optical Modul e Control Port s 0 - 3 ($0x79A)".
5.7.2.2.5 MOD_DEF_INT
MOD_DEF_INT is a single output, open-drain type signal and is active Low. A change in state of
any MOD_DE F _0:3 inputs ca use s this signa l to s w itch Low and remain in this stat e until a read of
the “Optical Module Sta tus Ports 0-3 ($0x799)". The signal the n r eturns to an inactive state.
5.7.2.2.6 TX_FAULT_INT
TX_FAULT_INT is a single outp ut, open -drain type signal and is active Low. A chang e in s tate of
any TX_FAULT _0:3 inputs causes this signal to switch Low and remain in this state until a read of
the “Optical Module Sta tus Ports 0-3 ($0x799)". The signal the n r eturns to an inactive state.
5.7.2.2.7 RX_LOS_INT
RX_LOS_INT is a si ngle output, open-drain type sign al an d is active low. A change in state of any
of the RX_LOS_3:0 inpu ts causes this signal to switc h low and remain in this state unt il a Read of
the “Optical Module Sta tus Ports 0-3 ($0x799)" has taken place. Th e si gnal ret urns to an inac tive
state.
Note: MOD_DEF_INT, TX_FAULT_INT, and RX_L OS_ I NT are open-drain type outputs. With the
three signals on the device, the system can decide which “Optical Module Status Ports 0-3
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($0x799)" bits t o lo ok at to ide nti fy th e i nter rupt condit ion s ou rce por t. Howe ve r , th is is a chieve d at
the expense of the three device signals.
5.7.3 I²C Module Configuration Interface
The I²C interface is supported on SFP optical modules. Details of the operation are found in the
SFP Multi-Source Agreement, which details the contents of the registers and addresses accessible
on a given Optical Module Inte rface supporting this interface.
The SFP MSA identif ies up to 512 8- bit registers that are acc essible i n eac h optical module. The
Optical Modu le Interface is rea d-only and supports either sequential or random acces s to the 8-bit
parameters. The maxim um clock rate of the interfac e is 100 kHz. All address-se lect sig nals on the
interna l E²PROM are tie d Low to give a device address equa l to zero (00h).
Several PHY vendors may offer copper/CAT5-ba sed SFP optica l compliant m odules. To progra m
the internal confi guration regist ers of these mod ules, the IXF1104 MAC I2C interface needs to
provide the capabil ity to write data to the SFP modules.
The IXF1104 MAC I2C int erf ace is designed to allow indiv idual writes of byte-wide data to the
SFP.
The spec ific interf ace in the IXF1104 MAC supports only a subs et of the full I²C interfa ce , and
only the features required to support the Optical Module Interfaces are implemented. This leads to
the following support features.
•Single I2C_CLK pin connected to al l optical module s and im plemented to sav e unnecessary
signals use.
•Four per-port I2C_DATA signals (I²C Data[3:0]) are required because of the optical module
requirement that all modu les must be add r es s ed as 00h.
•The int erface has both rea d and write functionality.
•Due to the single internal optical module control ler, only one optic al module may be a ccess ed
at any one time. Each access contains a single register Read. Since these register accesses will
most likel y be done during power-up or discovery of a new module, th es e re strictions should
not affec t norm al oper ation.
•The I2C interfac e supports byte write accesses to the full addre ss range.
Note: The I2C interface only s upports random single-byte reads and does not guara ntee c oherency when
readi ng two-byte registers .
5.7.3.1 I2C Control and Data Registers
In the IXF1104 MAC, the entire I²C interface is controlled through the following two registers:
•“I2C Control Ports 0 - 3 ($0x79B)” on page 223
•“I2C Data Ports 0 - 3 ($0x79F)” on page 223
These registers can be programmed by syste m software using the CPU interface.
5.7.3.2 I2C R ead O p er ation
To perform a read operation using the I2C interface, use the following sequence:
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1. Init ialize th e Control register by se tting the following values:
a. Enab l e th e I2C Controller by sett ing bit [25] to 0x1.
b. Initiat e the I2C trans fer by setting bit [24] of the control register to 0x1.
c. Selec t the port by us ing bits [17: 16].
d. Select the Read mode of operat ion by setting bit [15] to 0x1.
e. Select the Dev ice ID by setting bits [14:11].
f. Select the register addres s by setti ng bits [10 :0].
2. Set the Devic e ID field to 0xA and the register addres s (bits 10:8) to 0x0 to acces s the fiber
modu le ser ial E2PROM. Sett ing the Devic e ID f ield to 0xA and the Regist er Addres s [10:8] to
0x0 permits rea d-only access.
3. Set the Device ID field to 0xA and the Register Address [10:8] between the values of 0x1 and
0 x 7 to access the PHY reg isters .
4. Pol l the Rea d_Valid field, bit 20. Th e read data is ava ilabl e when this bit is set to 0x1.
Figure 24 show s an 8-bit read acce ss.
Note: The user sof tware ensures the order of the contiguous accesses required to read the High and Low
bytes of 16-bit-wide PHY registe r s.
Note: Only one optical module I²C access sequence can be run at any given ti me . If a sec ond write is
carried out to the “I2C Control Ports 0 - 3 ($0x79B) " and “I2C Data Ports 0 - 3 ($0x79F)" before a
r esult is re tur ned for the pre v ious wri te, the data for the first writ e is l ost. An internal state mac hine
completes the Optical Module Interface register access for the first write. It attempts to place the
data in the DataRead field and checks to see if the W r iteCommand bit is 00h. If it is not 00h, it
discards the dat a a nd signals the I²C acce ss st ate machine to begin a ne w cycle using the data from
the second write .
5.7.3.3 I2C Write Operation
The following sequenc e provides an example of writ ing data t o Regi ster Addres s 0xFF for Port 3:
1. Program the “I2C Control Ports 0 - 3 ($0x79B)" with the following information:
a. Enab l e th e I2C block by setting Register bit 25 to 0x1.
Figu re 24. I 2C Random Read Transac tion
DEVICE
ADDRESS DEVICE
ADDRESS
WORD
ADDRESS
I2C_Data Line
DUMMY W RITE
(* = DON'T CARE bit for 1k)
START
S
T
A
R
T
R
E
A
D
S
T
A
R
T
W
R
I
T
E
S
T
O
P
M
S
B
M
S
B
M
S
B
L
S
B
R
/
W
L
S
BDATAn
L
S
B
A
C
K
N
O
A
C
K
A
C
K
*
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b. Set the port to be a ccess ed by setting Register bits 17:16 to 0x3.
c. Sel ect a Wr ite access by setting Register bit 15 to 0x0.
d. Set the Device ID Register bits 14:11 to Ah (Atmel com patible).
e. Set th e 11-b it re gi s t er ad d r es s ( R egiste r bit s 10 : 0 ) to 0FF h .
f. E n able the I 2C controller by se tting Register bit 2 to 0x1.
g. Initiate the I2C tra n s f er by setting Registe r bit 24 to 0x1.
All other bits in this register s hould be set to 0x0.
This data is written into the “I2C Contr ol P orts 0 - 3 ($0x79B)" in a si ngl e cy cl e via th e CPU
interface.
2. W h e n th is re gist er is w r it ten an d the I2C Star t bi t is at a Log i c 1, th e I 2C access state machine
examines the Port Address Select and enables the I2C_DATA_0 :3 output for the selected port.
3. The sta te machin es uses the data i n the Devic e ID and Regist er Addre ss field s to build the data
frame to be sent to the optical modu le
4. The I2C _DATA_WRIT E_FSM internal state machine takes over the task of trans f erring the
actual data bet ween the IXF1104 MAC and the selected opt ical module (refer to the de tails in
Section 5.7.3.4, “I²C Protocol Specifics” on page 112).
5. The I2C_DATA_WRITE_FS M in tern al state machine uses the d ata from t h e W rite_D ata fi eld
bits [23:16] of the “I2C Data Ports 0 - 3 ($0x79F )” on page 223 and sets the Writ e_Complete
Register bit 22 of the “I2C Control Ports 0 - 3 ($0x79B)" to 0x1 to signify that the W rite
Access is complete.
6. The data is written through the CPU interface. The CPU must po ll the Write_Complete bit
until it is set to 0x1. It is safe to request a new access only when this bit is set.
Note: Only one optical module I2C ac cess sequence can be run at any given time. The data for the first
Write is lost if a second Write is carried out to the “I2C Control Ports 0 - 3 ($0x79B)" before a
res ult is returned for the previous Write. Make sure Wri te c omp lete = 0x1 before st arting the next
W rite sequence to ensure that no data is lost.
5.7.3.4 I²C Protocol Specifics
Section 5.7 .3.4 describ es the IXF1104 MAC I²C Protocol behavior, which i s controlled by an
internal state machine. Speci fic protocol states are defined below , with an additional description of
the hardware si gnals use d on the inte rface.
The Serial Clock Line (I2C_CLK) is an output fr om the IXF1 104 MAC. The serial data is
sync hronous wit h this clock and is driven off the ris ing edge by th e IXF1104 MAC and of f the
falling edge by the optical module. The IXF1104 MAC has only one I2C_CL K line that drives al l
of the optica l mo dules. I2C_CLK runs continuously when enabled (I²C Enable = 01h0).
The Serial Data (I2C_DATA_3:0) signals (one per port) are bi-directional for seri al data tran sfer.
These signals are open drain.
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5.7.3.5 Port Protocol Operation
5.7.3.6 Cloc k an d D ata Tr an si ti o n s
The I 2C_DATA is normal ly pulled High with an extra device. Data on the I2C_DATA pin changes
only during the I2C_CLK Low time peri ods (see Figure 25). Data change s duri ng I 2C_CLK High
periods indicate a start or stop condition.
5.7.3.6.1 Start Condition
A High-to-Low transition of I2C_DATA, with I2C_CL K Hig h , is a start condition that must
precede any o ther command (see Figure 26).
5.7 .3 .6. 2 Stop Condition
A Low-to-High trans ition of the I 2C_D ATA with I2C_CLK High is a stop condition. After a Read
se quence, the stop command pla ces the E² PR OM and the op tical module in a standby po wer mode
(see Figure 26).
Figure 25. Data Validity Timing
DATA STABLE DATA STABLE
DATA
CHANGE
I2C_Data
I2C_Clk
Figu re 26 . Start and Stop De fin iti on Timin g
START STOP
I2C_Data
I2C_Data
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5.7.3.6.3 Acknowledge
All add ress es and dat a words a re seria ll y trans mitted t o and f rom the op tica l module in 8- bit words .
The opt ical modul e E²PROM sends a zero to acknowledge that it has receive d each word, whic h
happens during the nin th clock cycle (see Figure 27).
5.7.3.6.4 Memory Reset
After an in terruption in protocol, power loss, or system reset, any 2-wire optical modul e can be
res et by following three ste ps :
1. Clock up to 9 cycles
2. Wa it for I2C_D ATA Hig h in ea ch cy cle whil e I2C_C LK is High
3. Initiate a start condition.
5. 7.3. 6. 5 Devi ce Addr essin g
All E²PROMs in SFP optical modul e devices req uire an 8-bi t devic e address word fol lowi ng a start
condition to enable the chip to read or write. The device address word consis ts of a m andatory one,
zero sequence for the four most-significant bits. This is common to all devices. The ne xt three bits
are the A2, A1, an d A0 device a ddress bits tha t are tied to zero in an optical m odule. The eighth bit
of the device address is the Rea d/Write operation select bit. A Read operation is i nitiated if this bit
is Hi g h an d a Writ e o pe r at i on is in i ti a t ed if th is bi t is Lo w.
Upon comp ariso n of the device ad dress, t he optical module out puts a zero. If a comparison is not
made, the optical module E²PROM returns to a standby state.
5.7.3.6.6 Random Read Operation
A random Read r equires a “du mmy” Byt e/Write sequence to l o ad the data w o rd address . The
“dum my” write is achieved by first sending the de vice addres s wo rd with the Re ad/Wri te bit
cle ared to Low, which signals a Write opera tion. The optic al module acknowledges receipt of the
device address word. The IXF1104 MAC sends the data word addres s, which is again
acknowled ged by the opt ical modul e. The IXF1104 MAC genera tes another start condition. This
comp letes the “dummy” write and se ts the optical module E²PROM pointers to the desired
location.
Figure 27. Acknowledge Timing
START ACKNOWLEDGE
I2C_Data
DATA IN
DATA OUT
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The IXF1104 MAC initiates a current address read by sending a de vice addres s with the Rea d/
W r ite bit set High. The optical module acknowl edges the devic e address and seriall y clocks out the
data word. The IXF1104 MAC does not respond with a zero but gene rates a stop condition (see
Figure 28).
5.8 LED Interface
The IXF1 104 MAC use s a Seria l i nterfa ce, cons ist ing of th ree s ign als, to provi de LED dat a to s ome
f orm of external dr iver . This prov ides the dat a for 12 sepa rate di rec t drive LEDs and allows three
LE Ds per MAC port.
There are two m odes of operation, ea ch with its own separate LED decode mapping. Modes of
o p erat ion and LEDs are detailed in t h e f o llowing se ctions.
5.8.1 Modes of Operation
The r e are two modes of operati on: Mode 0 and Mode 1. Mode selection is accomplished by using
the LED_SEL_MODE bit. This bit is globally selected and control s the operat ion of all ports (see
Table 109 “LED Control ($0x509)” on page 190).
Mode 0: (L ED_SEL_MOD E = 0 [Default]): Thi s mo de se l ect s o pe r at io n s co m p a ti b le with th e
SGS Tho mpson M5450 LED Displ ay Driver de vice. This device convert s the s erial data st ream,
output by the IXF1104 MAC, i nto 30 direct-drive LED outputs. Although the LED interfac e is
capable of driving all 30 LEDs , only twel ve will be driven in the four-port IXF1104 MAC, three
LEDs pe r port.
Mode 1: (LED_SEL_MOD E = 1): This mode is used with standa rd TT L (74LS599) or HCMOS
( 74HC599) octa l shift regi s ters wit h latches, providing the most ge neral and cost-effective
imp lementation of the seria l data stre am conversion.
In addition to these physical modes of operation, there are two types of specific LED data decodes
ava ilabl e for fiber and copper modes . This opti on is a glob al sel ecti on and contr ols the operati on of
all ports (se e Table 109 “LED Control ($0x509)” on pag e 190).
Figu re 28. R ando m Rea d
DEVICE
ADDRESS DEVICE
ADDRESS
WORD
ADDRESS
I2C _Data Line
DUMMY WRITE
(* = DON'T CARE bit for 1k)
START
S
T
A
R
T
R
E
A
D
S
T
A
R
T
W
R
I
T
E
S
T
O
P
M
S
B
M
S
B
M
S
B
L
S
B
R
/
W
L
S
BDATAn
L
S
B
A
C
K
N
O
A
C
K
A
C
K
*
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5.8.2 LED Interface Signal Descr iption
The IXF1104 MAC LED interface cons ists of three output signal signals that are 2.5 V CMOS
level pads. Table 31 provides LED signal names, pin numbers , and descriptions.
5.8.3 Mode 0: Detailed Operation
Note: Please refer to the SGS Thompson* M5450 datasheet for device-operation information.
The operation of the LED Interface in Mode 0 is based on a 36-bit counter loop. The data for each
LED i s place d in turn on th e se ria l data line a nd clo cked out by t he LE D_CLK. Figure 29 shows th e
bas ic timing relationsh ip and rela tive positioning in the da ta str eam of each bit.
Figure 29 shows the 36 clocks that are output on the L ED_CLK pin. The data is change d on the
falling edge of the cl ock and is valid for almost the entire cloc k cycle. This e nsures that the data is
valid during the rising edge of the LED_CLK, whic h clocks the data into the M5450 device.
The actual data shown in Figure 29 c onsists of a chain of 36 bits, 12 of which are valid LED
DATA. The 36-bit dat a chain is built up as follows:
Table 31. LED Interface Signal Description s
Pin Name Pin # Pin Description
LED_CLK K24
This signa l is an output t hat provi des a cont inuou s clock syn c hr onous to the
seri al da ta stre am output on the LED_DATA pin. This clock has a maximum
speed of 72 0 H z .
The behavior of this signal remains constant in all modes of operation.
LED_DATA M22
This signal pr ovides the data, in variou s formats, as a ser ial bit stream. T he dat a
must be valid on the rising edge of the LED_CLK signal.
In Mode 0, the data presented on this pin is TRUE (Logic 1 = High).
In Mode 1, the data presented on this pin is INVERTED (Logic 1 = Low).
LED_LATCH L22 This is an ou tput pin, a nd the signal is used only i n Mode 1 as t he Latc h enable
for the shif t r egister chain.
This signal is not used in Mode 0, and should be left unconnected.
Figure 29. Mode 0 Timing
122 23 24 25 26 27 28 29 30
13534333231302928272625234
LED_CLK
LED_DATA
LED_LATCH
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When im plemented on the bo ard with the M5450 device , the LED DATA bi t 1 appea rs on Output
bit 3 of the M5450 and the LED DATA bit 2 app ears on Output bit 4, etc. This means that Output
bits 1, 2, and 15 through 35 will never hav e valid data and should not be used .
5.8.4 Mode 1: Detailed Operation
Note: Please refer to generi c spec ifications for 74LS/ H C599 for information on devic e ope ration.
The operation of the LE D Interface in Mode 1 is based on a 36-bit counter loop. The data for each
LE D is pla ced in tu rn on the s erial data lin e and clocked out by the LED_ CLK. Figure 30 on
page 118 shows the basic timing rel ationship a nd relative positioning in the data st ream of each bit.
Figure 30 on page 118 shows the 36 cl ocks which are outp ut on the LED_CLK pi n. The data is
changed on the falling edge of the clock and is valid for the almost the entire clock cycle. This
ens ures that t he dat a is valid d uring the ri sing e dge of t he LED_ CLK, whic h cloc ks th e data in to the
shift register chain devices.
The LED_LATCH signal is r equired in Mode 1, and latches th e data shift ed into the shift regis ter
cha in in to the out put la tche s of the 74HC 599 devic e. Fi gure 30 shows that the LED_LATCH signal
is active High during the Low pe riod on the 35th LED_CLK cycle. This avoids any possibility of
tr ying to latch data as it is shifting through the registe r.
When this operation mode is implemented on a board with a shift register chain containing three
74HC599 devices, the L ED DATA bit 1 is outp ut on Shift r egister bit 1, a nd so on up th e cha in.
Only Shift register bits 3 1 and 32 do not c ontain valid data .
The actu a l da t a sho w n in F igure 30 consists of a 36-bit cha in, of whic h 12 bits are valid LED
DATA. The 36-bit data cha in is built up as shown in Figure 30.
Tab le 32. Mode 0 Clock Cycle to Data Bit Relationsh ip
LED_CLK Cycle LED_DATA
Name LED_DATA De scription
1START BIT
This bit synchronizes th e M 5450 de vice to expect 35 bits of da ta to
follow.
2:3 PAD BITS These bits are used only as fillers in the data stream to extend the
length from the actual 12-bit LED DATA to the required 18-bit frame
length . These bits shou ld always be a log ic 0.
4:15 LED DATA 1-12
These bits are the actual data transmitted to the M5450 device. The
decode fo r each individual bit in each mode is defined in Table 34 o n
page 119.
The data is TRUE. Logic 1 (LED O N) = High
36:3 8 PAD BITS These bits are used as fillers in th e data stream to extend the length
from the actual 30-bit LED DATA to the required 36-bit frame length.
These bit s shoul d always be a logic 0.
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Note: The LED_DATA signal is now inv erted from the state in Mode 0.
5.8.5 Power-On, Reset, Initialization
The LED int erface is disable d at power -on or re set. The sy stem softwa re contro ller must enable the
LED interface. The internal state machines and output s ignals are held in reset until the full Intel®
IXF1104 4-Port Gigab it Ethe rnet Medi a Access Contr oll er devic e configu rat ion is co mpleted. This
is done by setting the LED_ENABLE bit to a logic 1 (see Ta ble 109 “LED Control ($0x 509)” on
page 190). The power-on default for this bi t is logic 0.
5.8.6 LED DATA Decodes
The data transmitted on the LED_DATA line is determined by programming the global operation
mode as either fiber or copper. Table 34 shows th e data decode of the data for both fib er and cop per
MACs.
Figure 30. Mode 1 Timing
Table 33. M od e 1 Clock Cycle to Data Bit Relationship
LED_CLK Cycle LED_DA TA Name LED_DATA Description
1START BITThis bit has no meanin g in Mode 1 operat ion and is shift ed out of
the 16-stage shift register chain before the LED_LA TCH signal is
asserted.
2:3 PAD BITS These bits have no meaning in Mode 1 operat ion and are shifted
out of the 16-st age shi ft register chai n before th e LED_LATCH
signal is asserted.
4:1 5 LED DATA 1-1 2
These bits are the actual data to be transmitted to the 16-stage shift
register chain. The deco de fo r each bit in e ach mode i s defined in
Table 3 4 on page 119.
The data i s INV ER TD. Lo gic 1 (L ED ON ) = Low.
36 :38 PAD BI TS These bits have n o m eanin g in Mode 1 o peratio n and are latche d
int o positions 31 a nd 32 in the shift register chain. These bi t s a r e
not considered as valid data and should be ignored. They should
alw ays be a Lo gic 0 = Hig h.
122 23 24 25 26 27 28 29 30
13534333231302928272625234
LED_CLK
LED_DATA
LED_LATCH
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Note: The data decode of th e LED bits is independen t of the Physi cal mode sele ction.
5.8.6.1 LED Signaling Behavior
Operation in eac h mode for the decoded LED data in Table 3 4 is detailed in Table 35 and Ta ble 36.
5.8.6.1.1 Fiber LED Behavior
Tab le 34. LED_DATA# Decodes
LED_DATA# MAC Port # Fibe r Designati on Copper Designatio n
1
0
Rx LED—Amber Li nk LED—Amb er
2 Rx LED—Green Link LED—Green
3 TX LED —Gr een Act ivity LED—Gre en
4
1
Rx LED—Amber Li nk LED—Amb er
5 Rx LED—Green Link LED—Green
6 TX LED —Gr een Act ivity LED—Gre en
7
2
Rx LED—Amber Li nk LED—Amb er
8 Rx LED—Green Link LED—Green
9 TX LED —Gr een Act ivity LED—Gre en
10
3
Rx LED—Amber Li nk LED—Amb er
11 Rx LED—Green Link LED—Green
12 TX LED—Green Activity LED—Green
Table 35. LED Behavior (Fiber Mode)
Type Status Description
RXLED
Off Synchronization occurs but no packets are received
and the “Lin k LED Enable ( $0x502)” is not set.
Amber On RX Synchronization has not occurred o r no optical
signal ex ists.
Amber Blinking The port has r emote fau lt a nd t he “Link LED Enable
($0x502)” is not set (based on remote fault bit setting
received in Rx_Config word).
Green On RX Synchronization occurs and the “Link LED Enable
($0x502)” bit is set.
Green Blinking R X Sy nc hroniz ati o n o cc urs and the por t is receiv i n g
data.
TXLED Off The port is not transmitting data or the “Link LED
Enable ($0x502)” is not set.
Green Blinking The port is transmitting data and the “Link LED Enable
($0x502)” bit i s set
NOTE: Table 35 assumes the port is enabl ed in the “Port En able ($0x500)” and the LEDs are enabled in the
“LED Control ($0x509)”. If a port is not en able d, al l the LE Ds f or that po rt wi ll be off . If th e L EDs a re no t
enabled, all of the LEDs will be off.
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5.8.6.1.2 Copper LED Behavior
5.9 CPU Interface
The CPU inte rface block provides access to regis ters and statist ics in the IXF1104 MAC. The
inte rface i s async hron ous ext ernal ly and ope rate s withi n th e 125 MHz c lock doma in i nterna lly. The
interface provides access to the following:
•Receive statisti cs registers
•T ransmit statistics registers
•Receive FIFO registers
•T ra nsmit FIFO registers
•Global configuration and control registers
•MAC_0 to MAC_3 registers
The CPU interface width can be configured with the two strap signals (UPX_WIDTH[1:0]) to
operate as an 8-bit, 16- bit, or 32-bit bus . All internal acce sses to regi st ers are 32-bit (4, 2, or 1 dat a
cycl es respectiv ely are required to fully access a register). When operating in 8-bit or 16-bit mode,
read data for bytes [3:1] is strobed into read holding regis ters whe n byte [0] is read. Subs equent
reads of b yte s {1, 2, 3} in b yte mode or of b ytes {2 ,3} in 16-b it mode are suppli ed from the holdi ng
regis ter independent of the upper addre ss bits. On wr ite accesses in 8- bit mode, the data of byte s
{0, 1, 2} is simila rly captur ed in internal write hold ing registers and the complete 32-bit write is
commit ted when byt e[3] is writte n to the IXF1104 MAC. When writ ing in 16-bit mode , bytes [1:0]
are captured, and the double-word is com mi tted when bytes [3: 2] are writt en. The complete
address for write is ignored (except for th e write which ca uses the commit operation).
Tabl e 36 . L E D B ehavio r (Copper Mode)
Type Status Description
Link LED
Off Port does not have a remote fault and “LED Control
($0 x50 9) ” on page 190 bit is not set.
Amber On Port has an RGMII R XERR condition detect ed and
“LED Control ($0x509)” on pa ge 190 bit i s set
Amber Blinking Port has a remote fault and “LED Fault Disable
($0x50B) ” on page 191 is not set.
Green O n “LED Control ($0x509)” on page 190 bit is set a nd port
d o es not ha v e an RG MII RXER R error o r remo te fault
c ondition present.
Activity LED - Green
Off Port is not transmitti ng and receivin g data.
Blinking
“LED Control ($0x509)” on pa ge 190 set: Port is
tr ansmitti ng and/or recei ving.
“LED Control ($0x509)” on pa ge 190 not set: Port is
receiving data.
NOTE: Ta ble 3 4 “LED_D ATA # Dec o des” assu m es the port is enab l e d i n the “ Port Enab le ($0 x 500) ” on
page 188 and th e LED s ar e enab led in the “LED Control ($0x509)” on page 190. If a port is not
enabled, all the LEDs for that port are off. If the LEDs are not enabled, all of the LEDs are off.
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5.9.1 Functional Description
5.9.1.1 Read Access
Read access involves the following:
•Detect assertion of asynchronous Read control signal and latch address
•Gene rate internal Read stro be
•Drive valid data onto processor bus
•Assert asynchronous Ready signal for required length of time
Figure 31 shows the timing of the asynchronous interface for Read access.
5.9.1.2 Write Access
Write process involves the following:
•Detect asse rtion of asynchronous Write control signal and latch address
•Detec t de-assertion of asynchronous Write c ontrol signa l and latch data
•Generate internal Write strobe
•Assert asynchronous Ready signal for required length of time
Figure 32 shows the timing of the asynchronous interface for Write accesses.
Figure 31. Read Timing Diagram - Asynch ro nous Inte rface
T
CAS
T
CAH
T
CRR
T
CDRS
T
CDRH
T
CDRD
T
CRH
u
Px_ADD[10:0]
uPx_RdN
uPx_CsN
u
Px_Data[31:0]
uPx_RdyN
B5103-01
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5. 9.1.3 CPU Ti mi n g Parameters
For informati on on the CPU interface Read and Write cycle AC timing parameters , re fer to Figure
47 “CPU Interfac e Read Cycle AC Timing” on page 149, Fig u re 4 8 “C P U I nter f ace Write Cy c le
AC Timing” on pag e 149, and Table 54 “CPU Interface Write Cycle AC Signal P aramete rs” on
page 150.
5.9.2 Endian
The Endian of the CPU int erfa ce may be change d to allow con nection of various CPUs to the
Intel® IXF1 104 4- Po rt Gigabit Ethernet Media Acce ss Controller. The Endian selection is
determi ned by se tting the Endian bit in the “CPU Interfa ce ($0x508)".
The fol lowing describes Endianne ss contro l:
•There is a byte swapper between the inte rnal 32-bit bus and the external 32-bit bus.
•In 8-bit or 16-bit mo de ope ration, the byte packer/byte unpacker hold ing registers sink and
source da ta jus t like the 32-bit external bus in 32-bit mode.
•The “CPU Interfa ce ($0x508)" se lects Big-Endian or Little-Endian mode.
•The byt e swapper caus es the behavior s een in Table 37 for acces s in g a re g ister wit h da ta bits
data[31:0].
Figure 32. Wri te Timing Diagram - Asynch ronou s Interface
TCAS TCAH
TCWL
TCDWS
TCDWD
TCYD
TCWH
uPx_Add[12:0]
uPx_WrN
uPx_CsN
uPx_Data[31:0]
uPx_RdyN
TCDWH
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5.10 TAP Interface (JTAG)
The IXF1104 MAC includ es an IEEE 1149.1 compl iant Tes t Access Port (TAP) interface used
during boundary scan testing. The interface consists of the follo wing five signals:
•TDI – Seria l Dat a Input
•TMS – Te st Mode Select
•TCLK – TAP Clock
•TRST _L – Active Low asynchronous reset for the TAP
•TDO – Serial Data O utput
TDI and TMS require external pull-up resis tors t o float the signals High per the IEEE 1 149.1
spe cific ation . Pull-ups are re commended on TCK and TDO. For norm al operat ion, T RST_L can be
p u lled Lo w, per manently disabling th e JTAG interfa ce. If the JTAG interface is u sed, the TAP
controller must be re set as described in Section 5.1 0.1, “TAP State Machine” on page 123 and
returned to a logic High.
5.10.1 TAP State Machine
The TAP s i g nals drive a TAP co n trol l er, which implements t h e 16-state st ate mac hin e spec ifi ed b y
the IEEE 1 149.1 specif icati on. Following power-up, the TAP controller must be reset by one of
f ollowing two mechanisms:
•Asynchronous reset
•Syn chronous reset
Async hronous reset is achi eved by pulsing or holding TRST_L Low. Synchronous re set is
achiev ed by clocking TCLK with five clock pulses while TMS i s held or f loats High. This ens ures
that the bo undary scan cells do not block the p in to core connecti ons in the IXF1104 MAC.
Tab le 37. Byte Sw app er Behav ior
UPX_BADD
[1:0]
Little Endian Big Endian
32-bit 16-bit 8-bit132-bit 16-bit 8-bit1
UPX_DATA_
[31:0] UPX_DATA_
[15:0] UPX_DATA
[7:0] UPX_DATA
[31:0] UPX_DATA
[15:0] UPX_DATA
[7:0]
00 [31:0] [15:0] [7:0] [7:0]
[15:8]
[23:16
[31:24]
[7:0]
[15:8] [7:0]
01 – – [15:8] – – [15:8]
10 – [31:16] [23:16] – [23:16]
[31:24] [23:16]
11 – – [31:24] – – [31:24]
1. In 8-bit mode, data is output i n Little Endian form at regar dless of the IXF1 104 MAC Endian setting.
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5.10.2 Instruction Register and Supported Instructions
The i nstruction register is a 4-bit regi ster that enacts the bo undary scan in st ructions. Aft er the stat e
mac hine resets , the default instru ction is IDCODE. The decode logic in the TAP controller selects
the appropriate data re gister and c onfigures the boundary s can cells for the current in st ruction.
Table 38 shows the supported boundary-scan ins tructions.
Table 38. Instruction Register Descr iptio n
In st r u ct i o n Code Desc r ipt ion Da ta Reg i ster
BYPASS 1111 1-bit Bypass Bypass
EXTEST 0000 External Test Boundary Scan
SAMPLE 0001 Sample Boundary Boundary Scan
IDCODE 0110 ID Code Inspection ID
HIGHZ 0101 Float Boundary Bypass
CLAMP 0111 Clam p Boun dary Bypass
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5. 10.3 I D Regist er
The ID register is a 3 2-bit register. The IDCODE instruction connects this registe r between TDI
and TDO. See Ta ble 112 “J TAG ID ($0x50C)” on page 192 for detailed inf or ma tion.
5.10.4 Boundary Scan Register
The Boundary Scan register is a shift register made up of all the boundary scan cells associated
with the devic e s ignals. The number, type, and order of the boundary scan cells ar e specified in the
I XF1104 MAC BSDL file. The EXT EST and SAMPLE instructions connect this register between
TDI and TDO.
5.10.5 Bypass Register
The Bypas s regis ter is a 1-bit registe r that bypasses the IXF1104 MAC to reduce the JTAG chai n
length when acc essing other devi ces on the chain be si des th e IXF1104 MAC. The BYPASS,
HIGHZ, and CLAMP ins tructions co nnect this register between TDI a nd TDO.
5.11 Loopback Modes
The IXF1104 MAC provides two loopback modes for dev ice diagnos tic testing when it has bee n
in tegrate d into a user system . A line-side loopback allows the line-side receive int er f ace to be
looped back to the transmi t line-side int erface. A SPI3 loopback mode allows the SPI3 transmit
i n terface t o b e lo oped back to the SPI3 r eceive interface.
The IXF1 104 MAC line-side and SPI3 loopbac k modes are effe ctive dia gnosti c tools for va li dation
o f sys t em l evel connec tivity and interf ace compatibility.
I n loopback -mo de ope ration, the data pat h is interna lly redirected to allow for the data flow return
path. Redirect ion requires the data path to cir cumvent resources that are required during normal
traffic flow. Fo r example, while operating in SPI3 loopbac k mode , the data pa th does not pass
through the MAC or TX FIFO and those resource feat ures are not used. The re sult is a possible
degradation of throughput performance and statistic al data accuracy. Intel recommends that
loopback modes be us ed for diagnostic purposes only.
5.11.1 SPI3 Interface Loopback
To provide a diagnostic loopback feature on the SPI3 interface, it is pos sible to configure the
I XF1104 MAC to loop back any data written to the IXF1 104 MAC t hrough the SP I 3 transmit
interface back to the SPI3 receive interface. This is accomplished using the data path shown in
Figure 33.
Note: Loopback packets also appear on the line side TX inte rface.
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Note: There is a restriction when us ing this loopback mode. At lea st one cloc k cyc le is r equired between
a TEOP assertion and a TSOP assertion. T his is required when the pre-pend feature of the receive
FIFO is enabled to allow the addition of the extra two bytes to the data sent on the transmit
interfa ce. W here the pre-pend feature ha s not been ena bled, da ta can be sent back-to-ba ck on the
tr ans m it SPI3 interface with TSOP following TEOP on th e next cycle.
To configure the IXF1104 MAC to use the SPI3 loopback mode, the “RX FIFO SPI3 Loopbac k
Enable for Ports 0 - 3 ($0x5B2)" must be configured. Each IXF1104 MAC port ha s a uniq ue bit in
this regi ster des ignated to control loopback. It i s possible to have individual ports in a l oopback
mode while other ports continue to operate in a normal mode.
5.11.2 Line Side Interface Loopback
To provide a diagnostic loopba ck fe ature on th e line-side int erfaces, the IXF1104 MAC can be
configured to loop bac k any data rec eived by the IXF1104 MAC through one of the line interfaces
back to the corresponding transm it line interface. This is done by using the data path shown in
Figure 34. The li ne-side int erface can be either SerDes, RGMII or GMII. Please note tha t it is not
possible to loop one line-side interface back to a different one (for example , Rx SerDes looped
back to transmit RGMII).
Figure 33. S P I3 Interface Loo pb ack Path
SPI3 Interface
Block
TX
RX
Line Side
Interface
MAC
TX FIF O
RX FIFO
B3229-01
SPI3 Internal Loopback
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When the IXF1104 MAC is configure d in this l oopback mode, all of the MAC functions and
f eatures are av ailab le, including flow control and pause-packet generation.
To configure the IXF1104 MAC to use the line-side loopback mode, the “Loop RX Data to TX
FIFO (Line-Side Loopback) Por ts 0 - 3 ($0x61F)" must be configured. Each IXF1104 MAC port
has a unique bi t in this register designat ed to control the loopback. It i s poss ible to have indi vidual
ports in a lo opback mode whil e other port s continue to operat e in a normal mode.
Note: Line side interface loopback packets also appe ar at the SPI3 int erface.
5.12 Clocks
The IXF1104 MAC system interface has se veral reference clocks, including the following:
•SPI3 data path input clocks
•RGMII input and output clocks
•MDIO output clock
•JTAG input clo ck
•I2C clock
•LED output cloc k.
This secti on details the unique cloc k source requ irements.
5.12.1 System Interface Reference Clocks
The following syste m int erfac e cl ock is required by the IXF1104 MAC:
•CLK125
Figure 34. Line Side Interface Loop bac k Path
RX FIFO
SPI3 Interface
Block
TX
RX
Line Side
Interface
MAC
TX FIFO
B3230-01
Line Side Internal Loopback
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5.12.1.1 CLK125
The sys tem interfac e c lock, whi ch s upplies the clock to the majority of the internal cir cuitry, is the
125 MHz clock. The source of this clock m ust meet the following specifications:
•2.5 V CMOS drive
•+/- 50 ppm
•Maximum duty cycle distortion 40/60
5.12.2 SPI3 Receive and Transmit Clocks
The IXF1104 MAC transmit clock require me nts in clude th e following:
•3.3 V LVTTL drive
•+/- 50 ppm
•Maximum frequenc y of 133 MHz in MPHY mode
•Maximum frequenc y of 125 MHz in SPHY mode
•Maximum duty cycle distortion 45/55
The IXF1104 MAC meets the f ollowing speci f icat ions for the receive clock:
•3.3 V LVTTL drive
•+/- 50 ppm
•Maximum frequenc y of 133 MHz in MPHY mode
•Maximum frequenc y of 125 MHz in SPHY mode
•Maximum duty cycle distortion 45/55
5.12.3 RGMII Clocks
The RGMII in terfac e is governed by the Hewle tt-Packard* 1.2a specification. The IXF1104 MAC
compliant to this sp ecification with the following:
•2.5 V CMOS drive
•Maximum duty cycle distortion 40/60
•+/- 100 ppm
•125 MHz for 1000 Mbps , 25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps
5.12.4 MDC Clock
The IXF1104 MAC supports the IEEE 802.3 MII Mana gement Interface, also known as the
Management Data Input/Output (MDIO) Interface. T he IXF 1104 MAC meets the following
spe cifications for this clock:
•2.5 V CMOS drive
•2.5/18 MHz operation (se lectable by the MDC speed bit in the “MDIO Cont rol ($0x683)")
•50/50 duty cyc le for 2. 5 MHz operation
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•43/5 7 du ty cycl e fo r 18 M H z op er a t io n
5.12.5 JTAG Clock
The IXF1104 MAC support s JTAG. The source of this clock must meet the following
specifications:
•2.5 V CMOS drive
•Maxim um clock frequency 11 MHz
•Maxim um duty cycle distortion 40/6 0
5.12.6 I2C Clock
The IXF1104 MAC supports a single-output I2C cl ock t o suppor t all t en Opt ical Module int er faces .
The IXF1104 MAC meets the followi ng spe cifications for this clock:
•2.5 V CMOS drive
•Maximum clock frequency of 100 KHz
5. 12.7 L E D Cl ock
The IXF1104 MAC s upports a serial LED data stream and meets the following specifications for
this clock:
•2.5 V CMOS drive
•Maximum frequency of 720 Hz
•Maxim um duty cycle distortion 50/5 0
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6.0 Applications
6.1 Change Port Mode Initialization Sequence
Use the cha nge port mode initialization sequence aft er powe r-up and anytim e a port is configured
into or switching between fibe r or copper mode, switching to/from RGMII and GMII modes, or
switchi ng speeds and duplex in RGMII mode.
The following sequence applies to all four ports and can be done simultaneously for all ports or as
a subse t of the ports.
1. Place the MAC in rese t for the port (s) which require a change by as serting (s et to 1) th e “MAC
Soft Reset ($0x505)”.
2. Place the TX FIFO in reset for the port(s) whic h require a c hange by asserting (set to 1) the
“TX FIFO Port Reset ($0x620)”.
3. Disa ble the port(s) which require change by de-ass erting (set to 0) the appropriate bits in the
“Port Enable ($0x500)”.
4. Wait 1 μs.
5. De-assert (set to 0) “C lock and Int erfa ce Mode Change Enable Ports 0 - 3 ($0x794)” for the
ports being changed.
6. Set the speed, mode, and duplex a s follows for the ports being changed:
a. Cop per m ode:
Select coppe r mode for the “Interface Mode ($0x501 )” port s.
Se t the p er-po r t “MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)” to th e
appropriate speed and RGMII/GMII interface setting.
Se t the p er-po r t “Desi r ed Duplex ($ Port_I ndex + 0x02)”.
Note: Half-duple x is s uppor ted only whe n RGMII 10 Mbps or 100 Mbps is selec ted in t he
“MA C IF Mode and RGMII Speed ($ Port_Index + 0x10)”.
b. Fiber mo de:
Select fiber mo de by s etting the appropriat e bit to 0 in the “I nterface Mode ($0x501)”
ports.
7. Assert (s et to 1) “Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794)” for the po rts
be i ng ch ange d.
8. Wait 1 μs.
9. De-assert (set to 0) “ MAC Soft Reset ($0x505)” for the ports being changed.
10. De-assert (set to 0) “TX FIFO Port Re s et ($0x620)” for the ports being changed.
11. Wait 1 to 2 μs.
12 . S e t th e “Diverse Config Write ($ P ort_Index + 0x18)” to th e ap p rop r i at e v al ue as fol lo w s:
a. Cop per m ode:
Writ e th e r eser v ed bi ts to th e def aul t val u e.
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Enable packet padding and CRC appending on transmitted packets in bits 6 and 7, as
needed.
Set bit 5 to 0x0.
b. Fi ber Mode :
Writ e the reserv ed bits to the def ault valu e.
Enable Packet padding and CRC Appending on tr ansmitted packets in bits 6 and 7, as
needed.
Set bit 5 to 1 to enable auto-negotiation.
Set bit 5 to 0 to enable forced mode ope ration.
13. Assert (set to 1) “Port En able ($0x500)”.
14. Wait 1 to 2 μs.
15. Perform additional device confi gurations, as neede d.
6.2 Disable and Enable Port Sequences
I ntel recommends the following sequences to dis able and enable individual ports , and for dropp ed
links. When a link is dr opped, Int el recommends the port be complete ly res et and flushed to
r emove packet fragments that may interfere with the auto-negotiation proce ss on link recovery.
6.2.1 Disable Port Sequence
Use the following se quence to disable an individual port:
1. Disable the port using MAC port enable/disable bits [“Port E nable ($0x 500)” Bits (3-0)].
2. Apply T X FIFO soft reset [“TX FIFO Por t Reset ($0x620)” Bits(3-0)].
3. I ntroduce som e delay to al low com plet ion of packet transmis sion (not necessary if link is
dropped).
4. Flush TX [“Flush TX ($ Port_Index + 0x11)” Bit 0].
5. Apply MAC soft reset [ “MAC Soft Reset ($0x505)” Bits(3-0)].
6. Apply RX FIFO soft reset [“RX FIFO Port Reset ($0x59E)” Bits (3:0)].
6.2.2 Enable Port Sequence
Use the followi ng se quence to enable an indivi dual port:
1. Enable the port(s) using MAC port enable/ d is able bits [“Port Ena b le ($0x500) ” Bits (3-0)].
2. D isable TX FIFO soft reset [“TX FIFO Port Reset ($0x620)” Bits(3-0)].
3. Reset flus h TX [“Flu sh TX ($ Port_Index + 0x11)” Bit 0].
4. Disable MAC soft reset [“MAC Soft Re set ($0x505)” Bits( 3-0)].
5. Disable RX FIFO soft re set [ “RX FIFO Port Re set ($0x59E)” Bits(3:0)].
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7.0 Electrical Specifications
Table 39 through Table 58 “LED Interface AC Timing Parameters” on page 154 and Figure 35
“SPI3 Receive Interface Timing” on page 137 through Figure 52 “LED AC Interface Timing” o n
page 154 repre sent the ta rget specif icat ions of the f ollowing IXF1104 MAC interfaces:
— SPI3
—JTAG
—MDIO
— Paus e Control
—CPU
—LED
—System
— GMII and RGMII
—SerDes
— Optical Module
These specifications are not guaranteed and are subject to change without notice. Minimum and
maximu m values listed in Ta bl e 4 1 “D C S p e c if icatio ns ” on page 13 4 through Ta bl e 58 “LE D
Interface AC T iming P arameters ” on pa ge 154 apply over the recommend ed operating conditions
specified in Table 40.
Tab le 39 . Absol ute Maximum Ratings
Parameter Symbol Min Max Units Comments
Supply voltage
V DD - 0 .3 2. 2 volts Co r e di gital po w er
VDD2, VDD3 -0.3 4.25 volts I/O digital power
VDD4, VDD5 -0.3 4.25 volts I/O digital power
AVDD1P8_ 1/2 -0.3 2.2 v olts Analog power
AVDD2P5_ 1/2 -0.3 4.25 vol ts Anal og power
Operating
temperature Ambient TOPA -40 +85 °C Copper mode
Ambient TOPA 0.0 +70 °C Fiber mode
Storage tempera ture TST -40 +150 ° C –
Caution: E xceeding these values m ay cause permanent damage to the device. Functi onal
operation under these conditions is not implied. Expo s u re to maximum ra ting
conditions for extended pe riods may affect device reliability.
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7.1 DC Specifications
The IXF1104 MAC supports the followi ng I /O buffer types:
•2.5 V CMOS
•3.3 V LVTTL
•SerDes
Tab le 40. Recomm ended Op erating Condit ions
Parameter Symbol Min Typ Max Units
Reco mmended supply voltage
VDD 1.65 – 1.95 Volts
VDD2, VDD3 3.0 – 3.6 Volts
VDD4, VDD5 2.3 – 2.7 Volts
AVDD1P8_1
AVDD1P8_2 1.65 – 1.95 Volts
AVDD2P5_1
AVDD2P5_2 2.3 – 2.7 Volts
Operating Current
SerDes Operati on
Transmitting and
receiving in
1000 Mbps mode
VDD
AVDD1P8_1
AVDD1P8_2 –0.780–Amps
VDD4
VDD5
AVDD2P5_1
AVDD2P5_2 –0.050–Amps
VDD2, VDD3 – 0.246 – Amps
Operating Current
RGMII Operation
Transmitting and
receiving in
1000 Mbps mode
VDD
AVDD1P8_1
AVDD1P8_2 –0.757–Amps
VDD4
VDD5
AVDD2P5_1
AVDD2P5_2 –0.224–Amps
VDD2, VDD3 – 0.208 0.235 Amps
Recommended
operating
temperature
Ambient TOPA 0 – 70 °C
Case with heat
sink TOPC-HS 0 – 122 °C
Case without heat
sink TOPC-NHS 0 – 121 °C
Power
consumption
SerDes Operati on
Transmitting and
receiving in
1000 Mbps mode
– – 2.23 2.72 Watts
RGMII Operation
Transmitting and
receiving in
1000 Mbps mode
– – 2.84 3.4 Watts
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See Sect ion 5.1.7, “P acket Buf fe r Di mension s” on pa ge 80 for a dditio nal in form ation regardi ng I/O
buf fer types. The relat ed driver characteristics are des cribed in this section.
Caution: IXF1104 MAC input si gnals are not 5 V tolerant. Devices dri ving t he IXF11 04 MAC must provi de
3.3 V sig nal levels or us e level-s hifting buffe rs to provide 3.3 V-compatible levels . Otherwi se ,
damage to the IXF1104 MAC will occur.
Table 41. DC Sp ecifications
Parameter Symbol Min Typ Max Units Comments
2.5 V CMOS I/O Cells
Input High voltage VIH 1.7 – – V 2.5 V I/Os
Input low voltage VIL – – 0.7 V 2.5 V I/Os
Output High voltage VOH 2.0 – – V 2.5 V I/Os
Output low voltage VOL – – 0.4 V 2.5 V I/Os
3.3 V I/ O Cel ls
Input High voltage VIH 1.7 – – V 3.3 V LVTTL I/Os
Input low voltage VIL – – 0.7 V 3.3 V LVTTL I/Os
Output High voltage VOH 2.4 – – V 3.3 V LVTTL I/Os
Output low voltage VOL – – 0.4 V 3.3 V LVTTL I/Os
Table 42. SerDes Transmit Characteristics (Sheet 1 of 2)
Parameter Symbol
Normalized
Power
Drive
Settings1Min Typ Max Units Comments
Transmit differential
sig nal le ve l TxDfPP
0.50 180 230 325
mVpp diff AVDD1P8_2 terminated
to 1.8 V; Rloa d = 50 Ω
1.00 350 440 700
1.33 425 580 900
2.00 600 770 1050
Tr ansmit common
mod e volt age range TxCMV
0.50 1300 1600 1940
mV AVDD1P8_2 terminated
to 1.8V; RLoad = 50
ohms; FIR coeffs = 0
1.00 1000 1400 1870
1.33 800 1300 1825
2.00 700 1100 1760
Differential signal rise/
fa ll time Diff rise/
fall 1.00 60 96 132 ps R load = 50 Ω; 20% to
80% max
Differential output
impedance TxDiffZ – 60 105 150 Ω diff Nominal value = 100 Ω
differential
Receiver differential
voltage requirement at
center of r eceive eye RxDiffV – 200 – – mVp-p
diff –
1. Refer to Section 5.6.2.2, “Transmitter Programmable Driver-Power Levels” on page 104.
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7.1.1 Undershoot / Overshoot Specifications
The overshoot figures give n in this sec tion represe nt the maxim um voltage that can be applied
without af f ecting the rel iability of the device (see Table 44).
Caution: If these limits are exceeded, damage to the device will occur.
7.1.2 RGMII Electrical Characteristics
The RGMII si gnals (including MDIO /MDC) are ba sed on 2.5V CMOS interface voltages, as
defined by JEDEC EIA/JESD8-5 (see Table 45).
Receiver common
mode voltage range RxCMV – 900 1275 1650 mV –
Receiver termination
impedance RxZ – 40 51 62.5 Ω–
Signal detect level RxSigDet – 50 125 200 mVp-pdiff –
Tab le 43. Se rDes Recei ve Characteri stics
Parameter Symbol
Normalized
Power
Drive
Settings
Min Typ Max Units Comments
Receiver differential
voltage requirement at
center of receive eye RxDiffV – 200 – – mVp-p diff –
Receiver common
mode voltage range RxCMV – 900 1275 1650 mV –
Receiver termination
impedance RxZ – 40 51 62.5 Ω–
Signal detect level RxSigDet – 50 125 200 mVp-pdif f –
Tab le 42. Se rDes Tran smit Cha racteristics (She et 2 of 2)
Parameter Symbol
Normalized
Power
Drive
Settings1Min Typ Max Units Comments
1. Refer to Section 5.6.2.2, “Transm itter Progr ammable Driver-Pow er Lev els” on page 104.
Table 44. Undersh oot / Overshoot Limits
Pin Type Undershoot Overshoot
2.5 V CMOS -0 .60 V 3. 9 V
3.3 V LVTTL -0.60 V 3.9 V
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Table 45. RGMII Power
Symbol Parameter Conditions Min Max Units
VOH Output High Voltage IOH = -1.0 MA; VDD = MIN 2.0 VDD +.3 V
VOL Output Low Voltage IOL = 1.0 MA; VDD = MIN GND -.3 0.40 V
VIH Input High Volt age VIH > VIH_MIN; VDD = MIN – VDD +.3 V
VIL Input Low Voltag e VIL < VIL_MAX; VDD = MIN –.70V
IIH Input High Current VDD = MAX; VIN = 2. 5V – 15 µA
IIL Input Low Current VDD = MAX; VIN = 0. 4V -15 – µA
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7.2 SPI3 AC Timing Specifications
7. 2.1 Receive Int erf ace T imi ng
Figure 35 and Table 46 illustra te and provi de SP I 3 receive interface timing information.
Figure 35. SPI3 Receive Interface Tim i ng
RFCLK
RENB
RDAT[31:0]
RPRY
RMOD
RSOP
REOP
RERR
RVAL
RSX
THrenb
TSrenb
TPrdat
TPrprty
TPrmod
TPrsop
TPreop
TPrerr
TPrval
TPrsx
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Table 46. SPI3 Receive Interface S ignal Par ameters
Symbol Parameter Min Max Units
– RFC LK frequency 90 133 MHz
– RFCLK duty cycle 45 55 %
Tsrenb RENB setup time to RFCLK 1.8 – ns
Threnb RENB hold time to RFCLK 0.5 – ns
TPrdat R FCLK High to RDAT valid 1.5 3.7 ns
TPrprty RFCLK High to RPRTY valid 1.5 3.7 ns
TPrsop R FCLK Hig h to RSOP v alid 1 .5 3 .7 ns
TPreop R FCLK Hig h to REOP v alid 1 .5 3 .7 ns
TPrmod RFCLK High to RMOD valid 1.5 3.7 ns
TPrerr R FCLK High to RERR va lid 1 .5 3.7 ns
TPrval RFCLK High to RVAL valid 1.5 3.7 ns
TPrsx RFCLK High to RSX valid 1.5 3.7 ns
NOTES: Rece iv e I/O Timing
1. When a setup time is specified between an input and a clock, the setup time is the time in nanoseconds
from the 1.4-volt point of the input to the 1.4-volt point of the clock.
2. When a hold time is specified between an inp ut and a cl ock, the hold t ime is the time in nanoseconds from
the 1.4-volt p oint of the clock to the 1.4-volt point of the input.
3. Output propagation time is the time in nanoseconds from the 1.4-volt point of the reference signal to the
1.4-volt poi nt of the output.
4. Maximum propagation delays are measured with a 30 pF load when operating OIF-SPI3 standard 104
MHz. Over -c locked rates of 125 MHz o r hig her are measured using a load of 20 pF.
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7.2.2 Transmit Interface Timing
Figure 36 and Table 47 il lustr at e and pr o v id e SPI 3 tr an s mit in ter f ace ti m i ng inf o r mati on.
Figure 36. SPI3 Tran smi t Interface Timing
TFCLK
TENB
TDAT[31:0]
TPRTY
TMOD[1:0]
TSOP
TEOP
TERR
TADR
TSX
THtenbTStenb
THtdatTStdat
THtprtyTStrpty
THtmodTStmod
THtsopTStsop
THteopTSteop
THterrTSterr
THtadrTStadr
THtsxTStsx
DTPA
TPdtpa
STPA
TPstpa
PTPA
TPptpa
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Table 47. SPI3 Tran sm it Interface Signa l Parameters
Symbol Parameter Min Max Units
– TFCLK frequency – 133 MHz
– TFCLK duty cycle 45 55 %
TStenb TE NB se tu p time to TFCL K 1.8 – ns
THtenb TENB hold time to TFCLK 0.5 – ns
TStdat T DAT[31:0] setu p tim e to TFCL K 1.8 – ns
THt dat TDAT[31:0} hold time to TFCLK 0.5 – ns
TStprty TRPTY setup time to TFCLK 1.8 – ns
TH tp rty TPRTY hold tim e to TFCLK 0.5 – ns
TStsop TSOP setup time to TFCLK 1.8 – ns
THtsop TSOP hold time to TFCLK 0.5 – ns
TSteop TEOP setup time to TFCLK 1.8 – ns
THteop TEOP hold time to TFCLK 0.5 – ns
TStmod TM OD setu p time to TFCLK 1.8 – ns
THtmod TMOD hold time to TFCLK 0.5 – ns
TSterr TERR setup time to TFCLK 1.8 – ns
THterr TERR hold time to TFCLK 0.5 – ns
TStsx TSX setu p time to TFCLK 1.8 – ns
THtsx TSX ho ld time to TFCLK 0.5 – ns
TSta dr TADR setup time to TFCLK 1.8 – ns
THt adr TADR hold time to TFCLK 0.5 – ns
TPdtpa TFCLK High to DTPA valid 1.5 3.7 ns
TPstpa TFCLK High to STPA valid 1.5 3.7 ns
TPptpa TFCLK High to PTPA valid 1.5 3.7 ns
NOTES:T ransmit I/O Timing:
1. When a setup time is specified between an input and a clock, the setup time is the time in nanoseconds
from the 1.4 V point of the input to the 1.4-volt point of the clock.
2. When a hold time is specified between an in put and clock, the hold time is the time in nanoseconds from
the 1.4 V point of the clock to the 1.4-volt point of the input.
3. Output propagation delay time is the time in nanoseconds from the 1.4 V point of the reference signal to the
1.4 V point of the output.
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7.3 RGMII AC Timing Specification
Figure 37 and Table 48 provide RGMII interface timing paramete rs .
Figu re 37 . RGMII I nte rfa ce Timing
Table 48. RGMII Interface Timing P arameter s
Symbol Parameter Min Typ Max Unit
Tske w T D a t a-to- Cloc k O utput Sk ew ( at Trans m it te r ) - 5 00 0 50 0 ps
TskewR Data-to-Clock Input Skew (at Receiver)11–2.8ns
Tcyc Clock Cycle Duration27.2 8 8.8 ns
Du ty_T Du ty Cycle for G ig abit245 50 55 %
Du ty_G Du ty Cycl e for 10/1 00 T340 50 60 %
Tr/Tf Rise/Fall Time (20–80%) – – .75 ns
1. This implies that PC board design requires clocks to be routed so that an additional trace delay of greater
than 1.5 ns is added to the associated clock sig nal.
2. For 10 Mbps and 100 M bps Tcyc scales to 400 ns +/– 40 ns and 40 ns +/– 4 ns respective ly.
3. Duty cycle may be stretched/sh runk during speed ch anges or whi le transitioning to a received packet’s
clock domain, as long as mi nimum duty cy cle is not violated and stretching occurs for no m ore t han th ree
Tcyc of the lowest speed transitioned between.
B3251-01
TSkewT
TXC
(at Transmitter)
TXC
(at Receiver)
TD[3:0]
TX_CTL[n]
TSkewR
TD[3:0] TD[7:4]
TXEN TXERR
TSkewT
RXC
(at Transmitter)
RXC
(at Receiver)
RD[3:0]
RX_CTL
TSkewR
RD[3:0] RD[7:4]
RXDV RXERR
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7.4 GMII AC Timing Specification
7.4.1 1000 Base-T Operation
Figure 38 and Figure 39 and Table 49 and Table 50 provide GMII AC timing specifications.
7.4.1.1 1000 BASE-T Transmit Interface
Figure 38. 1000BASE-T Transm it Interface Timing
Table 49. GMI I 1000BA SE-T Tran sm i t Signa l Parameters
Symbol Parameter Min Typ1Max Unit2
t1 TXD[7:0], TXEN , TXER Set-u p to TXC High 2. 5 – – ns
t2 TXD[7:0], TXEN, TXER Hold from TXC High 0.5 – – ns
t3 TXEN sampled to CRS asserted – – 16 BT
t4 TXEN sampled to CRS de-asserted – – 16 BT
1. Typi ca l va lues are at 25 oC and are for design aid only; not guaranteed and not subject to production
testing.
2. Bit T ime (BT) is the duration of one bit as transferred to/from the PHY and is the reciprocal of bit rate. BT for
1000BASE-T = 10-9 or 1 ns .
B0634-01
GTX_CLK
TXEn
TXD[7:0]
TXER
CPS
t1
t3
t4
t2
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7.4.1.2 1000BASE-T Rece i ve Interface
Figure 39. 1000BASE-T Receive Interf ace Timing
Table 50. GMII 1000BAS E- T Receive Signal Parame ters
Symbol Parameter Min Typ1Max Unit2
t1 RXD[7:0], RX_DV, RXER Setup to Rx_CLK High 2.0 – – ns
t2 RXD[7:0], RX_DV, RXER Hold af ter Rx_CLK High 0.0 – – ns
1. Ty pical values are at 25oC and are for design aid only; not guaranteed and not subject to production
testing.
2. Bit Time (BT) is the duration of one bit as transferred to/from the PHY and is the reciprocal of bit rate. BT for
1000BASE-T = 10-9 or 1 ns.
RxDV
RXD[7:0]
CRS
t1
t2
RX_CLK
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7.5 SerDes AC Timing Spec ification
Figure 40. S erDes Timing Diagram
Table 51. SerDes Timing Parameters
Symbol Parameter Min Max Units
Tt Transmit eye width 800 – pS
Rt Receiv er eye width 280 – pS
Tv Transmit amplitude 1000 – mV
Rv Receiver amplitude 200 – mV
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7.6 MDIO AC Timing Sp ecification
The MDIO Interface on the IXF1104 MAC can operate in two modes – low-speed and high-speed.
In lo w -sp eed mode, th e M DC cl o ck si gnal operates a t a frequency o f 2 . 5 MHz. In high-speed
mode , the MDC clock signal operates at a frequency of 18 MHz. (See Figure 41 through Figure 44
and Table 52.)
7.6.1 MDC High-Speed Operation Timing
7.6.2 MDC Low-Speed Operation Timing
Figu re 41 . MD C Hig h- Spe e d Op e rat i on Timi ng
Figure 42. MDC Low-Speed Operatio n Timi ng
24 ns
(3 X 1 25 MHz clocks) 32 ns
(4 X 125 MHz clocks)
MDC
56 ns (17.85 MHz)
200 ns
(25 X 125 MHz clocks) 200 ns
(25 X 125 MHz clocks)
MDC
400 ns (2.5 MHz)
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7.6.3 MDIO AC Timing
Figure 43. MDIO Write Timing Diagram
Figure 44. M DI O Read Timing Diag ram
Table 52. MDIO Timing Parameters
Parameter Symbol Min Typ1Max Units Test Conditions
MDIO Setup before MDC. t1 10 – – ns MDC = 17.8 MHz
10 – – ns MDC = 2.5 M Hz
MDIO Hold after MDC. t2 10 – – ns MDC = 17.8 MHz
10 – – ns MDC = 2.5 M Hz
MDC to MDIO Output delay t3 0 – 42 ns MDC = 17.8 M Hz
0 – 300 ns MDC = 2.5 MHz
1. Typical values are at 25 oC and are for design aid only; not guarante ed and not subject to production
testing.
t1
MDC
MDIO
t2
VMAX
VMIN
t3
MDC
MDIO
VMAX
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7.7 Optical Module and I2C AC Timing Specification
7.7.1 I2C Interface Timing
Fi gure 45 and Figure 46 il lustrate bus timing and write cycle, and Table 53 sh ow s the I2C I n terf ace
AC timing characteristics.
Figure 45. Bus Timing Diagram
Figure 46. Write Cycle Diagram
Table 53. I2C AC Timing Characteristics (Sheet 1 of 2)
Symbol Parameter Min Max Units
fSCL Clock frequency, SCL - 100 kHz
tLOW Cl oc k puls e w idth low 4.7 µs
tHIGH Cl oc k pu ls e w idth High 4.0 µs
tINo is e supp r es s io n 100 µs
tAA Clock low to data valid out 0.1 4.5 µs
tBUF Time the bus must be free before a new transmission starts 4.7 - µs
tHD.STA Start hold time 4.0 - µ s
I2C_Clk
I2C_Data Out
tDH
tSV.SAT
tAA
tBUF
tHD.STA
tHIGH tR
tSU.STO
tSU.DAT
tHD.DAT
tLOW
tF
I2C_Data In
tLOW
ACK
8th
BIT
WORD n
I2C_Clk
I2C_Data
STOP
CONDITION START
CONDITION
tWR(1)
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tSU.STA Start setup time 4.7 – µs
tHD.DAT Data in hold time 0 – µs
tSU.DAT Data in setu p time 200 – ns
tRInputs rise time – 1.0 µs
tFInputs fall time – 300 ns
tSU.STO Stop setup time 4.7 – µs
tDH Data out hold time 100 – ns
tWR W rite cycle t ime – 10 ms
Table 53. I2C AC Timing Characteristics (Sheet 2 of 2)
Symbol Parameter Min Max Units
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7.8 CPU AC Timing Specification
7.8.1 CPU Interface Read Cycle AC Timing
Figure 47, Figure 48, and Table 54 illustrate the CPU interface read and write cycle AC timing.
7.8.2 CPU Interface Write Cycle AC Timing
Figure 47. CPU Interface Read Cycle AC Timing
Figure 48. CPU Interface Write Cycle AC Timing
TCAS TCAH
TCRR
TCDRS
TCDRH
TCDRD
TCRH
uPx_ADD[12:0]
uPx_RdN
uPx_CsN
uPx_Data[31:0]
uPx_RdyN
TCAS TCAH
TCWL
TCDWS
TCDWD
TCYD
TCWH
uPx_Add[12:0]
uPx_WrN
uPx_CsN
uPx_Data[31:0]
uPx_RdyN
TCDWH
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Table 54. CPU Interface W rite Cycle AC Signal Parameters
Symbol Parameter Min Max
Tcas Address, chip select setup time 5 ns –
Tcah Address, chip sel ect hol d time 10 ns –
Tc rr Ready asse rtion to read de-ass ertion 10 ns –
Tcrh Read High wi dth 24 ns –
Tcdrs Read data setup time to ready assertion 10 ns –
Tcdrh Read data hold time after read de-assertion 8 ns 32 ns
Tcdrd R ea d da ta dr iv in g de lay 24 ns 35 5 ns
Tcwl Write assertion width 40 ns –
Tcwh Ready assertion to write assertion 16 ns –
Tcdws Write data setup to write de-assertion 10 ns –
Tcdwh Write data hold tim e after ready asser tion 5 ns –
Tcdwd W rite data sampli ng delay 8 ns 32 ns
Tcyd Ready width in write cycle 24 ns 40 ns
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7.9 Transmit Pause Control A C Timing Specification
Figure 49 and Table 55 show th e pause cont rol AC timi ng specifications . The Pause Control
inte rface operate s as an async hrono us inter face relat ive to the main sys tem clock (CLK125). There
is, however, a relationship between the TXPAUSEADD bus and th e strobe signal (TXPAUSEFR) .
Figu re 49. P ause C ontro l Interf ace Timing
Table 55. Tran smit Pause Co ntrol Interface Timing Parame te rs
Symbol Parameter Min Max Units
Tsu TXPAUSEADD stable prior to TXPAUSEFR High 16 – ns
Tpw TXPAUSEFR pulse width 16 – ns
Thold TXPAUSEADD stable after TXPAUSEFR High 16 – ns
TxPauseAdd[1:0]
TxPauseFr
Tsu(min) = 16 ns Thold(min) = 16 ns
Tpw (min) = 16 ns
000 : XON packet on all ports
001 : XOFF Port0
010 : XOFF Port1
011 : XOFF Port2
100 : XOFF Port3
110-1 01 : Re serve d
111 : XO FF on all ports
TXPAUSEADD[2:0]
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7.10 JTAG AC Timing Specification
Figure 50 and Tabl e 56 provide t he J TAG AC timing spec ifications.
Figure 50. JTAG AC Timing
Table 56. JTAG AC Timing Parameters
Symbol Parameter Min Max Units
Tjc TCLK cy cle time 90 - ns
Tjh TCLK High time 0.4 x Tjc 0.6 x Tj c ns
Tjl TCLK low time 0.4 x Tj c 0.6 x Tjc ns
Tjval TCLK falling edge to TDO valid - 25 ns
Tjsu TMS/TDI setup to TCLK 20 - ns
Tjsh TMS/TDI hold from TCLK 5 - ns
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7.11 System AC Timing Specification
Figure 51 and Table 57 illust rat e the syste m reset AC timin g spec ifica tion s.
Figure 51. System Reset AC Timing
Table 57. System Reset AC Timing Parameters
Symbol Parameter Min Max Units
Trw Res et pulse width 1.0 - µs
Trt Reset recovery ti m e 200 - µs
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7.12 LED AC Timing Specification
Figure 52 and Tabl e 58 provide the LED AC timing spe cifications.
Figure 52. LED AC Interface Timing
Table 58. LED Interface AC Timi ng P arameters
Symbol Parameter Min Max Units
Tcyc LED_CLK cycle time 1.36 1.40 ms
Thi LED _CL K Hi gh ti me 680 700 µs
Tlow LED_CLK low time 680 700 µs
Tdatd LED_CLK falling edge to LED_DATA valid 2 5 ns
Tlath LE D_CLK rising edge to LED_LATCH rising edge 690 700 µs
Tlatl LED_CLK falling edge to LED_LATCH falling edge 690 700 µs
LED_CLK
LED_DATA
L
ED_LATCH
Tcyc
Tlow
Thi
Tdatd
Tha
tl
Tlath
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8.0 Register Set
The registers s hown in this secti on provide acc es s for configuration, alarm monitoring, and control
of the chip. Table 59 “MAC Control Registers ($ Port Inde x + Offset)” on page 156 through
Table 69 “Optical Module Registe r s ($ 0x799 - 0x79F )” on page 162 provide register map deta ils.
The regis ters are listed by ascendi ng address in the tabl e.
8.1 Document Structure
The following s ections are structured to provide a general overview of the regis ter map. Later
sections provide detailed descriptions of each regis ter segment or bit.
All registers are acc es sed and addres se d as 32-bit doublewor ds. When acces sed using 8- or 16-bit
accesses, the CPU interface packs or unpacks the partial accesses into a 32-bit register value.
8.2 Graphical Representation
Fi gure 53 repres ents an overview of th e IXF1104 MAC global control st atus registers that are used
to configure or report on all ports. All regis ter loc ations shown in Figure 53 represent a 32-bit
double word.
Figure 53. Memor y Overvi ew Diagram
B0744-01
Global Configuration
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Port 3 MAC Control & Statistics
Port 2 MAC Control & Statistics
Port 1 MAC Control & Statistics
Port 0 MAC Control & Statistics
- RX Block Configuration
- TX Block Configuration
0x7FF
0x500
0x480
0x400
0x380
0x300
0x280
0x200
0x180
0x100
0x080
0x000
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8.3 Per P o rt Registers
Section 8.4 covers all of the registers that are repli ca ted in each port o f the IXF1104 MAC. These
registers perform an identical function in each port.
The address vector for the IXF1104 MAC is 11 bits wide. This al lows for 7 bits of port-specific
acc ess and a 4-bit vec tor to address ea ch port a nd all global register s. The address format is s hown
in Figure 54.
8.4 Register Ma p
Table 59 through Table 69 “Optical Module Registers ($ 0x799 - 0x79F)” on page 162 present the
IXF1104 MAC m emory map details . Global control and status registers are used to configure or
report on all ports, and some registers are replicated on a per-port basis.
Note: All IXF1104 MAC registers are 32 bits.
Figure 54. Register Over view Diagram
Po rt Select & Global R egisters P e r-Port Registers
10 0
6
Table 59. MAC Control Registers ($ Port Index + Offset) (Sheet 1 of 2)
Register Bit Size M o de1Ref Page Offset
“Station Addr ess ($ Port_Index +0 x00 – +0x01)” Low 32 R/W 163 0x00
“Station Addr ess ($ Port_Index +0 x00 – +0x01)” High 32 R/W 163 0x01
“Desired Duplex ($ Port_Index + 0x02)” 32 R/W 163 0x02
“FD FC Type ($ Port_Index + 0x03)” 32 R/W 163 0x03
Reserved 32 R – 0x04
“C olli s ion Distance ($ Port_Index + 0x05)” 32 R/W 164 0x05
“C olli s ion Threshold ($ Port_Index + 0x06)” 32 R/W 164 0x06
“FC TX Timer V alue ($ Port_Index + 0x07)” 32 R/W 164 0x07
“FD FC Address ($ Port_Index + 0x0 8 – + 0x09)”
FDFCAddressLow 32 R/W 164 0x08
“FD FC Address ($ Port_Index + 0x0 8 – + 0x09)”
FDFCAddressHigh 32 R/W 164 0x09
“IPG Receive Time 1 ($ Port_Index + 0x0A)” 32 R/W 165 0x0A
“IPG Receive Time 2 ($ Port_Index + 0x0B)” 32 R/W 165 0x0B
“IPG Transmit Ti me ($ Port_Index + 0x0C)” 32 R/W 165 0x0C
Reserved – RO – 0x0D
“Pau s e Thr e s ho ld ( $ Port _I nd ex + 0x0E ) ” 32 R/W 166 0x0E
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“Max Fram e Size (Addr: P ort_Index + 0x0F)” 32 R/W 166 0x0F
“MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)” 32 R/W 167 0x10
“Flush TX ($ Port_Index + 0x11)” 32 R/W 167 0x11
“FC Enable ($ Port_Index + 0x12)” 32 R/W 168 0x12
“FC Back Pressure Length ($ Port_Index + 0x13)” 32 R/W 168 0x13
“Short Runts Threshold ($ Port_Index + 0x14)” 32 R/W 169 0x14
“Dis card Unkn own Control Frame ($ Port_In dex +
0x15)” 32 R/W 169 0x15
“RX Config Word ($ Port_Index + 0x16)” 32 RO 169 0x16
“TX Config Word ($ Port_Index + 0x17)” 32 R/W 170 0x17
“Diverse Config Writ e ($ Port_Index + 0x18)” 32 R/W 171 0x18
“RX Packet Filter Control ($ Port_Index + 0x19)” 32 R/W 172 0x19
“Port Multicast Address ($ Port_Index +0x1A – +0x1B)”
PortMulticastAddressLow 32 R/W 173 0x1A
“Port Multicast Address ($ Port_Index +0x1A – +0x1B)”
PortMulticastAddressHigh 32 R/W 173 0x1B
Table 60. MAC RX St atisti cs Registers ($ Port Index + Offset) (Sheet 1 of 2)
Register Bit Size Mo de1Ref Page Offset
RxOctetsTotalOK 32 R 174 0x20
RxOctetsBAD 32 R 174 0x21
RxUCPckts 32 R 174 0x22
RxMCPkts 32 R 174 0x23
RxBCPkts 32 R 174 0x24
RxPkts64Octets 32 R 174 0x25
RxPkts65to127Octets 32 R 174 0x26
RxPkts128to255Octets 32 R 174 0x27
RxPkts256to511Octets 32 R 174 0x28
RxPkts512to1023Octets 32 R 174 0x29
RxPkts1024to1518Octets 32 R 174 0x2A
RxPkts1519toMaxOctets 32 R 174 0x2B
RxFCSErrors 32 R 174 0x2C
RxTagged 32 R 174 0x2D
RxDataError 32 R 174 0x2E
RxAlign Errors 32 R 174 0x2F
RxLongErrors 32 R 174 0x30
RxJabberErrors 32 R 174 0x31
PauseMacControlReceivedCounter 32 R 174 0x32
Tab le 59. MAC Co ntrol Registers ($ Port Index + Offset) (Sheet 2 of 2)
Register Bit Size Mo de1Ref Page Offset
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RxUnknownMacControlFrameCounter 32 R 174 0x33
RxVeryLongErrors 32 R 174 0x34
RxRuntErrors 32 R 174 0x35
RxShortErrors 32 R 174 0x36
RxCarrierExtendError 32 R 174 0x37
RxSequenceErrors 32 R 174 0x38
RxSymbolErrors 32 R 174 0x39
Table 61. MAC TX Statisti cs Registers ($ Port Index + Offset )
Register Bit Size M o de1Ref Page Offset
OctetsTransmittedOK 32 R 178 0x40
OctetsTransmittedBad 32 R 178 0x41
TxUCPkts 32 R 178 0x42
TxMCPkts 32 R 178 0x43
TxBCPkts 32 R 178 0x44
TxPkts64Octets 32 R 178 0x45
TxPkts65to127Octets 32 R 178 0x46
TxPkts128to255Octets 32 R 178 0x47
TxPkts256to511Octets 32 R 178 0x48
TxPkts512to1023Octets 32 R 178 0x49
TxPkts1024to1518Octets 32 R 178 0x4A
TxPkts1519toMaxOctets 32 R 178 0x4B
TxDeferred 32 R 178 0x4C
TxTotalCollisions 32 R 178 0x4D
TxSingleCollisions 32 R 178 0x4E
TxMultipleCollisions 32 R 178 0x4F
TxLateCollisions 32 R 178 0x50
TxExcessiveCollisionErrors 32 R 178 0x51
TxExcessiveDeferralErrors 32 R 178 0x52
TxExcessiveLengthDrop 32 R 178 0x53
TxUnderrun 32 R 178 0x54
TxTagged 32 R 178 0x55
TxCRCError 32 R 178 0x56
TxPauseFrames 32 R 178 0x57
TxFlowControlCollisionsSend 32 R 178 0x58
Table 60. MAC RX Statistics Registers ($ Port Index + Offset) (Sheet 2 of 2)
Register Bit Size M o de1Ref Page Offset
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Table 62. PHY Autoscan Registers ($ Port Index + Offset)
Register Bit Size Mo de1Ref Page Offset
“PHY Control ($ Port Index + 0x60)” 32 RO 181 0x60
“PHY Status ($ Port Index + 0x61)” 32 RO 182 0x61
“PHY Identification 1 ($ Port Index + 0x62)” 32 RO 183 0x62
“PHY Identification 2 ($ Port Index + 0x63)” 32 RO 184 0x63
“Auto-Negotiation Advertisement ($ Port I ndex + 0x64)” 32 RO 184 0x64
“Auto-Negotiation Link Partner Base Page Ability ($ Port
Index + 0x65)” 32 RO 185 0x65
“Auto-Negotiation Expansion ($ Port Index + 0x66)” 32 RO 186 0x66
“Auto-Negot iati on Next Page Transmit ($ Port In dex +
0x67)” 32 RO 187 0x67
Reserved 32 RO – 0x68 - 0x6F
Tab le 63. Gl obal Status and Configuration Registers ($ 0x500 - 0X50C)
Register Bit Size Mo de1Ref Page Address
“ Port Ena ble ($0x 500)” 32 R/W 188 0x500
“Interface Mode ($0x501)” 32 R/W 188 0x501
“Link LED Enable ($0x502)” 32 R/W 189 0x502
Reserved 32 RO – 0x503 - 0x504
“ M AC Sof t R es et ($ 0x 505) ” 32 R/W 189 0x505
“ M D IO Soft Res et ($ 0x 50 6)” 32 R/W 190 0x506
Reserved 32 RO – 0x507
“CPU Interface ($0x508)” 32 R/W 190 0x508
“LED Control ($0x509)” 32 R/W 190 0x509
“LED Flas h Rate ($0x50A)” 32 R/W 191 0x50A
“LED Fault Disable ($0x50B)” 32 R/W 191 0x50B
“JTAG ID ($0x50C)” 32 R 192 0x50C
Table 64. RX FIFO Registers ($ 0x580 - 0x5BF) (Sheet 1 of 2)
Register Bit Size Mo de1Ref Page Address
“RX FIFO High W atermark Port 0 ($0x580)” 32 R/W 193 0x580
“RX FIFO High W atermark Port 1 ($0x581)” 32 R/W 193 0x581
“RX FIFO High W atermark Port 2 ($0x582)” 32 R/W 193 0x582
“RX FIFO High W atermark Port 3 ($0x583)” 32 R/W 194 0x583
Reserved 32 RO – 0x584 - 0x589
“RX FIFO Low Watermark Port 0 ($ 0x58A)” 32 R/W 194 0x58A
“RX FIFO Low Watermar k Port 1 ($0x58B)” 32 R/W 194 0x58B
“RX FIFO Low Watermar k Port 2 ($0x58C)” 32 R/W 195 0x58C
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“R X FI FO Low Wate rmark Port 3 ($0x58D)” 32 R/W 195 0x58D
Reserved 32 RO – 0x58E - 0x593
RX FIFO Overflow Frame Drop Counter Port 0 32 R 195 0x594
RX FIFO Overflow Frame Drop Counter Port 1 32 R 195 0x595
RX FIFO Overflow Frame Drop Counter Port 2 32 R 195 0x596
RX FIFO Overflow Frame Drop Counter Port 3 32 R 195 0x597
Rese rved 32 RO – 0x598 - 0x 59D
“RX FIFO Port Reset ($0x59E)” 32 R/W 196 0x59E
“RX FIFO Errored Frame Drop Enable ($0x59F)” 32 R/W 196 0x59F
“RX FIFO Overflow Event ($0x5A0)” 32 R 197 0x5A0
Reserved 32 R – 0x5A1 - 0x5A5
RX FIFO Errored Frame Drop Counter Port 0 32 R 198 0x5A2
RX FIFO Errored Frame Drop Counter Port 1 32 R 198 0x5A3
RX FIFO Errored Frame Drop Counter Port 2 32 R 198 0x5A4
RX FIFO Errored Frame Drop Counter Port 3 32 R 198 0x5A5
Reserved 32 RO – 0x5A6 - 0x5B1
“RX F IFO SPI3 Loopback Enable for Ports 0 - 3
($0x5B2)” 32 R/W 199 0x5B2
“RX FIFO Padding and CRC Strip Enable ($0x5B3)” 32 R/W 200 0x5B3
Reserved 32 R – 0x5B4 - 0x5B7
“RX FIFO Transfer Threshold Port 0 ($0x5B8)” 32 R/W 201 0x5B8
“RX FIFO Transfer Threshold Port 1 ($0x5B9)” 32 R/W 201 0x5B9
“RX FIFO Transfer Threshold Port 2 ($0x5BA)” 32 R/W 201 0x5BA
“RX FIFO Transfer Threshold Port 3 ($0x5BB)” 32 R/W 202 0x5BB
Rese rved 32 R – 0x5BC - 0x5BF
Table 65. TX FIFO Registers ($ 0x600 - 0x63E) (Sheet 1 of 2)
Register Bit Size M o de1Ref Page Address
TX FIFO High Watermark Port 0 32 R/W 203 0x600
TX FIFO High Watermark Port 1 32 R/W 203 0x601
TX FIFO High Watermark Port 2 32 R/W 203 0x602
TX FIFO High Watermark Port 3 32 R/W 203 0x603
Reserved 32 RO – 0x604 - 0x609
TX FIFO Low Watermark Port 0 32 R/W 204 0x60A
TX FIFO Low Watermark Port 1 32 R/W 204 0x60B
TX FIFO Low Watermark Port 2 32 R/W 204 0x60C
TX FIFO Low Watermark Port 3 32 R/W 204 0x60D
Table 64. RX FIFO Registers ($ 0x580 - 0x5BF) (Sheet 2 of 2)
Register Bit Size M o de1Ref Page Address
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Reserved 32 RO – 0x60E - 0x613
TX FIFO MAC Threshold Port 0 32 R/W 205 0x614
TX FIFO MAC Threshold Port 1 32 R/W 205 0x615
TX FIFO MAC Threshold Port 2 32 R/W 205 0x616
TX FIFO MAC Threshold Port 3 32 R/W 205 0x617
Reserved – RO – 0x 618 - 0x6 1D
TX FIFO O v erflow /Underflow Event/Out of Sequence 32 R 206 0x61E
Loop RX Data to TX FIFO 32 R/W 207 0x61F
TX FIFO Port Reset 32 R/W 207 0x620
TX FIFO Overflow Frame Drop Counter Port 0 32 R 208 0x621
TX FIFO Overflow Frame Drop Counter Port 1 32 R 208 0x622
TX FIFO Overflow Frame Drop Counter Port 2 32 R 208 0x623
TX FIFO Overflow Frame Drop Counter Port 3 32 R 208 0x624
TX FIFO Errored Frame Drop Counter Port 0 32 R 209 0x625
TX FIFO Errored Frame Drop Counter Port 1 32 R 209 0x626
TX FIFO Errored Frame Drop Counter Port 2 32 R 209 0x627
TX FIFO Errored Frame Drop Counter Port 3 32 R 209 0x628
Reserved 32 R – 0x62 9 - 0x6 2C
TX FIFO Occup ancy Counter for Port 0 32 R 210 0x62D
TX FIFO Occup ancy Counter for Port 1 32 R 210 0x62E
TX FIFO Occup ancy Counter for Port 2 32 R 210 0x62F
TX FIFO Occup ancy Counter for Port 3 32 R 210 0x630
Reserved 32 R – 0x63 1 - 0x63E
Tab le 66. MDI O Register s ($ 0x680 - 0x683)
Register Bit Size Mo de1Ref Page Address
“MDI O Single Comm and ($0x680)” 32 R/W 211 0x680
“MDI O Single Read and W rite Data ($ 0x681)” 32 R/W 211 0x681
“ Autos ca n P HY Addres s E na ble ($0 x 68 2) ” 32 R/W 212 0x682
“MDIO Control ($0x683)” 32 R/W 212 0x683
Table 67. SPI3 Registers ($ 0x700 - 0x716) (Sheet 1 of 2)
Register Bit Size Mo de1Ref Page Address
“SPI3 Transmit and Global Configuration ($0x700) ” 32 R/W 213 0x700
“SPI3 R eceive Configu ration ($0x701)” 32 R/W 215 0x701
Tab le 65. TX FIFO Reg isters ($ 0x600 - 0x63E) (Sheet 2 of 2)
Register Bit Size Mo de1Ref Page Address
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Reserved 32 R – 0x702 - 0x709
“Address Parity Error Packet Drop Counter ($0x70A)” 32 R 219 0x70A
Reserved 32 R – 0x70B - 0x716
Table 68. SerDes Registers ($ 0x780 - 0x798)
Register Bit Size M o de1Ref Page Address
Reserved 32 RO – 0x780 - 0x783
“TX Driver Power Leve l Ports 0 - 3 ($0x784)” 32 R/W 220 0x784
Reserved 32 RO – 0x785 - 0x786
“TX and RX Power-Down ($0x787)" 32 R/W 220 0x787
Reserved 32 RO – 0x788 - 0x792
“RX Signal Detect Level Ports 0 - 3 ($0x793)” 32 R/W 220 0x793
“C lock and Interface Mode Ch ange En able Ports 0 - 3
($0x794)” 32 R/W 221 0x794
Reserved 32 RO – 0x795 - 0x798
Table 69. Optica l Module Registers ($ 0x799 - 0x79F)
Register Bit Size M o de1Ref Page Address
“Optical Module Sta tus Ports 0-3 ($0x799)” 32 R 222 0x799
“Optical Module Control Ports 0 - 3 ($0x79A)” 32 R/W 222 0x79A
“I2C Control Ports 0 - 3 ($0x79B)” 32 R/W 223 0x79B
Reserved 32 RO – 0 x79C - 0x79E
“I2C Data Ports 0 - 3 ($0x79F)” 32 R/W 223 0x79F
Table 67. SPI3 Registers ($ 0x700 - 0x716) (Sheet 2 of 2)
Register Bit Size M o de1Ref Page Address
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8.4.1 MAC Control Registers
Table 70 through Table 92 “Port Multi ca st Address ($ Po rt_Index +0x1A – +0x1B)” on page 173
pr ovide det ails on the control and status regis ters associated wit h ea ch MAC port. The register
address is ‘Port_index + 0x**’, where the port index is set at any value from 0x0 through 0x5. All
r egisters are 32-bit. The unused bits of th e reg isters are re ad-only and are set perman ently to zero.
Table 70. Sta tion Address ($ Por t_Index +0x00 – +0x01)
Name Description Address Type1Default
Station Address
Low
Source MAC address bit 31-0.
T hi s ad dr e s s is inse r te d in th e sou r c e ad dr e ss
field when transmitting pause frames, and is also
used to compare against unic ast pause fram es
at the receiving side.
Port_Index
+ 0x00 R/W 0x0000000
Station Address
High
Source MA C add r ess bit 4 7-32.
T hi s ad dr e s s is inse r te d in th e sou r c e ad dr e ss
field when transmitting pause frames, and is also
used to compare against unic ast pause fram es
at the receiving side. Bits 15:0 of this register are
ass igned t o bits 47:32 of the station address.
Port_Index
+ 0x01 R/W 0x00000000
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 71. Desired Duplex ($ Port_I ndex + 0x02)
Bit Name Description Type1Default
Register D escrip t ion : Chooses between half-duplex and full-duplex operation in RGMII
100 Mbps or 10 M bps mode only.
This register must be set to the default value of 1 and must not be changed when operating in
RGMII 1000 Mbps, GMII, or fiber mode.
0x00000001
31:1 Reserved Reserved R 0x00000000
0 Duple x Select
0 = Half-duplex
1 = Full-duplex
NOTE: Half-d uplex operatio n applies only to
10/100 Mbps speed on copper media in RGMII
mode only . Gigabit speed on either media requires
full-duplex.
R/W 1
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 72. FD FC Type ($ Port_In dex + 0x03)
Name Description Address Type1Default
FD FC Type This value fills the Type field of the Transmitted
Pause frames. Only bits 15:0 of this register are
used.
Port_Index
+ 0x 03 R/W 0x00008808
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Table 73. Collision Di stance ($ Port_Index + 0x05)
Name Description Address Type1Default
Collision
Distance
This is a 10-bit value that set s the limit for late
coll is ion. Collis i on s ha pp en ing at by te tim e s
beyond the configured value are considered to be
late collisions. (Only valid in half-duplex).
Port_Index
+ 0x 05 R/W 0x00000043
1. RO = Read Only , No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
Table 74. Collision T hre sho ld ($ Port_Ind ex + 0x06)
Name Description Address Type1Default
Collision
Threshold
This is a 4-bit value that sets the limit for
excessive coll isions. When the numb er of
tra ns mis si on attemp ts pe r forme d f or a pac ke t
exceeds this value, it is considered to be an
excessive coll ision and the fr ame is dropped.
(O nl y va lid in ha lf -d uple x).
Port_Index
+ 0x 06 R/W 0x0000000F
1. RO = Read Only , No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
Table 75. FC TX Timer Value ($ Port_Index + 0x07)
Name Description Address Type1Default
FC TX T imer
Value
The 16-bit pause length inserted in the flow
control pause frame sent to the receiving
st at io n. Th e va lue is in 51 2-bit ti me s. Port_Index
+ 0x07 R/W 0x0000005E
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
Table 76. FD FC Address ($ P ort_Ind ex + 0x08 – + 0x09)
Name Description Address Type1Default
FD FC Address Low The lowest 32 bits of the 48-bit globally
as signed multicast pause frame dest ination
address.
Port_Index
+ 0x08 R/W 0xC2000001
FD FC Address High The highest 16 bits (47:32) of the globally
as signed multicast pause frame dest ination
address. The higher 16-bit address is
derived from bits 15:0 of this register.
Port_Index
+ 0x09 R/W 0x00000180
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
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Table 77. IPG Receive Time 1 ($ Port_Index + 0x0A)
Name Description Address Type1Default
IPG Receive Time 1
This timer is used during half-duplex operation
when there is a p acket w aitin g for
transmission from the MAC. This timer starts
after CRS is de-asserted. If CRS is asserted
during this time, no transmission is initiated
and the counter restarts once CRS is de-
as serted again.
Th e va lu e sp ecif ied in this reg is t e r is
calculated as follows: (regis ter_value * 8) =
RXIPG1 in terms of bit times. Therefore, a
default value of 8 gives the following: (8 * 8 =
64 bit t imes for the defa ult).
Port_Index
+ 0x 0A R/W 0x00000008
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 78. IPG Receive Time 2 ($ Port_Index + 0x0B)
Name Description Address Type1Default
IPG Receive Time 2
This is only used in half-duplex operation. It
starts counting at the same time as RXIPG1.
Once RXIPG1 expires, a frame is transmitted
when RXIPG2 expires regardless of the CRS
value. If CRS is asserted before RXIPG1
expires, no transmission occurs and both
RXIPG1 an RXIPG2 are reset once CRS is
de-asserted again.
Th e va lu e sp ecif ied in this reg is t e r is
calculated as follows: (register_value +5) * 8 =
RXIPG2 in terms of bit times. Therefore, a
default of 7 gives the following:
(7+5) * 8 = 96 bit times for default.
Port_Index
+ 0x 0B R/W 0x00000007
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 79. IPG Transmit Time ($ Port_Index + 0x0C)
Name Description Address Type1Default
IPG Transmit Time
This is a 10-bit value configuring IPG time for
back-to- back transmissions.
Th e va lu e sp ecif ied in this reg is t e r is
calculated as follows: (register_value +4) * 8 =
TXIPG in terms of bit times. Therefore, a
default value of 8 gives the following:
(8+4) * 8 = 96 bit times for the default.
Port_Index
+ 0x 0C R/W 0x00000008
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Table 80. Pause Threshold ($ Port_Index + 0x0E)
Name Description Address Type1Default
Pause
Threshold
When a pause frame has been sent, an internal
timer checks when the next pause f rame m ust
be s cheduled for t ransmission to keep the link
partner in pause mode (this is required only if
the f l ow c on tro l ha s to be ex tend ed f or o ne mo re
sess io n). The pau se t hresh old va lu e i s a 16 -bit
value that sets the time in terms of 512-bit
quantum after the prev ious pause f rame when
the next pause frame has to be sent. This
ensures that the link partner is kept in pause
mode continuously.
Port_Index
+ 0x 0E R/W 0x0000002F
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
Table 81. Max Frame Size (Addr: Port_Index + 0x0F)
Name Description Address Type1Default
M ax Frame Size
Th is is a 14-bit value configu ring the m aximum
frame size the MAC can receive or transmit
without activating any error counters, and
without truncation.
This value is excluding the 4-byte CRC in the
transmit direction when CRC append is
enabled in the MAC. Hence, t his value has to
be set four bytes less when CRC append is
enabled in the MAC .
The maximum frame size is internally adjust ed
by +4 if the frame is VLAN tagged.
Port_Inde
x + 0x 0F R/W 0x000005EE
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
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Table 82. MAC I F Mode an d RGM II Speed ($ Port_Index + 0x10)
Bit Name Description Type1Default
Register D escription – M AC IF Mode: Determines the MAC operation frequency and mode
per port.
Changes to the data setting of this register must be made in conjunction with the “C l ock a n d
Interface Mode Change Enable Ports 0 - 3 ($0x794) " to ensure a safe transition to a new
operational mode. Changes to this register must follow a proper sequence. Refer to Section
6.1, “Cha nge Port Mode Initialization Sequence” on pag e 130 for the prop er se quence f or
changing the port mode and speed.
0x00000003
31:3 Reserved Reserved R 0x00000000
2: 0 P or t Mo de
These bit s are us ed to define the clock m ode and
the RGMII/GMII mode of operation.
000 = Reserv ed
001 = Reserv ed
010 = GMII 1000 Mbps operation
011 = Reserved
100 = RGMII 10 Mbps operation
101 = RGMII 100 Mbps operation
11x = RGMII 1000 Mbps operation
R/W 011
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 83. Flush TX ($ Port_Index + 0x11)
Bit Name Description Type1Default
Register D escrip t ion : Used to flush all TX data. It is used if all traffic sent to a port should be
stopped. 0x00000000
31:1 Reserved Reserved R 0x00000000
0Flush TX This bit flushes all TX data and is used if all the
traffic sent to a port should be stopped. R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Table 84. FC Enable ($ Port_Index + 0x12)
Bit Name Description Type1Default
Register Description: Indicat es which flow control mod e is used for the RX and TX MAC . 0x0000 0007
31:3 Reserved Reserved R 0x00000000
2TX HDFC
When TX HDF C is enab led (ha l f-du pl ex mod e
only), the MAC generates deliberate collisions on
incoming packets when the RX FIFO occupancy
crosses the High Watermark (flow control).
0 = Disable TX half-duplex flow control
1 = Enable TX half-duplex flow control
R/W 1
1TX FDFC
0 = Disable TX full-duplex flow control [the MAC
will not generate internally any flow control
frames based on t he RX FIFO watermarks or
the Transmit Pause Control interface
1 = Enable TX full-duplex flow control [enables
the MAC to send flow control frames to the
link partner based on the RX FIFO
programmable watermarks or the T ransmit
Pause Control interface]
R/W 1
0RX FDFC
0 = Disable RX full-duplex flow control [the MAC
will not respond to flow control frames sent to
it by the link partner]
1 = Enable RX full-duplex flow control [MAC will
resp ond to fl ow cont rol fram es sent by the lin k
partner and will stop packet transmission for
the time specified in the flow control frame]
R/W 1
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
Table 85. FC Back Pressure Length ($ Port_Index + 0x13)
Name Description Address Type1Default
FC Back Pressure
Length
This register sets number the byte cycles
for which the collision has to be applied.
The 6-bit configuration holds the val ue in
bytes , wh ic h ap plie s to t he min im um
length/duration of back pressure in half-
duplex mode. Flow control in the receive
path is executed by deliberately colliding
the incoming packets in half-duplex mode.
Register bits 5:0 are used alone .
Port Add +
0x13 R/W 0x0000000C
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
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Table 86. Short Runts Thresho ld ($ Port_Ind ex + 0x14)
Name Description Address Type1Default
Shor t Runts
Threshold
The 5- bit conf igura tio n hold s th e value in bytes,
which applies to the threshold in determining
between runts and short. The bits 4:0 of this
register are alone used.
A r eceiv ed pa ck et is repo r ted a s a sh ort p acket
when the length (exclu ding Preamble and
SFD) is less than this value.
A received packet is reported as a runt packet
when the length (exclu ding Preamble and
SFD) is equal to or greater than this value and
less than 64-bytes.
NOTE: This register is only relevant when the
IXF 110 4 MA C port is con f ig ured fo r
copper op era tion (the line side
interface is configured for either RGMII
or GMII).
Port_I ndex +
0x14 R/W 0x00000008
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Tab le 87. Disc ard Unknown Control Frame ($ Port_Index + 0x15)
Bit Name Description Type1Default
Register D escrip t ion : Discards or forwards unknown control frames. Known control frames
ar e pau se fr am es . 0x00000000
31:1 Reserved Reserved R 0x00000000
0Discard Unknown
Control Frame 0 = Forw ard unk nown control frames
1 = Discard unknown control frame s R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Tab le 88. RX Config Word ($ P o rt_Index + 0x16) (S heet 1 of 2)
Bit Name Description Type1Default
Reg ist er De sc ript ion : This register is used in fiber MAC only for auto-negotiation and to report
the receive status. The lower 16 bits of this register are the “config_reg” received from the link
partner, as described in IEEE 802.3 2000 Edition, Section 37.2.1. 0x00000000
31:22 Reserved Reserved RO 0x000
21 An_complete
Auto-negotiation complete. This bit remains
cleared from the time auto-negotiation is reset until
auto-negotiation reaches the “LINK_OK” state. It
remains set until auto-negotiation is disabl ed or
restarted.
This bit is only valid if auto-negotiation is enabled.
RO 0
20 R x Sy nc 0 = Loss of synchronization
1 = Bit synchronization. The bit remains Low until
the register is read. RO 0
1. RO = Rea d O nly, No c le ar on Read ; R = Re ad, C lea r on Rea d; W = Wr i te on ly ; R/W = Read /W r ite , No cl e ar;
R/W/C = Read/Write, Clear on Write
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19 RX Config 0 = Rec eiving idle/d ata st ream
1 = Receiving /C / order ed set s RO 0
18 Config Changed
0 = RxConfigWord has changed si nce last read
1 = RxConfigWord has not changed since last
read.
This bit remains High until the register is read.
R0
17 Invalid Word 0 = Have not received an invalid symbol
1 = Hav e receive d an invalid symbol
This bit remains High until the register is read. RO 0
16 Car rier S ense 0 = De vice is no t rece ivin g idle chara cters ; c arri er
sense is true.
1 = Device is receiving idle characters; carrier
sense is false.
RO 0
15 Next Page Next Page request RO 0
14 Reserved Reserved RO 0
13:122Remote Fault [1:0]
Remote fault definitions:
00 =No error, link okay
01 =Offlin e
10 =Link failure
11 = Auto-negotiation_Error
R/W 00
11:9 Reserved Reserved RO 000
8 As y m Pau se As y m Pau se. The abi lity to send paus e f ra mes . R O 0
7Sym Pause Sym Pause. The ability to send and receive pause
frames. RO 0
6 Half Duplex Half-duplex RO 0
5 Full Duplex Full-duplex RO 0
4:0 Reserved Reserved RO 0x0
Table 89. TX Config Word ($ Port_Ind ex + 0x17) (Sheet 1 of 2)
Bit Name Description Type1Default
Register Description: This register is used in fiber MAC for auto-negotiation only. The
c ontents of this regi ster are sent as the config _word. The contents of this reg ister are the
“config_reg” sent to the link partner, as described in IEEE 802.3 2000 Edition, subclause 37.2.1. 0x000001A0
31:16 Reserved Reserved RO 0x0000
15 Next Page Next Page request R/W 0
14 Reserved Write as 0, ignore on read R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = W rite only; R/W = Read/Write , No clear;
R/W/C = Read/Write, Clear on Write
NOTE: A value of 0x0 must be wri tten to all reserv ed bits of the “TX Config Word ($ Port_Index + 0x17)”
Register.
Table 88. RX Co nfig Wo rd ($ Port_I ndex + 0x16) (Sheet 2 of 2)
Bit Name Description Type1Default
1. RO = Read O nly , No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
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13:122Remote Fault [1:0]
Remote fault definitions:
00 =No er ror, lin k oka y
01 =Offline
10 =Link failure
11 =Auto-negotiation_Error
R/W 00
11:9 Reserved Write as 0, ignore on Read R/W 000
8 Asym Paus e Asym Pause. The ability to send pause fram es. R/ W 1
7Sym Pause Sym Pause. The ability to send and receive pause
frames. R/W 1
6 Half Duplex Half-duplex R/W 0
5 Full Duplex Ful l-dup lex R/W 1
4:0 Reserved Write as 0, ignore on read R/W 0x00
Tab le 90. Dive rse Con fig Write ($ Port_Ind ex + 0x18) (Sheet 1 of 2)
Bit Name Description Type1Default
Register D escrip t ion : This register contains various configuration bits for general use. 0x00110D
31:19 Reserved Reserved RO 0x0000
18:13 Reserved Write as 0, ignore on Read. R/W 0x0000
12 Reserved2Write as 1, ignore on Read. R/W 1
11-9 Reserved2Write as 0, ignore on Read. R/W 0x0
8Reserved
2Write as 1, ignore on Read. R/W 1
7 pad_enable
0 = Normal ope ration
1 = Ena ble padding of undersized packet s
NOTE: Assertion of this bit results in the
automatic addition of a CRC to the
padded packet.
R/W 0
6 crc_add 0 = Normal ope ration
1 = Enable automat ic CRC appending R/W 0
5AN_enable
Enable auto-negotiation (used for fiber mode only)
to be performed by the hardware state machines
in the MAC .
The hardware auto-negotiation (AN) state
machine co ntrols t he config w ords tr ansmitted
when this bit is set.
NOTE: In copper mode, this bit must be set to 0
(reserved).
R/W 0
42Reserved Write as 0, ignore on Read. R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/W rite, No clear;
R/W/C = Read/Write, Clear on Write
2. Reserved bi ts must be written to the default value f or proper oper ation .
Tab le 89. TX Co nfig Word ($ Port_Index + 0x17) (Sheet 2 of 2)
Bit Name Description Type1Default
1. RO = Read On ly, No clear on Read; R = Read, Clear on Read; W = W r ite only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
NOTE: A value of 0x0 must be written to all reserved bits of the “TX Config Word ($ Port_Index + 0x17)”
Register.
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3:22Reserved Writ e as 1, ignore on Re ad. R/W 11
12Reserved Wr ite as 0, ignor e on Read . R/W 0
02Reserved Wr ite as 1, ignor e on Read . R/W 1
Table 90. Diverse Config Write ($ Port_Index + 0x18) (Sheet 2 of 2)
Bit Name Description Type1Default
1. RO = Read Only , No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
2. Reserved bits must be written to the default value for proper operation.
Table 91. RX Packet Filter Control ($ Port_Index + 0x19) (Sh eet 1 of 2)
Bit Name Description Type1Default
Register Description: This register allows for specific packet types to be marked for filtering
and is us ed in conjunct ion with the “RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2
- 0x5A5)”.0x00000000
31:6 Reserved Reserved 0
5 CRC Error Pass
This bit enables a Global filter on frames with a
CRC Error.
0 = When CRC Error Pass = 0, all frames with a
CRC Error are marked as bad. 2
1 = Frames with a CRC Error are not marked as
bad and are passed to the SPI3 interface for
transfer as good frames, regardless of the
state of the bits in the “RX FIFO Errored
Frame Drop Enable ($0x59F)”.
NOTE: When the CRC Error Pass Filter bit = 0, it
t akes preced ence over th e other fi lter bits.
Any pack et, whet her is a Pause, Unicas t,
Multicast or Broadcast pa cket with a CRC
error, is marked as a bad frame when
CRC Error Pass = 0
R/W 0
4 Pause Frame Pass
This bit enables a Global filter on Pause frames.
0 = All pause frames are dropped.2
1 = All pause frames are passed to the SPI3
Interface.
NOTE: Pause Frames can only be filtered if
RXFD flow control is enabled in the “FC
Enable ($ Po rt_Index + 0x12)”.
R/W 0
3 VLAN Drop En
This bit enables a global f ilter on VLAN frames.
0 = All VLAN frames are passed to the SPI3
Interface.
1 = All VLAN frames are dropped.2
R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
2. Used in conjunction with the “RX FIFO Errored Frame Drop Enable ($0x59F)” on page 196. This allows the
frame to be dropped in the RX FIFO. Otherwise, the frame is sent out the SP3 interface and may be
optionally signaled with an RERR (see bit 0 of “SPI3 Receive Configuration ($0x70 1)”.
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2 B/Cas t Drop En
This bit enables a Global filter on broadcast
frames.
0 = All broadc ast frames are passed to the SPI3
Interface.
1 = All broadc ast fram es are droppe d.2
R/W 0
1 M/Cast Match En
This bit enables a filter on multicast frames.
0 = All m uticast fr ames ar e good and passed to
the SPI3 Inter fa ce.
1 = Only multicast frames with a destination
address that matches the
Por tMultic astAddr ess are for ward ed. All ot her
muticast frames are dropped.2
R/W 0
0 U/Cast Match En2
This bit enables a filter on unicast frames.
0 = All unicast frames are good and are passed
to the SPI3 Interface.
1 = Only unicast fr ames wi th a Destination
Address that matc hes th e Station Address
are forwarded. All other unicast f rames are
dropped.2
NOTE: The VLA N fil ter ov erri des th e unicast filte r .
Therefore, a VLAN frame cannot be
filtered based on the unicast address.
R/W 0
Tab le 92. Po rt M u lticast Address ($ Po rt_Index +0x1A – +0x1B)
Name Description Address Type*Default
Po rt Mu ltic as t
Ad d r es s Lo w
Thi s ad dres s c om pa res ag ai ns t m ult i cas t fra me s
a t the rece iving s ide if multicast filt ering is
enabled.
This register contains bits 31:0 of the address.
Port_Index
+ 0x 1A R/W 0x0000000
Po rt Mu ltic as t
Address High
Thi s ad dres s c om pa res ag ai ns t m ult i cas t fra me s
a t the rece iving s ide if Multicast filt ering is
enabled.
This register contains bits 47:32 of the address.
Port_Index
+ 0x 1B R/W 0x00000000
1. RO = Read Only , No clear on Read; R = Read, Clear on Read; W = W rite only; R/W = Read/Wri te, No clear;
R/W/C = Read/Write, Clear on Write
Tab le 91. RX Packet Filter Control ($ Port_Index + 0x19) (Sheet 2 of 2)
Bit Name Description Type1Default
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
2. Used in con j unc t ion w ith th e “RX FIFO Errored Frame Drop Enable ($0x59F)” on page 196. This allows the
f ram e t o be droppe d in the RX FIFO . Oth er w is e, t h e fr am e is sen t out the S P3 in t erfac e an d ma y be
optional ly signaled with an RERR (s ee bit 0 of “SPI3 Receive Configuration ($0x701)”.
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8.4.2 MAC RX Statistics Register Overview
The MAC RX Stati stics registers contain the MAC rece iver statistic counters and are cleare d when
read. The software polls these registers and accumulates values to ensure that the counters do not
wrap. The 32-bit co unters wrap after approximately 30 seconds.
Table 93 covers the RX statistics f or the four MAC ports. Port_Index is the port num ber (0, 1, 2, or
3).
Table 93. MAC RX Statistics ($ Port_Index + 0x20 – + 0x39) (Sheet 1 of 4)
Name Description Address Type1Default
RxOctetsTotalOK
Counts the bytes received in all legal frames,
includin g all byt es from the destination MAC
address to and including the cyclic redundancy
check (CRC). The initial preamble and Start of
Frame Delimiter (SFD) bytes are not counted.
Port_Index
+ 0x20 R 0x00000000
RxOctetsBAD2
Counts the bytes received in all bad frames with
legal size (frames with CRC error, alignment
errors, or code violations) , including all bytes
from the destination MAC address to (and
including) the CRC. The initial preamble and
SFD bytes are not counted. Frames with illegal
size do not add to this counter (shorts, runts,
longs, jabbers, and very longs).
Note: This register does not count octets on
undersize d rec eiv ed pack ets .
Port_Index
+ 0x21 R 0x00000000
RxUCPkts
The total number of unicast p ackets received
(excluding bad packets).
Note: This count includes non-pause control and
VLAN packets, which are also counted in other
counters. These packet types are counted twice.
Take care when summing register counts for
reporting Management Information Base (MIB)
information.
Port_Index
+ 0x22 R 0x00000000
RxMCPkts
The total number of multicast packets received
(excluding bad packets)
Note: This count includes pause control packets,
which are also counted in the PauseMacControl-
Rece ivedCounter. These packet ty pes are
counted twice. T ake care when summing register
counts for reporting MIB information.
Port_Index
+ 0x23 R 0x00000000
RxBCPkts The total numb er of Broadcast pack ets received
(excluding bad packets). Port_Index
+ 0x24 R 0x00000000
RxPkts64Octets The total number of packets receiv ed (inclu ding
bad packets) that were 64 octets in length.
Incremented for tagged packets with a length of
64 bytes, including tag field.
Port_Index
+ 0x25 R 0x00000000
1. RO = Read Onl y , No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
2. When sending in large frames, the counters can only handle certain limits. The behavior of the LongErrors
and VeryLongErrors counters is as follows: Ve ryLongErrors counts frames that are 2*maxframesize,
dependent upon where maxframesize is set. If maxframesize sets greater than half of the available count in
RxOctetsBad (2^14-1), V eryLongErrors is never incremented, but LongErrors is incremented. This is due to
a limitation in the counter size, which means that an accurate count will not occur in the RxOctetsBAD
counter if the frame is larger than 2^14-1.
3. This register is relevant only when configured for copper operation.
4. This register is re levant only wh en conf igured for fiber operation (line side interface is Se rDes).
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RxPkts65to127
Octets
The total number of packets received (including
bad packets) that were 65-127 octets in length.
Incremented for tagged packets with a length of
65-127 by tes, including tag field.
Port_Index
+ 0x 26 R 0x00000000
RxPkts128t0255
Octets
The total number of packets received (including
bad packets) that were 128-255 octets in length.
Incremented for tagged packets with a length of
128-255 by tes, includ ing tag field .
Port_Index
+ 0x 27 R 0x00000000
RxPkts256to511
Octets
The total number of packets received (including
bad packets) that were 256-511 octets in length.
Incremented for tagged packets with a length of
256-511 bytes, includ ing tag field.
Port_Index
+ 0x 28 R 0x00000000
RxPkts512to1023O
ctets
The total number of packets received (including
bad packets) that were 512-1023 octets in
length. Incremented for tagged packets with a
length of 512-1023 bytes, includin g tag field.
Port_Index
+ 0x 29 R 0x00000000
RxPkts1024to1518
Octets
The total number of packets received (including
bad packets) that w ere 102 4-1 518 octe ts in
length. Incremented for tagged packet with a
length between 1024-1522, including the tag.
Port_Index
+ 0x2A R 0x00000000
RxPkts1519toMaxO
ctets
The total number of packets received (including
bad packets) that were gr eater than 1518 octet s
in length. Incremented for tagged packet with a
length be tw een 15 23-max frame si ze, including
the tag.
Port_Index
+ 0x2B R 0x00000000
RxFCSErrors
Number of frames received with legal size, but
with wrong CRC field (also cal led Frame Check
Sequence (F CS) field).
NOTE: Legal size is 64 bytes through the value
programmed in the “M ax F r am e Size
(Addr: Port_Index + 0x0F)” on
page 166.
Port_Index
+ 0x2C R 0x00000000
RxTagged Number of OK frames with VLAN tag.
(Ty pe fiel d = 0x8100) Port_Index
+ 0x2D R 0x00000000
RxDataError3Number of frames received with legal length,
containing a code violation (signaled with
RX_ERR on RGMII).
Port_Index
+ 0x2E R 0x00000000
Tab le 93. MAC RX Stati stics ($ Port_Index + 0x20 – + 0x39) (Sheet 2 of 4)
Name Description Address Type1Default
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Wri te, No clear;
R/W/C = Read/Write, Clear on Write
2. When sending in large frames, the counters can only handle certain limits. The behavior of the LongErrors
and V eryLongErrors counters is as follows: VeryLongErrors counts frames that are 2*maxframesize,
dependent upon where maxframesize is set. If maxframesize sets greater than half of the available count in
RxOc te ts Bad ( 2^ 14- 1), V er y Lo ngEr ro rs is ne ve r i nc reme nt ed, but LongE rr ors is in cr em ent ed . Thi s is du e t o
a limitation in the counter size, which means that an accurate count will not occur in the RxOctetsBAD
cou n ter if the fram e is lar ger tha n 2^ 14 - 1.
3. This registe r is relevant only when config ured for copper op eration.
4. This register is relevant only when configured for fiber operation (line side interface is SerDes).
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RxAlignErrors3
Frames with a legal frame size, but containing
less than eight additional bits. This occurs when
the frame is not by te aligned. The CRC of the
frame is wrong when the additional bits are
strip ped. If the CRC is OK, then the frame is not
c ounted but treated as an OK frame . This
counter increments in 10 Mbps or 100 Mbps
RGMII mode only.
NOTE: This counter increments in 10 or 100
Mbps RGMII mode only.
Port_Index
+ 0x2F R 0x00000000
RxLongErrors2
Frames bigger than the maximum allowed, with
both OK CRC and the integral number of octets.
Default maximum allowed is 1518 bytes
untagged and 1522 bytes tagged, but the value
c an be changed b y a register.
Fra me s bi gger t ha n the l arg er of
2*maxframesize and 50,000 bits are not counted
here, but they are counted in the VeryLongError
counter.
Port_Index
+ 0x30 R 0x00000000
RxJabberErrors
Frames bigger than the maximum allowed, with
either a bad CRC or a non-integral number of
octets. The default maximum allowed is 1518
bytes untagged and 1522 bytes tagged, but the
value can be changed by a register.
Fra me s bi gger t ha n the l arg er of
2*maxframesize and 50,000 bits are not counted
here, but they are counted in the VeryLongError
counter.
Port_Index
+ 0x31 R 0x00000000
RxPauseMacContr
olReceivedCounter
Number of Pa use MAC control frames re ceived.
This statistic register increment s on any valid 64-
byte pause frame with a valid CRC and also
increments on a 64-byte pause frame with an
invalid CRC if bit 5 of the “RX Packet Filter
Control ($ Port_Index + 0x19)” is set to 1.
Port_Index
+ 0x32 R 0x00000000
RxUnknownMac
ControlFrame
Counter
Number of MAC control frames received with an
op code differ ent from 0001 (P ause). Port_Index
+ 0x33 R 0x00000000
RxVeryLongErrors2Fr a me s bi gger t ha n the l arg er of
2*m ax fr a m es iz e an d 50,00 0 bit s Port_Index
+ 0x34 R 0x00000000
Table 93. MAC RX Statistics ($ Port_Index + 0x20 – + 0x39) (Sheet 3 of 4)
Name Description Address Type1Default
1. RO = Read Onl y , No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
2. When sending in large frames, the counters can only handle certain limits. The behavior of the LongErrors
and VeryLongErrors counters is as follows: Ve ryLongErrors counts frames that are 2*maxframesize,
dependent upon where maxframesize is set. If maxframesize sets greater than half of the available count in
RxOctetsBad (2^14-1), V eryLongErrors is never incremented, but LongErrors is incremented. This is due to
a limitation in the counter size, which means that an accurate count will not occur in the RxOctetsBAD
counter if the frame is larger than 2^14-1.
3. This register is relevant only when configured for copper operation.
4. This register is re levant only wh en conf igured for fiber operation (line side interface is Se rDes).
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RxRuntErrors3
The total number of packets received that are
less than 64 octets in length, but longer than or
equal to 96 bit times, which corresponds to a 4-
byte frame with a well-fo rmed p ream ble an d
SFD. This is the shortest fragment and can be
trans m itted in case of a colli s ion event on a half-
dupl ex segm ent. This c ounter indicate s fragm ent
sizes, which is expect ed on half-duplex
segments but not on full-duplex links, and the
counter is only fully updated after receipt of a
good fra m e follo win g a fr agment.
NOTE: The ShortRuntsThreshold register
controls the byte count used to
dete r mine t he dif f ere nce b etw een R u nts
and S ho rt s an d t he ref ore con tro ls wh ic h
counter is incremented for a given frame
size. This counter is only upda ted after
receipt of two good frames.
NOTE: This counter is only valid when the
selected port within the IXF1 1 04 MAC is
operating in copper (RGMII or GMII)
mode. The RuntError counter is not
updated when the selected port within
the IXF1104 MAC is configured to
operated in fiber (SerDes) mode.
Port_Index
+ 0x 35 R 0x00000000
RxShort Errors3
The total number of packets received that are
less than 96 bit times, which corresponds to a 4-
byte frame with a well-fo rmed p ream ble an d
SFD. This counter indicates fragment sizes
ill eg al in al l mod es an d is onl y fu ll y up date d af ter
reception of a good fr ame following a fragment .
NOTE: This register is only relevant when the
IXF 1104 MAC port is config ured for
copper operation (the line side interface
is c onfigured for either R GMII or GMII
operation). This register will not
increment wh en the IXF1104 MA C port
i s co nfi gured for f ib er op eratio n us ing
the SerDes interface.
Port_Index
+ 0x 36 R 0x00000000
RxCarrier Extend
Error Not applicab le. P ort_Index
+ 0x 37 R 0x00000000
RxSequenceErrors4Records the number of se quencing erro rs that
occur in fiber mode. Port_Index
+ 0x 38 R 0x00000000
RxSymbolErrors4Records the number of sym bol errors
encou ntere d by the PH Y. P ort_Index
+ 0x 39 R 0x00000000
Tab le 93. MAC RX Stati stics ($ Port_Index + 0x20 – + 0x39) (Sheet 4 of 4)
Name Description Address Type1Default
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Wri te, No clear;
R/W/C = Read/Write, Clear on Write
2. When sending in large frames, the counters can only handle certain limits. The behavior of the LongErrors
and V eryLongErrors counters is as follows: VeryLongErrors counts frames that are 2*maxframesize,
dependent upon where maxframesize is set. If maxframesize sets greater than half of the available count in
RxOc te ts Bad ( 2^ 14- 1), V er y Lo ngEr ro rs is ne ve r i nc reme nt ed, but LongE rr ors is in cr em ent ed . Thi s is du e t o
a limitation in the counter size, which means that an accurate count will not occur in the RxOctetsBAD
cou n ter if the fram e is lar ger tha n 2^ 14 - 1.
3. This registe r is relevant only when config ured for copper op eration.
4. This register is relevant only when configured for fiber operation (line side interface is SerDes).
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8.4.3 MAC TX Statistics Register Overview
The M A C TX Stat istics registers contain all the MAC t ran sm it statistic counte r s and ar e cleared
when read. The software must poll these registers to accumulate values and to ensure that the
counters do not wrap. The 32-bi t counters wrap after ap proximately 30 seconds.
Table 94 covers all four MAC ports TX statistics. Port_In dex is the port number (0, 1, 2, or 3).
Table 94. MAC TX Stati stics ($ Port_Index +0x40 – +0x58 ) (Sheet 1 of 4)
Name Description Address Type1Default
OctetsTransmittedOK
Counts the bytes transmitted in all legal
frames. The count includes all bytes
from the dest ination MAC address to
and including the CRC. The initial
preamble and SFD bytes are not
counted. Any initial collided
transmission attempts before a
successful fr ame transmission do not
add to this counter.
Port_Index +
0x40 R 0x00000000
OctetsTransmittedBad
Count s the bytes transmitted in all bad
frames. The count includes all bytes
from the dest ination MAC address to
and including the CRC. The initial
preamble and SFD bytes are not
counted.
Late collision counted: The count is
close to the actual number of bytes
transmitted before the frame is
discarded.
Excessive collision counted: The count
is close to the actual number of bytes
transmitted before the frame is
discarded.
TX under-run counted: The count is
ex pect ed to mat c h the n umb er of b yt es
actually transmitted before the frame is
discarded.
TX CRC error counted: All bytes not
sent with success are counted by this
counter.
An y ini ti al co ll id ed trans m is si on
attempts befo re a successful fram e
transmission do not add to this counter.
Port_Index +
0x41 R 0x00000000
TxUCPkts Th e tot a l num b er of un ic as t pac ke ts
transm itted ( excluding bad pa ckets). Port_Index +
0x42 R 0x00000000
TxMCPkts
Th e tota l num b er of mu ltic as t pac ke ts
transm itted ( excluding bad pa ckets).
NOTE: This count includes pause
control packets, which are also
cou nte d in the
Tx Pa useF r am e s C ou n te r.
Thus, these type s of packets
are counted twice. Take care
when summing register counts
for reporting MIB information.
Port_Index +
0x43 R 0x00000000
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
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TxBCPkts Th e total number of broadcast packets
tran s mitted (ex c l ud in g ba d pac kets). Por t _Ind ex +
0x44 R 0x00000000
TxPkts64Octets
The total number of packets
transmitted (including bad packets) that
were 64 octets in length. Incremented
for tagged packets with a length of 64
byt e s, in clud ing tag fi e ld .
Por t_I nd ex +
0x45 R 0x00000000
Txpkts65to127Octets
The total number of packets
transmitted (including bad packets) that
were 65-127 octets in length.
Incremented for tagged packets with a
length of 65 -127 by te s, in cl udin g ta g
field.
Por t_I nd ex +
0x46 R 0x00000000
Txpkts128to255Octets
The total number of packets
transmitted (including bad packets) that
were 128-255 octets in length.
Incremented for tagged packets with a
length of 128-255 bytes, includin g tag
field.
Por t_I nd ex +
0x47 R 0x00000000
Txpkts256to511Octets
The total number of packets
transmitted (including bad packets) that
were 256- 511 oc tets in lengt h.
Incremented for tagged packets with a
length of 256-511 bytes, includ ing tag
field.
Por t_I nd ex +
0x48 R 0x00000000
Txpkts512to1023Octets
The total number of packets
transmitted (including bad packets) that
were 512-1023 octets in length.
Incremented for tagged packets with a
length of 512-1023 bytes, including tag
field.
Por t_I nd ex +
0x49 R 0x00000000
Txpkts1024to1518Octets
The total number of packets
transmitted (including bad packets) that
were 1024-1518 octets in length.
Incremented for tagged packet with a
length be t ween 1024 - 15 2 2, in cl udin g
the tag.
Por t_I nd ex +
0x4A R 0x00000000
Txpkts1519toMaxOctets
The total number of packets
transmitted (including bad packets) that
were greater than 1518 octets in
length. Incremented for tagged packet
with a length between 1523 - max fame
size, including the tag.
Por t_I nd ex +
0x4B R 0x00000000
TxDeferred
Number of times the initial transmission
attempt of a frame is postponed due to
another frame already being
transmitted on the Ethernet network.
TxTotalCollisions.
NOTE: NA - half-duplex only
Por t_I nd ex +
0x4C R 0x00000000
TxTotalCollisions Sum of all collision events.
NOTE: NA - half-duplex only P ort _I ndex +
0x4D R 0x00000000
Tab le 94. MAC TX Statisti cs ($ Port_Index +0 x40 – +0x58) (Sheet 2 of 4)
Name Description Address Type1Default
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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TxSingleCollisions
A count of successfully transmi tted
frame s on a par ticul ar interface wh ere
the transmission is inhibited by exactly
one coll is ion. A fram e t ha t is counte d
by an insta nc e of thi s obje ct is als o
counted by the corresponding instance
of either the UnicastPkts,
MulticastPkts, or BroadcastPkts, and is
not counted by the corresponding
instance of the MultipleCollisionFrames
object.
NOTE: NA - half-duplex only
Port_Index +
0x4E R 0x00000000
TxMultipleCollisions
A count of successfully transmi tted
frame s on a par ticul ar interface for
which transmission is inhibited by more
than one collision. A frame that is
counted by an instance of this object is
also counted by the corr espondi ng
instance of either the UnicastPkts,
MulticastPkts, or BroadcastPkts, and is
not counted by the corresponding
instance of the SingleCollisionFrames
object.
NOTE: NA - half-duplex only
Port_Index +
0x4F R 0x00000000
TxLateCollisions
The number of times a collision is
detected on a particular interface later
than 512 bit-times into the transmission
of a packet. Such frame are terminated
and disc arde d.
NOTE: NA - half-duplex only
Port_Index +
0x50 R 0x00000000
TxExcessiveCollisionErrors
A count of frames, which collides 16
ti me s an d is th en dis ca r de d by the
MAC. Not effecting xMultipleCollisions
NOTE: NA - half-duplex only
Port_Index +
0x51 R 0x00000000
TxExcessiveDeferralErrors
Num b er of ti m e s fr am e tra ns m is sion i s
postponed more than 2*MaxFrameSize
because of another fr ame alr eady
being tr a ns mi tt e d on the E th er n et
network. This causes the MAC to
di sc a r d the fra m e.
NOTE: NA - half-duplex only
Port_Index +
0x52 R 0x00000000
TxExcessiveLengthDrop
Frame transmissions aborted by the
MAC because the frame is longer than
max im um fram e siz e. Thes e fr am e s
are truncated by the MAC when the
maximum frame size violation is
detected by the MAC.
Port_Index +
0x53 R 0x00000000
TxUnderrun
Internal TX error that causes the MAC
to end the transmission before the end
of the frame because the MAC did not
get the ne eded data in time for
transmission. The frames are lost and
a fragment or a CRC error is
transmitted.
Port_Index +
0x54 R 0x00000000
Table 94. MAC TX Stati stics ($ Port_Index +0x40 – +0x58 ) (Sheet 3 of 4)
Name Description Address Type1Default
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
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8.4.4 PHY Autoscan Registers
Note: These re gis ter hold the current value s of the PHY regi sters only when Autos ca n (see Section 5.5.8,
“Autoscan Operat ion” on page 103) is ena bled and the IXF1104 MAC is confi gured in copp er
mode. These registe rs are not applicable in fiber mode.
TxTagged Numb er of OK fr ames with VLAN tag.
(Type field = 0x 8100). Por t_I nd ex +
0x55 R 0x00000000
TxCRCError Number of frames transmitted with a
legal size but with the wrong CRC field
(also called FCS field) .
Por t_I nd ex +
0x56 R 0x00000000
TxPauseFrames Number of pause MAC frames
transmitted. P ort _Ind ex +
0x57 R 0x00000000
TxFlowControlCollisions
Send
Intentionally generates collisions to
curb reception of incoming traffic due to
insufficient memory available for
additional frames. The port must be in
half-duplex mode with flow control
enabled.
NOTE: To receiv e a cor re ct s tat i stic , a
last frame may have to be
trans mi tte d after the last flo w
control collisions send.
NOTE: NA - half-duplex only
Por t_I nd ex +
0x58 R 0x00000000
Tab le 95. PHY Con trol ($ Port Index + 0x60) (Sheet 1 of 2)
Bit Name Description Type1Default
0x00000010
001000
31:16 Reserved Reserved RO 0x0000
15 Reset
PHY Soft Reset. Resets the PHY registers to their
default value.
This register bit self-clears after the reset is
complete.
0 = Normal Operatio n
1 = PHY reset
RO 0
14 Loopback 0 = Disable loopback mode
1 = Enable loopback mode RO 0
13 Speed Selection
0.6 (Speed< 1> 0.13 (Speed<0>)
00 =1 0 Mb ps
01 =1 00 Mbps
10 =1000 Mbps (manual mode not allowed)
11 = Reserved
RO 02
1. RO = Read Only; RR = Clear on Read; W = Wri te; R/W = Read/Write
2. This register is ignored if auto-negotiation is enabled.
Tab le 94. MAC TX Statisti cs ($ Port_Index +0 x40 – +0x58) (Sheet 4 of 4)
Name Description Address Type1Default
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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12 Auto-Negotiation
Enable
0 = Disable auto-negotiation process
1 = Enable auto-negotiation process
This register bit must be enable d for
1000BASE-T operation.
RO 1
11 Power-Down 0 = Normal operation
1 = Power-down RO 0
10 Isolate 0 =
1 = Electrically isolate PHY from GMII RO 0
9Restart
Auto-Negotiation 0 = Normal operation
1 = Restart auto-negotiation process RO 0
8 D up le x Mo de 0 = Half-duplex mode
1 = Full-duplex m ode RO 12
7 Collis io n Tes t
0 = Disable COL signal test
1 = Enable COL signal test
This register bit is ignored unless loopback is
enabled (Register bit 0.14 = 1)
RO 0
6Sp eed Selec tion
1000 Mbps
0.6 (Speed<1>) 0.13 (Speed<0>)
00 = 10 Mbps
01 = 100 Mbps
10 = 1000 Mbps (manual mode now allowed)
11 = Reserved
RO 02
5:0 Reserved Reserved RO 0
Table 96. PHY Status ($ Port Index + 0x61) (Sheet 1 of 2)
Bit Name Description Type1Default
0x001111001
00001001
31:16 Reserved Reserved RO 0
15 100BASE-T4 0 = PHY not a ble to operate in 100BASE -T4
1 = PHY able to operate in 100BASE-T4 RO 0
14 100BASE-X
Full-Duplex
0 = PHY not able to operate in 100BASE-X in full-
duplex mode
1 = PHY able to operate in 100BASE-X in full-
duplex mode RO 1
13 100BASE-X
Half-Duplex
0 = PHY not a ble to operate in 100BASE -X i n
half-duplex mode
1 = PHY able to operate in 100BASE-X in half-
duplex mode RO 1
12 10 Mbps
Full-Duplex
0 = PHY not able to operate in 10 Mbps in full-
duplex mode
1 = PHY able to operate in 10 Mbps in full-duplex
mode RO 1
1. R = Read O nly; RR = Clear on Read; W = Write; R/W = Read/Write
Table 95. PHY Control ($ Port Index + 0x60) (Sheet 2 of 2)
Bit Name Description Type1Default
1. RO = Read Only; RR = Clear on Read; W = Write ; R/W = Read/Write
2. This register is igno red if auto-negoti ation i s enabled.
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11 10 Mbps
Half-Duplex
0 = PHY not able to operate in 10 Mbps in half-
duplex mode
1 = PHY able to operate in 10 Mbps in half-
duplex mode RO 1
10 100BASE-T2
Full-Duplex
0 = PHY not able to operate in 10BASE-T2 in full-
duplex mode (not supported)
1 = PHY able to operate in 100BASE-T2 in full-
duplex mode RO 0
9100BASE-T2
Half-Duplex
0 = PHY not able to operate in 100BASE-T2 in
half-duplex mode
1 = PHY able to operate in 100BASE-T2 in half-
duplex mode RO 0
8 Extended Status 0 = No exte nded status informat ion i n Register 15
1 = Extended sta tus inform ation i n Reg ister 15 RO 1
7 Reserved Reserved RO 0
6MF Preamble
Suppression
0 = PHY will not accept management frames with
preamble suppressed
1 = PHY will accept ma nagement f rames with
preamble suppressed
RO 0
5 Reserved Reserved RO 0
4 Remote Fault 0 =
1 = Rem ote fau lt cond ition d etecte d RO 0
3Auto-Negotiation
Ability 0 =
1 = PHY is able to perform auto-negotiation RO 1
2Link Status 0 = Link is down
1 = Link is up RO 0
1 Jabber D etect 0 = Jabber condition not detected
1 = Jabber condition detected RO 0
0 Extended Capability 0 = No extended register capabilities
1 = Extended register capabilitie s RO 1
Tab le 97. PHY Id entificatio n 1 ($ Port Index + 0x62)
Bit Name Description Type1Default
0x00013
31:16 Reserved Reserved RO 0
15:0 PHY I D Num ber The PHY identifier is composed of register bits
18.3 of the OUI (Organizationally Unique
Identifier) RO h0013
1. RO = Read Only; RR = Clear on Read; W = Wri te; R/W = Read/Write
Tab le 96. PHY Status ($ P o rt Index + 0x61) (Sheet 2 of 2)
Bit Name Description Type1Default
1. R = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
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Table 98. PHY Identification 2 ($ Port Index + 0x63)
Bit Name Description Type1Default
0x001111001
00000000
31:16 Reserved Reserved RO 0
15:10 PHY ID Number The PHY ident ifier is composed of register bit s
24:19 of the OUI (Organ izati onally Un ique
Identifier) RO 011110
9:4 Manufacturer’s Model S ix bit s containing th e manufa cturer’s p art number R O 01000 0
3:0 Manufacturer’s
Revision Number Four bits containing the manufacturer’s revision
number RO 0000
1. RO = Read Only; RR = Clear on Read; W = Write ; R/W = Read/Write
Table 99. Auto -Nego tiation Advertisement ($ Port Index + 0x64) (Sheet 1 of 2)
Bit Name Description Type1Default
0x00000100
111100001
31:16 Reserved Reserved RO 0
15 Next Page 0 =
1 = Manual co ntrol of Next Page (software) RO 0
14 Reserved Reserved RO 0
13 Remote Fault 0 = No remote fault
1 = Remote fault RO 0
12 Reserved Reserved RO 0
11 ASM_DIR
Advertise Asymmetric Pause Direction register bit.
This register bit is used in conjunction with Pause
(Register bit 4.10)
0 = Link partner is not capable of asymmetric
pause
1 = Link partner is capable of asymmetric pause
RO 1
10 Pause Advertise to link partner that Pause operation is
desire d (IEEE 802.3x Stan dard) RO 0
9 100BASE-T4
0 = 100BASE-T4 capability is not available
1 = 100BASE-T4 capability is available
The IXF1 104 MAC does not support 100BASE-T4,
but allows this register bit to be set to advertise in
auto-negotiation sequence for 100BASE-T 4
operation. If this capability is desired, an external
100BASE-T4 transceiver can be switched in.
RO 0
8100BASE-TX
Full-Duplex
0 = DTE is not 100BASE-TX, full-duplex mode
capable
1 = DTE is 100BASE-TX, full-duplex mode
capable RO 1
7100BASE-TX
Half-Duplex
0 = DTE is not 100BASE-TX, half-duplex mode
capable
1 = DTE is 100BASE-TX, half-duplex mode
capable RO 1
1. RO = Read Only; RR = Clear on Read; W = Write ; R/W = Read/Write
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610BASE-T
Full-Duplex 0 = DTE is not 1 0BASE-T, full-duple x m ode
capable
1 = DTE is 10BASE-T, full-duplex mode capable RO 1
510BASE-T
Half-Duplex 0 = DTE is not 10BASE-T, half-duplex mode
capable
1 = DTE is 10BASE-T, half-duplex mode capable RO 1
4:0 Selector Field,
S[4:0]
00001 =IE EE 8 02.3
00010 =IEEE 802.9 ISLAN-16T
00000 =Reserved for future auto-negotiation
development
11111 =Reserved for future auto-negotiation
development
Unspec ified or reserved combinations shou ld not
be tran s mitte d
S etting this f ie ld to a valu e oth er tha n 0000 1 w ill
most likely ca u se auto -negotiation to fail
RO 00001
Table 100. Auto-Negotiation Link Partner Base Page Abilit y ($ Port Index + 0x65) (Sheet 1 of 2)
Bit Name Description Type1Default
0x0---
01001111000
01
31:16 Reserved Reserved RO 0
15 Next Page
0 = Link partner has no ability to send multiple
pages
1 = Link partner has the abil ity to send mul tiple
pages RO NA
14 Acknowledge
0 = Link p a rtn er ha s no t r ecei ve d Li nk Co de W or d
from the IXF1104 MAC
1 = Link partner has received Link Code Word
from the IXF1104 MAC RO NA
13 Remote Fault 0 = No remote fault
1 = Rem ote fau lt RO NA
12 Reserved Reserved RO 0
11 ASM_DIR
Adverti se Asymm etric Pause Dire ction Reg ister
bit. This register bit is used in conjunction with
Pause (Registe r bit 4.10)
0 = Link partner is not capable of asymmetric
pause
1 = Link partner is capable of asymmetric pause
RO 1
10 Lin k Par tne r Paus e Link partner wants to utilize Pause Operation as
defined i n IEE E 802.3x S tandard RO 0
9 1000BASE-T4 0 = Link partner is not 100BASE-T4 capable
1 = Link partner is 100BASE-T4 capable RO 0
1. RO = Read Only; RR = Clear on Read; W = Wri te; R/W = Read/Write
Tab le 99. Auto-Ne gotiation Advertisem ent ($ Port Index + 0x64) (Sheet 2 of 2)
Bit Name Description Type1Default
1. RO = Read Only; RR = Clear on Read; W = Wri te; R/W = Read/Write
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8100BASE-TX
Full-Duplex
0 = Link partner is not 100BASE-TX, full-duplex
mode capable
1 = Link partner is 100BASE-TX, full-duplex
mode capable RO 1
7100BASE-TX
Half-Duplex
0 = Link partner is not 100BASE-TX, half-duplex
mode capable
1 = Link p artner is 100BASE-TX, half-duplex
mode capable RO 1
610BASE-T
Full-Duplex
0 = Link partn er is not 10BASE -T, ful l-d uplex
mode capable
1 = Link partner is 10BASE-T, full-duplex mode
capable RO 1
510BASE-T
Half-Duplex
0 = Link partner is not 10BASE-T, half-duplex
mode capable
1 = Link partner is 10BASE-T, half-duplex mode
capable RO 1
4:0 Selector Field, S[4:0]
00001 =IEEE 802 .3
00010 =I EEE 802.9 I SLAN-16T
00000 =Reserved for future auto-negotiation
development
11111 =Reserved for future auto-negotiation
development
Unspecified o r r eserv ed com binat ions should not
be transmitted
Setting this field to a value other than 00001 will
mos t lik ely ca us e au to-n ego tia tio n to fa il
RO 00001
Table 101. Auto-Negotiation Expansion ($ Port Index + 0x66) (Sheet 1 of 2)
Bit Name Description Type1Default
0x0000000
31:6 Reserved Reserved RO 0
5 Base Page
This register bit indicates the status of the auto-
negotiation variable, base page. It flags
synchronization with the auto-negotiation state
diagram allowing detection of interrupted links.
This register bit i s only used if Re gister bit 16.1
(alternate Next Page feature) is set.
0 = base_page = false
1 = base_page = true
RO 0
4Parallel Detection
Fault 0 = Paralle l detection fault has not occurred
1 = Pa ralle l detection faul t has occurred RO 0
3Link Partner Next Page
Able 0 = Link partner is not Next Page able
1 = Link partner is Next Page able RO 0
1. RO = Read Only; RR = Clear on Read; W = Write ; R/W = Read/Write
Table 100. Aut o-Negotiation Link Partner Base Page Ability ($ Port Index + 0x65) (Sheet 2 of 2)
Bit Name Description Type1Default
1. RO = Read Only; RR = Clear on Read; W = Write ; R/W = Read/Write
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2 Next Page Able 0 = Local device is not Next Page able
1 = Local device is Next Page able RO 0
1 Page Received
Indicates that a new page has been received and
the received code word has been loaded into
Register 5 (base pages) or Register 8 (next pages)
as s pecifi ed in the EEE 802.3 Standard.
This bit cl ears on Read.
RO 0
0Link Partner Auto-
Negotiation Able 0 = Li nk partner i s not aut o-negotiation able
1 = Link partner is auto-negotia tion ab le RO 0
Tab le 102 . Auto-Negotiation Next Page Transmi t ($ Port Index + 0x67)
Bit Name Description Type1Default
0x0000000
31:16 Reserved Reserved RO 0
15 Next Page (NP) 0 = Last page
1 = Additional Next Pages follow RO 0
14 Reserved Reserved RO 0
13 Me ss age Page (M P ) 0 = Unformatted page
1 = Message page RO 0
12 Ack no w le dg e 2 0 = Cannot c omply with message
1 = Com plies with message RO 0
11 Toggle (T) 0 = Previous value of the transmitted Link Code
Word was logic one
1 = Previous value of the transmitted Link Code
Word was logic zero RO 0
10:0 Message/Unformatted
Code Field 11- bit message code field
See IEEE 802.3 Annex 28C RO 0
1. RO = Read Only; RR = Clear on Read; W = Wri te; R/W = Read/Write
Tab le 101 . Auto-Negotiation Expansion ($ Port Index + 0x66) (Continued) (S heet 2 of 2)
Bit Name Description Type1Default
1. RO = Read Only; RR = Clear on Read; W = Wri te; R/W = Read/Write
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8.4.5 Global Status and Configuration Register Overview
Table 103 through Ta ble 1 12 “J TAG ID ($0x50C)” on pag e 192 provid e an ov ervi ew for th e Gl obal
Control and Status Registers.
Table 103. Port Enab le ($0x500)
Bit Name Description Type*Default
Register Description: A control register for each port in the IXF1104 MAC. Port ID = bit
position in the register. To make a port active, the bit must be set High. For example, Port 2
active implies a register value of 0000.0100. Setting the bit to 0 de-asserts the enable. The
default state for this register is for all four ports to be disabled. 0x00000000
31:4 Reserved Reserved RO 0x0000000
3 Port 3 Enable Port 3
0 = Disable
1 = Enable R/W 0
2 Port 2 Enable Port 2
0 = Disable
1 = Enable R/W 0
1 Port 1 Enable Port 1
0 = Disable
1 = Enable R/W 0
0 Port 0 Enable Port 0
0 = Disable
1 = Enable R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
Table 104. Interface Mode ($0x501)
Bit Name Description Type1Default
Register Description: If_Mode – Four bits of this register determines the PHY interface
mode.
0 = Fiber (SerDes/OMI interface)
1 = Copper (GMII or RGMII interface)
Changes to the data setting of this register must be made in conjunction with the “Clock and
Interface Mode Change Enable Ports 0 - 3 ($0x794)" to ensure a safe transition to a new
oper a tion al mo de (s ee S ection 6.1, “ Change Port Mode In itial ization Sequence” on page 130).
Th e E nabl e cl oc k mode cha ng e bi t has to be set ba ck to 1 af ter the co nf igur a tio n ch ange t ake s
effect.
0x00000000
31:4 Reserved Reserved RO 0x0000000
3 Port 3 Interface Mode 0 = Fiber mode
1 = Copper mode R/W 0
2 Port 2 Interface Mode 0 = Fiber mode
1 = Copper mode R/W 0
1 Port 1 Interface Mode 0 = Fiber mode
1 = Copper mode R/W 0
0 Port 0 Interface Mode 0 = Fiber mode
1 = Copper mode R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
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Tab le 105 . Link LED Enable ($0x50 2)
Bit Name Description Type1Default
Register D escrip t ion : Per port bit should be set upon detection of link to enable proper
operation of the link LE Ds. 0x00000000
31:4 Reserved Reserved R/W 0x00000
3 Link LED Enable Por t 3 Port 3 link
0 = No link
1 = Link R/W 0
2 Link LED Enable Por t 2 Port 2 link
0 = No link
1 = Link R/W 0
1 Link LED Enable Por t 1 Port 1 link
0 = No link
1 = Link R/W 0
0 Link LED Enable Por t 0 Port 0 link
0 = No link
1 = Link R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Tab le 106 . MAC Soft Reset ($0 x505)
Bit Name Description Type1Default
Register D escrip t ion : Per-port software-activated reset of the MAC core. 0x00000000
31:4 Reserved Reserved R/W 0x00000
3 Soft ware Reset MAC 3 Port 3
0 = Res et inactive
1 = Ena ble R/W 0
2 Soft ware Reset MAC 2 Port 2
0 = Res et inactive
1 = Ena ble R/W 0
1 Soft ware Reset MAC 1 Port 1
0 = Res et inactive
1 = Ena ble R/W 0
0 Soft ware Reset MAC 0 Port 0
0 = Res et inactive
1 = Ena ble R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Table 107. MDIO Soft Reset ($0x506)
Bit Name Description Type1Default
Register Description: Software- activ ated reset of the MDIO module. 0x0000 0000
31:1 Reserved Reserved RO 0x00000000
0 Software MDIO Reset 0 = Reset inactive
1 = Reset active R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
Table 108. CPU Interface ($0x508)
Bit Name Description Type1Default
Register Description: CPU Interface Endian select. Allows the user to select the Endian of
the CPU interface to allow for various CPUs to be connected to the IXF1104 MAC. 0x00000000
31:25 Reserved Reserved RO 0x00
24 CPU Endian
Reserved in Little Endian
Valid in Big endian
0 = Little Endian
1 = Big Endian
R/W 0
23:1 Reserved Reserved RO 0x000000
0 CPU Endian Control
Reserved in Big Endian
Valid in Little Endian
0 = Little Endian
1 = Big Endian
R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
NOTE: S ince the Endian ess of the bus is unknow n whe n writing to th is register, write 0x0100 0001 to s et the
bit and 0x0 to clear it.
Table 109. LED Control ($ 0x509)
Bit Name Description Type1Default
Register Description: Global select ion of LED m ode. 0x000000 00
31:2 Reserved Reserved RO 0x00000000
1 LED Enable 0 = Disable LED Block
1 = Enable LED Block R/W 0
0LED Control
0 = Enable LED Mode 0 for use with SGS
T ho m so n M545 0 LED dri ve r (De faul t )
1 = LED Mode 1 for use with Standard Octal Shift
register R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
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Tab le 110. LED Flash Rate ($0x50A)
Bit Name Description Type1Default
Register D escrip t ion : Global selection of LED flash rate. 0x00000000
31:3 Reserved Reserved RO 0x00000000
2:0 LED Flash Rate
Control
000 =100 ms flash ra te
001 =200 ms flash ra te
010 =300 ms flash ra te
011 = 400 ms flash rate
100 = 500 ms flash rate
101 = Reserv ed
110 = Reserv ed
111 = Reserved
R/W 000
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Tab le 111. LED Fault Disable ($0x50B)
Bit Name Description Type1Default
Register D escrip t ion : Per-port fault disable. Disables the LED flashing for local or remote
faults. 0x00000000
31:4 Reserved Reserved RO 0x0000000
3LED Port 3 Fault
Control
Port 3
0 = Faul t enabled
1 = Faul t disab led R/W 0
2LED Port 2 Fault
Control
Port 2
0 = Faul t enabled
1 = Faul t disab led R/W 0
1LED Port 1 Fault
Control
Port 1
0 = Faul t enabled
1 = Faul t disab led R/W 0
0LED Port 0 Fault
Control
Port 0
0 = Faul t enabled
1 = Faul t disab led R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Table 112. JTAG ID ($0x50C)
Bit Name Description Type1Default
Register Description: T he value of th is register fol lows the same sch eme as the device
identification register found in the IEEE 1149.1 specification. The upper four bits correspond to
s ilicon steppi ng. The next 16 bits store a Part ID Number. The next 11 bits contai n a JEDEC
manufacturer ID. Bit zero = 1 if the chip is the first in a stack. The encoding scheme used for
the Product ID field is implementation-dependent.
0x10450013
31:28 Version Version RO 00012
27:12 Part ID Part ID RO 0000010001
010000
11:8 JEDEC Continua tion
Characters JEDEC Continuation Characters RO 0000
7:1 JEDEC ID JEDEC ID RO 0001001
0Fixed Fixed RO 1
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
2. These bits vary with stepping.
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8.4.6 RX FIFO Register Overview
Table 113 thro ugh Table 131 provide an overview of the RX FIFO regis ters, which include the R X
FIFO High and Low watermarks.
Tab le 113. RX FI FO High Water m ark Port 0 ($0x580)
Bit Name Description Type1Default
Register D escrip t ion : The default value of 0x0E6 represents 230 eight-byte locations. This
equa te s to 18 40 by te s of da t a. A un it en try in th is re gi st er e qu ates to 8 byte s of da ta . W hen t he
amount of data stored in the RX FIFO exceeds the high watermark, flow control is
auto mati c ally initiated within the MA C to avoid an overflo w condition. 0x0E6
31:12 Reserved Reserved RO 0x00000
11: 0 RX FIFO High
W atermark Port 0
The high water mark value.
NOTE: Must be greater than the RX FIFO Low
Watermark and R X FI FO tr ansfer threshold. R/W 0x0E6
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Tab le 114. RX FIFO High Waterm ark Port 1 ($0x581)
Bit Name Description Type1Default
Register D escrip t ion : The default value of 0x0E6 represents 230 eight-byte locations. This
equa te s to 18 40 by te s of da t a. A un it en try in th is re gi st er e qu ates to 8 byte s of da ta . W hen t he
amount of data stored in the RX FIFO exceeds the high watermark, flow control is
auto mati c ally initiated within the MA C to avoid an overflo w condition. 0x0E6
31:12 Reserved Reserved RO 0x00000
11: 0 RX FIFO High
W atermark Port 1
The high water mark value.
NOTE: Must be greater than the RX FIFO Low
Watermark and R X FI FO tr ansfer threshold. R/W 0x0E6
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Tab le 115. RX FIFO High Waterm ark Port 2 ($0x582)
Bit Name Description Type1Default
Register D escrip t ion : The default value of 0x0E6 represents 230 eight-byte locations. This
equa te s to 18 40 by te s of da t a. A un it en try in th is re gi st er e qu ates to 8 byte s of da ta . W hen t he
amount of data stored in the RX FIFO exceeds the high watermark, flow control is
auto mati c ally initiated within the MA C to avoid an overflo w condition.
0x0E6
31:12 Reserved Reserved RO 0x00000
11: 0 RX FIFO High
W atermark Port 2
The high water mark value.
NOTE: Must be greater than the RX FIFO Low
Watermark and R X FI FO tr ansfer threshold. R/W 0x0E6
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Table 116. RX FIFO High Watermark P ort 3 ($0x583)
Bit Name Description Type1Default
Register Description: The default value of 0x0E6 represents 230 eight-byte locations. This
equ at e s to 18 40 byt es of da ta. A unit ent ry i n thi s r egi st er eq ua tes t o 8 byt es of data. Wh en the
amount of data stored in the RX FIFO exceeds the high watermark, flow control is
automatically initiated within the MAC to avoid an overflow condition. 0x0E6
31:12 Reserved Reserved RO 0x00000
11: 0 RX FIFO High
Waterma rk Port 3
The high wat er mark value.
NOTE: Must be greater than the RX FIFO Low
Watermark and RX FIFO transfer threshold. R/W 0x0E6
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
Table 117. RX FIFO Low Waterm ark Port 0 ($0x58A)
Bit Name Description Type1Default
Register Description: The default value of 0x072 represents 114 eight-byte locations. This
equates to 912 bytes of dat a. A unit entry in this register equates to 8 bytes of data. When the
amount of data stored in the RX FIFO falls below the Low Watermark, flow control is
automatically de-asserted within the MAC to allow more line-side data to be captured by the
RX FIFO.
0x072
31:12 Reserved Reserved RO 0x00000
11: 0 RX FIFO Low
Waterma rk Port 0 The High W atermark value
NOTE: S hould never be greater or equal to the
High Watermark. R/W 0x072
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
Table 118. RX FIFO Low Watermark Port 1 ($0x58B)
Bit Name Description Type1Default
Register Description: The default value of 0x072 represents 114 eight-byte locations. This
equates to 912 bytes of dat a. A unit entry in this register equates to 8 bytes of data. When the
amount of data stored in the RX FIFO falls below the Low Watermark, flow control is
automatically de-asserted within the MAC to allow more line-side data to be captured by the
RX FIFO.
0x072
31:12 Reserved Reserved RO 0x00000
11: 0 RX FIFO Low
Waterma rk Port 1
The High Watermark value
NOTE: S hould never be greater or equal to the
High Watermark. R/W 0x072
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
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2
Table 119. RX FIFO Low Watermark Port 2 ($0x58C)
Bit Name Description Type1Default
Register D escrip t ion : The default value of 0x072 represents 114 eight-byte locations. This
equates to 912 bytes of data. A unit entry in this register equates to 8 bytes of data. When the
amount of data stored in the RX FIFO falls below the Low Watermark, flow control is
automati cally de-asserted within the MAC to allo w more line-side dat a to be captured by the
RX FIFO.
0x072
31:12 Reserved Reserved RO 0x00000
11: 0 RX FIFO Low
W atermark Port 2 The High Watermark value
NOTE: Shou ld never be gre ater or equal to the
High Watermark. R/W 0x072
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Tab le 120 . RX FIFO Low Watermark Port 3 ($0x58D)
Bit Name Description Type1Default
Register D escrip t ion : The default value of 0x072 represents 114 eight-byte locations. This
equates to 912 bytes of data. A unit entry in this register equates to 8 bytes of data. When the
amount of data stored in the RX FIFO falls below the Low watermark, flow control is
automati cally de-asserted within the MAC to allo w more line-side dat a to be captured by the
RX FIFO.
0x072
31:12 Reserved Reserved RO 0x00000
11: 0 RX FIFO Low
W atermark Port 3
The High watermark value
NOTE: Shou ld never be gre ater or equal to the
High Watermark.
R/W 0x072
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Tab le 121 . RX FIFO Overflow F ram e Drop Counter Ports 0 - 3 ($0x594 – 0x597)
Name Description Address Type1Default
RX FIFO Overflow
Frame Drop
Counter on port 0
When RX FIFO on port 0 beco me s full or
reset, the number of frames lost/dropped on
this port are shown in this register. 0x594 R 0x00000000
RX FIFO Overflow
Frame Drop
Counter on port 1
When RX FIFO on port 1 beco me s full or
reset, the number of frames lost/dropped on
this port are shown in this register. 0x595 R 0x00000000
RX FIFO Overflow
Frame Drop
Counter on port 2
When RX FIFO on port 2 beco me s full or
reset, the number of frames lost/dropped on
this port are shown in this register. 0x596 R 0x00000000
RX FIFO Overflow
Frame Drop
Counter on port 3
When RX FIFO on port 3 beco me s full or
reset, the number of frames lost/dropped on
this port are shown in this register. 0x597 R 0x00000000
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
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Table 122. RX FIFO Port Reset ($0x59E)
Bit Name Description Type1Default
Register Description: The soft reset register for each port in the RX block. Port ID = bit
position in the register. To make the reset active, the bit must be set High. For example, reset
of port 1 implies register value = 0 000_0018. Setting the bit to 0 de-asserts th e reset. 0x00000000
31:4 Reserved Reserved RO 0x0000000
3Reset RX FIFO for
Port 3
Port 3
0 = De-assert reset
1 = Reset R/W 0
2Reset RX FIFO for
Port 2
Port 2
0 = De-assert reset
1 = Reset R/W 0
1Reset RX FIFO for
Port 1
Port 1
0 = De-assert reset
1 = Reset R/W 0
0Reset RX FIFO for
Port 0
Port 0
0 = De-assert reset
1 = Reset R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
Table 123. RX FIFO Errored Frame Drop Enable ($0x59F) (Sheet 1 of 2)
Bit Name Description Type1Default
Register Description: This register configures the dropping of error packets (DEBAD).
NOTE: Jumbo packets are not dropped. 0x00000000
31:4 Reserved Reserved RO 0x0000000
3RX FIFO Errored
Frame Drop Enable
Port 3
This bit is used in conjunction with MAC filter bits.
This all ows the user to select wh ether the e rrored
packet s are to be dr opped or not.
1 = Fram e Drop Enab le
0 = Frame Drop Disable
R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
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2RX FIFO Errored
Frame Drop Enable
Port 2
This bit i s used in conjunction with MAC filt er bits.
This allows the user to select whether the errored
packets are to be dropped or not.
1 = Frame Drop Enable
0 = Frame Drop Disable
R/W 0
1RX FIFO Errored
Frame Drop Enable
Port 1
This bit i s used in conjunction with MAC filt er bits.
This allows the user to select whether the errored
packets are to be dropped or not.
1 = Frame Drop Enable
0 = Frame Drop Disable
R/W 0
0RX FIFO Errored
Frame Drop Enable
Port 0
This bit i s used in conjunction with MAC filt er bits.
This allows the user to select whether the errored
packets are to be dropped or not.
1 = Frame Drop Enable
0 = Frame Drop Disable
R/W 0
Tab le 124 . RX FIFO Overflow Even t ($0x5A0)
Bit Name Description Type1Default
Register D escrip t ion : This register prov ides a status if a FIFO-full situation occurs (for
ex amp le, a FIFO ov er flo w ). The b it pos it ion equ al s the po r t numb er. T his r egi ste r is cl ear e d on
Read. 0x00000000
31:4 Reserved Reserved RO 0x0000000
3RX FIFO Overflow
Event on Port 3
Port 3
0 = FIFO ov erflow ev ent di d not occur
1 = FIFO overflow event occurred R0
2RX FIFO Overflow
Event on Port 2
Port 2
0 = FIFO ov erflow ev ent di d not occur
1 = FIFO overflow event occurred R0
1RX FIFO Overflow
Event on Port 1
Port 1
0 = FIFO ov erflow ev ent di d not occur
1 = FIFO overflow event occurred R0
0RX FIFO Overflow
Event on Port 0
Port 0
0 = FIFO ov erflow ev ent di d not occur
1 = FIFO overflow event occurred R0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Tab le 123 . RX FIFO Errore d Frame Drop Enab le ($0x59F) (Sheet 2 of 2)
Bit Name Description Type1Default
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Table 125. RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5) (Sheet 1 of 2)
Name Description Address Type Default
RX FIFO Errored
Frame Dr op Counter
on Port 0
This register counts all frames dropped from the
RX FIFO fo r port 0 by meet ing one of t he
following conditions:
•Frames are r emoved in con j un c ti o n
with the“RX FIFO Errored Frame
Drop Enable ($0x59F)” and the “RX
Packet Filter Control ($ Po rt_Index +
0x19)”.
•Fr am es ar e g reate r tha n the “Max
Frame Size (Addr: Port_Index +
0x0F)”.
This register is cleared on Read.
0x5A2 R 0x00000000
RX FIFO Errored
Frame Dr op Counter
on Port 1
This register counts all frames dropped from the
RX FIFO fo r port 1 by meet ing one of t he
following conditions:
•Frames are r emoved in con j un c ti o n
with the“RX FIFO Errored Frame
Drop Enable ($0x59F)” and the “RX
Packet Filter Control ($ Po rt_Index +
0x19)”.
•Fr am es ar e g reate r tha n the “Max
Frame Size (Addr: Port_Index +
0x0F)”.
This register is cleared on Read.
0x5A3 R 0x00000000
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RX FIFO Errored
Frame Drop Counter
on Port 2
This register counts all frames dropped from the
RX FIFO for port 2 by meeting one of the
following cond itions:
•Frames are removed in conjunction
with the“RX FIFO Errored Frame
Drop Enable ($0x59F)” and t h e “RX
Packet Filter Control ($ Port_Index +
0x19)”.
•Frames are greater than the “Max
Frame Size (Addr: Port_Index +
0x0F)”.
This register is cleared on Read.
0x5A4 R 0x00000000
RX FIFO Errored
Frame Drop Counter
on Port 3
This register counts all frames dropped from the
RX FIFO for port 3 by meeting one of the
following cond itions:
•Frames are removed in conjunction
with the“RX FIFO Errored Frame
Drop Enable ($0x59F)” and t h e “RX
Packet Filter Control ($ Port_Index +
0x19)”.
•Frames are greater than the “Max
Frame Size (Addr: Port_Index +
0x0F)”.
This register is cleared on Read.
0x5A5 R 0x00000000
1. RO = Read On ly, No clear on Read; R = Read, Cl ear on Read; W = Write only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
Tab le 126 . RX FIFO SPI3 L oo pback Enabl e for Ports 0 - 3 ($0x5B2)
Bit Name Description Type1Default
Register Description: Enables the TX SPI3 port to send packets into the RX_FIFO instead of
into the TX FIFO, creating a SPI3 loopback. 0x00000000
31:12 Reserved Reserved RO 0x00000
11 SPI3 loopback enable
for Port 3 0 = Disabled
1 = Enabl ed R/W 0x0
10 SPI3 loopback enable
for Port 2 0 = Disabled
1 = Enabl ed R/W 0x0
9SPI3 loopback enable
for Port 1 0 = Disabled
1 = Enabl ed R/W 0x0
8SPI3 loopback enable
for Port 0 0 = Disabled
1 = Enabl ed R/W 0x0
7:0 Reserved Write as 0, ignore on Read. R/W 0x00
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Tab le 125 . RX FIFO Errore d Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5) (Sheet 2 of 2)
Name Description Address Type Default
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Table 127. RX FIFO Padding and CRC Strip Enab le ($0x5B 3)
Bit Name Description Type1Default
Register Description: This control register enables to pre-pend every packet with two extra
bytes and also enables the CRC stripping of a pa cket. 0x00000000
31:8 Reserved Reserved RO 0x000000
7CRC S t ripping Enable
for Port 3
CRC stripping is enabled for Port 3.
0 = Disabled
1 = Enable d R/W 0
6CRC S t ripping Enable
for Port 2
CRC stripping is enabled for Port 2.
0 = Disabled
1 = Enabled R/W 0
5CRC S t ripping Enable
for Port 1
CRC stripping is enabled for Port 1.
0 = Disabled
1 = Enabled R/W 0
4CRC S t ripping Enable
for Port 0
CRC stripping is enabled for Port 0.
0 = Pre-pending Disabled
1 = Pre-pending Enabled R/W 0
3Pre-pending Enable2
Port 3
Enable s pre-pending of two byte s at the start of
every packet – Port 3.
0 = Disabled
1 = Enable d
R/W 0
2Pre-pending Enable2
Port 2
Enable s pre-pending of two byte s at the start of
every packet – Port 2.
0 = Disabled
1 = Enable d
R/W 0
1Pre-pending Enable2
Port 1
Enable s pre-pending of two byte s at the start of
every packet – Port 1.
0 = Disabled
1 = Enable d
R/W 0
0Pre-pending Enable2
Port 0
Enable s pre-pending of two byte s at the start of
every packet – Port 0.
0 = Disabled
1 = Enable d
R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
2. Pre-pending should not be enabled in loopback mode.
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Table 128. RX FIFO Transfer Threshold Port 0 ($0x5B8)
Bit Name Description Type Default
Register D escrip t ion : RX FIFO transfer threshold for port 0 in 8-byte location. 0x000000BE
31:12 Reserved Reserved RO 0x00000
11:0 RX FIFO Trans f er
Threshold - Port 0
RX FIFO transfer threshold for port 0. This m ust
be less than the RX FIFO High water mark.
User defina ble control register that sets the
threshold where a packet starts transitioning to the
SPI3 int er f ac e f rom the RX FIFO be fo r e the EOP
i s received. Pack ets received in the RX FIFO
below this threshold are treated as s tore and
forward.
NOTE: Do not program the RX FIFO transfer
threshold below a setting of 0xBE
(1520bytes).
R/W 0x0BE
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 129. RX FIFO Transfer Threshold Port 1 ($0x5B9)
Bit Name Description Type Default
Register D escrip t ion : RX FIFO transfer threshold for port 1in 8-byte location. 0x000000BE
31:12 Reserved Reserved RO 0x00000
11:0 RX FIFO T ransfer
Threshold - Port 1
RX FIFO transfer threshold for port 1. This must
be less than the RX FIFO High watermark.
User definable control register that sets the
thres hold where a packet starts tra nsitioning to
the SPI3 interface from the RX FIFO before the
EOP is received. Packets received in the RX
FIFO below this threshold are treated as store
and forward.
NOTE: Do not program the RX FIFO transfer
thres hold below a setting of 0x BE
(1520bytes).
R/W 0x0BE
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Table 130. RX FIFO Transfer Threshold Port 2 ($0x5BA)
Bit Name Description Type Default
Register Description: RX FIFO transfer threshold for port 2 in 8-byte location. 0x000000BE
31:12 Reserved Reserved RO 0x00000
11:0 RX FIFO Transfer
Threshold - Port 2
RX FIFO transfer threshold for port 2. This must be
less than the RX FIFO High water mark.
User definable control reg ister that sets the
thr esh ol d whe r e a pack et st art s t ran si tio ning to t he
SP I3 inte rface fr om the RX FI FO be fore th e EOP is
received. Packets received in the RX FIFO below
this threshold are treated as store and forward.
NOTE: Do not program the RX FIFO tr ansfer
thr eshold below a sett ing of 0x BE
(1520bytes).
R/W 0x0BE
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
Table 131. RX FIFO Transfer Threshold Port 3 ($0x5BB)
Bit Name Description Type Default
Register Description: RX FIFO transfer threshold for port 3 in 8-byte location. 0x000000BE
31:12 Reserved Reserved RO 0x00000
11:0 RX FIFO Transfer
Threshold - Port 3
RX FIFO transfer threshold for port 3. This must
be less than the RX FIFO High water mark.
User definable cont rol register th at sets the
thr eshol d wher e a pack et sta rts trans iti oning to th e
SPI3 inter face from the RX FIFO before the EOP
is received. Packets received in the RX FIFO
below this threshold are treated as store and
forward.
NOTE: Do not progra m the RX FIF O trans fe r
threshold below a setting of 0xBE
(1520bytes).
R/W 0x0BE
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
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8.4.7 TX FIFO Register Overview
Table 132 thro ugh Table 139 provide an overview of the TX FI F O registers, which include the TX
FIFO High and Low watermark.
Table 132. TX FIFO High Watermar k Ports 0 - 3 ($0x6 00 – 0x603)
Name Description Address Type1Default
TX FIFO High
W atermark Port 0
High watermark for TX FIFO Port 0. The
default value of 0x3E0 represents 992 8-byte
locations. This equates to 7936 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the am ount of dat a stored in the TX
FIFO exceeds the high wat erma rk, flow control
is automatically initiated on the SPI3 interface to
request th at the swi tch fabr ic stops data
trans fers to avoid an overflow condit ion.
0x600 R/W 0x000003E0
TX FIFO High
W atermark Port 1
High watermark for TX FIFO Port 1. The
default value of 0x3E0 represents 992 8-byte
locations. This equates to 7936 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the am ount of dat a stored in the TX
FIFO excee ds the high waterma rk, flow control
is automatically initiated on the SPI3 interface to
request th at the swi tch fabr ic stops data
trans fers to avoid an overflow condit ion.
0x601 R/W 0x000003E0
TX FIFO High
W atermark Port 2
High watermark for TX FIFO Port 2. The
default value of 0x3E0 represents 992 8-byte
locations. This equates to 7936 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the am ount of dat a stored in the TX
FIFO excee ds the high waterma rk, flow control
is automatically initiated on the SPI3 interface to
request th at the swi tch fabr ic stops data
trans fers to avoid an overflow condit ion.
0x602 R/W 0x000003E0
TX FIFO High
W atermark Port 3
High watermark for TX FIFO Port 3. The
default value of 0x3E0 represents 992 8-byte
locations. This equates to 7936 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the am ount of dat a stored in the TX
FIFO excee ds the high waterma rk, flow control
is automatically initiated on the SPI3 interface to
request th at the swi tch fabr ic stops data
trans fers to avoid an overflow condit ion.
0x603 R/W 0x000003E0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Table 133. TX FIFO Low Watermark Register Ports 0 - 3 ($0x60A – 0x60D)
Name Description Address Type1Default
TX FIFO Low
W atermark Port 0
Low watermark for TX FIFO Port 0. The
default value of 0x0D0 represents 208 8-byte
locations. This equates to 1664 bytes of data. A
unit entry in t his register equate s to 8 bytes of
data. When the amount of data stored in the TX
FIFO falls below the low watermark, flow control
is automatically de-asserted on the SPI3
interface to allow further data to be sent by the
switch fabric to the IXF1 1 04 MAC.
0x60A R/W 0x000000D0
TX FIFO Low
W atermark Port 1
Low watermark for TX FIFO Port 1. The
defau lt va lu e of 0x 0D0 repr e s en ts 208 8-byte
locations. This equates to 1664 bytes of data. A
unit entry in t his register equate s to 8 bytes of
data. When the amount of data stored in the TX
FIFO falls below the low watermark, flow control
is automatically de-asserted on the SPI3
interface to allow further data to be sent by the
switch fabric to the IXF1 1 04 MAC.
0x60B R/W 0x000000D0
TX FIFO Low
W atermark Port 2
Low watermark for TX FIFO Port 2. The
defau lt va lu e of 0x 0D0 repr e s en ts 208 8-byte
locations. This equates to 1664 bytes of data. A
unit entry in t his register equate s to 8 bytes of
data. When the amount of data stored in the TX
FIFO falls below the low watermark, flow control
is automatically de-asserted on the SPI3
interface to allow further data to be sent by the
switch fabric to the IXF1 1 04 MAC.
0x60C R/W 0x000000D0
TX FIFO Low
W atermark Port 3
Low watermark for TX FIFO Port 3. The
defau lt va lu e of 0x 0D0 repr e s en ts 208 8-byte
locations. This equates to 1664 bytes of data. A
unit entry in t his register equate s to 8 bytes of
data. When the amount of data stored in the TX
FIFO falls below the low watermark, flow control
is automatically de-asserted on the SPI3
interface to allow further data to be sent by the
switch fabric to the IXF1 1 04 MAC.
0x60D R/W 0x000000D0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
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Table 134. TX FIFO MAC Threshold Register Ports 0 - 3 ($0x614 – 0x617)
Name Description Address Type1Default
TX FIFO MAC
T hresh old Port 0
MAC threshold for TX FIFO Port 0. The
default value of 0x1BE re presen ts 446 8-byte
locations. This equates to 3568 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
FIFO reaches this threshold, data is forwarded
to the MAC core and line-side interfaces for
onward transmission. By setting the threshold to
an a ppr o pri ate va lu e, the us er c an co nf igur e the
TX FIFO to operate in a “cut-through” mode
rather than the default “store and forward”
operation mode.
0x614 R/W 0x000001BE
TX FIFO MAC
T hresh old Port 1
MAC threshold for TX FIFO Port 1. The
default value of 0x1BE re presen ts 446 8-byte
locations. This equates to 3568 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the am ount of dat a stored in the TX
FIFO reaches this threshold, data is forwarded
to the MAC core and line-side interfaces for
onward transmission. By setting the threshold to
an a ppr o pri ate va lu e, the us er c an co nf igur e the
TX FIFO to operate in a “cut-through” mode
rather than the default “store and forward”
operation mode.
0x615 R/W 0x000001BE
TX FIFO MAC
T hresh old Port 2
MAC threshold for TX FIFO Port 2. The
default value of 0x1BE re presen ts 446 8-byte
locations. This equates to 3568 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the am ount of dat a stored in the TX
FIFO reaches this threshold, data is forwarded
to the MAC core and line-side interfaces for
onward transmission. By setting the threshold to
an a ppr o pri ate va lu e, the us er c an co nf igur e the
TX FIFO to operate in a “cut-through” mode
rather than the default “store and forward”
operation mode.
0x616 R/W 0x000001BE
TX FIFO MAC
T hresh old Port 3
MAC threshold for TX FIFO Port 3. The
default value of 0x1BE re presen ts 446 8-byte
locations. This equates to 3568 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the am ount of dat a stored in the TX
FIFO reaches this threshold, data is forwarded
to the MAC core and line-side interfaces for
onward transmission. By setting the threshold to
an a ppr o pri ate va lu e, the us er c an co nf igur e the
TX FIFO to operate in a “cut-through” mode
rather than the default “store and forward”
operation mode.
0x617 R/W 0x000001BE
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Table 135. TX FIFO Overflow/Underflow/Out of Sequence Event ($0x61E) (Sheet 1 of 2)
Bit Name Description Type1Default
Register Description: TX FIFO Out of Sequence Event:
These register bits provide status information, and indicate if out-of-sequence data has been
received. The bit position equals the port number + 8. These bits are cleared on Read. 0x0
Register Description: TX FIFO Underflow Event:
This register provides a status that a FIFO Empty situation has occurred (for example, a FIFO
under-run). The bit position equals the port number + 4. This register is cleared on Read. 0x0
Register Description: TX FIFO Overflow Event:
This register provides a status that a FIFO full situation has occurred (for example, a FIFO
ov erflow ). The bit position equals the port number. Thi s regi ster is cleared on Read. 0x0
31:12 Reserved Reserved RO 0x00000
11 FOSE3 Port 3
0 = FIFO out of sequence event did not occur
1 = FIFO out of sequence event occurred R0
10 FOSE2 Port 2
0 = FIFO out of sequence event did not occur
1 = FIFO out of sequence event occurred R0
9 FOSE1 Port 1
0 = FIFO out of sequence event did not occur
1 = FIFO out of sequence event occurred R0
8 FOSE0 Port 0
0 = FIFO out of sequence event did not occur
1 = FIFO out of sequence event occurred R0
7FUE3 Port 3
0 = FIFO underflow event did n ot occur
1 = FIFO underflow event occurred R0
6FUE2 Port 2
0 = FIFO underflow event did n ot occur
1 = FIFO underflow event occurred R0
5FUE1 Port 1
0 = FIFO underflow event did n ot occur
1 = FIFO underflow event occurred R0
4FUE0 Port 0
0 = FIFO underflow event did n ot occur
1 = FIFO underflow event occurred R0
3FOE3 Port 3
0 = FIFO overflow event did not occur
1 = FIFO overflow event occurred R0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
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2FOE2 Port 2
0 = FIFO ov erflow ev ent di d not occur
1 = FIFO overflow event occurred R0
1FOE1 Port 1
0 = FIFO ov erflow ev ent di d not occur
1 = FIFO overflow event occurred R0
0FOE0 Port 0
0 = FIFO ov erflow ev ent di d not occur
1 = FIFO overflow event occurred R0
Tab le 136 . Loop RX Data to TX FIFO (Line-Side Loopback) P orts 0 - 3 ($0x61F)
Bit Name Description Type1Default
Register Description: This register enables dat a rece ived from the line-side re ceive interface
through the MAC to be sent to the TX FIFO and back to the line-side transmit interface. 0x00000000
31:4 Reserved Reserved RO 0x0000000
3Port 3 Line-S ide
Loopback 0 = Disable line- s ide loopb ack
1 = Ena ble line-side loopback R/W 0
2Port 2 Line-S ide
Loopback 0 = Disable line- s ide loopb ack
1 = Ena ble line-side loopback R/W 0
1Port 1 Line-S ide
Loopback 0 = Disable line- s ide loopb ack
1 = Ena ble line-side loopback R/W 0
0Port 0 Line-S ide
Loopback 0 = Disable line- s ide loopb ack
1 = Ena ble line-side loopback R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Tab le 137 . TX FIFO Port Reset ($0x620) (Sheet 1 of 2)
Bit Name Description Type1Default
Register D escrip t ion : This is a port reset register for each port in the TX block. Port ID = bit
position in the register. To make the port active, the bit must be set to Low. (For example, reset
of Port 3 implies register value = 1000, setting the bit to 1 asserts the port reset). 0x00000000
31:4 Reserved Reserved RO 0x0000000
3 Por t 3 Re s et Port 3
0 = De-assert Reset
1 = Assert Reset R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Tab le 135 . TX FIFO Overflow/Und erflow/ Ou t of Sequence Event ($0x61E ) (Sheet 2 of 2)
Bit Name Description Type1Default
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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2Port 2 Reset Port 2
0 = De-assert Reset
1 = Assert Reset R/W 0
1Port 1 Reset Port 1
0 = De-assert Reset
1 = Assert Reset R/W 0
0Port 0 Reset Port 0
0 = De-assert Reset
1 = Assert Reset R/W 0
Table 138. TX FIFO Overfl ow Fram e Drop Coun ter Ports 0 - 3 ($0x621 – 0x624)
Name Description Address Type*Default
TX FIFO overflow
frame drop counter
on Port 0
When TX FIFO on Port 0 becomes full or
rese t, the numb er of fram e s lo st or remov e d
on this port is shown in this register. This
register is cleared on Read. 0x621 R 0x00000000
TX FIFO overflow
frame drop counter
on Port 1
When TX FIFO on Port 1 becomes full or
rese t, the numb er of fram e s lo st or remov e d
on this port is shown in this register. This
register is cleared on Read. 0x622 R 0x00000000
TX FIFO overflow
frame drop counter
on Port 2
When TX FIFO on Port 2 becomes full or
rese t, the numb er of fram e s lo st or remov e d
on this port is shown in this register. This
register is cleared on Read. 0x623 R 0x00000000
TX FIFO overflow
frame drop counter
on Port 3
When TX FIFO on Port 3 becomes full or
rese t, the numb er of fram e s lo st or remov e d
on this port is shown in this register. This
register is cleared on Read. 0x624 R 0x00000000
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
Table 137. TX FIFO Port Reset ($0x620) (Sheet 2 of 2)
Bit Name Description Type1Default
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
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Table 139. TX FIFO Erro red Fr ame Drop Counte r P o rts 0 - 3 ($0x 625 – 0x629)
Name Description Address Type*Default
TX FIFO errored
frame drop counter
on Port 0
This register provid es the number of packets
droppe d by the TX FIFO due to the following:
Data Parity Errors
Short SOPs (two consecutive SOPs for a port
with no EOP)
Sm al l P ac ke ts ( 9-14 by tes)
Fr am es rec ei ved that are si gn al ed wi th TE RR
on the SPI3 TX interface.
NOTE: This regis ter is cleare d on Read.
0x625 R 0x00000000
TX FIFO errored
frame drop counter
on Port 1
This register provid es the number of packets
droppe d by the TX FIFO due to the following:
Data Parity Errors
Short SOPs (two consecutive SOPs for a port
with no EOP)
Sm al l P ac ke ts ( 9-14 by tes)
Fr am es rec ei ved that are si gn al ed wi th TE RR
on the SPI3 TX interface.
NOTE: This regis ter is cleare d on Read.
0x626 R 0x00000000
TX FIFO errored
frame drop counter
on Port 2
This register provid es the number of packets
droppe d by the TX FIFO due to the following:
Data Parity Errors
Short SOPs (two consecutive SOPs for a port
with no EOP)
Sm al l P ac ke ts ( 9-14 by tes)
Fr am es rec ei ved that are si gn al ed wi th TE RR
on the SPI3 TX interface.
NOTE: This regis ter is cleare d on Read.
0x627 R 0x00000000
TX FIFO errored
frame drop counter
on Port 3
This register provid es the number of packets
droppe d by the TX FIFO due to the following:
Data Parity Errors
Short SOPs (two consecutive SOPs for a port
with no EOP)
Sm al l P ac ke ts ( 9-14 by tes)
Fr am es rec ei ved that are si gn al ed wi th TE RR
on the SPI3 TX interface.
NOTE: This regis ter is cleare d on Read.
0x628 R 0x00000000
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Table 140. TX FIFO Occupancy Counter for Port s 0 - 3 ($0x62D – 0x630)
Name Description Address Type Default
Occupancy for Tx
FIFO Port 0 Thi s regi ste r gives t he O ccup an cy for TX FI FO
Port 0. T his is a Read only re gister 0x62D R 0x00000000
Occupancy for Tx
FIFO Port 1 Thi s regi ste r gives t he O ccup an cy for TX FI FO
Port 1. T his is a Read only re gister 0x62E R 0x00000000
Occupancy for Tx
FIFO Port 2 Thi s regi ste r gives t he O ccup an cy for TX FI FO
Port 2. T his is a Read only re gister 0x62F R 0x00000000
Occupancy for Tx
FIFO Port 3 Thi s regi ste r gives t he O ccup an cy for TX FI FO
Port 3. T his is a Read only re gister 0x630 R 0x00000000
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
Table 141. TX FIFO Port Drop Enable ($0x63 D)
Bit Name Description Type Default
Register Description: Independently enables the individual TX FIFOs to drop erroneous
packets. 0x0000000f
31:4 Reserved Reserved RO 0x000000
3 Port 3 Drop 0 = Disable the TXFIFO from dropping erroneous packets
1 = Ena ble the TXFIFO to drop erroneous packets R/W 1
2 Port 2 Drop 0 = Disable the TXFIFO from dropping erroneous packets
1 = Ena ble the TXFIFO to drop erroneous packets R/W 1
1 Port 1 Drop 0 = Disable the TXFIFO from dropping erroneous packets
1 = Ena ble the TXFIFO to drop erroneous packets R/W 1
0 Port 0 Drop 0 = Disable the TXFIFO from dropping erroneous packets
1 = Ena ble the TXFIFO to drop erroneous packets R/W 1
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Wri t e only; R/W = Read/Write, No clear;
R/W/C = Read/Write, Clear on Write
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8.4.8 MDIO Register Overview
Table 142 through Table 145 provide an overview of the MDIO registers.
Tab le 142 . MDIO S ingle Comm an d ($0x680)
Bit Name Description Type1Default
Register D escrip t ion : Gives the CPU the ability to perform single MDIO read and write
ac cesses to the ex ternal PHY for por ts that are c onfigu red in copper mode. 0x00010000
31:21 Reserved Reserved RO 00000000000
20 MDIO Command
Performs the MDIO ope ration. Cleare d wh en
done.
0 = MDIO ready, operation complete
1 = Perform operation
R/W 0
19:18 Reserved Reserved RO 00
17:16 OP Code
MDIO Op Code; two bits identify operation to be
performed:
00 =Reserved
01 =Wri t e op er a tion (as define d in IEEE 802 . 3,
clause 22.2.4.5)
10 =Read operation (as defined in IEEE 802.3,
clause 22.2.4.5)
11 = Reserved
R/W 01
15:10 Reserved Reserved RO 000000
9:8 PHY Address Sets bi t s 1:0 of the e xt ern al PHY ad dre ss. Bi t s 4 :2
of the PHY address are fixed at 000. R/W 00
7:5 Reserved Reserved RO 000
4: 0 REG Add r e ss Five-bit address to one among 32 registers in an
addressed PHY device. R/W 00000
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Tab le 143 . MDIO S ingle Read an d Write D ata ($0x6 81)
Bit Name Description Type1Default
Register D escrip t ion : MDIO read and write data. 0x00000000
31:16 MDIO Read Data MDIO Read data from external device. RO 0x0000
15:0 MD IO Write Data MDIO Write data to ex te rna l device . R/W 0x 00 00
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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Table 144. Autoscan PHY Address Enab le ($0x682 )
Bit Name Description Type1Default
Register Description: Defi nes valid PH Y addresses. Each bit enables the corresponding
PH Y address.
0 = Disable the PHY address
1 = Enable the PHY address
NOTE: A utoscan is only applicable fo r the ports in copper mode.
0x00000000
31:4 Reserved Reserved RO 0x0000000
3:0 Au toscan PHY
Address
Autoscan PHY address enable
0 = Disable address
1 = Enable address R/W 1111
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
Table 145. MDIO Control ($0x683)
Bit Name Description Type1Default
Register Description: Mi scellaneous control bits. 0x000000 00
31:4 Reserved Reserved RO 0x000
3MDIO in Progress
MDIO progress. This bit reflects the status of
M DIO tr ansaction
0 = MDIO Single command not in progress
1 = MDIO Single Command in progress
RO 0
2MDIO in Progress
Enable
Enable s the MDIO in pro gress bit
0 = Disable MDIO in progress register bit
1 = Enable MDIO in progress register bit R/W 0
1 Autoscan Enable Autoscan enable
0 = Disable Autoscan
1 = Enable Autoscan R/W 0
0 MDC Speed MDC sp eed
0 = MD C run s at 2.5 MHz
1 = MD C run s at 18 MHz R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
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8.4.9 SPI3 Register Overview
Table 146 through Tabl e 148 “Address Parity Error Packet Drop Counter ($0x70A)” on page 219
pr ovide an overview of the SPI3 reg is ters.
Tab le 146 . SPI3 Transm it and Global Configu ration ($0x7 00) (Sheet 1 of 3)
Bit Name Description Type1Default
Register D escrip t ion : T hi s reg iste r gives the conf igu ra tio n rel ate d to the SP I3 Tra ns mi tte r
and Global configuration (4 x 8 mode). 0x00200000
31:24 Reserved Reserved RO 0x00
23 SPI3 Transmitter Soft
Reset 1 = The SP I3 TX block is reset. R/W 0
22 SPI3 Receiver Soft
Reset 1 = The SPI3 RX block is reset. R/W 0
21 SPHY/ MPHY Mode
0 = Ind icates that SP I3 blo ck operates in 32-bit
MPHY mode.
1 = Ind ic at es t ha t the S PI3 bl ock o pe r ates i n 4 x 8
SPHY mode.
This configuration affects both the SPI3 transmitter
and receiver funct ionality.
R/W 1
20 Tx_ad_prtyer_drop
Indicates whether to drop packets received wit h
parity error during the address selection phase
(Tsx an d nTen b High) sh ou ld be dr op pe d.
0 = Do not drop packets with address parity err or
1 = Drop packets with address parity error
Th is is ap plicable only in MPH Y mode of
operation. This bit is ignored in SPHY (4 x 8) mode
as there will be no address selection.
R/W 0
19 Da t_ pr t ye r _d r p Port 3
SPHY/ MPHY Mod e :
Indicates whether to drop packets with data parity
error for port 3.
0 = Do not dr op packets with data parity error
(default)
1 = Drop packets with data parity error
R/W 0x0
18 Da t_ pr t ye r _d r p Port 2
SPHY/ MPHY Mod e :
Indicates whether to drop packets with data parity
error for port 2.
0 = Do not dr op packets with data parity error
(default)
1 = Drop packets with data parity error
R/W 0
17 Da t_ pr t ye r _d r p Port 1
SPHY/ MPHY Mod e :
Indicates whether to drop packets with data parity
error for port 1.
0 = Do not dr op packets with data parity error
(default)
1 = Drop packets with data parity error
R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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16 Dat_prtyer_drp Port 0
SPHY/MPHY Mode:
Indicates whether to drop packets with data parity
error for port 0.
0 = Do not drop packets with data parity error
(default)
1 = Drop packets with data parity error
R/W 0
15:8 Reserved Write as 0, ig nore on Read. R/W 00000000
7 T x_parity_s ense Po rt 3
SPHY Mode :
Indicates the parity sense to check the parity on
TDAT bus for p ort 3.
0 = Odd Parity
1 = Even Parity
MPHY Mode:
NA
R/W 0
6 T x_parity_s ense Po rt 2
SPHY Mode :
Indicates the parity sense to check the parity on
TDAT bus for port 2.
0 = Odd Parity
1 = Even Parity
MPHY Mode:
NA
R/W 0
5 T x_parity_s ense Po rt 1
SPHY Mode :
Indicates the parity sense to check the parity on
TDAT bus for port 1.
0 = Odd Parity
1 = Even Parity
MPHY Mode:
NA
R/W 0
4 T x_parity_s ense Po rt 0
SPHY Mode :
Indicates the parity sense to check the parity on
TDAT bus for port 0.
0 = Odd Parity
1 = Even Parity
MPHY Mode:
Indicates the parity sense to check the parity on
TD AT bu s for a ll ports.
0 = Odd Parity
1 = Even Parity
R/W 0
3 Tx_port_enable Port 3
SPHY Mode :
0 = Di s ables the selected SPI3TX port 3.
1 = Enables the selected SPI3 TX port 3.
MPHY Mode:
0 = Disables the selected SPI3 TX port 3.
1 = Enables the selected SPI3 TX port 3.
R/W 1
Table 146. SPI3 Transm it and Glob al Configuration ($0 x700) (Sh eet 2 of 3)
Bit Name Description Type1Default
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
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2 Tx_p ort_enable P ort 2
SPHY Mode:
0 = Disables the selected SPI3 TX port 2
1 = Ena bles the select ed SP I3 TX por t 2
MPHY Mode:
0 = Disables the selected SPI3 TX port 2
1 = Ena bles the select ed SP I3 TX por t 2
R/W 1
1 Tx_p ort_enable P ort 1
SPHY Mode:
0 = Disables the selected SPI3 TX port 1
1 = Ena bles the select ed SP I3 TX por t 1
MPHY Mode:
0 = Disables the selected SPI3 TX port 1
1 = Ena bles the select ed SP I3 TX por t 1
R/W 1
0 Tx_p ort_enable P ort 0
SPHY Mode:
0 = Disables the selected SPI3 TX port 0
1 = Ena bles the select ed SP I3 TX por t 0
MPHY Mode:
0 = Disables the selected SPI3 TX port 0
1 = Ena bles the select ed SP I3 TX por t 0
R/W 1
Tab le 147 . SPI3 Receive Configuration ($0x701) (Sheet 1 of 4)
Bit Name Description Type1Default
Register D escrip t ion : T his reg i s te r giv es the conf iguratio n r el at e d to the SP I3 rec e iv er. 0x0 00 00F8 0
31:28 Reserved Reserved RO 0x0
27 B2B_PAUSE Port 3
SPHY Mode:
Indicates the number of pause cycles to be
int roduc e d betw ee n ba ck - to - ba c k tr an s f ers for
port 3.
0 = Zero pause cycles
1 = Two pause cycles
MPHY Mode:
NA
R/W 0
26 B2B_PAUSE Port 2
SPHY Mode:
Indicates the number of pause cycles to be
int roduc e d betw ee n ba ck - to - ba c k tr an s f ers for
port 2.
0 = Zero pause cycles
1 = Two pause cycles
MPHY Mode:
NA
R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Tab le 146 . SPI3 Transm it and Global Configu ration ($0x7 00) (Sheet 3 of 3)
Bit Name Description Type1Default
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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25 B2B_PAUSE Port 1
SPHY Mode:
Indicates the numb er of pause cycles to be
introduced between back- to-back transfers fo r
por t 1.
0 = Zero pause cy cles
1 = Tw o paus e cy cle s
MPHY Mo de :
NA
R/W 0
24 B2B_PAUSE Port 0
SPHY Mode:
Indicates the numb er of pause cycles to be
introduced between back- to-back transfers fo r
por t 0.
0 = Zero pause cy cles
1 = Tw o paus e cy cle s
MPHY Mo de :
Indicates the numb er of pause cycles to be
introduced be tween back-to-back transfers for all
ports.
0 = Zero pause cy cles
1 = Tw o paus e cy cle s
R/W 0
23:2 2 RX_BU RST Port 3
SPHY Mode:
NA
MPHY Mo de :
NA
R/W 0x0
21:2 0 RX_BU RST Port 2
SPHY Mode:
NA
MPHY Mo de :
NA
R/W 0x0
19:1 8 RX_BU RST Port 1
SPHY Mode:
NA
MPHY Mo de :
NA
R/W 0x0
17:1 6 RX_BU RST Port 0
SPHY Mode:
NA
MPHY Mo de :
Selects the maximum burst size on the RX path
for all ports.
0x = 64 bytes maximum bur st size
10 =128 bytes maximum burst size
11 = 256 bytes maximu m burst size
R/W 0x0
Table 147. SPI3 Receive Configura tion ($0x701) (Continued) (Sheet 2 of 4)
Bit Name Description Type1Default
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
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15 Rx_parity_sense Port 3
SPHY Mode:
Indicates the parity se nse to ch eck the p arity on
RDAT bus for port 3.
0 = Odd Parity
1 = Even Parity
MPHY Mode:
NA
R/W 0x0
14 Rx_parity_sense Port 2
SPHY Mode:
Indicates the parity se nse to ch eck the p arity on
RDAT bus for port 2.
0 = Odd Parity
1 = Even Parity
MPHY Mode:
NA
R/W 0x0
13 Rx_parity_sense Port 1
SPHY Mode:
Indicates the parity se nse to ch eck the p arity on
RDAT bus for port 1.
0 = Odd Parity
1 = Even Parity
MPHY Mode:
NA
R/W 0x0
12 Rx_parity_sense Port 0
SPHY Mode:
Indicates the parity se nse to ch eck the p arity on
RDAT bus for port 0.
0 = Odd Parity
1 = Even Parity
MPHY Mode:
Indicates the parity se nse to ch eck the p arity on
RDAT bus for all ports.
0 = Odd Parity
1 = Even Parity
R/W 0x0
11 Rx_port_enable
Port 3
SPHY Mode:
0 = Disables the selected SPI3 RX port.
1 = Enables the selected SPI3 RX port.
MPHY Mode:
0 = Disables the selected SPI3 RX port.
1 = Enables the selected SPI3 RX port.
R/W 0x1
10 Rx_port_enable
Port 2
SPHY Mode:
0 = Disables the selected SPI3 RX port.
1 = Enables the selected SPI3 RX port.
MPHY Mode:
0 = Disables the selected SPI3 RX port.
1 = Enables the selected SPI3 RX port.
R/W 0x1
Tab le 147 . SPI3 Receive Configuration ($0x701) (Continued) (Sheet 3 of 4)
Bit Name Description Type1Default
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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9Rx_port_enable
Port 1
SPHY Mode:
0 = Dis ab les the selec te d S PI3 RX po rt .
1 = Enables the selected SPI3 RX port.
MPHY Mo de :
0 = Dis ab les the selec te d S PI3 RX po rt .
1 = Enables the selected SPI3 RX port.
R/W 0x1
8Rx_port_enable
Port 0
SPHY Mode:
0 = Dis ab les the selec te d S PI3 RX po rt .
1 = Enables the selected SPI3 RX port.
MPHY Mo de :
0 = Dis ab les the selec te d S PI3 RX po rt .
1 = Enables the selected SPI3 RX port.
R/W 0x1
7 Rx_core_enable
SPHY Mode:
NA . Wr ite as 1, ignore on Read.
MPHY Mo de :
0 = Disables the RX SPI3 core.
1 = Enables the RX SPI3 core.
R/W 0x1
6:1 IBA[5:0]
SPHY Mode:
NA . Wr ite as 0, ignore on Read.
MPHY Mo de :
Sets the 6-bit value appended to the 2-bit
address during the port address selection.
R/W 0x00
0 RERR_enable
SPHY Mode/MPHY Mode:
Frames marked to be filtered (based on the
settings in the “RX Packet Filter Con tro l ($
Port_Index + 0x19)”) or fr am e s ab ov e the “Max
Frame Size (Addr: Port_Index + 0x0F)” that are
not dropped in the RX FIFO (see “RX FIFO
Errored Frame Drop Enable ($0x59F)”can be
optionally indicated with an RERR when sent out
the SPI3 interface.
0 = Packets not indic a ted with RE RR.
1 = Pack ets indi cate d w ith RERR.
R/W 0
Table 147. SPI3 Receive Configura tion ($0x701) (Continued) (Sheet 4 of 4)
Bit Name Description Type1Default
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
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Table 148. Address Pari ty Error Pa cket Drop Coun ter ($0x70A)
Bit Name Description Type1Default
Register D escription : This register counts the number of pa ckets d roppe d due to parity error
detection during the address selection cycle. 0x00000000
31:8 Reserved Reserved RO 0x000000
7:0 Add ress Par ity Error
Packet Drop Counter
This is an 8-bit counter that counts the number of
packets dropped due to parity error detection
during the address selection cycle. This gets
cleared when read and saturates at 8’hFF. There
is only one counter for address parity drop as
address will be used only in MPHY mode of
operatio n. Th e co unter ge ts cl eared onc e the
re gi ster is read.
R0x00
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
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8.4.10 SerDes Register Overview
Table 149 through Table 152 “Cl ock and Interface Mode Change Enable Ports 0 - 3 ($0x794 )” on
page 221 define the cont ents of the SerDe s re gisters at base location 0x780, which co ntain the
control and status for the four SerDes interfaces on the IX F1104 MAC.
Table 149. TX Driver Power Level Ports 0 - 3 ($0x784)
Bit Name Description Type Default
Register Description: Allows selection of various programmable drive strengths on each
SerDes port. Refer to Section 5.6.2.2, “Transmitter Programmable Driver-Power Levels” on
page 104.0x0000dddd
31:16 Reserved Reserved RO 0x0000
15:12 DRVPWR3[3:0] Encoded input that sets Power Level for Port 3 R/W 1101
11:8 DRVPWR2[3:0] Encoded input that sets Power Level for Port 2 R/W 1 101
7:4 DRVPWR1[3:0] Encoded input that sets Power Level for Port 1 R/W 1101
3:0 DRVPWR0[3:0] Encoded input that sets Power Level for Port 0 R/W 1 101
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
Table 150. TX and RX Power-Dow n ($0x787)
Bit Name Description Type Default
Register Description: TX and RX power-down bits to allow per-port power-down of unused
ports 0x00000000
31:14 Reserved Reserved RO 0x0000000
13:10 TPWRDWN[3:0] TX power-down for Ports 3-0 (1 = Power-down) R/W 0000
9:4 Reserved Reserved RO 0x0 0
3:0 RPWRDWN[3:0] RX Power-down for Ports 3-0 (1 = Power-down) R/W 0000
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
Table 151. RX Signal Detect Level Ports 0 - 3 ($0x793)
Bit Name Description Type1Default
Register Description: This register shows the status of the Rx input in relation to the level of
the sign al being received from the line. This register is m eant for de bug and t est use. 0x00000000
31:4 Reserved Reserved RO 0x0000000
3:0 SIGDET[3:0] Signal Detect for Ports 0-3
0 = Noise
1 = Signal RO 0x0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
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Tab le 152 . Clock and Interface Mode Change E nable Ports 0 - 3 ($0x794)
Bit Name Description Type1Default
Register D escription : This regist er is used when a c hange t o the operational mode or speed
of the IXF1104 MAC is required. This register ensures that when a change is made that the
internal clocking of the IXF1104 MAC is managed correctly and no unexpected effects of the
operational or speed change are observable on the line interfaces. 0x00000000
31:4 Reserved Reserved RO 0x0000000
3Clock and Interface
Mod e Change Enabl e
Port 32
Enables internal clock generator for Port 3 to
sample the “MA C IF Mode and RGMII Spee d ($
Port_Index + 0x10)" and the “Interface Mode
($0x501)".
0 = Set to zero w hen changes are being made to
the “MAC IF Mode and RGMII Speed ($
Port_Index + 0x10)" and the “Interface Mode
($0x501)".
1 = Set to 1 for the configuration changes to take
effect.
R/W 0
2Clock and Interface
Mod e Change Enabl e
Port 22
Enables internal clock generator for Port 2 to
sample the “MA C IF Mode and RGMII Spee d ($
Port_Index + 0x10)" and the “Interface Mode
($0x501)".
0 = Set to zero w hen changes are being made to
the “MAC IF Mode and RGMII Speed ($
Port_Index + 0x10)" and the “Interface Mode
($0x501)".
1 = Set to 1 for the configuration changes to take
effect.
R/W 0
1 Clock and Interface
Mod e Change Enabl e
Port 12
Enables internal clock generator for Port 1 to
sample the “MA C IF Mode and RGMII Spee d ($
Port_Index + 0x10)" and the “Interface Mode
($0x501)".
0 = Set to zero w hen changes are being made to
the “MAC IF Mode and RGMII Speed ($
Port_Index + 0x10)" and the “Interface Mode
($0x501)".
1 = Set to 1 for the configuration changes to take
effect.
R/W 0
0 Clock and Interface
Mod e Change Enabl e
Port 02
Enables internal clock generator for Port 0 to
sample the “MA C IF Mode and RGMII Spee d ($
Port_Index + 0x10)" and the “Interface Mode
($0x501)".
0 = Set to zero w hen changes are being made to
the “MAC IF Mode and RGMII Speed ($
Port_Index + 0x10)" and the “Interface Mode
($0x501)".
1 = Set to 1 for the configuration changes to take
effect.
R/W 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
2. Refer to Section 6.1, “Change Port Mod e Initialization Se quence” on pag e 130 for the proper sequence to
change the port mode and speed in conjunction with this register.
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8.4.11 Optical Module Register Overview
Table 153 through Table 156 “I2C Da ta Ports 0 - 3 ($0x79F )” on page 223 provide an overview of
th e Optical Module Registe r s.
Note: All registers in this s ection are only applica ble to ports that are configured in fiber m ode.
Table 153. Optica l Module Status Ports 0-3 ($0x799)
Bit Name Description Type1Default
Register Description: This register provides a means to control and monitor the interface to
the optical modules when a port is used in fiber mode. 0x00000000
31:24 Reserved Reserved RO 0x00
23:20 Rx_LOS_3:0 Rx_LOS inputs for Ports 0-3 R 0x0
19:14 Reserved Reserved 0X00
13:10 Tx_FAULT_3:0 Tx_F AULT inputs for Ports 0-3 R 0x0
9:4 Reserved Reserved 0X00
3:0 MOD_DE F_3:0 MO D_DE F inputs for Ports 0-3 R 0 x 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
Table 154. Optical Modu le Contro l Ports 0 - 3 ($0x79A)
Bit Name Description Type1Default
Register Description: This reg ister provid es acc ess to opt ical module interrup t enable s and
sets the TX_DISABLE output for the ports configured in fiber mode. 0x1E000
31:17 Reserved Reserved RO 0x0000
16:13 I2C_port_enable When set, individually enables the four I2C ports. R /W 0xF
12 RX_LOS_EN Enable for RX_LOS_INT operation
1 = Enabled R/W 0
11 TX_FAULT_EN Enable for TX_FAULT_INT operation
1 = Enabled R/W 0
10 MOD_DEF_EN Enable for MOD_DEF_INT operation
1 = Enabled R/W 0
9:4 Reserved Reserved RO 0X00
3:0 TX_DISABLE_3:0 Tx_DISABLE outputs for Ports 0-3 R/W 0x0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write , No
clear; R/W/C = Read/Write, Clear on Write
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Table 155. I2C Co ntro l Ports 0 - 3 ($0x79B)
Bit Name Description Type1Default
Register Description: This register controls and monitors the interface to the optical m odule s
when used in fiber mode. 0x00000000
31:29 Reserved Reserved RO 0x0
28 Port address Err (R) Port addressing error. R 0
27 wp_err An attempt to write to the protected E2PROM has
occurred. R0
26 no_ack_err
This bit is set to 1 when a write and subs equent
read from an Optical Module Interface has failed.
This signal should be used to validate the data
being read. Data is only valid if this bit is equal to
zero.
R0
25 I2C_enable Enable the I2C block. R/ W 0
24 I2C_start Start the I2C transfer. R/W 0
23 Reserved Reserved RO 0
22 write_complete Bit is asserted when write access is complete. R 0
21 Reserved Reserved RO 0
20 Read_complete Bit asserted wh en rea d access is complete. R 0
19:18 Reserved Reserved RO 0
17:16 Port Select Selects the port for which the I2C transaction is
targ eted. Valid range is 0 to 3. R/W 00
15 Read/Write 0 = Write tr ansaction
1 = Read transactio n R/W 0
14:11 Device ID Most-significant four bits of device address field. R/W 0x0
10: 0 Regi ster Add r es s Bit s 10 :8 se lect th e le as t- s ig nific ant thr e e bi ts of
the device address field
Bits 7:0 select the word/register address R/W 0x000
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 156. I2C Data Ports 0 - 3 ($0x79F )
Bit Name Description Type1Default
Reg ist er D es cript io n: These registers ho ld dat a bytes that are read and written using the I2C
interface to Optical Module Interfaces connected to each port of the Intel® IXF1 104 4-Port
Gigabit Ethernet Media Access Controller. 0x00000000
31:24 Reserved Reserved RO 0x00
23: 16 Write Data Bit 23=MSB, Bit 16 = LSB
Data to be written to the Optical Module Interface. R/W 0X00
15:8 Reserved Reserved RO 0x00
7:0 Read Data Bit 7 = MSB, Bit 0 = LSB
Data read fr om th e Op tica l Mo d ule Interfa ce. R/W 0X00
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
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9.0 Mechanical Specifications
The IXF1104 MAC is pa ckaged in a 576-ball BGA package with 6 balls removed diag onally from
eac h corne r, for a tot al of 55 2 balls use d measur ing 25 mm x 25 mm. The pit ch of th e package ba lls
is 1 mm.
9.1 Overview
CBGA (sta ndard and RoHS-c om pliant) and FC-PBGA packa ges are suite d f or applications
requiring high I/O counts and high elect r ical performance, and are recommended for high-power
applic ations with high noise immunity re quirements.
Note: T he FC-PBGA package will not be available until mi d-2006. Please see your field sales
repr ese ntative for m o r e deta iled informa tion.
9.1.1 Features
•Fli p chip die attach ; surface mount second-level interconnec t
•Hi gh el ec tr i cal p er fo rman c e
•High I/O counts
•Area arr ay I/O options
•Multiple power - zone offering supp orts core and four addi tional voltages
•JEDEC-compliant package
9.2 Package Specifics
The IXF1104 MAC uses the following package:
•576-ball BGA package with 6 balls removed diagonally from each corner, for a total of 552
balls used
•Ball pitch of 1.0 mm
•Overall package di mensions of 25 mm x 25 mm
Intel® I XF1104 4-Port Gigab it Ethernet Media Access Contro ller
225 Datasheet
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9.3 Package Info rmation
9.3.1 CBGA Package Diagrams
Figure 55 and Figure 56 i llustrate the CBGA top, bot tom, and side package vi ews .
Figure 55. CBGA Package Diagram
B0034-01
3.902
3.938
Chip
Substrate
7.804
7.877
(25 ± 0.2)
(25 ± 0.2)
47P6802
Note: All dimensions are in mm.
B0035-03
(25 ± 0.2)
(23)
(25 ± 0.2)
(23)
(23x) TYP
Chip Carrier
A01 Corner
(23x) TYP
(0.825 MAX)
(0.325 MIN)
(Reference)
(0.825 MAX)
(0.325 MIN)
(575X) (ø
0.8 ± 0.05)
(I/O Pads)
(Reference)
ø
0.20
DA
L S BS
Note: All dimensions are in mm.
= Ball
= No ball
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
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Figure 56. CBGA Pa ckage Side View Diagram
B0555-01
Seating Plane
0.15 C
(4.237 Max)
(3.619 Min)
(3.327 Max)
(2.809 Min)
(0.857 Max)
(0.779 Min)
(4.16 Max)
(3.43 Min)
(6X)
(3.24 Max)
(2.72 Min)
(6X)
(2.47 Max)
(2.03 Min)
0.81 ± 0.1
(0.77 Max)
(0.69 Min)
(6X)
Chip
C4 Encapsulant
Fillet
45L4867 (552)
Solder ball
Note: All dimensions are in mm.
Intel® I XF1104 4-Port Gigab it Ethernet Media Access Contro ller
227 Datasheet
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9.3.2 Flip Chip-Plastic Ball Grid Array Package Diagram
Figure 57 illustrates the FC-PBGA top and bottom package views and Figure 58 lists the FC-
PBGA mechanical specifications.
Note: Please contact your field sales representative for more information on the FC-PBGA package.
Figure 57. FC-PBGA Pack age (Top and Bottom Views)
B5181-02
Basic
1.00 mm
Basic
1.00 mm
łeee (0.25)
łb
(0.55 min
0.75 max)
01
Terminal A01
Identifier
Lid
Seating Plane
Substrate
ABC
02
03
CA
MB
łfff (0.10) C
M
e
A
E
D
e
= No Ball
= Ball
Notes:
All dimensions are in millimeters.
Legend:
TOP VIEW
BOTTOM VIEW
C
aaa (0.20)
ccc (0.35)// C
A
(3.27 max)
A1
(0.40 min)
bbb (0.25)// C
25.0 Nom – 0.2
25.0 Nom – 0.2
All around
ddd (0.20)
B
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 228
Document Number: 278757
Re vision N umber: 009
Re vision D ate: 27-Oct-2005
Figure 58. F C -PBGA Me chan ical Specifications
Intel® I XF1104 4-Port Gigab it Ethernet Media Access Contro ller
229 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
9.3.3 Top Label Marking Example
Figure 59 shows the IXF1104 MAC non-RoHS-compliant devic e marking lab el.
Note: In cont ras t to the Pb-Free (RoHS-c ompliant) package , the non-R oHS -compliant package does not
have the “e1” symbol.
Figure 59. Packag e Mar king Exam ple
Character Font
Size
0.04
-
0.1 0”
0.06 - 0.10”
25.0 mm
7.5 x 7.5 m m
25.0 mm
P
in 1 mark
AAA000AAA = In tel Product Number
0.19 - 0.24”
®
0.07 - 0.12”
R
NO TE: * "Pin 1 " does mean a Pin1 indicator, not an actual mark.
Country
XX = Intel Silicon re vision number, A0, A1, B0 …
Note: Diameter of Trademark Circles are 70 mils.
Height of circles surrounding Pb-redced symbol are
equal to overall character height
Sub st rat e P N = Subs trat e material number (barel y visib le)
JJJJJJJJ = Manufacturing Lot Number
Syww9001 = Intel Finished Process Order (FPO) numbe
r
Country = Assy plant Country of Origin
Topside fields not to scale
Diameter of Pin 1 mark is 70 mils,
and is located opposite the top-side
substrate “Pin 1” identifier.
QQ = Quality Level, P: Prot o Type, PQ: Potent i al Qual’able ,
“ ”: Production (no marking)
++
++ = Rework Indicator
Syww9001
Back of the die
(Bare Silicon)
Subs tr at e P N
e1e1
= Pb-Reduced indicator (Same as Jedec)
B5131-01
NOTE: The actual product name marking is IXF1104CE, no t HFIXF1104CE (leaded versio n) and
WF IXF1104C E ( Pb - r ed uc ed ) , du e t o lid le ss pac ka ge spac e li mi tat i on .
Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller
Datasheet 230
Document Number: 278757
Re vision N umber: 009
Re vision D ate: 27-Oct-2005
10.0 Product Orderi ng Info r m a tion
Table 157 and Figure 60 provide IXF1104 MAC product ordering information.
Table 157. Product In f orma tion
Product Number Revision Package
Type RoHS-
Compliant
HFIXF1 104CE.B0 B0 CBGA No
WFIXF1104CE.B0 B0 CBGA Yes
HPIXF1104BE.B01B0 PBGA No
NOTE:
1. Please contact your field sales representative for detailed
inf orm a t io n on the F C- PBG A pack ag e.
Intel® IXF 1104 4-Port Gigab it Eth ernet Media Access Contro ller
231 Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
Figure 60. Orderi ng Informat i on – Sample
HF E1104 CIXF B0
Pr o d uct Re vision
xn = 2 Al phanumeric characters
Tem perature Range
A = Ambient (0 – 550C)
C = Commercial (0 – 700C)
E = Ex tend ed (-40 – 850C)
Internal Package Designator
L = LQFP
P = PLCC
N = DIP
Q = PQFP
H = QFP
T = TQFP
B = BGA
C = CBGA
E = TBGA
K = HSBGA (BGA with heat slug
Product Code
xxxxx = 3-5 Digit alphanumeric
IXA Product Prefix
LXT = PHY layer devi ce
IXE = Switching engine
IXF = Formatting device (MAC/Framer)
I XP = Net w o r k pr oces sor
Intel Pa ckage Designa tor
B5118-03
