EL4083CS - Intersil Corporation

FN7157

EL4083

Current Mode Four Quadrant Multiplier

The EL4083 makes use of an Elantec

fully complimentary oxide isolated

bipolar process to produce a patent

pending cur rent in, c urrent ou t four quad rant multip lier. Inp ut

and output signal summing and direct interface to other

current mode devices can be accomplished by simple

connection to reduce component count and preserve

bandwidth. The selection of an appropriate series resistor

value allows an input to accept a voltage signal of any size

and optimize dynamic range. The differential outputs offer

significant perform ance im provements which greatly extend

the usable gain control range at high frequencies. The bias

current is programmable to accommodate the voltage and

power dissipation constraints of the package and available

systems supplies.

The devices can implement all the classic four quadrant

multiplier applications and are uniquely well suited to gain

control and signal summing of broadband signals.

Pinout

EL4083

8-PIN PDIP, SO

TOP VIEW

Features

• Novel current mode design

- Virtual ground current summing inputs

- Differential ground referenced current outputs

• High speed (both inputs)

- 200MHz bandwidth

- 12ns 1% settling time

• Low distortion

- THD < 0. 03% @ 1MHz

- THD < 0.1% @ 10MHz

• Low noise (RL = 50Ω)

- 100dB dynamic range

- 10Hz to 20 kHz

- 73dB dynamic range

- 10Hz to 10MHz

• Wide supply conditions

- ±5 to ±15V operation

- Programmable bias current

• 0.2dB gain tolerance to 25MHz

Features

• Four quadrant multiplication

• Gain control

• Controlled signal summing and multiplexing

• HDTV video fading and switching

• Mixing/modulating/demodulating (phase detection)

• Frequency doubling

• Division

• Squaring

• Square r ooting

• RMS and power measurement

• Vector addition-RMS summing

• CRT focus and geometry correction

• Polynomial function generation

• AGC circuits

Ordering Information

PART

NUMBER TEMP.

RANGE PACKAGE PKG. NO.

EL4083CN -40°C to +85°C 8-Pin PDIP MDP0031

EL4083CS -40°C to +85°C 8-Pin SO MDP0027

Manufactured under U.S. Patent No. 5,389,840

Data Sheet December 1995, Rev. B

OBSOLETE PRODUCT

NO RECOMMENDED REPLACEMENT

contact our Technical Support Center at

1-888-INTERSIL or www.intersil.com/tsc

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Absolute Maximum Ratings (TA = 25 °C)

VSVoltage between VS+ and VS-. . . . . . . . . . . . . . .+33V

IZ(BIAS) Z, Bias Current . . . . . . . . . . . . . . . . . . . . . . . . .+2.4mA

IXX Input Current. . . . . . . . . . . . . . . . . . . . . . . . .±2.4mA

IYY Input Current. . . . . . . . . . . . . . . . . . . . . . . . .±2.4mA

PDMaximum Power Dissipation. . . . . . . . . . . . . . See Curves

TAOperating Temperature Range EL4083 . . -40°C to +85°C

TJOperating Junction Temperature EL4083. . . . . . . . .150°C

TST Storage Temperature . . . . . . . . . . . . . . . -65°C to +150°C

Electrical Specifications TA = 25°C, VS = ±5, IZ = 1.6mA unless otherwise specified.

PARAMETER CONDITIONS MIN TYP MAX UNITS

POWER SUPPLIES

Operating Supply Voltage Range ±4.5 ±16.5 V

ICC VS = ±15V, IZ = 0.2mA 7.2 8.5 9.5 mA

ICC VS = ±5V, IZ = 1.6mA 42.0 44.0 45 mA

IEE VS = ±15V, IZ = 0.2mA 9.5 10.0 12 mA

IEE VS = ±5V, IZ = 1.6mA 45 47 48 mA

MULTIPLIER PERFORMANCE

Transfer Function (Note 1) (IXY-IXY) = K(IX × IY)/IZ

K Val ue 0.92 0.965 1.01

Total Error (Note 2) -2mA < IX, IY < 2mA ±0.5 ±2 %FS

vs. Temp TMIN to TMAX ±1.5 ±3 %FS

Linearity (Note 3) 0.25 0.5 %FS

Bandwidth (Note 4) -3dB (Figure 2) 200 225 MHz

X Feedthrough DC to IXY or IXY (Note 1) IX = ±2mA, IY = 0 (unnulled) 0.15 1.6 %FS

Y Feedthrough DC to IXY or IXY (Note1) IY = ±2mA, IX = 0 (unnulled) 0.15 1.6 %FS

AC Feedthrough, X to IXY or IXY (Note 5) IX = 4mAPP, IY = nulled

f = 3.58MHz -80 dB

f = 100MHz -28 dB

AC Feedthrough, X to (IXY-IXY) (Note 5) IX = 4mAPP, IY = nulled,

DC < f < 1 GHz -50 dB

AC Feedthrough, Y to IXY or IXY (Note 5) IY = 4mAPP, IX = nulled

f = 3.58MHz -64 dB

f = 100MHz -26 dB

AC Feedthrough, Y to (IXY-IXY)-(Note 5) IY = 4mAPP, IX = nulled

DC < f < 1 GHz -50 dB

INPUTS (IX, IY)

Full Scale Range FRS = 1.25 × IZ (Nominal) ±2 mA

Clipping Level CL = 2 × IZ2.85 3.2 mA

ZIN (IX)30 40 48 Ω

ZIN (IY)30 36 48 Ω

Input Offset Voltages at Input Pins, IZ = 1.6mA -4 +4 mV

(VOSX,VOSY)I

Z = 0.2mA -12 +12 mV

Input Offset Currents (Note 1) RSX = RSY = 1K, VX = VY = 0 ±10 ±40 µA

IXOS, IYOS TMIN to TMAX ±20 nA/°C

Nonlinearity

IXIY = 2mA, - 2mA < IX < 2mA 0.1 0.6 %FS

IYIX = 2mA, - 2mA < IY < 2mA 0.1 0.4 %FS

EL4083

Distortion, IX (to IXY or IXY)I

Y = 2mA, - 2mA < IX < 2mA

f = 3.58MHz -55 dB

f = 100MHz -25 dB

Distortion, IY (to IXY or IXY)I

X = 2mA, - 2mA < Iy < 2mA

f = 3.58MHz -56 dB

f = 100MHz -26 dB

Distortion, IX (to (IXY - IXY)I

Y = 2mA, -2mA < IX < 2mA

f = 3.58MHz -66 dB

f = 100MHz -35 dB

Distortion, IY (to (IXY - IXY)I

X = 2mA, -2mA < IY < 2mA

f = 3.58MHz -66 dB

f = 100MHz -34 dB

Diff Gain @ 3.58MHz

IXIZ = 0.2mA, IY = 0.25mA 0.2 %

IYIZ = 0.2mA, IX = 0.25mA 0.17 %

IXIZ = 1.6mA, IY = 2mA 0.1 %

IYIZ = 1.6mA, IX = 2mA 0.05 %

Diff Phase @ 3.58MHz

IXIZ = 0.2mA, IY = 0.25mA 0.5 deg °

IYIZ = 0.2mA, IX = 0.25mA 0.5 deg °

IXIZ = 1.6mA, IY = 2mA 0.05 deg °

IYIZ = 1.6mA, IX = 2mA 0.05 deg °

OUTPUTS (IXY, IYX)

Output IOS (Note 1) IX = IY = 0 -15 ±120 µA

Dif f Output IOS (Note 1) IX = IY = 0, (IXY-IXY) ±0.1 ±80 µA

Voltage Compliance ±1.5 ±2.0 V

Max Output Current Swing ±2.85 ±3.2 mA

Noise Spectral Density

10Hz < f < 10MHz RL = 50Ω125 pA/√Hz

IZ (BIAS)

Current Range Tested 0.2 1.6 mA

Input Voltage IZ = 0.2mA ±25 mV

Input Voltage IZ = 1.6mA ±25 mV

NOTES:

1. Specifications are provisional for the EL4083.

2. Error is defined as the maximum deviation from the ideal transfer function expressed as a percentage of the full scale output.

3. Linearity is defined as the error remaining after compensating for scale factor (gain) variation and input and output referre d offset errors.

4. Bandwidth is guaranteed using the squaring mode test circuit of Figure 4.

5. Relative to full scale output with full scale sinewave on signal input and zero port input null ed. Specification represents feedthrough of the

fundamental.

Electrical Specifications TA = 25°C, VS = ±5, IZ = 1.6mA unless otherwise specified. (Continued)

PARAMETER CONDITIONS MIN TYP MAX UNITS

EL4083

EL4083 Block Diagram

AC Test Fixture

Burn-In Circuit

FIGURE 1.

FIGURE 2. AC BANDWIDTH TEST FIXTURE

FIGURE 3. BURN-IN CIRCUIT PDIP

EL4083

Typical Performance Curves

FIGURE 4.

8-Pin Plastic DIP

Maximum Power Dissipation

vs Ambient Temperature

FIGURE 5.

8-Pin SO

Maximum Power Dissipation

vs Ambient Temperature

FIGURE 6. (IX, IY BANDWIDTH VS IZ)FIGURE 7. (IX, IY 1% SETTLING TIME VS IZ)

FIGURE 8. OUTPUT NOISE DENSITY VS IZ BIAS

Typical Performance Curves (Continued)

FIGURE 9. OPTIONAL EXTERNAL TRIM NETWORKS

Input Offset Trim(s)

RTI = (VS × 1.6mA)/(16µA × IZ)

Output Offset Trim

RTO = (VS × 1.6mA)/(30µA × IZ)

FIGURE 10. VZIN VS IZ (TYPICAL) FIGURE 11. (IZIN BANDWIDTH VS IZ

EL4083

General Operating Information

IZ Input (Bias, Divisor) and Power Supplies

The IZ pin is a lo w im pe dan ce (< 20Ω) vi rtual grou nd curren t

input. It can accept positive current from a resistor

connected to a positive voltage source or the positive

supply . Th e i ns tan tane ous bias fo r th e m ult iplier gain c ore is

proportional to this current value. Negative applied current

will pu t the multi plier portio n of the circuit in a ze ro bias st ate

and the voltage at the pin will be clamped at a diode drop

below ground. The part will respond in a similar manner to

currents from a current source such as the output of a

transconductance amplifier or one of its own outputs. The

overall transfer equation for the EL4083 is:

K(IX × IY)/IZ = (IXY-IXY), K ~ 1

As can be seen from the equation, the Z input can serve as a

divisor input. However, it is different from the other two

inputs in that the value of its current determines the supply

current of the pa rt and the bandwidth and compl ia nce range

of the outputs and other two inputs. Table 1 gives the

equations describing these and other important

relationships. These dependencies can complicate and/or

limit the usefulness of this pin as a computational input. The

IZ dependence of the impedance of the multiplying inputs

can be particularly troublesome. See the IZ divider and the

RMS#2 circuit sections of the application note for some

ways of dealing with this.

The primary intended use for the Z input is as a

programming pin similar in function to those on

progra mmable op am ps. This enab les one to tr ade off power

consumption against bandwidth and settling time and allow

the part to fu nctio n with in its p ower diss ipati on ratin g over it s

full operational supply range (±4.5V - ±16.5V). The E4083

has been desig ned to function wel l f or I Z va lue s in the range

of 200µA < IZ < 1.6mA which c orresponds to IX an d IY sign al

bandwidths of about 50MHz to over 200MHz. Higher values

of IZ may cause problems at temperature extremes while

lower values down to zero will progressively degrade the

input referred D.C. offsets and reduce speed. Below about

50µA of bias current the internal servo amplifier loop which

maintains the IZ pin at ground will lose regulation and the

voltage at t he pin will sta rt to move negati ve (se e Figur e 10).

This is accompanied by a significant increase in input

impedance of the pin. Figure 11 shows the A.C. bandwidth

of the I Z inp ut as a function of the D.C. value of IZ. Figures 6

and 7 show the bandwidth and 1% settling time of the

multipl yi ng inp uts , IX and IY, as functions of IZ.

TABLE 1. BASIC DESIGN EQUATIONS AND RELATIONSHI PS

Positive Supply Current IS+ = 3.4mA + IZ × 26

Negative Supply Current IS- = 4.5mA + IZ × 27

Power Dissipation (See Figures 4 and 5) PWR = (+VS - (-VS)) × (4mA + IZ × 26.5)

Multiplying Input(s) Impedance RZX = RZY = (32Ω) × 1.6mA/IZ

Multiplying Input(s) Clip Point IX (clip) = IY (clip) = IZ × 2

Multiplying Input(s) Full Scale Value IX (fs) = IY (fs)= IZ × 1.25 (nominal)

Multiplying Input Resistor Values RX = VX (peak)/IX (fs)

(In Terms of Peak Input Signal) RY = VY (peak)/IY (fs)

Full Scale Output (Single Ended) IXY = IXY = IX (fs) × IY (fs)/(IZ×2)

Full Scale Output (Differential) (IXY - IXY) = IX (fs) × IY (fs)/IZ

IZ (Bias) Input Voltage vs IZ(See Figure 10)

IZ Signal Bandwidth vs IZ(See Figure 11)

IX, IY Signal Bandwidth vs IZ(See Figure 6)

IX, IY 1% Settling Time vs IZ(See Figure 7)

EL4083

IX and IY (Multiplier) Inputs and Offset Trimming

The IX and IY pins are low impedance (IZ dependent) virtual

ground current inputs that accept bipolar signals. The input

referred clip value is equal to IZ × 2 while the full scale value

has be en chosen to be 1.25 × IZ to maintain exce llent disto rtion

and line arity perfo rma nc e. O per ating at hig her full sc al e v alues

will degrade these two parameters and, to some extent,

bandwidth while improving the signal to noise performance,

feedthrough and control range.

The EL4083 is fundamentally different from conventional

voltage mode multipliers in that the available input range can

be tailo red to accom modat e volt age sources of alm ost an y siz e

by selecting appropriate input series resistor values. If desired,

one can interface with voltages that are much greater than the

suppli es from which the part is powered. C urrent source si gnals

can be connected directly to the multiplier inputs. The parts’

dynamic range can also be tailored to a large extent for a

current signal by the appropriate selection of IZ. These inputs

act in the same manner as a virtual ground input of an

operat ional amplif ier and thus ca n serve as a su mming node fo r

any number of voltage and/or current signals. Outputs of

compon en ts suc h as curr ent out put D ACs , trans co ndu ctance

amplifiers and current conveyors can be directly connected to

the inputs.

Ideally, a multiplier should give zero output if either one of its

multiplying inputs is zero. A nonzero output under these

conditions is caused by a combination of input and output

referred offsets. An output referred offset can be thought of as

a fixed value added to the output and thus only affects D.C.

accuracy. An input referred offset at a multiplying input allows

signal to feedthrough from the other multiplying input to the

output(s). The EL4083 is trimmed during testing at Elantec for

X and Y input referred offset for IZ = 1.6 mA. The internal trim

networks provide a current to each input which nulls the

feedthrough caused by internal device mismatches. These

current values are ratioed to the value of IZ so that the input

referred nulls are largely maintained at different values of IZ.

Howeve r, there will be some m istracking in the trim networks so

that the input referred null point will deviate away from zero at

values of IZ low er than 1.6mA. Figure 9 shows optiona l externa l

input and output referred offset trim networks which can be

used as needed to improve performance.

As mentioned, the output referred offset only affects D.C.

accuracy which may not be an issue in A.C. applications. In

gain contro l applic ations one may only need to nu ll feedthro ugh

with respect to the gain control input.

In gain control (VCA) applications the X input should be used

as the co ntro l inpu t and th e sig nal ap plied to the Y input since it

has slightly higher bandwidth and better linearity and distortion

performance.

Current Outputs (IXY, IXY), Feedthrough and

Distortion

Another unique feature of the EL4083 is the differential ground

referenced current output structure. These outputs can drive

50Ω terminated lines and reactive loads such as transformers,

baluns, and LC tank and filter circuits directly (See EL2082

Data Sheet_Receiver IF Amplifier (Figure 19). The EL2082 also

has a current output.). Unlike low impedance follower buffers,

these outp uts do not in teract with the lo ad to p roduce ringin g or

instability. If a high level low impedance output is required, the

outputs can be recovered differentially and converted to a

single ended output with a fast op amp such as the EL2075

(see Figure 19). The outputs can also drive current input

devices such as CMF amps, current conveyors and its own

inputs directly by simple connection.

Figures 12 and 14 show the nulled gain and feedthrough

characteristics of the IXY and IXY outputs which are virtually

identical and differ only in phase. Figure 12 is with the A.C.

signal app lied to the X in put with Y us ed as the gain co ntrol an d

in Figur e 14 these sign als are r eversed. Not e that in both cases

the signal feedthrough rolls up and peaks near the cutoff

frequency. This is quite typical of the performance of all

previous fo ur quad ran t mult ip lie rs. Fi gure s 13 an d 15 sh ow the

corresponding gain/feedthrough characteristics for the

differentially recovered output signal IXY-IXY. Note that in this

case the peak f eedthrough at high frequenc ies is lo wer by more

than 40dB (See EL2082 Data Sheet - Receiver IF Amplifier

[Figure 19]. The EL2082 also has a current output).

General Operating Information

Figures 16 and 17 show the total harmonic distortion for the

single-ended and differential recovered outputs for a full scale

A.C. input signal on one input and a full scale D.C. control

signal on the other. Note that above about one megahertz to

the cutoff frequency the THD of the differentially recovered

si gnal is as much as 10d B lower than the single-ended signals.

FIGURE 12. NULLED IXY AND IXY FREQUENCY

RESPONSE (SIGNAL ON XIN, GAIN

CONTROLLED BY YIN)

FIGURE 13. NULLED (IXY-IXY) FREQUENCY

RESPONSE (SIGNAL ON XIN,

GAIN CONTROLLED BY YIN)

FIGURE 14. NULLED IXY AND IXY FREQUENCY

RESPONSE (SIGNAL ON YIN,

GAIN CONTROLLED BY XIN)

FIGURE 15. NULLED (IXY--IXY) FREQUENCY

RESPONSE (SIGNAL ON YIN,

GAIN CONTROLLED BY XIN)

FIGURE 16. FULL LEVEL XIN THD VS

FREQUENCY FIGURE 17. FULL LEVEL YIN THD VS

FREQUENCY

EL4083

Applications

Basic Product Functions

Figures 18 and 19 are the basic schematics for many of the

applications of the EL4083. These can perform signal

mixing, frequency doubling, modulation, demodulation, gain

control/voltage-controlled amplification, multiplication and

squaring. Figure 18 has resistively terminated differential

outputs and has the widest bandwidth. The figure also

shows the option of using the EL2260 dual CMF ampl ifie r to

recover the outputs differentially at very low impedance.

This has a maximum 3dB bandwidth of 130MHz and settles

to 1% i n 25n s. Fig ure 19 uses an EL2075 at the outpu ts as a

differential to single ended converter with gain to take

advantage of the performance enhancements of the

differentially recovered output mentioned above and to

provide a high level low impedance drive. The -3dB

bandwidth of this circuit is over 150MHz using good layout

techniques. However, to achieve this bandwidth one must

restrict the output swing to little more than 1VPP to avoid

running into the 500V/µs minimum slew rate of the EL2075.

Table 2 shows the input signal assignments for the

applications listed above.

*X means not connected if function is not used.

TABLE 2. INPUT SIGNAL ASSIGNMENTS

FOR FIGURES 18 AND 19 CIRCUITS

APPLICATION VXVY

Mixer Signal 1 Signal 2

Frequency Doubler Signal Signal

Modulator Modulating Signal Carrier

Demodulator Local Oscillator Modulated Signal

Gain Control/VCA Gain Control Signal

Multiplier Signal 1 Signal 2

Squarer Signal Signal

IZ = VCC/RZ

RX = VX (MAX) / (1.25 × IZ)

RY = VY (MAX) / (1.25 × IZ)

*1. 51Ω Resistors omitted when using EL2260

*2. Optimum value of RF determined by supplies and amount or tolerable peaking

(-3dB BW ~ 90MHz @ VS = ±5V, BW ~ 150MHz @ ±15V)

FIGURE 18. BASIC SCHEMATIC (DUAL DIFF OUTS)

EL4083

Other Applications

Elantec has also published an applications note covering

other applications of the EL4083. These include dividers,

squaring and square rooting circuits, several RMS and

power measurement circuits, and a wideband AGC circuit.

Also presented are two polynomial computation examples

for video and some HDTV quality fader and summing

circuits. The EL4083 has been found flexible enough to

easily implement all of the classic four quadrant multiplier

applications and also offer interesting new applications

possibilities.

EL4083 Macromodel

This macrom odel is compatibl e with PSPICE (copywritten by

Microsim Corporation). It has been designed to work

accurately for fixed values of IZ (bias) in the range of 200µA

to 1.6mA. The additional simulation burden imposed by

including provision for a time varying IZ was thought not

worthwhile. The value of IZ is specified to the model by the

parameter NS. The relation between IZ and NS is;

IZ=200µA×NS. All other inputs can accept time varying

signals.

The model will provide good transient and frequency

respons e and set tli ng time es timat es as well as time do main

switching results. Input and output impedance and overload

responses are correctly modeled. The D.C. current drawn

from supplies for a given value of IZ is also corr ect.

Noise, PSRR and the temperature dependence of A.C.

parameters such as frequency response and settling time

are not modeled. Linearity and distortion results from the

model will be worse than the real part by about a factor of

three and do not show the correct frequency dependence.

The macromodel is constructed from simple controlled

sources, passive components and stripped transistor and

diode models. As such it should be usable, perhaps with

slight modification, on all but student or demonstration

simulators where the model’s size may be a problem.

FIGURE 19. BASIC SCHEMATIC (SINGLE ENDED CONVERTED)-(150MHZ VCA)

IZ = VCC/RZ

RX = VX (MAX) / (1.25 × IZ)

RY = VY (MAX) / (1.25 × IZ)

*Optimized for Wide Bandwidth

EL4083

EL4083 Macromodel (Continued)

*EL4083 Macromodel

*Revis io n A, August 22, 199 4

*Connection: IZ(BIAS)

* | IX(in)

* | | IY(in)

* | | | VEE

* | | | | VCC

* | | | | | IXY

* | | | | | | /IXY

* | | | | | | |

.subckt EL4083 ZIN XIN YIN VEE VCC IXY IYX

.MODEL M1MP5DIODE D TT=60p IS=1f CJO=300f VJ=600m XTI=3 EG=1.11 RS=80m

.MODEL M2MDCAP D TT=100n IS=2e-17 CJO=1p VJ=800m RS=300

.MODEL M3MNPN1 NPN CJC=1.3p TF=120p IS=1.04f BF=120 CJS=480f

.MODEL M4MPNP1 PNP CJC=1.79p TF=50.166666666667p IS=1f BF=90 CJS=480f

C1 N9 N7 9p

C2 N7 0 350f

C3 N19 N16 9p

C4 N16 0 350f

D1 0 N15 M2MDCAP 12

D10 0 N26 M1MP5DIODE 1

D11 N26 N27 M1MP5DIODE 1

D12 N29 N30 M1MP5DIODE 1

D13 0 N31 M1MP5DIODE 1

D14 VBP N34 M1MP5DIODE 2

D15 N34 VBP M1MP5DIODE 2

D16 0 N34 M2MDCAP 12.5

D17 N35 0 M2MDCAP 12.5

D18 N35 VBN M1MP5DIODE 2

D19 VBN N35 M1MP5DIODE 2

D2 N15 0 M2MDCAP 12

D20 N42 N10 M2MDCAP 4

D21 N10 0 M2MDCAP 4

D22 0 N20 M2MDCAP 4

D23 N20 N45 M2MDCAP 4

D3 0 N12 M1MP5DIODE 8

D4 N55 N13 M1MP5DIODE 8

D5 0 N25 M2MDCAP 6

D6 N25 0 M2MDECAP 6

D7 0 N22 M1MP5DIODE 8

D8 N54 N23 M1MP5DIODE 8

D9 0 N28 M1MP5DIODE 1

EV94 0 VBN 0 N45 1

EV95 VBP 0 N42 0 1

EV96 N54 0 N21 0 650m

EV97 N55 0 N11 0 650m

EV98 N27 0 N28 0 1

EV99 N29 0 SWIN 0 1

FI10 VN-VEE VFI10 1

FI11 VCC VP-VFI11 1

FI12 VCC N39 VFI12 1

FI13 N37 VEE VFI13 1

FI14 VCC N38 VFI14 1

FI15 N36 VEE VFI15 1

FI16 N45 VEE VFI16 1

FI17 VCC N42 VFI17 1

FI18 N37 N36 VFI18 500m

FI19 N38 N39 VFI19 500m

FI20 VN+ VN- VFI20 500m

EL4083

EL4083 Macromodel (Continued)

FI21 VP+ VP- VFI21 500m

FI22 0 N21 VFI22 1

FI23 N21 0 VFI23 1

FI24 N24 0 VFI24 2

FI25 N14 0 VFI25 2

FI26 N11 0 VFI26 1

FI27 0 N11 VFI27 1

FI28 VCC VEE VFI28 21

FI 29 N28 ZB1 VFI29 1

FI5 N33 0 VFI5 1

FI6 0 N33 VFI6 1

FI7 N35 N34 VFI7 1

FI8 VN+ VEE VFI8 1

FI9 VCC VP+ VFI9 1

IIBGN 0 VEE 2.2m

IIBGP VCC 0 2.46m

IIISWB N32 VEE 629u

IIISWI SWIN VEE 555u

IIZSU N28 VEE 10u

L1 N7 IXA 71n

L2 XIN N7 4n

L3 N16 IYA 71n

L4 YIN N16 4n

L5 N46 IYX 4n

L6 N47 IXY 4n

Q10 N10 VP+[VEE] M4MPNP1 2

Q10 N46 VN+ N36[VEE] M3MNPN1 2

Q11 N47 VN+ N37 [VEE] M3MNPN1 2

Q12 N46 VN- N37 [VEE] M3MNPN1 2

Q13 0 N34 N56 [VEE] M4MPNP1 400m

Q14 0 N34 N57 [VEE] M4MPNP1 400m

Q15 0 N35 N58 [VEE] M3MNPN1 400m

Q16 0 N35 N59 [VEE] M3MNPN1 400m

Q2 0 N10 VP- [VEE] M4MPNP1 2

Q3 0 N20 VN+ [VEE] M3MNPN 1 2

Q4 0 N20 VN- [VEE] M3MNPN1 2

Q5 N46 VP- N39 [VEE] M4MPNP1 2

Q6 N47 VP+ N39 [VEE] M4MPNP1 2

Q7 N46 VP+ N38 [VEE] M4MPNP1 2

Q8 N47 VP- N38 [VEE] M4MPNP1 2

Q9 N47 VN- N36 [VEE] M3MNPN1 2

R1 N15 N7 60 TC=824u 7.67u

R10 N16 N17 450 TC=0 0

R11 YIN N16 100 TC=0 0

R12 0 SWIN 500 TC=824u 7.67u

R13 N56 N38 35 TC=0 0

R14 N57 N39 35 TC=0 0

R15 N37 N58 35 TC=0 0

R16 N36 N59 35 TC=0 0

R17 N46 IYX 100 TC=0 0

R18 N47 IXY 100 TC=0 0

R2 N11 IXC 6.25 TC=0 0

R3 N9 IXC 4.5 TC=0 0

R4 N7 IXA 1.5K TC=0 0

R5 XIN N7 100 TC=0 0

R6 N25 N16 156 TC=82 4u 7.67 u

R7 N21 IYC 6.25 TC=0 0

R8 ITC N19 45 TC=0 0

R9 N17 IYA 45 TC=0 0

RSU VEE 0 16K TC=0 0

EL4083

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. N o license is granted by implication or other wise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

EL4083 Macromodel (Continued)

VFI10 N43 N44 0.0

VFI11 N40 N41 0.0

VFI12 ZB4 ZB5 0.0

VFI13 ZB5 ZB6 0.0

VFI14 ZB3 ZB4 0.0

VFI15 ZB6 ZB7 0.0

VFI16 N44 ZB9 0.0

VFI17 N41 ZB8 0.0

VFI18 IYB IYC 0.0

VFI19 IYA IYB 0.0

VFI20 IXB IXC 0.0

VFI21 IXA IXB 0.0

VFI22 N22 N24 0.0

VFI23 N23 N24 0.0

VFI24 ZB2 ZB3 0.0

VFI25 ZB1 ZB2 0.0

VFI26 N13 N14 0.0

VF127 N12 N14 0.0

VFI28 ZB9 VEE 0.0

VFI29 ZIN N26 0.0

VF15 N30 N32 0.0

VFI6 N31 N32 0.0

VFI7 N33 0 0.0

VFI8 ZB8 N43 0.0

VFI9 ZB7 N40 0.0

.ENDS

EL4083