LMH6552 www.ti.com SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 1.5 GHz Fully Differential Amplifier Check for Samples: LMH6552 FEATURES DESCRIPTION 1 * 2 * * * * * * * The LMH6552 is a high performance fully differential amplifier designed to provide the exceptional signal fidelity and wide large-signal bandwidth necessary for driving 8 to 14 bit high speed data acquisition systems. Using TI's proprietary differential current mode input stage architecture, the LMH6552 allows operation at gains greater than unity without sacrificing response flatness, bandwidth, harmonic distortion, or output noise performance. 1.5 GHz -3 dB Small Signal Bandwidth @ AV = 1 1.25 GHz -3 dB Large Signal Bandwidth @ AV = 1 800 MHz Bandwidth @ AV = 4 450 MHz 0.1 dB Flatness 3800 V/s Slew Rate 10 ns Settling Time to 0.1% - -90 dB THD @ 20 MHz - -74 dB THD @ 70 MHz 20 ns Enable/Shutdown Pin 5 to 12V Operation With external gain set resistors and integrated common mode feedback, the LMH6552 can be configured as either a differential input to differential output or single ended input to differential output gain block. The LMH6552 can be AC or DC coupled at the input which makes it suitable for a wide range of applications including communication systems and high speed oscilloscope front ends. The performance of the LMH6552 driving an ADC14DS105 is 86 dBc SFDR and 74 dBc SNR up to 40 MHz. APPLICATIONS * * * * * * * * Differential ADC Driver Video Over Twisted Pair Differential Line Driver Single End to Differential Converter High Speed Differential Signaling IF/RF Amplifier Level Shift Amplifier SAW Filter Buffer/Driver The LMH6552 is available in an 8-pin SOIC package as well as a space saving, thermally enhanced 8-Pin WSON package for higher performance. Typical Application 274: 50: Single-Ended AC-coupled Source V 127: 68.1: - 127: 49.9: 0.1 PF 100: 620 nH + LMH6552 + ADC14DS105 + 22 pF V - 100: 620 nH 14-Bit 105 MSPS VREF 68.1: 274: Figure 1. Single-Ended Input Differential Output ADC Driver 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2007-2013, Texas Instruments Incorporated LMH6552 SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings ESD Tolerance (1) (2) Human Body Model 2000V Machine Model 200V Supply Voltage 13.2V Common Mode Input Voltage VS Maximum Input Current (pins 1, 2, 7, 8) 30 mA (3) Maximum Output Current (pins 4, 5) Maximum Junction Temperature 150C Soldering Information For soldering specifications see SNOA549C (1) (2) (3) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical Characteristics tables. Human Body Model, applicable std. MIL-STD-883, Method 30157. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). The maximum output current (IOUT) is determined by device power dissipation limitations. See POWER DISSIPATION of Application Information for more details. Operating Ratings (1) Operating Temperature Range (2) -40C to +85C -65C to +150C Storage Temperature Range Total Supply Voltage 4.5V to 12V Package Thermal Resistance (JA) 8-Pin SOIC 150C/W 8-Pin WSON (1) (2) 2 58C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical Characteristics tables. The maximum power dissipation is a function of TJ(MAX), JA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX)- TA) / JA. All numbers apply for packages soldered directly onto a PC Board. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 5V Electrical Characteristics (1) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = +5V, V- = -5V, AV= 1, VCM = 0V, RF = RG = 357, RL = 500, for single ended in, differential out. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units AC Performance (Differential) SSBW LSBW Small Signal -3 dB Bandwidth (2) Large Signal -3 dB Bandwidth VOUT = 0.2 VPP, AV = 1, RL = 1 k 1500 VOUT = 0.2 VPP, AV = 1 1000 VOUT = 0.2 VPP, AV = 2 930 VOUT = 0.2 VPP, AV = 4 810 VOUT = 0.2 VPP, AV = 8 590 VOUT = 2 VPP, AV = 1, RL = 1 k 1250 VOUT = 2 VPP, AV = 1 950 VOUT = 2 VPP, AV = 2 820 VOUT = 2 VPP, AV = 4 740 VOUT = 2 VPP, AV = 8 590 MHz MHz 0.1 dB Bandwidth VOUT = 0.2 VPP, AV = 1 450 MHz Slew Rate 4V Step, AV = 1 3800 V/s Rise/Fall Time, 10%-90% 2V Step 600 ps 0.1% Settling Time 2V Step 10 ns Overdrive Recovery Time VIN = 1.8V to 0V Step, AV = 5 V/V 6 ns Distortion and Noise Response HD2 HD3 IMD3 2nd Harmonic Distortion VOUT = 2 VPP, f = 20 MHz, RL = 800 -92 VOUT = 2 VPP, f = 70 MHz, RL = 800 -74 VOUT = 2 VPP, f = 20 MHz, RL = 800 -93 VOUT = 2 VPP, f = 70 MHz, RL = 800 -84 Two-Tone Intermodulation f 70 MHz, Third Order Products, VOUT = 2 VPP Composite -87 dBc Input Noise Voltage f 1 MHz 1.1 nV/Hz Input Noise Current f 1 MHz 19.5 pA/Hz Noise Figure (See Figure 48) 50 System, AV = 9, 10 MHz 10.3 dB 3rd Harmonic Distortion dBc dBc Input Characteristics (4) IBI Input Bias Current 60 110 A IBoffset Input Bias Current Differential VCM = 0V, VID = 0V, IBoffset = (IB - IB )/2 2.5 18 A CMRR Common Mode Rejection Ratio RIN Input Resistance DC, VCM = 0V, VID = 0V 80 dBc Differential 15 CIN Input Capacitance Differential CMVR Input Common Mode Voltage Range CMRR > 38 dB 3.5 0.5 pF 3.8 V - (3) (3) + Output Performance IOUT (1) (2) (3) (4) Output Voltage Swing (3) Differential Output 14.8 15.4 VPP Linear Output Current (3) VOUT = 0V 70 80 mA Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. See Application Information for information on temperature de-rating of this device." Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. IBI is referred to a differential output offset voltage by the following relationship: VOD(offset) = IBI*2RF Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 3 LMH6552 SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 www.ti.com 5V Electrical Characteristics (1) (continued) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = +5V, V- = -5V, AV= 1, VCM = 0V, RF = RG = 357, RL = 500, for single ended in, differential out. Boldface limits apply at the temperature extremes. Symbol ISC Parameter Conditions Min (2) Typ (3) Max (2) Units Short Circuit Current One Output Shorted to Ground VIN = 2V Single Ended (5) 141 mA Output Balance Error VOUT Common Mode /VOUT Differential, VOD = 1V, f < 1 MHz -60 dB dB Miscellaneous Performance ZT Open Loop Transimpedance Differential 108 PSRR Power Supply Rejection Ratio DC, (V+ - |V-|) = 1V 80 IS Supply Current (3) RL = 19 Enable Voltage Threshold dB 22.5 mA 3.0 V Disable Voltage Threshold ISD 25 28 2.0 Enable/Disable time 15 Disable Shutdown Current 500 V ns 600 A Output Common Mode Control Circuit VOSCM Common Mode Small Signal Bandwidth VIN+ = VIN- = 0 400 Slew Rate VIN+ = VIN- = 0 607 Input Offset Voltage Common Mode, VID = 0, VCM = 0 1.5 16.5 mV -3.2 8 A (6) Input Bias Current Voltage Range 3.7 CMRR Measure VOD, VID = 0V Input Resistance VO,CM/VCM Gain (5) (6) 0.995 MHz V/s 3.8 V 80 dB 200 k 1.0 1.012 V/V Short circuit current should be limited in duration to no more than 10 seconds. See POWER DISSIPATION of Application Information for more details. Negative input current implies current flowing out of the device. 2.5V Electrical Characteristics (1) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = +2.5V, V- = -2.5V, AV = 1, VCM = 0V, RF = RG = 357, RL = 500, for single ended in, differential out. Boldface limits apply at the temperature extremes. Symbol SSBW LSBW (1) (2) (3) 4 Parameter Small Signal -3 dB Bandwidth Large Signal -3 dB Bandwidth Conditions (2) Min (2) Typ (3) VOUT = 0.2 VPP, AV = 1, RL = 1 k 1100 VOUT = 0.2 VPP, AV = 1 800 VOUT = 0.2 VPP, AV = 2 740 VOUT = 0.2 VPP, AV = 4 660 VOUT = 0.2 VPP, AV = 8 498 VOUT = 2 VPP, AV = 1, RL = 1 k 820 VOUT = 2 VPP, AV = 1 690 VOUT = 2 VPP, AV = 2 620 VOUT = 2 VPP, AV = 4 589 VOUT = 2 VPP, AV = 8 480 Max (2) Units MHz MHz Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. See Application Information for information on temperature de-rating of this device." Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Limits are 100% production tested at 25C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 2.5V Electrical Characteristics (1) (continued) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = +2.5V, V- = -2.5V, AV = 1, VCM = 0V, RF = RG = 357, RL = 500, for single ended in, differential out. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units 0.1 dB Bandwidth VOUT = 0.2 VPP, AV = 1 300 MHz Slew Rate 2V Step, AV = 1 2100 V/s Rise/Fall Time, 10% to 90% 2V Step 700 ps 0.1% Settling Time 2V Step 10 ns Overdrive Recovery Time VIN = 0.7 V to 0 V Step, AV = 5 V/V 6 ns Distortion and Noise Response HD2 HD3 IMD3 2nd Harmonic Distortion VOUT = 2 VPP, f = 20 MHz, RL = 800 -82 VOUT = 2 VPP, f = 70 MHz, RL = 800 -65 VOUT = 2 VPP, f = 20 MHz, RL = 800 -79 VOUT = 2 VPP, f = 70 MHz, RL = 800 -67 Two-Tone Intermodulation f 70 MHz, Third Order Products, VOUT = 2 VPP Composite -77 dBc Input Noise Voltage f 1 MHz 1.1 nV/Hz Input Noise Current f 1 MHz 19.5 pA/Hz Noise Figure (See Figure 48) 50 System, AV = 9, 10 MHz 10.2 dB 54 90 A VCM = 0V, VID = 0V, IBoffset = (IB- - IB+ )/2 2.3 18 A 3rd Harmonic Distortion dBc dBc Input Characteristics (4) IBI Input Bias Current IBoffset Input Bias Current Differential CMRR Common-Mode Rejection Ratio DC, VCM = 0V, VID = 0V 75 RIN Input Resistance Differential 15 CIN Input Capacitance Differential 0.5 pF CMVR Input Common Mode Range CMRR > 38 dB 1.0 1.3 V 6.0 VPP (3) (3) dBc Output Performance Output Voltage Swing (5) Differential Output 5.6 IOUT Linear Output Current (5) VOUT = 0V 55 ISC Short Circuit Current One Output Shorted to Ground, VIN = 2V Single Ended (6) Output Balance Error 65 mA 131 mA VOUT Common Mode /VOUT Differential, VOD = 1V, f < 1 MHz 60 dB 107 dB Miscellaneous Performance ZT Open Loop Transimpedance Differential PSRR Power Supply Rejection Ratio DC, VS = 1V IS Supply Current (5) RL = Enable Voltage Threshold 80 17 20.4 3.0 mA V Disable Voltage Threshold ISD dB 24 27 2.0 Enable/Disable Time 15 Disable Shutdown Current 500 V ns 600 A Output Common Mode Control Circuit (4) (5) (6) Common Mode Small Signal Bandwidth VIN+ = VIN- = 0 310 MHz Slew Rate VIN+ = VIN- = 0 430 V/s IBI is referred to a differential output offset voltage by the following relationship: VOD(offset) = IBI*2RF Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Short circuit current should be limited in duration to no more than 10 seconds. See POWER DISSIPATION of Application Information for more details. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 5 LMH6552 SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 www.ti.com 2.5V Electrical Characteristics (1) (continued) Unless otherwise specified, all limits are ensured for TA = 25C, V+ = +2.5V, V- = -2.5V, AV = 1, VCM = 0V, RF = RG = 357, RL = 500, for single ended in, differential out. Boldface limits apply at the temperature extremes. Symbol VOSCM Parameter Input Offset Voltage Input Bias Current Conditions Min Common Mode, VID = 0, VCM = 0 (7) Input Resistance (7) (3) Max (2) 15 -2.9 1.19 Measure VOD, VID = 0V VO,CM/VCM Gain Typ 1.65 Voltage Range CMRR (2) 0.995 Units mV A 1.25 V 80 dB 200 k 1.0 1.012 V/V Negative input current implies current flowing out of the device. CONNECTION DIAGRAM 1 8 +IN -IN - 2 + 7 VCM 3 6 4 5 EN V- V+ +OUT -OUT Figure 2. 8-Pin SOIC-Top View See Package Number D0008A - IN 1 8 + IN VCM 2 7 EN V+ 3 6 V- + OUT 4 5 - OUT DAP Figure 3. 8-Pin WSON-Top View See Package Number NGS0008C PIN DESCRIPTIONS Pin No. 6 Pin Name Description 1 -IN Negative Input 2 VCM Output Common Mode Control 3 V+ Positive Supply 4 +OUT Positive Output 5 -OUT Negative Output 6 V- Negative Supply 7 EN Enable 8 +IN Positive Input DAP DAP Die Attach Pad (See THERMAL PERFORMANCE for more information) Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 Typical Performance Characteristics V+ = +5V, V- = -5V (TA = 25C, RF = RG = 357, RL = 500, AV = 1, for single ended in, differential out, unless specified). Frequency Response vs. Gain Frequency Response vs. Gain 1 0 -1 -2 AV = 4 AV = 2 -3 -4 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 1 AV = 1 0 AV = 8 -5 -6 -7 VOUT = 0.2 VPP -8 -1 -3 AV = 4 -4 -5 AV = 2 -6 -7 VOUT = 0.2 VPP -8 DIFFERENTIAL INPUT -9 1 SINGLE-ENDED INPUT 10 100 1000 FREQUENCY (MHz) -9 10000 1000 Frequency Response vs. VOUT Frequency Response vs. VOUT 1 VOD = 0.5 VPP 10000 VOD = 0.5 VPP 0 NORMALIZED GAIN (dB) -1 VOD = 2 VPP -3 -4 VOD = 4 VPP -5 -6 V+ = +5V - -7 V = -5V -8 AV = 2 V/V DIFFERENTIAL INPUT -9 1 10 100 1000 -1 -2 -4 VOD = 4 VPP -5 + -6 V = +5V -7 V = -5V -8 AV = 2 V/V SINGLE-ENDED INPUT -9 10000 VOD = 2 VPP -3 - 1 FREQUENCY (MHz) Frequency Response vs. Supply Voltage Frequency Response vs. Supply Voltage 1 V = -5V RL = 500: RF = 357: + V = +2.5V - -3 V = -2.5V -4 RL = 500: -5 RF = 357: VOD = 0.2 VPP AV = 1 V/V 100 0 + -1 V = +2.5V -2 V = -2.5V -3 RL = 1 k: -4 RF = 301: - + -5 V = +5V -6 V = -5V -7 RL = 1 k: - -8 DIFFERENTIAL INPUT 10 AV = 1 V/V DIFFERENTIAL INPUT 1 NORMALIZED GAIN (dB) 0 -1 VOD = 0.2 VPP 2 - -2 10000 3 + 1 1000 Figure 7. V = +5V -7 100 FREQUENCY (MHz) 2 -6 10 Figure 6. 3 NORMALIZED GAIN (dB) 100 Figure 5. -2 -9 10 Figure 4. 1 NORMALIZED GAIN (dB) 1 FREQUENCY (MHz) 0 -8 AV = 1 AV = 8, RF = 400: -2 1000 10000 -9 RF = 301: 1 10 100 1000 10000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 8. Figure 9. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 7 LMH6552 SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics V+ = +5V, V- = -5V (continued) (TA = 25C, RF = RG = 357, RL = 500, AV = 1, for single ended in, differential out, unless specified). Frequency Response vs. Capacitive Load Suggested ROUT vs. Capacitive Load 30 1 -1 CL = 82 pF, RO = 16: -2 SUGGESTED RO (:) NORMALIZED GAIN (dB) 0 CL = 39 pF, RO = 21: -3 CL = 15 pF, RO = 24: -4 CL = 5.6 pF, RO = 23: -5 -6 VOD = 200 mVPP 10 + -7 AV = 1 LOAD = (CL || 1 k:) IN -8 SERIES WITH 2 ROUTS -9 1 10 100 V = +5V - V = -5V LOAD = 1 k: || CAP LOAD 0 1000 10 1 CAPACITIVE LOAD (pF) Figure 10. Figure 11. Frequency Response vs. Resistive Load Frequency Response vs. Resistive Load 1 1 RL = 1 k: NORMALIZED GAIN (dB) RL = 200: -1 RL = 500: -2 RL = 800: -3 -4 V+ = +5V -5 V = -5V -6 AV = 1 V/V RF = 357: -7 VOUT = 0.2 VPP -8 SINGLE-ENDED INPUT -9 1 10 100 RL = 1 k: 0 RL = 200: -1 RL = 500: -2 RL = 800: -3 -4 + V = +5V -5 V- = -5V -6 AV = 1 V/V -7 RF = 357: VOUT = 2 VPP -8 SINGLE-ENDED INPUT 1000 -9 10000 1 10 FREQUENCY (MHz) 1000 10000 Figure 12. Figure 13. Frequency Response vs. RF 1 VPP Pulse Response Single Ended Input 0.8 RF = 301: 1 0.6 0 0.4 -1 RF = 357: -2 0.2 RF = 400: -3 VOD (V) NORMALIZED GAIN (dB) 100 FREQUENCY (MHz) 2 + -4 V = +5V -5 V = -5V -6 -9 + V = +2.5V VOUT = 2 VPP RL = 1 k: -8 0 -0.2 AV = 1 V/V -7 - -0.4 V = -2.5V -0.6 RL = 500: RF = 357: DIFFERENTIAL INPUT 1 10 100 1000 10000 FREQUENCY (MHz) -0.8 0 5 10 15 20 25 30 35 40 45 50 TIME (ns) Figure 14. 8 100 FREQUENCY (MHz) 0 NORMALIZED GAIN (dB) 20 Figure 15. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 Typical Performance Characteristics V+ = +5V, V- = -5V (continued) (TA = 25C, RF = RG = 357, RL = 500, AV = 1, for single ended in, differential out, unless specified). 2 VPP Pulse Response Single Ended Input Large Signal Pulse Response 1.5 2.5 2 1 1.5 1 VOD (V) VOD (V) 0.5 0 0.5 0 -0.5 + + -0.5 V = +5 V = -5V -1 0 5 RL = 500: -2 -2.5 10 15 20 25 30 35 40 45 50 RF = 357: 0 5 10 15 20 25 30 35 40 45 50 TIME (ns) TIME (ns) Figure 16. Figure 17. Output Common Mode Pulse Response Distortion vs. Frequency Single Ended Input 80 -50 V+ = +5V -55 V- = -5V -60 RL = 800O VOD = 2 VPP -65 VOCM = 0V 60 40 DISTORTION (dBc) COMMON MODE VOUT (mV) - V = -5V -1.5 RL = 500: RF = 357: -1.5 V = +5V -1 - 20 0 + V = +5V -20 - V = -5V -40 RL = 500: -60 RL = 357: 0 5 -70 -75 HD3 -80 -85 -90 -95 -100 VOD = 2 VPP -80 HD2 10 15 20 25 30 35 40 45 50 -105 1 25 50 75 100 125 150 175 200 225 250 TIME (ns) FREQUENCY (MHz) Figure 18. Figure 19. Distortion vs. Supply Voltage Distortion vs. Supply Voltage -20 RL = 800: VOUT = 2 VPP -30 DISTORTION (dBc) fc = 75 MHz -40 -50 HD2 -60 -70 -80 HD3 -90 3 5 7 9 11 12 TOTAL SUPPLY VOLTAGE (V) Figure 20. Figure 21. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 9 LMH6552 SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics V+ = +5V, V- = -5V (continued) (TA = 25C, RF = RG = 357, RL = 500, AV = 1, for single ended in, differential out, unless specified). Distortion vs. Output Common Mode Voltage -40 Distortion vs. Output Common Mode Voltage -40 + + V = +5V - - -50 V = -5V -60 VOUT = 2 VPP V = -5V -50 RL = 800: DISTORTION (dBc) fc = 20 MHz -70 HD2 -80 RL = 800: VOUT = 2 VPP -60 fc = 75 MHz HD2 -70 -80 -90 HD3 HD3 -100 -90 0.5 0 1 1.5 2 2.5 0.5 0 3 1 Maximum VOUT vs. IOUT Minimum VOUT vs. IOUT -2 -2.2 3.6 -2.4 MINIMUM VOUT (V) MAXIMUM VOUT (V) Figure 23. 4 3.4 3.2 3 2.8 + 2.6 V = +5V V = -5V 2.4 RF = 357: 2.2 V = 3.8V SINGLE-ENDED INPUT -10 -20 -30 -40 50 60 + - V = -5V RF = 357: -2.6 VIN = 3.8V SINGLE-ENDED -2.8 3 -3.2 -3.4 -3.8 -50 -4 -60 0 10 20 30 40 OUTPUT CURRENT (mA) Figure 24. Figure 25. Open Loop Transimpedance Open Loop Transimpedance 120 120 110 MAGNITUDE 100 PHASE () 90 0 80 PHASE -45 70 -90 60 + 50 V = +5V V = -5V 40 0.01 0.1 -135 1 10 100 -180 1000 MAGNITUDE, |Z| (dB :) 110 MAGNITUDE, |Z| (dB :) 3 V = +5V OUTPUT CURRENT (mA) MAGNITUDE 100 90 0 80 PHASE -45 70 -90 60 + 50 V = +2.5V V = -2.5V 40 0.01 0.1 FREQUENCY (MHz) -135 1 10 100 -180 1000 FREQUENCY (MHz) Figure 26. 10 2.5 -3.6 IN 0 2 Figure 22. 3.8 2 1.5 VOCM (V) VOCM (V) PHASE () DISTORTION (dBc) V = +5V Figure 27. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 Typical Performance Characteristics V+ = +5V, V- = -5V (continued) (TA = 25C, RF = RG = 357, RL = 500, AV = 1, for single ended in, differential out, unless specified). Closed Loop Output Impedance 1000 Closed Loop Output Impedance 1000 + V = +5V 100 V- = -5V 10 - 100 VIN = 0V AV = 1 V/V V = -2.5 VIN = 0V AV = 1 V/V 10 |Z| (:) 1 |Z| (:) + V = +2.5V 0.1 1 0.01 0.1 0.001 10 1 0.1 100 0.01 0.01 1000 0.1 Figure 28. Overdrive Recovery Overdrive Recovery INPUT 2 0.4 0 0 + -0.4 -2 V = +5V -4 V = -5V -0.8 -6 AV = 5 V/V -1.2 - RF = 324: -8 RL = 200: -10 0 200 400 600 800 -1.6 -2 1000 OUTPUT VOLTAGE (VOD) 0.8 INPUT VOLTAGE (V) 1.2 OUTPUT 0.8 INPUT 1.6 6 OUTPUT VOLTAGE (VOD) 4 2 4 3 0.6 2 0.4 OUTPUT 1 0 + V = +2.5V -1 - -2 -3 0 200 -0.6 400 600 800 -0.8 1000 Figure 31. PSRR 90 -100 PSRR (dBc DIFFERENTIAL) PSRR (dBc DIFFERENTIAL) RF = 324: TIME (ns) -110 80 +PSRR 70 60 -PSRR 50 40 V+ = +5V 30 V- = -5V VIN = 0V 0 1 0.1 -0.4 -4 PSRR 10 AV = 5 V/V RL = 200: 100 RL = 500: -0.2 V = -2.5V Figure 30. AV = 2 V/V 0.2 0 TIME (ns) 20 1000 100 Figure 29. 10 8 10 1 FREQUENCY (MHz) FREQUENCY (MHz) INPUT VOLTAGE (V) 0.0001 0.01 -90 -80 -PSRR -70 +PSRR -60 -50 -40 -30 -20 -10 + V = +2.5V - V = -2.5V AV = 2 V/V RL = 500: VIN = 0V 0 10 100 1000 0.1 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 32. Figure 33. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 11 LMH6552 SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics V+ = +5V, V- = -5V (continued) (TA = 25C, RF = RG = 357, RL = 500, AV = 1, for single ended in, differential out, unless specified). CMRR Balance Error 85 80 -10 -15 BALANCE ERROR (dBc) 75 70 65 CMRR (dB) 60 55 50 45 40 AV = 2 V/V 35 RL = 500: 30 R = 357: F 25 VOUT = 1.0 VPP 20 0.1 10 1 100 1000 + -20 V = +2.5V -25 V = -2.5V - -30 -35 + -40 V = +5V -45 V = -5V - -50 -55 RL = 500: -60 -65 -70 AV = 1 V/V RF = 357: 10 1 Figure 34. Figure 35. Noise Figure Noise Figure 15 + + V = +5V V = +2.5V - AV = 9 V/V RF = 275: 50: SYSTEM 13 12 AV = 9 V/V RF = 275: 50: SYSTEM 13 12 11 11 10 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (MHz) FREQUENCY (MHz) Figure 36. Figure 37. Input Noise vs. Frequency Differential S-Parameter Magnitude vs. Frequency 6 210 5 175 NOISE VOLTAGE 140 4 INVERTING CURRENT NOISE CURRENT 105 2 NON-INVERTING CURRENT 70 NOISE CURRENT 1 35 0 -10 MAGNITUDE (dB) 0 CURRENT NOISE (pA/ Hz) VOLTAGE NOISE (nV/ Hz) V = -2.5V 14 NOISE FIGURE (dB) NOISE FIGURE (dB) - V = -5V 14 3 S21 S22 S11 -20 (SINGLE-ENDED INPUT) -30 -40 S11 -50 -60 S12 0 0.0001 0.001 0.01 0.1 1 10 + V = +5V - V = -5V -70 AV = 1 V/V 0 100 -80 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 38. 12 1000 FREQUENCY (MHz) 15 10 100 FREQUENCY (MHz) Figure 39. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 Typical Performance Characteristics V+ = +5V, V- = -5V (continued) (TA = 25C, RF = RG = 357, RL = 500, AV = 1, for single ended in, differential out, unless specified). Differential S-Parameter Phase vs. Frequency 3rd Order Intermodulation Products vs. VOUT -20 400 300 S11 V = +5V - IMD 3 (dBc) V = -5V AV = 1 V/V S22 100 S12 0 - V = -5V -40 RF = 357: + 200 PHASE () + V = +5V -30 -50 AV = 2 V/V RL = 200: -60 -70 -80 -100 RL = 800: -90 S11 (SINGLE-ENDED INPUT) -200 -100 S21 -110 -300 10 100 1000 fc = 75 MHz (200 kHz SPACING) SINGLE-ENDED INPUT 0 2 3 4 5 6 7 FREQUENCY (MHz) DIFFERENTIAL VOUT (VPP) Figure 40. Figure 41. 3rd Order Intermodulation Products vs. VOUT 3rd Order Intermodulation Products vs. Center Frequency -20 -65 + V = +2.5V -30 - -60 RL = 800: -70 -80 + V = +2.5V - V = -2.5V -75 VOD = 2 VPP AV = 2 V/V IMD 3 (dBc) -50 RL = 800: -70 RF = 360: AV = +2 V = -2.5V -40 RF = 357: IMD 3 (dBc) 1 RL = 200: -80 -85 + -90 V = +5V -90 - -100 fc = 75 MHz (200 kHz SPACING) SINGLE-ENDED INPUT -110 0 1 2 3 4 5 6 7 DIFFERENTIAL VOUT (VPP) -95 SINGLE-ENDED INPUT 200 kHz SPACING -100 50 60 70 80 V = -5V 90 100 CENTER FREQUENCY (MHz) Figure 42. Figure 43. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 13 LMH6552 SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 www.ti.com APPLICATION INFORMATION The LMH6552 is a fully differential current feedback amplifier with integrated output common mode control, designed to provide low distortion amplification to wide bandwidth differential signals. The common mode feedback circuit sets the output common mode voltage independent of the input common mode, as well as forcing the V+ and V- outputs to be equal in magnitude and opposite in phase, even when only one of the inputs is driven as in single to differential conversion. The proprietary current feedback architecture of the LMH6552 offers gain and bandwidth independence with exceptional gain flatness and noise performance, even at high values of gain, simply with the appropriate choice of RF1 and RF2. Generally RF1 is set equal to RF2, and RG1 equal to RG2, so that the gain is set by the ratio RF/RG. Matching of these resistors greatly affects CMRR, DC offset error, and output balance. A minimum of 0.1% tolerance resistors are recommended for optimal performance, and the amplifier is internally compensated to operate with optimum gain flatness with values of RF between 270 and 390 depending on package selection, PCB layout, and load resistance. The output common mode voltage is set by the VCM pin with a fixed gain of 1 V/V. This pin should be driven by a low impedance reference and should be bypassed to ground with a 0.1 F ceramic capacitor. Any unwanted signal coupling into the VCM pin will be passed along to the outputs, reducing the performance of the amplifier. This pin must not be left floating. The LMH6552 can be operated on a supply range as either a single 5V supply or as a split +5V and -5V. Operation on a single 5V supply, depending on gain, is limited by the input common mode range; therefore, AC coupling may be required. For example, in a DC coupled input application on a single 5V supply, with a VCM of 1.5V, the input common voltage at a gain of 1 will be 0.75V which is outside the minimum 1.2V to 3.8V input common mode range of the amplifier. The minimum VCM for this application should be greater than 2.5V depending on output signal swing. Alternatively, AC coupling of the inputs in this example results in equal input and output common mode voltages, so a 1.5V VCM would be achievable. Split supplies will allow much less restricted AC and DC coupled operation with optimum distortion performance. The LMH6552 is equipped with an ENABLE pin to reduce power consumption when not in use. The ENABLE pin, when not driven, floats high (on). When the ENABLE pin is pulled low the amplifier is disabled and the amplifier output stage goes into a high impedance state so the feedback and gain set resistors determine the output impedance of the circuit. For this reason input to output isolation will be poor in the disabled state and the part is not recommended in multiplexed applications where outputs are all tied together. WSON PACKAGE Due to it's size and lower parasitics, the WSON requires the lower optimum value of 275 for RF. This will give a flat frequency response with minimal peaking. With a lower RF value the WSON package will have a reduction in noise compared to the SOIC with its optimum RF = 360. FULLY DIFFERENTIAL OPERATION The LMH6552 will perform best in a fully differential configuration. The circuit shown in Figure 44 is a typical fully differential application circuit as might be used to drive an analog to digital converter (ADC). In this circuit the closed loop gain AV = VOUT/ VIN = RF/RG, where the feedback is symmetric. The series output resistors, RO, are optional and help keep the amplifier stable when presented with a capacitive load. Refer to DRIVING CAPACITIVE LOADS for details. 14 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 RF RO RG VS + CL VCM a RL VO RG RO RF ENABLE Figure 44. Typical Application When driven from a differential source, the LMH6552 provides low distortion, excellent balance, and common mode rejection. This is true provided the resistors RF, RG and RO are well matched and strict symmetry is observed in board layout. With an intrinsic device CMRR of 80 dB, using 0.1% resistors will give a worst case CMRR of around 60 dB for most circuits. 357: 50: 58: RS = 50: VS 357: VCM a + RL RS = 50: 58: 357: ENABLE 50: 357: Figure 45. Differential S-Parameter Test Circuit The circuit configuration shown in Figure 45 was used to measure differential S parameters in a 50 environment at a gain of 1 V/V. Refer to Figure 39 and Figure 40 in Typical Performance Characteristics V+ = +5V, V- = -5V for measurement results. SINGLE ENDED INPUT TO DIFFERENTIAL OUTPUT OPERATION In many applications, it is required to drive a differential input ADC from a single ended source. Traditionally, transformers have been used to provide single to differential conversion, but these are inherently bandpass by nature and cannot be used for DC coupled applications. The LMH6552 provides excellent performance as a single-to-differential converter down to DC. Figure 46 shows a typical application circuit where an LMH6552 is used to produce a differential signal from a single ended source. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 15 LMH6552 SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 www.ti.com RF AV, RIN V RS + RG RO + VS a VCM RT - + - ADC + - IN+ RO RG RM IN- VO LMH6552 V - RF (c) RG E1 = R + R G F (c) (c) 2(1 - E1) AV = (c) E1 + E2 (c) (c) 2RG + RM (1-E2) RIN = 1 + E2 (c) RG + RM E2 = R + R + R F M (c) G RS = RT || RIN RM = RT || RS Figure 46. Single Ended Input with Differential Output When using the LMH6552 in single-to-differential mode, the complimentary output is forced to a phase inverted replica of the driven output by the common mode feedback circuit as opposed to being driven by its own complimentary input. Consequently, as the driven input changes, the common mode feedback action results in a varying common mode voltage at the amplifier's inputs, proportional to the driving signal. Due to the non-ideal common mode rejection of the amplifier's input stage, a small common mode signal appears at the outputs which is superimposed on the differential output signal. The ratio of the change in output common mode voltage to output differential voltage is commonly referred to as output balance error. The output balance error response of the LMH6552 over frequency is shown in Typical Performance Characteristics. To match the input impedance of the circuit in Figure 46 to a specified source resistance, RS, requires that RT || RIN = RS. The equations governing RIN and AV for single-to-differential operation are also provided in Figure 46. These equations, along with the source matching condition, must be solved iteratively to achieve the desired gain with the proper input termination. Component values for several common gain configurations in a 50 environment are given in Table 2. Gain Component Values for 50 System WSON Package. Typically RS=50 while RM=RS||RT. Table 2. Gain Component Values for 50 System WSON Package Gain RF RG RT RM 0 dB 275 255 59 26.7 6 dB 275 127 68.1 28.7 12 dB 275 54.9 107 34 357: 50: 348: RS = 50: VS a 56.2: VCM + RL 348: 26.4: ENABLE 50: 357: Figure 47. Single Ended Input S-Parameter Test Circuit (50 System) 16 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 The circuit shown in Figure 47 was used to measure S-parameters for a single-to-differential configuration. Figure 39 and Figure 40 in Typical Performance Characteristics are taken using the recommended component values for 0 dB gain. SINGLE SUPPLY OPERATION Single supply operation is possible on supplies from 5V to 10V; however, as discussed earlier, AC input coupling is recommended for low supplies such as 5V due to input common mode limitations. An example of an AC coupled, single supply, single-to-differential circuit is shown in Figure 48. Note that when AC coupling, both inputs need to be AC coupled irrespective of single-to-differential or differential-to-differential configuration. For higher supply voltages DC coupling of the inputs may be possible provided that the output common mode DC level is set high enough so that the amplifier's inputs and outputs are within their specified operating ranges. RF RO RG RS VS VO1 VI1 + a RT RL CL VCM VO RG RM VI2 VO2 RO RF ENABLE *VCM = VO1 + VO2 2 *BY DESIGN VICM = VOCM VICM = VI1 + VI2 2 Figure 48. AC Coupled for Single Supply Operation SPLIT SUPPLY OPERATION For optimum performance, split supply operation is recommended using +5V and -5V supplies; however, operation is possible on split supplies as low as +2.25V and -2.25V and as high as +6V and -6V. Provided the total supply voltage does not exceed the 4.5V to 12V operating specification, non-symmetric supply operation is also possible and in some cases advantageous. For example, if a 5V DC coupled operation is required for low power dissipation but the amplifier input common mode range prevents this operation, it is still possible with split supplies of (V+) and (V-). Where (V+) - (V-) = 5V and V+ and V- are selected to center the amplifier input common mode range to suit the application. OUTPUT NOISE PERFORMANCE AND MEASUREMENT Unlike differential amplifiers based on voltage feedback architectures, noise sources internal to the LMH6552 refer to the inputs largely as current sources, hence the low input referred voltage noise and relatively higher input referred current noise. The output noise is therefore more strongly coupled to the value of the feedback resistor and not to the closed loop gain, as would be the case with a voltage feedback differential amplifier. This allows operation of the LMH6552 at much higher gain without incurring a substantial noise performance penalty, simply by choosing a suitable feedback resistor. Figure 49 shows a circuit configuration used to measure noise figure for the LMH6552 in a 50 system. An RF value of 275 is chosen for the SOIC package to minimize output noise while simultaneously allowing both high gain (9 V/V) and proper 50 input termination. Refer to SINGLE ENDED INPUT TO DIFFERENTIAL OUTPUT OPERATION for calculation of resistor and gain values. Noise figure values at various frequencies are shown Figure 36 in Typical Performance Characteristics. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 17 LMH6552 SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 www.ti.com 275: V RS = 50: 1 PF 2:1 (TURNS) 10: VCM a VS + + - + 10: 50: 50: VO LMH6552 1 PF V - 275: AV = 9 V/V Figure 49. Noise Figure Circuit Configuration DRIVING ANALOG TO DIGITAL CONVERTERS Analog-to-digital converters present challenging load conditions. They typically have high impedance inputs with large and often variable capacitive components. As well, there are usually current spikes associated with switched capacitor or sample and hold circuits. Figure 50 shows a combination circuit of the LMH6552 driving the ADC12DL080. The two 125 resistors serve to isolate the capacitive loading of the ADC from the amplifier and ensure stability. In addition, the resistors, along with a 2.2 pF capacitor across the outputs (in parallel with the ADC input capacitance), form a low pass anti-aliasing filter with a pole frequency of about 60 MHz. For switched capacitor input ADCs, the input capacitance will vary based on the clock cycle, as the ADC switches between the sample and hold mode. See your particular ADC's datasheet for details. 357: 50: Single-Ended AC-coupled Source V 169: 61.8: + LMH6552 CIN 2.2 pF - ~ 7- 8 pF 125: 169: 61.8: 12-Bit 80 MSPS 125: + 49.9: ADC12DL080 + V VREF - 0.1 PF 357: Figure 50. Driving a 12-bit ADC Figure 51 shows the SFDR and SNR performance vs. frequency for the LMH6552 and ADC12DL080 combination circuit with the ADC input signal level at -1 dBFS. The ADC12DL080 is a dual 12-bit ADC with maximum sampling rate of 80 MSPS. The amplifier is configured to provide a gain of 2 V/V in single to differential mode. An external band-pass filter is inserted in series between the input signal source and the amplifier to reduce harmonics and noise from the signal generator. In order to properly match the input impedance seen at the LMH6552 amplifier inputs, RM is chosen to match ZS || RT for proper input balance. 18 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 90 SFDR (dBc) 85 80 (dB) 75 70 65 SNR (dBFs) 60 55 50 0 5 10 15 20 25 30 35 40 INPUT FREQUENCY (MHz) Figure 51. LMH6552/ADC12DL080 SFDR and SNR Performance vs. Frequency Figure 52 shows a combination circuit of the LMH6552 driving the ADC14DS105. The ADC14DS105 is a dual channel 14-bit ADC with a sampling rate of 105 MSPS. The circuit in Figure 52 has a 2nd order low-pass LC filter formed by the 620 nH inductor along with the 22 pF capacitor across the differential outputs of the LMH6552. The filter has a pole frequency of about 50 MHz. Figure 53 shows the combined SFDR and SNR performance over frequency with a -1 dBFs input signal and a sampling rate of 1000 MSPS. 274: 50: Single-Ended AC-coupled Source V 127: 68.1: + 49.9: 100: 620 nH + LMH6552 127: ADC14DS105 + 22 pF V - 100: 620 nH 14-Bit 105 MSPS VREF 68.1: 0.1 PF 274: Figure 52. Driving a 14-bit ADC The amplifier is configured to provide a gain of 2 V/V in a single-to-differential mode. The LMH6552 common mode voltage is set by the ADC14DS105. Circuit testing is the same as described for the LMH6552 and ADC12DL080 combination circuit. The 0.1 F capacitor, in series with the 49.9 resistor, is inserted to ground across the 68.1 resistor to balance the amplifier inputs. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 19 LMH6552 SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 www.ti.com 100 95 SFDR (dBc) 90 85 (dB) 80 75 70 SNR (dBFs) 65 60 55 50 0 5 10 15 20 25 30 35 40 INPUT FREQUENCY (MHz) Figure 53. LMH6552/ADC14DS105 SFDR and SNR Performance vs. Frequency The amplifier and ADC should be located as close as possible. Both devices require that the filter components be in close proximity to them. The amplifier needs to have minimal parasitic loading on the output traces and the ADC is sensitive to high frequency noise that may couple in on its input lines. Some high performance ADCs have an input stage that has a bandwidth of several times its sample rate. The sampling process results in all input signals presented to the input stage mixing down into the first Nyquist zone (DC to Fs/2). The LMH6552 is capable of driving a variety of Texas Instruments Analog-to-Digital Converters. This is shown in TABLE 3. DIFFERENTIAL INPUT ADC's COMPATIBLE WITH LMH6552 DRIVER, which offers a list of possible signal path ADC and amplifier combinations. The use of the LMH6552 to drive an ADC is determined by the application and the desired sampling process (Nyquist operation, sub-sampling or over-sampling). See application note AN-236 for more details on the sampling processes and application note AN-1393 'Using High Speed Differential Amplifiers to Drive ADCs. For more information regarding a particular ADC, refer to the particular ADC datasheet for details. TABLE 3. DIFFERENTIAL INPUT ADC's COMPATIBLE WITH LMH6552 DRIVER Product Number Max Sampling Rate (MSPS) Resolution Channels ADC1173 15 8 SINGLE ADC1175 20 8 SINGLE ADC08351 42 8 SINGLE ADC1175-50 50 8 SINGLE ADC08060 60 8 SINGLE ADC08L060 60 8 SINGLE ADC08100 100 8 SINGLE ADC08200 200 8 SINGLE ADC08500 500 8 SINGLE ADC081000 1000 8 SINGLE ADC08D1000 1000 8 DUAL ADC10321 20 10 SINGLE ADC10D020 20 10 DUAL ADC10030 27 10 SINGLE ADC10040 40 10 DUAL ADC10065 65 10 SINGLE ADC10DL065 65 10 DUAL ADC10080 80 10 SINGLE ADC11DL066 66 11 DUAL 20 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com Product Number SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 Max Sampling Rate (MSPS) Resolution Channels ADC11L066 66 11 SINGLE ADC11C125 125 11 SINGLE ADC11C170 170 11 SINGLE ADC12010 10 12 SINGLE ADC12020 20 12 SINGLE ADC12040 40 12 SINGLE ADC12D040 40 12 DUAL ADC12DL040 40 12 DUAL ADC12DL065 65 12 DUAL ADC12DL066 66 12 DUAL ADC12L063 63 12 SINGLE ADC12C080 80 12 SINGLE ADC12DS080 80 12 DUAL ADC12L080 80 12 SINGLE ADC12C105 105 12 SINGLE ADC12DS105 105 12 DUAL ADC12C170 170 12 SINGLE ADC14L020 20 14 SINGLE ADC14L040 40 14 SINGLE ADC14C080 80 14 SINGLE ADC14DS080 80 14 DUAL ADC14C105 105 14 SINGLE ADC14DS105 105 14 DUAL ADC14155 155 14 SINGLE DRIVING CAPACITIVE LOADS As noted previously, capacitive loads should be isolated from the amplifier output with small valued resistors. This is particularly the case when the load has a resistive component that is 500 or higher. A typical ADC has capacitive components of around 10 pF and the resistive component could be 1000 or higher. If driving a transmission line, such as 50 coaxial or 100 twisted pair, using matching resistors will be sufficient to isolate any subsequent capacitance. BALANCED CABLE DRIVER With up to 15 VPP differential output voltage swing and 80 mA of linear drive current the LMH6552 makes an excellent cable driver as shown in Figure 54. The LMH6552 is also suitable for driving differential cables from a single ended source. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 21 LMH6552 SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 www.ti.com 100: TWISTED PAIR 357: 50: 169: RS = 50: + VS a VCM 61.8: - 2 VPP 169: 27.6: 50: 357: AV = 2 V/V ENABLE Figure 54. Fully Differential Cable Driver POWER SUPPLY BYPASSING The LMH6552 requires supply bypassing capacitors as shown in Figure 55 and Figure 56. The 0.01 F and 0.1 F capacitors should be leadless SMT ceramic capacitors and should be no more than 3 mm from the supply pins. These capacitors should be star routed with a dedicated ground return plane or trace for best harmonic distortion performance. A small capacitor, ~0.01 F, placed across the supply rails, and as close to the chip's supply pins as possible, can further improve HD2 performance. Thin traces or small vias will reduce the effectiveness of bypass capacitors. Also shown in both figures is a capacitor from the VCM and ENABLE pins to ground. These inputs are high impedance and can provide a coupling path into the amplifier for external noise sources, possibly resulting in loss of dynamic range, degraded CMRR, degraded balance and higher distortion. + V 10 PF 0.1 PF + VCM 0.01 PF ENABLE 0.1 PF 0.1 PF 10 PF - V 0.1 PF Figure 55. Split Supply Bypassing Capacitors 22 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 V + 10 PF 0.1 PF 0.01 PF + VCM 0.1 PF ENABLE 0.01 PF Figure 56. Single Supply Bypassing Capacitors POWER DISSIPATION The LMH6552 is optimized for maximum speed and performance in the small form factor of the standard SOIC package, and is essentially a dual channel amplifier. To ensure maximum output drive and highest performance, thermal shutdown is not provided. Therefore, it is of utmost importance to make sure that the TJMAXof 150C is never exceeded due to the overall power dissipation. Follow these steps to determine the maximum power dissipation for the LMH6552: 1. Calculate the quiescent (no-load) power: PAMP = ICC* (VS) where * VS = V+ - V-. (Be sure to include any current through the feedback network if VOCM is not mid-rail.) (1) 2. Calculate the RMS power dissipated in each of the output stages: PD (rms) = rms ((VS - V+OUT) * I+OUT) + rms ((VS - V-OUT) * I-OUT) where * VOUT and IOUT are the voltage and the current measured at the output pins of the differential amplifier as if they were single ended amplifiers and VS is the total supply voltage (2) 3. Calculate the total RMS power: PT = PAMP + PD (3) The maximum power that the LMH6552 package can dissipate at a given temperature can be derived with the following equation: PMAX = (150 - TAMB)/ JA where * * * * TAMB = Ambient temperature (C) JA = Thermal resistance, from junction to ambient, for a given package (C/W) For the SOIC package JA is 150C/W For WSON package JA is 58C/W (4) NOTE If VCM is not 0V then there will be quiescent current flowing in the feedback network. This current should be included in the thermal calculations and added into the quiescent power dissipation of the amplifier. Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 23 LMH6552 SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 www.ti.com THERMAL PERFORMANCE The WSON package is designed for enhanced thermal performance and features an exposed die attach pad (DAP) at the bottom center of the package that creates a direct path to the PCB for maximum power dissipation. The DAP is floating and is not electrically connected to internal circuitry. Compared to the traditional leaded packages where the die attach pad is embedded inside the molding compound, the WSON reduces one layer in the thermal path. The thermal advantage of the WSON package is fully realized only when the exposed die attach pad is soldered down to a thermal land on the PCB board with thermal vias planted underneath the thermal land. The thermal land can be connected to any power or ground plane within the allowable supply voltage range of the device. Based on thermal analysis of the WSON package, the junction-to-ambient thermal resistance (JA) can be improved by a factor of two when the die attach pad of the WSON package is soldered directly onto the PCB with thermal land and thermal vias are 1.27 mm and 0.33 mm respectively. Typical copper via barrel plating is 1 oz, although thicker copper may be used to further improve thermal performance. For more information on board layout techniques, refer to Application Note 1187 "Leadless Lead Frame Package (LLP)." This application note also discusses package handling, solder stencil and the assembly process. ESD PROTECTION The LMH6552 is protected against electrostatic discharge (ESD) on all pins. The LMH6552 will survive 2000V Human Body model and 200V Machine model events. Under normal operation the ESD diodes have no affect on circuit performance. There are occasions, however, when the ESD diodes will be evident. If the LMH6552 is driven by a large signal while the device is powered down the ESD diodes will conduct. The current that flows through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is possible to power up a chip with a large signal applied to the input pins. Using the shutdown mode is one way to conserve power and still prevent unexpected operation. BOARD LAYOUT The LMH6552 is a very high performance amplifier. In order to get maximum benefit from the differential circuit architecture board layout and component selection is very critical. The circuit board should have a low inductance ground plane and well bypassed broad supply lines. External components should be leadless surface mount types. The feedback network and output matching resistors should be composed of short traces and precision resistors (0.1%). The output matching resistors should be placed within 3 or 4 mm of the amplifier as should the supply bypass capacitors. Refer to POWER SUPPLY BYPASSING for recommendations on bypass circuit layout. Evaluation boards are available free of charge through the product folder on ti.com. By design, the LMH6552 is relatively insensitive to parasitic capacitance at its inputs. Nonetheless, ground and power plane metal should be removed from beneath the amplifier and from beneath RF and RG for best performance at high frequency. With any differential signal path, symmetry is very important. Even small amounts of asymmetry can contribute to distortion and balance errors. EVALUATION BOARD See the LMH6552 Product Folder for evaluation board availability and ordering information. 24 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 LMH6552 www.ti.com SNOSAX9H - APRIL 2007 - REVISED MARCH 2013 REVISION HISTORY Changes from Revision G (March 2013) to Revision H * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 24 Submit Documentation Feedback Copyright (c) 2007-2013, Texas Instruments Incorporated Product Folder Links: LMH6552 25 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) LMH6552MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH65 52MA LMH6552MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH65 52MA LMH6552SD/NOPB ACTIVE WSON NGS 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 6552 LMH6552SDX/NOPB ACTIVE WSON NGS 8 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 6552 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMH6552MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMH6552SD/NOPB WSON NGS 8 1000 178.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 LMH6552SDX/NOPB WSON NGS 8 4500 330.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH6552MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMH6552SD/NOPB WSON NGS 8 1000 210.0 185.0 35.0 LMH6552SDX/NOPB WSON NGS 8 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NGS0008C SDA08C (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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