127:
+
-
LMH6552
V+
V-
22 pF
VREF
127:
-
+
100:
100:
274:
274:
ADC14DS105
14-Bit
105
MSPS
620 nH
620 nH
49.9:
68.1:
68.1:
0.1 PF
50:
Single-Ended
AC-coupled
Source
LMH6552
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SNOSAX9H –APRIL 2007–REVISED MARCH 2013
1.5 GHz Fully Differential Amplifier
Check for Samples: LMH6552
1FEATURES DESCRIPTION
The LMH6552 is a high performance fully differential
2• 1.5 GHz −3 dB Small Signal amplifier designed to provide the exceptional signal
Bandwidth @ AV= 1 fidelity and wide large-signal bandwidth necessary for
• 1.25 GHz −3 dB Large Signal driving 8 to 14 bit high speed data acquisition
Bandwidth @ AV= 1 systems. Using TI's proprietary differential current
mode input stage architecture, the LMH6552 allows
• 800 MHz Bandwidth @ AV= 4 operation at gains greater than unity without
• 450 MHz 0.1 dB Flatness sacrificing response flatness, bandwidth, harmonic
• 3800 V/µs Slew Rate distortion, or output noise performance.
• 10 ns Settling Time to 0.1% With external gain set resistors and integrated
–−90 dB THD @ 20 MHz common mode feedback, the LMH6552 can be
configured as either a differential input to differential
–−74 dB THD @ 70 MHz output or single ended input to differential output gain
• 20 ns Enable/Shutdown Pin block. The LMH6552 can be AC or DC coupled at the
• 5 to 12V Operation input which makes it suitable for a wide range of
applications including communication systems and
APPLICATIONS high speed oscilloscope front ends. The performance
of the LMH6552 driving an ADC14DS105 is 86 dBc
• Differential ADC Driver SFDR and 74 dBc SNR up to 40 MHz.
• Video Over Twisted Pair The LMH6552 is available in an 8-pin SOIC package
• Differential Line Driver as well as a space saving, thermally enhanced 8-Pin
• Single End to Differential Converter WSON package for higher performance.
• High Speed Differential Signaling
• IF/RF Amplifier
• Level Shift Amplifier
• SAW Filter Buffer/Driver
Typical Application
Figure 1. Single-Ended Input Differential Output ADC Driver
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2007–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMH6552
SNOSAX9H –APRIL 2007–REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)
ESD Tolerance (2)
Human Body Model 2000V
Machine Model 200V
Supply Voltage 13.2V
Common Mode Input Voltage ±VS
Maximum Input Current (pins 1, 2, 7, 8) 30 mA
Maximum Output Current (pins 4, 5) (3)
Maximum Junction Temperature 150°C
Soldering Information
For soldering specifications see SNOA549C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) Human Body Model, applicable std. MIL-STD-883, Method 30157. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(3) The maximum output current (IOUT) is determined by device power dissipation limitations. See POWER DISSIPATION of Application
Information for more details.
Operating Ratings (1)
Operating Temperature Range (2) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Total Supply Voltage 4.5V to 12V
Package Thermal Resistance (θJA)
8-Pin SOIC 150°C/W
8-Pin WSON 58°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics tables.
(2) The maximum power dissipation is a function of TJ(MAX),θJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX)– TA) / θJA. All numbers apply for packages soldered directly onto a PC Board.
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SNOSAX9H –APRIL 2007–REVISED MARCH 2013
±5V Electrical Characteristics (1)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= +5V, V−=−5V, AV= 1, VCM = 0V, RF= RG= 357Ω, RL=
500Ω, for single ended in, differential out. Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units
AC Performance (Differential)
SSBW Small Signal −3 dB Bandwidth (2) VOUT = 0.2 VPP, AV= 1, RL= 1 kΩ1500
VOUT = 0.2 VPP, AV= 1 1000
VOUT = 0.2 VPP, AV= 2 930 MHz
VOUT = 0.2 VPP, AV= 4 810
VOUT = 0.2 VPP, AV= 8 590
LSBW Large Signal −3 dB Bandwidth VOUT = 2 VPP, AV= 1, RL= 1 kΩ1250
VOUT = 2 VPP, AV= 1 950
VOUT = 2 VPP, AV= 2 820 MHz
VOUT = 2 VPP, AV= 4 740
VOUT = 2 VPP, AV= 8 590
0.1 dB Bandwidth VOUT = 0.2 VPP, AV= 1 450 MHz
Slew Rate 4V Step, AV= 1 3800 V/μs
Rise/Fall Time, 10%-90% 2V Step 600 ps
0.1% Settling Time 2V Step 10 ns
Overdrive Recovery Time VIN = 1.8V to 0V Step, AV= 5 V/V 6 ns
Distortion and Noise Response
HD2 2nd Harmonic Distortion VOUT = 2 VPP, f = 20 MHz, RL= 800Ω −92 dBc
VOUT = 2 VPP, f = 70 MHz, RL= 800Ω −74
HD3 3rd Harmonic Distortion VOUT = 2 VPP, f = 20 MHz, RL= 800Ω −93 dBc
VOUT = 2 VPP, f = 70 MHz, RL= 800Ω −84
IMD3 Two-Tone Intermodulation f ≥70 MHz, Third Order Products, VOUT =−87 dBc
2 VPP Composite
Input Noise Voltage f ≥1 MHz 1.1 nV/√Hz
Input Noise Current f ≥1 MHz 19.5 pA/√Hz
Noise Figure (See Figure 48) 50ΩSystem, AV= 9, 10 MHz 10.3 dB
Input Characteristics
IBI Input Bias Current (4) 60 110 µA
IBoffset Input Bias Current Differential VCM = 0V, VID = 0V, IBoffset = (IB−- IB+)/2 2.5 18 µA
(3)
CMRR Common Mode Rejection Ratio (3) DC, VCM = 0V, VID = 0V 80 dBc
RIN Input Resistance Differential 15 Ω
CIN Input Capacitance Differential 0.5 pF
CMVR Input Common Mode Voltage Range CMRR > 38 dB ±3.5 ±3.8 V
Output Performance
Output Voltage Swing (3) Differential Output 14.8 15.4 VPP
IOUT Linear Output Current (3) VOUT = 0V ±70 ±80 mA
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ> TA. See Application Information for information on temperature de-rating of this device."
Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical
Quality Control (SQC) methods.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(4) IBI is referred to a differential output offset voltage by the following relationship: VOD(offset) = IBI*2RF
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±5V Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= +5V, V−=−5V, AV= 1, VCM = 0V, RF= RG= 357Ω, RL=
500Ω, for single ended in, differential out. Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units
ISC Short Circuit Current One Output Shorted to Ground VIN = 2V ±141 mA
Single Ended (5)
Output Balance Error ΔVOUT Common Mode /ΔVOUT −60 dB
Differential, ΔVOD = 1V, f < 1 MHz
Miscellaneous Performance
ZTOpen Loop Transimpedance Differential 108 dBΩ
PSRR Power Supply Rejection Ratio DC, (V+- |V-|) = ±1V 80 dB
ISSupply Current (3) RL=∞19 22.5 25 mA
28
Enable Voltage Threshold 3.0 V
Disable Voltage Threshold 2.0 V
Enable/Disable time 15 ns
ISD Disable Shutdown Current 500 600 μA
Output Common Mode Control Circuit
Common Mode Small Signal VIN+= VIN−= 0 400 MHz
Bandwidth
Slew Rate VIN+= VIN−= 0 607 V/μs
VOSCM Input Offset Voltage Common Mode, VID = 0, VCM = 0 1.5 ±16.5 mV
Input Bias Current (6) −3.2 ±8 µA
Voltage Range ±3.7 ±3.8 V
CMRR Measure VOD, VID = 0V 80 dB
Input Resistance 200 kΩ
Gain ΔVO,CM/ΔVCM 0.995 1.0 1.012 V/V
(5) Short circuit current should be limited in duration to no more than 10 seconds. See POWER DISSIPATION of Application Information for
more details.
(6) Negative input current implies current flowing out of the device.
±2.5V Electrical Characteristics (1)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= +2.5V, V−=−2.5V, AV= 1, VCM = 0V, RF= RG= 357Ω,
RL= 500Ω, for single ended in, differential out. Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units
SSBW Small Signal −3 dB Bandwidth (2) VOUT = 0.2 VPP, AV= 1, RL= 1 kΩ1100
VOUT = 0.2 VPP, AV= 1 800
VOUT = 0.2 VPP, AV= 2 740 MHz
VOUT = 0.2 VPP, AV= 4 660
VOUT = 0.2 VPP, AV= 8 498
LSBW Large Signal −3 dB Bandwidth VOUT = 2 VPP, AV= 1, RL= 1 kΩ820
VOUT = 2 VPP, AV= 1 690
VOUT = 2 VPP, AV= 2 620 MHz
VOUT = 2 VPP, AV= 4 589
VOUT = 2 VPP, AV= 8 480
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ> TA. See Application Information for information on temperature de-rating of this device."
Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical
Quality Control (SQC) methods.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
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SNOSAX9H –APRIL 2007–REVISED MARCH 2013
±2.5V Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= +2.5V, V−=−2.5V, AV= 1, VCM = 0V, RF= RG= 357Ω,
RL= 500Ω, for single ended in, differential out. Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units
0.1 dB Bandwidth VOUT = 0.2 VPP, AV= 1 300 MHz
Slew Rate 2V Step, AV= 1 2100 V/μs
Rise/Fall Time, 10% to 90% 2V Step 700 ps
0.1% Settling Time 2V Step 10 ns
Overdrive Recovery Time VIN = 0.7 V to 0 V Step, AV= 5 V/V 6 ns
Distortion and Noise Response
HD2 2nd Harmonic Distortion VOUT = 2 VPP, f = 20 MHz, RL= 800Ω-82 dBc
VOUT = 2 VPP, f = 70 MHz, RL= 800Ω-65
HD3 3rd Harmonic Distortion VOUT = 2 VPP, f = 20 MHz, RL= 800Ω-79 dBc
VOUT = 2 VPP, f = 70 MHz, RL= 800Ω-67
IMD3 Two-Tone Intermodulation f ≥70 MHz, Third Order Products, −77 dBc
VOUT = 2 VPP Composite
Input Noise Voltage f ≥1 MHz 1.1 nV/√Hz
Input Noise Current f ≥1 MHz 19.5 pA/√Hz
Noise Figure (See Figure 48) 50ΩSystem, AV= 9, 10 MHz 10.2 dB
Input Characteristics
IBI Input Bias Current (4) 54 90 µA
IBoffset Input Bias Current Differential VCM = 0V, VID = 0V, IBoffset = (IB−- IB+)/2 2.3 18 μA
(3)
CMRR Common-Mode Rejection Ratio (3) DC, VCM = 0V, VID = 0V 75 dBc
RIN Input Resistance Differential 15 Ω
CIN Input Capacitance Differential 0.5 pF
CMVR Input Common Mode Range CMRR > 38 dB ±1.0 ±1.3 V
Output Performance
Output Voltage Swing (5) Differential Output 5.6 6.0 VPP
IOUT Linear Output Current (5) VOUT = 0V ±55 ±65 mA
ISC Short Circuit Current One Output Shorted to Ground, VIN = 2V ±131 mA
Single Ended (6)
Output Balance Error ΔVOUT Common Mode /ΔVOUT 60 dB
Differential, ΔVOD = 1V, f < 1 MHz
Miscellaneous Performance
ZT Open Loop Transimpedance Differential 107 dBΩ
PSRR Power Supply Rejection Ratio DC, ΔVS= ±1V 80 dB
ISSupply Current (5) RL=∞17 20.4 24 mA
27
Enable Voltage Threshold 3.0 V
Disable Voltage Threshold 2.0 V
Enable/Disable Time 15 ns
ISD Disable Shutdown Current 500 600 µA
Output Common Mode Control Circuit
Common Mode Small Signal VIN+= VIN−= 0 310 MHz
Bandwidth
Slew Rate VIN+= VIN−= 0 430 V/μs
(4) IBI is referred to a differential output offset voltage by the following relationship: VOD(offset) = IBI*2RF
(5) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(6) Short circuit current should be limited in duration to no more than 10 seconds. See POWER DISSIPATION of Application Information for
more details.
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1
4
3
5
8
7
6
V+
+ OUT
VCM
- IN
- OUT
+ IN
EN
V-
2
DAP
-
4
+OUT 5-OUT
36
V+ V-
EN
27
VCM +
18
-IN +IN
LMH6552
SNOSAX9H –APRIL 2007–REVISED MARCH 2013
www.ti.com
±2.5V Electrical Characteristics (1) (continued)
Unless otherwise specified, all limits are ensured for TA= 25°C, V+= +2.5V, V−=−2.5V, AV= 1, VCM = 0V, RF= RG= 357Ω,
RL= 500Ω, for single ended in, differential out. Boldface limits apply at the temperature extremes.
Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units
VOSCM Input Offset Voltage Common Mode, VID = 0, VCM = 0 1.65 ±15 mV
Input Bias Current (7) −2.9 µA
Voltage Range ±1.19 ±1.25 V
CMRR Measure VOD, VID = 0V 80 dB
Input Resistance 200 kΩ
Gain ΔVO,CM/ΔVCM 0.995 1.0 1.012 V/V
(7) Negative input current implies current flowing out of the device.
CONNECTION DIAGRAM
Figure 2. 8-Pin SOIC-Top View
See Package Number D0008A
Figure 3. 8-Pin WSON-Top View
See Package Number NGS0008C
PIN DESCRIPTIONS
Pin No. Pin Name Description
1 -IN Negative Input
2 VCM Output Common Mode Control
3 V+ Positive Supply
4 +OUT Positive Output
5 -OUT Negative Output
6 V- Negative Supply
7 EN Enable
8 +IN Positive Input
DAP DAP Die Attach Pad (See THERMAL PERFORMANCE for more information)
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-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
1 10 100 10000
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
1000
V+ = +2.5V
V- = -2.5V
RL = 500:
RF = 357:
VOD = 0.2 VPP
AV = 1 V/V
V+ = +5V
V- = -5V
RL = 500:
RF = 357:
DIFFERENTIAL INPUT
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
1 10 100 10000
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
1000
V+ = +2.5V
V- = -2.5V
RL = 1 k:
RF = 301:
VOD = 0.2 VPP
AV = 1 V/V
V+ = +5V
V- = -5V
RL = 1 k:
RF = 301:
DIFFERENTIAL INPUT
110 100 1000 10000
FREQUENCY (MHz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
NORMALIZED GAIN (dB)
V+ = +5V
V- = -5V
AV = 2 V/V
DIFFERENTIAL INPUT
VOD = 4 VPP
VOD = 2 VPP
VOD = 0.5 VPP
110 100 1000 10000
FREQUENCY (MHz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
NORMALIZED GAIN (dB)
V+ = +5V
V- = -5V
AV = 2 V/V
SINGLE-ENDED INPUT
VOD = 4 VPP
VOD = 2 VPP
VOD = 0.5 VPP
110 100 1000 10000
FREQUENCY (MHz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
NORMALIZED GAIN (dB)
AV = 8, RF = 400:
VOUT = 0.2 VPP
SINGLE-ENDED INPUT
AV = 4
AV = 2
AV = 1
110 100 1000 10000
FREQUENCY (MHz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
NORMALIZED GAIN (dB)
VOUT = 0.2 VPP
DIFFERENTIAL INPUT
AV = 8
AV = 4
AV = 1
AV = 2
LMH6552
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SNOSAX9H –APRIL 2007–REVISED MARCH 2013
Typical Performance Characteristics V+= +5V, V−=−5V
(TA= 25°C, RF= RG= 357Ω, RL= 500Ω, AV= 1, for single ended in, differential out, unless specified).
Frequency Response Frequency Response
vs. vs.
Gain Gain
Figure 4. Figure 5.
Frequency Response Frequency Response
vs. vs.
VOUT VOUT
Figure 6. Figure 7.
Frequency Response Frequency Response
vs. vs.
Supply Voltage Supply Voltage
Figure 8. Figure 9.
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0 5 10 15 20 25 30 35 40 45 50
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
VOD (V)
TIME (ns)
V+ = +2.5V
V- = -2.5V
RL = 500:
RF = 357:
110000
FREQUENCY (MHz)
-9
-5
-2
2
NORMALIZED GAIN (dB)
1000
100
10
0
-4
-8
1
-1
-3
-6
-7
V+ = +5V
V- = -5V
AV = 1 V/V
VOUT = 2 VPP
RL = 1 k:
RF = 301:
RF = 357:
RF = 400:
DIFFERENTIAL INPUT
110 100 1000 10000
FREQUENCY (MHz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
NORMALIZED GAIN (dB)
RL = 200:
RL = 1 k:
RL = 500:
RL = 800:
V+ = +5V
V- = -5V
AV = 1 V/V
RF = 357:
VOUT = 0.2 VPP
SINGLE-ENDED INPUT
110 100 1000 10000
FREQUENCY (MHz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
NORMALIZED GAIN (dB)
RL = 200:
RL = 1 k:
RL = 500:
RL = 800:
V+ = +5V
V- = -5V
AV = 1 V/V
RF = 357:
VOUT = 2 VPP
SINGLE-ENDED INPUT
110 100 1000
FREQUENCY (MHz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
NORMALIZED GAIN (dB)
CL = 82 pF, RO = 16:
CL = 39 pF, RO = 21:
CL = 15 pF, RO = 24:
CL = 5.6 pF, RO = 23:
VOD = 200 mVPP
AV = 1
LOAD = (CL || 1 k:) IN
SERIES WITH 2 ROUTS
CAPACITIVE LOAD (pF)
110 100
0
10
20
30
SUGGESTED RO (:)
V+ = +5V
V- = -5V
LOAD = 1 k: || CAP LOAD
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Typical Performance Characteristics V+= +5V, V−=−5V (continued)
(TA= 25°C, RF= RG= 357Ω, RL= 500Ω, AV= 1, for single ended in, differential out, unless specified).
Frequency Response Suggested ROUT
vs. vs.
Capacitive Load Capacitive Load
Figure 10. Figure 11.
Frequency Response Frequency Response
vs. vs.
Resistive Load Resistive Load
Figure 12. Figure 13.
Frequency Response
vs.
RF1 VPP Pulse Response Single Ended Input
Figure 14. Figure 15.
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FREQUENCY (MHz)
DISTORTION (dBc)
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-1051 25 50 75 100 125 150 175 200 225 250
HD2
HD3
V+ = +5V
V- = -5V
RL = 800Ö
VOD = 2 VPP
VOCM = 0V
0 5 10 15 20 25 30 35 40 45 50
-80
-60
-40
-20
0
20
40
60
80
COMMON MODE VOUT (mV)
TIME (ns)
V+ = +5V
V- = -5V
RL = 500:
RL = 357:
VOD = 2 VPP
0 5 10 15 20 25 30 35 40 45 50
-1.5
-1
-0.5
0
0.5
1
1.5
VOD (V)
TIME (ns)
V+ = +5
V- = -5V
RL = 500:
RF = 357:
05 10 15 20 25 30 35 40 45 50
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
VOD (V)
TIME (ns)
V+ = +5V
V- = -5V
RL = 500:
RF = 357:
LMH6552
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SNOSAX9H –APRIL 2007–REVISED MARCH 2013
Typical Performance Characteristics V+= +5V, V−=−5V (continued)
(TA= 25°C, RF= RG= 357Ω, RL= 500Ω, AV= 1, for single ended in, differential out, unless specified).
2 VPP Pulse Response Single Ended Input Large Signal Pulse Response
Figure 16. Figure 17.
Distortion
vs.
Output Common Mode Pulse Response Frequency Single Ended Input
Figure 18. Figure 19.
Distortion Distortion
vs. vs.
Supply Voltage Supply Voltage
Figure 20. Figure 21.
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120
0.01 11000
FREQUENCY (MHz)
40
70
MAGNITUDE, |Z| (dB :)
100
10
0.1
100
90
60
50
80
110
-180
-45
-90
-135
0
MAGNITUDE
PHASE
V+ = +5V
V- = -5V
PHASE (°)
120
0.01 11000
FREQUENCY (MHz)
40
70
MAGNITUDE, |Z| (dB :)
100
10
0.1
100
90
60
50
80
110
-180
-45
-90
-135
0
MAGNITUDE
PHASE
V+ = +2.5V
V- = -2.5V
PHASE (°)
00.5 1 1.5 2 2.5 3
VOCM (V)
-100
-90
-80
-70
-60
-50
-40
DISTORTION (dBc)
V+ = +5V
V- = -5V
RL = 800:
VOUT = 2 VPP
fc = 20 MHz
HD2
HD3
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Typical Performance Characteristics V+= +5V, V−=−5V (continued)
(TA= 25°C, RF= RG= 357Ω, RL= 500Ω, AV= 1, for single ended in, differential out, unless specified).
Distortion Distortion
vs. vs.
Output Common Mode Voltage Output Common Mode Voltage
Figure 22. Figure 23.
Maximum VOUT Minimum VOUT
vs. vs.
IOUT IOUT
Figure 24. Figure 25.
Open Loop Transimpedance Open Loop Transimpedance
Figure 26. Figure 27.
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0
40
100
PSRR (dBc DIFFERENTIAL)
80
60
20
90
70
50
30
10
11000
FREQUENCY (MHz)
100
10
0.1
+PSRR
-PSRR
V+ = +5V
V- = -5V
AV = 2 V/V
RL = 500:
VIN = 0V
0.1 1000
FREQUENCY (MHz)
0
-40
-70
-110
PSRR (dBc DIFFERENTIAL)
100
10
1
-90
-50
-10
-100
-80
-60
-30
-20
+PSRR
-PSRR
V+ = +2.5V
V- = -2.5V
AV = 2 V/V
RL = 500:
VIN = 0V
0 200 400 600 800 1000
-10
-8
-6
-4
-2
0
2
4
6
8
10
OUTPUT VOLTAGE (VOD)
TIME (ns)
V+ = +5V
V- = -5V
AV = 5 V/V
RF = 324:
RL = 200:-2
-1.6
-1.2
-0.8
-0.4
0
0.4
0.8
1.2
1.6
2
INPUT VOLTAGE (V)
INPUT
OUTPUT
0 200 400 600 800 1000
-4
-3
-2
-1
0
1
2
3
4
OUTPUT VOLTAGE (VOD)
TIME (ns)
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
INPUT VOLTAGE (V)
V+ = +2.5V
V- = -2.5V
AV = 5 V/V
RF = 324:
RL = 200:
INPUT
OUTPUT
0.01 1 100 1000
FREQUENCY (MHz)
0.0001
10
1000
|Z| (:)
10
0.1
100
0.001
0.1
1
0.01
V+ = +5V
V- = -5V
VIN = 0V
AV = 1 V/V
0.01 0.1 110 1000
FREQUENCY (MHz)
0.01
0.1
100
1000
|Z| (:)
100
1
10
V+ = +2.5V
V- = -2.5
VIN = 0V
AV = 1 V/V
LMH6552
www.ti.com
SNOSAX9H –APRIL 2007–REVISED MARCH 2013
Typical Performance Characteristics V+= +5V, V−=−5V (continued)
(TA= 25°C, RF= RG= 357Ω, RL= 500Ω, AV= 1, for single ended in, differential out, unless specified).
Closed Loop Output Impedance Closed Loop Output Impedance
Figure 28. Figure 29.
Overdrive Recovery Overdrive Recovery
Figure 30. Figure 31.
PSRR PSRR
Figure 32. Figure 33.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: LMH6552
0.0001 0.01 1 100
FREQUENCY (MHz)
100.1
0.001
VOLTAGE NOISE (nV/
Hz)
NOISE VOLTAGE
INVERTING CURRENT
NOISE CURRENT
NON-INVERTING CURRENT
NOISE CURRENT
6
0
4
5
3
2
1
210
0
140
175
105
70
35
CURRENT NOISE (pA/
Hz)
0 20 40 60 80 100 120 140 160 180 200
10
11
12
13
14
15
NOISE FIGURE (dB)
FREQUENCY (MHz)
V+ = +5V
V- = -5V
AV = 9 V/V
RF = 275:
50: SYSTEM
0 20 40 60 80 100 120 140 160 180 200
10
11
12
13
14
15
NOISE FIGURE (dB)
FREQUENCY (MHz)
V+ = +2.5V
V- = -2.5V
AV = 9 V/V
RF = 275:
50: SYSTEM
0.1 11000
FREQUENCY (MHz)
20
40
65
85
CMRR (dB)
100
10
75
55
30
25
35
45
50
60
70
80
AV = 2 V/V
RL = 500:
RF = 357:
VOUT = 1.0 VPP
11000
FREQUENCY (MHz)
-70
-50
-30
-10
BALANCE ERROR (dBc)
100
10
-20
-40
-60
-15
-25
-35
-45
-55
-65
V+ = +2.5V
V- = -2.5V
RL = 500:
RF = 357:
AV = 1 V/V
V+ = +5V
V- = -5V
LMH6552
SNOSAX9H –APRIL 2007–REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics V+= +5V, V−=−5V (continued)
(TA= 25°C, RF= RG= 357Ω, RL= 500Ω, AV= 1, for single ended in, differential out, unless specified).
CMRR Balance Error
Figure 34. Figure 35.
Noise Figure Noise Figure
Figure 36. Figure 37.
Input Noise Differential S-Parameter Magnitude
vs. vs.
Frequency Frequency
Figure 38. Figure 39.
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Product Folder Links: LMH6552
50 60 70 80 90 100
-100
-95
-90
-85
-80
-75
-70
-65
IMD 3 (dBc)
CENTER FREQUENCY (MHz)
V+ = +2.5V
V- = -2.5V
V+ = +5V
V- = -5V
RL = 800:
RF = 360:
AV = +2
VOD = 2 VPP
SINGLE-ENDED INPUT
200 kHz SPACING
10 100 1000
-300
-200
-100
0
100
200
300
400
PHASE (°)
FREQUENCY (MHz)
S11
S22
S12
S11
(SINGLE-ENDED INPUT) S21
V+ = +5V
V- = -5V
AV = 1 V/V
0 1 2 3 4 5 6 7
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
IMD 3 (dBc)
DIFFERENTIAL VOUT (VPP)
fc = 75 MHz (200 kHz SPACING)
SINGLE-ENDED INPUT
RL = 200:
RL = 800:
V+ = +5V
V- = -5V
RF = 357:
AV = 2 V/V
LMH6552
www.ti.com
SNOSAX9H –APRIL 2007–REVISED MARCH 2013
Typical Performance Characteristics V+= +5V, V−=−5V (continued)
(TA= 25°C, RF= RG= 357Ω, RL= 500Ω, AV= 1, for single ended in, differential out, unless specified).
Differential S-Parameter Phase 3rd Order Intermodulation Products
vs. vs.
Frequency VOUT
Figure 40. Figure 41.
3rd Order Intermodulation Products 3rd Order Intermodulation Products
vs. vs.
VOUT Center Frequency
Figure 42. Figure 43.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LMH6552
LMH6552
SNOSAX9H –APRIL 2007–REVISED MARCH 2013
www.ti.com
APPLICATION INFORMATION
The LMH6552 is a fully differential current feedback amplifier with integrated output common mode control,
designed to provide low distortion amplification to wide bandwidth differential signals. The common mode
feedback circuit sets the output common mode voltage independent of the input common mode, as well as
forcing the V+and V−outputs to be equal in magnitude and opposite in phase, even when only one of the inputs
is driven as in single to differential conversion.
The proprietary current feedback architecture of the LMH6552 offers gain and bandwidth independence with
exceptional gain flatness and noise performance, even at high values of gain, simply with the appropriate choice
of RF1 and RF2. Generally RF1 is set equal to RF2, and RG1 equal to RG2, so that the gain is set by the ratio RF/RG.
Matching of these resistors greatly affects CMRR, DC offset error, and output balance. A minimum of 0.1%
tolerance resistors are recommended for optimal performance, and the amplifier is internally compensated to
operate with optimum gain flatness with values of RFbetween 270Ωand 390Ωdepending on package selection,
PCB layout, and load resistance.
The output common mode voltage is set by the VCM pin with a fixed gain of 1 V/V. This pin should be driven by a
low impedance reference and should be bypassed to ground with a 0.1 µF ceramic capacitor. Any unwanted
signal coupling into the VCM pin will be passed along to the outputs, reducing the performance of the amplifier.
This pin must not be left floating.
The LMH6552 can be operated on a supply range as either a single 5V supply or as a split +5V and −5V.
Operation on a single 5V supply, depending on gain, is limited by the input common mode range; therefore, AC
coupling may be required. For example, in a DC coupled input application on a single 5V supply, with a VCM of
1.5V, the input common voltage at a gain of 1 will be 0.75V which is outside the minimum 1.2V to 3.8V input
common mode range of the amplifier. The minimum VCM for this application should be greater than 2.5V
depending on output signal swing. Alternatively, AC coupling of the inputs in this example results in equal input
and output common mode voltages, so a 1.5V VCM would be achievable. Split supplies will allow much less
restricted AC and DC coupled operation with optimum distortion performance.
The LMH6552 is equipped with an ENABLE pin to reduce power consumption when not in use. The ENABLE
pin, when not driven, floats high (on). When the ENABLE pin is pulled low the amplifier is disabled and the
amplifier output stage goes into a high impedance state so the feedback and gain set resistors determine the
output impedance of the circuit. For this reason input to output isolation will be poor in the disabled state and the
part is not recommended in multiplexed applications where outputs are all tied together.
WSON PACKAGE
Due to it's size and lower parasitics, the WSON requires the lower optimum value of 275Ωfor RF. This will give a
flat frequency response with minimal peaking. With a lower RFvalue the WSON package will have a reduction in
noise compared to the SOIC with its optimum RF= 360Ω.
FULLY DIFFERENTIAL OPERATION
The LMH6552 will perform best in a fully differential configuration. The circuit shown in Figure 44 is a typical fully
differential application circuit as might be used to drive an analog to digital converter (ADC). In this circuit the
closed loop gain AV= VOUT/ VIN = RF/RG, where the feedback is symmetric. The series output resistors, RO, are
optional and help keep the amplifier stable when presented with a capacitive load. Refer to DRIVING
CAPACITIVE LOADS for details.
14 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMH6552
VSVCM RL
357:
50:
ENABLE
a
+
-
357:
357:
357:
50:
58:
58:
RS = 50:
RS = 50:
VS
RG
RG
VCM RLVO
RF
RF
CL
RO
RO
ENABLE
a+
-
LMH6552
www.ti.com
SNOSAX9H –APRIL 2007–REVISED MARCH 2013
Figure 44. Typical Application
When driven from a differential source, the LMH6552 provides low distortion, excellent balance, and common
mode rejection. This is true provided the resistors RF, RGand ROare well matched and strict symmetry is
observed in board layout. With an intrinsic device CMRR of 80 dB, using 0.1% resistors will give a worst case
CMRR of around 60 dB for most circuits.
Figure 45. Differential S-Parameter Test Circuit
The circuit configuration shown in Figure 45 was used to measure differential S parameters in a 50Ω
environment at a gain of 1 V/V. Refer to Figure 39 and Figure 40 in Typical Performance Characteristics V+=
+5V, V−=−5V for measurement results.
SINGLE ENDED INPUT TO DIFFERENTIAL OUTPUT OPERATION
In many applications, it is required to drive a differential input ADC from a single ended source. Traditionally,
transformers have been used to provide single to differential conversion, but these are inherently bandpass by
nature and cannot be used for DC coupled applications. The LMH6552 provides excellent performance as a
single-to-differential converter down to DC. Figure 46 shows a typical application circuit where an LMH6552 is
used to produce a differential signal from a single ended source.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LMH6552
VSVCM RL
357:
50:
ENABLE
a+
-
357:
348:
348:
50:
26.4:
56.2:
RS = 50:
RG
RG
RF
RF
RO
+
-RO
LMH6552
IN-
IN+
ADC
V+
V-
VO
+
-
RT
RS
RM
VS
AV, RIN
a
AV = 2(1 - E1)
E1 + E2
¨
¨
©
§
¨
¨
©
§
RIN = 2RG + RM (1-E2)
1 + E2
¨
¨
©
§
¨
¨
©
§
E2 = RG + RM
RG + RF + RM
¨
¨
©
§
¨
¨
©
§
¨
¨
©
§
E1 = RG
RG + RF
¨
¨
©
§
RS=RT || RIN
RM=RT || RS
+
-
VCM
LMH6552
SNOSAX9H –APRIL 2007–REVISED MARCH 2013
www.ti.com
Figure 46. Single Ended Input with Differential Output
When using the LMH6552 in single-to-differential mode, the complimentary output is forced to a phase inverted
replica of the driven output by the common mode feedback circuit as opposed to being driven by its own
complimentary input. Consequently, as the driven input changes, the common mode feedback action results in a
varying common mode voltage at the amplifier's inputs, proportional to the driving signal. Due to the non-ideal
common mode rejection of the amplifier's input stage, a small common mode signal appears at the outputs which
is superimposed on the differential output signal. The ratio of the change in output common mode voltage to
output differential voltage is commonly referred to as output balance error. The output balance error response of
the LMH6552 over frequency is shown in Typical Performance Characteristics.
To match the input impedance of the circuit in Figure 46 to a specified source resistance, RS, requires that RT||
RIN = RS. The equations governing RIN and AVfor single-to-differential operation are also provided in Figure 46.
These equations, along with the source matching condition, must be solved iteratively to achieve the desired gain
with the proper input termination. Component values for several common gain configurations in a 50Ω
environment are given in Table 2. Gain Component Values for 50ΩSystem WSON Package. Typically RS=50Ω
while RM=RS||RT.
Table 2. Gain Component Values for 50ΩSystem WSON Package
Gain RFRGRTRM
0 dB 275Ω255Ω59Ω26.7Ω
6 dB 275Ω127Ω68.1Ω28.7Ω
12 dB 275Ω54.9Ω107Ω34Ω
Figure 47. Single Ended Input S-Parameter Test Circuit (50ΩSystem)
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Product Folder Links: LMH6552
RG
RG
VCM RLVO
RF
RF
CL
RO
RO
ENABLE
+
-
VSa
VO1
VO2
VI2
VI1
RM
RT
RS
VICM = VOCM
VICM = VI1 + VI2
2
*VCM = VO1 + VO2
2
*BY DESIGN
LMH6552
www.ti.com
SNOSAX9H –APRIL 2007–REVISED MARCH 2013
The circuit shown in Figure 47 was used to measure S-parameters for a single-to-differential configuration.
Figure 39 and Figure 40 in Typical Performance Characteristics are taken using the recommended component
values for 0 dB gain.
SINGLE SUPPLY OPERATION
Single supply operation is possible on supplies from 5V to 10V; however, as discussed earlier, AC input coupling
is recommended for low supplies such as 5V due to input common mode limitations. An example of an AC
coupled, single supply, single-to-differential circuit is shown in Figure 48. Note that when AC coupling, both
inputs need to be AC coupled irrespective of single-to-differential or differential-to-differential configuration. For
higher supply voltages DC coupling of the inputs may be possible provided that the output common mode DC
level is set high enough so that the amplifier's inputs and outputs are within their specified operating ranges.
Figure 48. AC Coupled for Single Supply Operation
SPLIT SUPPLY OPERATION
For optimum performance, split supply operation is recommended using +5V and −5V supplies; however,
operation is possible on split supplies as low as +2.25V and −2.25V and as high as +6V and −6V. Provided the
total supply voltage does not exceed the 4.5V to 12V operating specification, non-symmetric supply operation is
also possible and in some cases advantageous. For example, if a 5V DC coupled operation is required for low
power dissipation but the amplifier input common mode range prevents this operation, it is still possible with split
supplies of (V+) and (V−). Where (V+) - (V−) = 5V and V+and V−are selected to center the amplifier input
common mode range to suit the application.
OUTPUT NOISE PERFORMANCE AND MEASUREMENT
Unlike differential amplifiers based on voltage feedback architectures, noise sources internal to the LMH6552
refer to the inputs largely as current sources, hence the low input referred voltage noise and relatively higher
input referred current noise. The output noise is therefore more strongly coupled to the value of the feedback
resistor and not to the closed loop gain, as would be the case with a voltage feedback differential amplifier. This
allows operation of the LMH6552 at much higher gain without incurring a substantial noise performance penalty,
simply by choosing a suitable feedback resistor.
Figure 49 shows a circuit configuration used to measure noise figure for the LMH6552 in a 50Ωsystem. An RF
value of 275Ωis chosen for the SOIC package to minimize output noise while simultaneously allowing both high
gain (9 V/V) and proper 50Ωinput termination. Refer to SINGLE ENDED INPUT TO DIFFERENTIAL OUTPUT
OPERATION for calculation of resistor and gain values. Noise figure values at various frequencies are shown
Figure 36 in Typical Performance Characteristics.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LMH6552
169:
+
-
LMH6552
V+
V-
2.2 pF
VREF
169:
-
+
125:
125:
357:
357:
ADC12DL080
12-Bit
80 MSPS
CIN
~ 7- 8 pF
61.8:
50:
Single-Ended
AC-coupled
Source
61.8:
49.9:
0.1 PF
10:
275:
+
-
LMH6552
V+
V-
VO
+
-
VS
275:
10:
50:
RS = 50:
VCM 50:
2:1 (TURNS)
AV = 9 V/V
1 PF
1 PF
a
LMH6552
SNOSAX9H –APRIL 2007–REVISED MARCH 2013
www.ti.com
Figure 49. Noise Figure Circuit Configuration
DRIVING ANALOG TO DIGITAL CONVERTERS
Analog-to-digital converters present challenging load conditions. They typically have high impedance inputs with
large and often variable capacitive components. As well, there are usually current spikes associated with
switched capacitor or sample and hold circuits. Figure 50 shows a combination circuit of the LMH6552 driving the
ADC12DL080. The two 125Ωresistors serve to isolate the capacitive loading of the ADC from the amplifier and
ensure stability. In addition, the resistors, along with a 2.2 pF capacitor across the outputs (in parallel with the
ADC input capacitance), form a low pass anti-aliasing filter with a pole frequency of about 60 MHz. For switched
capacitor input ADCs, the input capacitance will vary based on the clock cycle, as the ADC switches between the
sample and hold mode. See your particular ADC's datasheet for details.
Figure 50. Driving a 12-bit ADC
Figure 51 shows the SFDR and SNR performance vs. frequency for the LMH6552 and ADC12DL080
combination circuit with the ADC input signal level at −1 dBFS. The ADC12DL080 is a dual 12-bit ADC with
maximum sampling rate of 80 MSPS. The amplifier is configured to provide a gain of 2 V/V in single to
differential mode. An external band-pass filter is inserted in series between the input signal source and the
amplifier to reduce harmonics and noise from the signal generator. In order to properly match the input
impedance seen at the LMH6552 amplifier inputs, RMis chosen to match ZS|| RTfor proper input balance.
18 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMH6552
127:
+
-
LMH6552
V+
V-
22 pF
VREF
127:
-
+
100:
100:
274:
274:
ADC14DS105
14-Bit
105
MSPS
620 nH
620 nH
49.9:
68.1:
68.1:
0.1 PF
50:
Single-Ended
AC-coupled
Source
05 10 15 20 25 30 35 40
INPUT FREQUENCY (MHz)
50
55
60
65
70
75
80
85
90
(dB)
SFDR (dBc)
SNR (dBFs)
LMH6552
www.ti.com
SNOSAX9H –APRIL 2007–REVISED MARCH 2013
Figure 51. LMH6552/ADC12DL080 SFDR and SNR Performance vs. Frequency
Figure 52 shows a combination circuit of the LMH6552 driving the ADC14DS105. The ADC14DS105 is a dual
channel 14-bit ADC with a sampling rate of 105 MSPS. The circuit in Figure 52 has a 2nd order low-pass LC
filter formed by the 620 nH inductor along with the 22 pF capacitor across the differential outputs of the
LMH6552. The filter has a pole frequency of about 50 MHz. Figure 53 shows the combined SFDR and SNR
performance over frequency with a −1 dBFs input signal and a sampling rate of 1000 MSPS.
Figure 52. Driving a 14-bit ADC
The amplifier is configured to provide a gain of 2 V/V in a single-to-differential mode. The LMH6552 common
mode voltage is set by the ADC14DS105. Circuit testing is the same as described for the LMH6552 and
ADC12DL080 combination circuit. The 0.1 µF capacitor, in series with the 49.9Ωresistor, is inserted to ground
across the 68.1Ωresistor to balance the amplifier inputs.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LMH6552
0 5 10 15 20 25 30 35 40
50
100
(dB)
INPUT FREQUENCY (MHz)
55
60
65
70
75
80
85
90
95 SFDR (dBc)
SNR (dBFs)
LMH6552
SNOSAX9H –APRIL 2007–REVISED MARCH 2013
www.ti.com
Figure 53. LMH6552/ADC14DS105 SFDR and SNR Performance vs. Frequency
The amplifier and ADC should be located as close as possible. Both devices require that the filter components
be in close proximity to them. The amplifier needs to have minimal parasitic loading on the output traces and the
ADC is sensitive to high frequency noise that may couple in on its input lines. Some high performance ADCs
have an input stage that has a bandwidth of several times its sample rate. The sampling process results in all
input signals presented to the input stage mixing down into the first Nyquist zone (DC to Fs/2).
The LMH6552 is capable of driving a variety of Texas Instruments Analog-to-Digital Converters. This is shown in
TABLE 3. DIFFERENTIAL INPUT ADC's COMPATIBLE WITH LMH6552 DRIVER, which offers a list of possible
signal path ADC and amplifier combinations. The use of the LMH6552 to drive an ADC is determined by the
application and the desired sampling process (Nyquist operation, sub-sampling or over-sampling). See
application note AN-236 for more details on the sampling processes and application note AN-1393 'Using High
Speed Differential Amplifiers to Drive ADCs. For more information regarding a particular ADC, refer to the
particular ADC datasheet for details.
TABLE 3. DIFFERENTIAL INPUT ADC's COMPATIBLE WITH LMH6552 DRIVER
Product Number Max Sampling Rate (MSPS) Resolution Channels
ADC1173 15 8 SINGLE
ADC1175 20 8 SINGLE
ADC08351 42 8 SINGLE
ADC1175-50 50 8 SINGLE
ADC08060 60 8 SINGLE
ADC08L060 60 8 SINGLE
ADC08100 100 8 SINGLE
ADC08200 200 8 SINGLE
ADC08500 500 8 SINGLE
ADC081000 1000 8 SINGLE
ADC08D1000 1000 8 DUAL
ADC10321 20 10 SINGLE
ADC10D020 20 10 DUAL
ADC10030 27 10 SINGLE
ADC10040 40 10 DUAL
ADC10065 65 10 SINGLE
ADC10DL065 65 10 DUAL
ADC10080 80 10 SINGLE
ADC11DL066 66 11 DUAL
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Product Folder Links: LMH6552
LMH6552
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SNOSAX9H –APRIL 2007–REVISED MARCH 2013
Product Number Max Sampling Rate (MSPS) Resolution Channels
ADC11L066 66 11 SINGLE
ADC11C125 125 11 SINGLE
ADC11C170 170 11 SINGLE
ADC12010 10 12 SINGLE
ADC12020 20 12 SINGLE
ADC12040 40 12 SINGLE
ADC12D040 40 12 DUAL
ADC12DL040 40 12 DUAL
ADC12DL065 65 12 DUAL
ADC12DL066 66 12 DUAL
ADC12L063 63 12 SINGLE
ADC12C080 80 12 SINGLE
ADC12DS080 80 12 DUAL
ADC12L080 80 12 SINGLE
ADC12C105 105 12 SINGLE
ADC12DS105 105 12 DUAL
ADC12C170 170 12 SINGLE
ADC14L020 20 14 SINGLE
ADC14L040 40 14 SINGLE
ADC14C080 80 14 SINGLE
ADC14DS080 80 14 DUAL
ADC14C105 105 14 SINGLE
ADC14DS105 105 14 DUAL
ADC14155 155 14 SINGLE
DRIVING CAPACITIVE LOADS
As noted previously, capacitive loads should be isolated from the amplifier output with small valued resistors.
This is particularly the case when the load has a resistive component that is 500Ωor higher. A typical ADC has
capacitive components of around 10 pF and the resistive component could be 1000Ωor higher. If driving a
transmission line, such as 50Ωcoaxial or 100Ωtwisted pair, using matching resistors will be sufficient to isolate
any subsequent capacitance.
BALANCED CABLE DRIVER
With up to 15 VPP differential output voltage swing and 80 mA of linear drive current the LMH6552 makes an
excellent cable driver as shown in Figure 54. The LMH6552 is also suitable for driving differential cables from a
single ended source.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LMH6552
VCM 0.01 PF
V+
V-0.1 PF
0.1 PF
10 PF
10 PF
0.1 PF
+
-
0.1 PF
ENABLE
VSVCM
ENABLE
100:
TWISTED PAIR
50:
2 VPP
357:
169:
AV = 2 V/V
50:
a+
-
357:
169:
27.6:
61.8:
RS = 50:
LMH6552
SNOSAX9H –APRIL 2007–REVISED MARCH 2013
www.ti.com
Figure 54. Fully Differential Cable Driver
POWER SUPPLY BYPASSING
The LMH6552 requires supply bypassing capacitors as shown in Figure 55 and Figure 56. The 0.01 µF and 0.1
µF capacitors should be leadless SMT ceramic capacitors and should be no more than 3 mm from the supply
pins. These capacitors should be star routed with a dedicated ground return plane or trace for best harmonic
distortion performance. A small capacitor, ~0.01 µF, placed across the supply rails, and as close to the chip's
supply pins as possible, can further improve HD2 performance. Thin traces or small vias will reduce the
effectiveness of bypass capacitors. Also shown in both figures is a capacitor from the VCM and ENABLE pins to
ground. These inputs are high impedance and can provide a coupling path into the amplifier for external noise
sources, possibly resulting in loss of dynamic range, degraded CMRR, degraded balance and higher distortion.
Figure 55. Split Supply Bypassing Capacitors
22 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMH6552
VCM
V+
10 PF
0.1 PF
+
-
0.1 PF0.01 PF
0.01 PF
ENABLE
LMH6552
www.ti.com
SNOSAX9H –APRIL 2007–REVISED MARCH 2013
Figure 56. Single Supply Bypassing Capacitors
POWER DISSIPATION
The LMH6552 is optimized for maximum speed and performance in the small form factor of the standard SOIC
package, and is essentially a dual channel amplifier. To ensure maximum output drive and highest performance,
thermal shutdown is not provided. Therefore, it is of utmost importance to make sure that the TJMAXof 150°C is
never exceeded due to the overall power dissipation.
Follow these steps to determine the maximum power dissipation for the LMH6552:
1. Calculate the quiescent (no-load) power:
PAMP = ICC* (VS)
where
• VS= V+- V−. (Be sure to include any current through the feedback network if VOCM is not mid-rail.) (1)
2. Calculate the RMS power dissipated in each of the output stages:
PD(rms) = rms ((VS- V+OUT) * I+OUT) + rms ((VS−V−OUT) * I−OUT)
where
• VOUT and IOUT are the voltage and the current measured at the output pins of the differential amplifier as if they were
single ended amplifiers and VSis the total supply voltage (2)
3. Calculate the total RMS power:
PT= PAMP + PD(3)
The maximum power that the LMH6552 package can dissipate at a given temperature can be derived with the
following equation:
PMAX = (150° – TAMB)/ θJA
where
• TAMB = Ambient temperature (°C)
•θJA = Thermal resistance, from junction to ambient, for a given package (°C/W)
• For the SOIC package θJA is 150°C/W
• For WSON package θJA is 58°C/W (4)
NOTE
If VCM is not 0V then there will be quiescent current flowing in the feedback network. This
current should be included in the thermal calculations and added into the quiescent power
dissipation of the amplifier.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LMH6552
LMH6552
SNOSAX9H –APRIL 2007–REVISED MARCH 2013
www.ti.com
THERMAL PERFORMANCE
The WSON package is designed for enhanced thermal performance and features an exposed die attach pad
(DAP) at the bottom center of the package that creates a direct path to the PCB for maximum power dissipation.
The DAP is floating and is not electrically connected to internal circuitry. Compared to the traditional leaded
packages where the die attach pad is embedded inside the molding compound, the WSON reduces one layer in
the thermal path.
The thermal advantage of the WSON package is fully realized only when the exposed die attach pad is soldered
down to a thermal land on the PCB board with thermal vias planted underneath the thermal land. The thermal
land can be connected to any power or ground plane within the allowable supply voltage range of the device.
Based on thermal analysis of the WSON package, the junction-to-ambient thermal resistance (θJA) can be
improved by a factor of two when the die attach pad of the WSON package is soldered directly onto the PCB
with thermal land and thermal vias are 1.27 mm and 0.33 mm respectively. Typical copper via barrel plating is 1
oz, although thicker copper may be used to further improve thermal performance.
For more information on board layout techniques, refer to Application Note 1187 “Leadless Lead Frame Package
(LLP).” This application note also discusses package handling, solder stencil and the assembly process.
ESD PROTECTION
The LMH6552 is protected against electrostatic discharge (ESD) on all pins. The LMH6552 will survive 2000V
Human Body model and 200V Machine model events. Under normal operation the ESD diodes have no affect on
circuit performance. There are occasions, however, when the ESD diodes will be evident. If the LMH6552 is
driven by a large signal while the device is powered down the ESD diodes will conduct. The current that flows
through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is
possible to power up a chip with a large signal applied to the input pins. Using the shutdown mode is one way to
conserve power and still prevent unexpected operation.
BOARD LAYOUT
The LMH6552 is a very high performance amplifier. In order to get maximum benefit from the differential circuit
architecture board layout and component selection is very critical. The circuit board should have a low
inductance ground plane and well bypassed broad supply lines. External components should be leadless surface
mount types. The feedback network and output matching resistors should be composed of short traces and
precision resistors (0.1%). The output matching resistors should be placed within 3 or 4 mm of the amplifier as
should the supply bypass capacitors. Refer to POWER SUPPLY BYPASSING for recommendations on bypass
circuit layout. Evaluation boards are available free of charge through the product folder on ti.com.
By design, the LMH6552 is relatively insensitive to parasitic capacitance at its inputs. Nonetheless, ground and
power plane metal should be removed from beneath the amplifier and from beneath RFand RGfor best
performance at high frequency.
With any differential signal path, symmetry is very important. Even small amounts of asymmetry can contribute to
distortion and balance errors.
EVALUATION BOARD
See the LMH6552 Product Folder for evaluation board availability and ordering information.
24 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LMH6552
LMH6552
www.ti.com
SNOSAX9H –APRIL 2007–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision G (March 2013) to Revision H Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 24
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: LMH6552
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
LMH6552MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH65
52MA
LMH6552MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH65
52MA
LMH6552SD/NOPB ACTIVE WSON NGS 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 6552
LMH6552SDX/NOPB ACTIVE WSON NGS 8 4500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 6552
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMH6552MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMH6552SD/NOPB WSON NGS 8 1000 178.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1
LMH6552SDX/NOPB WSON NGS 8 4500 330.0 12.4 3.3 2.8 1.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 21-Mar-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMH6552MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMH6552SD/NOPB WSON NGS 8 1000 210.0 185.0 35.0
LMH6552SDX/NOPB WSON NGS 8 4500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 21-Mar-2013
Pack Materials-Page 2
MECHANICAL DATA
NGS0008C
www.ti.com
SDA08C (Rev A)
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