IDT6116SA IDT6116LA CMOS STATIC RAM 16K (2K x 8 BIT) Integrated Device Technology, Inc. FEATURES: DESCRIPTION: * High-speed access and chip select times -- Military: 20/25/35/45/55/70/90/120/150ns (max.) -- Commercial: 15/20/25/35/45ns (max.) * Low-power consumption * Battery backup operation -- 2V data retention voltage (LA version only) * Produced with advanced CMOS high-performance technology * CMOS process virtually eliminates alpha particle soft-error rates * Input and output directly TTL-compatible * Static operation: no clocks or refresh required * Available in ceramic and plastic 24-pin DIP, 24-pin Thin Dip and 24-pin SOIC and 24-pin SOJ * Military product compliant to MIL-STD-833, Class B The IDT6116SA/LA is a 16,384-bit high-speed static RAM organized as 2K x 8. It is fabricated using IDT's high-performance, high-reliability CMOS technology. Access times as fast as 15ns are available. The circuit also offers a reduced power standby mode. When CS goes HIGH, the circuit will automatically go to, and remain in, a standby power mode, as long as CS remains HIGH. This capability provides significant system level power and cooling savings. The low-power (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1W to 4W operating off a 2V battery. All inputs and outputs of the IDT6116SA/LA are TTLcompatible. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. The IDT6116SA/LA is packaged in 24-pin 600 and 300 mil plastic or ceramic DIP and a 24-lead gull-wing SOIC, and a 24 -lead J-bend SOJ providing high board-level packing densities. Military grade product is manufactured in compliance to the latest version of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. FUNCTIONAL BLOCK DIAGRAM A0 V CC 128 X 128 MEMORY ARRAY ADDRESS DECODER GND A 10 I/O 0 I/O CONTROL INPUT DATA CIRCUIT I/O 7 CS OE WE CONTROL CIRCUIT 3089 drw 01 The IDT logo is aregistered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. 5.1 MARCH 1996 3089/1 1 IDT6116SA/LA CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS CAPACITANCE (TA = +25C, F = 1.0 MHZ) A7 A6 A5 A4 A3 A2 A1 A0 I/O 0 I/O 1 I/O 2 GND 1 2 3 4 5 6 7 8 9 10 11 12 P24-2 P24-1 D24-2 D24-1 SO24-2 & S024-4 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 A9 Symbol Parameter(1) CIN Input Capacitance CI/O I/O Capacitance Conditions Max. Unit VIN = 0V 8 pF VOUT = 0V 8 pF NOTE: 3089 tbl 03 1. This parameter is determined by device characterization, but is not production tested. WE OE A10 CS I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 3089 drw 02 ABSOLUTE MAXIMUM RATINGS (1) DIP/SOIC/SOJ TOP VIEW Symbol Rating Commercial Military Terminal Voltage VTERM(2) with Respect to GND -0.5 to + 7.0 -0.5 to +7.0 PIN DESCRIPTIONS A0-A13 Address Inputs I/O0-I/O7 Data Input/Output CS Chip Select WE Write Enable OE Output Enable VCC Power GND Ground 3089 tbl 01 TA Operating Temperature TBIAS Unit V -55 to +125 C Temperature Under Bias -55 to + 125 -65 to +135 C TSTG Storage Temperature -55 to + 125 -65 to +150 C PT Power Dissipation 1.0 1.0 W IOUT DC Output Current 50 50 mA 0 to + 70 NOTES: 3089 tbl 04 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC +0.5V. TRUTH TABLE(1) Mode Standby CS OE WE H X X I/O High-Z Read L L H DATAOUT Read L H H High-Z Write L X L DATAIN NOTE: 1. H = VIH, L = VIL, X = Don't Care. 3089 tbl 02 5.1 2 IDT6116SA/LA CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES RECOMMENDED DC OPERATING CONDITIONS RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Ambient Temperature Grade Symbol GND VCC Parameter Min. Typ. Max. Unit V V VCC Supply Voltage 4.5 5.0 5.5(2) Military -55C to +125C 0V 5.0V 10% GND Supply Ground 0 0 0 Commercial 0C to +70C 0V 5.0V 10% VIH Input High Voltage 2.2 3.5 VCC +0.5 V VIL Input Low Voltage -0.5(1) -- 0.8 V 3089 tbl 05 NOTES: 3089 tbl 06 1. VIL (min.) = -3.0V for pulse width less than 20ns, once per cycle. 2. VIN must not exceed VCC +0.5V. DC ELECTRICAL CHARACTERISTICS VCC = 5.0V 10% IDT6116SA Min. Max. Symbol Parameter Test Conditions |ILI| Input Leakage Current VCC = Max., VIN = GND to VCC |ILO| Output Leakage Current VCC = Max. CS = VIH, VOUT = GND to VCC IDT6116LA Min. Max. MIL. -- 10 -- 5 COM'L. -- 5 -- 2 MIL. -- 10 -- 5 COM'L. -- 5 -- 2 Unit A A VOL Output Low Voltage IOL = 8mA, VCC = Min. -- 0.4 -- 0.4 V VOH Output High Voltage IOH = -4mA, VCC = Min. 2.4 -- 2.4 -- V 3089 tbl 07 DC ELECTRICAL CHARACTERISTICS (1) VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC - 0.2V 6116SA15(2) 6116LA15(2) Symbol Parameter ICC1 Operating Power Supply Current, CS VIL, Outputs Open, VCC = Max., f = 0 SA ICC2 ISB ISB1 Power Com'l. 6116SA20 6116LA20 Mil. Com'l. 105 -- 105 LA 95 -- Dynamic Operating Current, CS VIL, VCC = Max., Outputs Open, f = fMAX(4) SA 150 LA Standby Power Supply Current (TTL Level) CS VIH, VCC = Max., Outputs Open, f = fMAX(4) Full Standby Power Supply Current (CMOS Level), CS V HC, VCC = Max., VIN V HC or VIN VLC, f = 0 Mil. 6116SA25 6116LA25 6116SA35 6116LA35 Com'l. Mil. Com'l. Mil. Unit 130 80 90 80 90 mA 95 120 75 85 75 85 -- 130 150 120 135 100 115 140 -- 120 140 110 125 95 105 SA 40 -- 40 50 40 45 25 35 LA 35 -- 35 45 35 40 25 30 SA 2 -- 2 10 2 10 2 10 LA 0.1 -- 0.1 0.9 0.1 0.9 0.1 0.9 NOTES: 1. All values are maximum guaranteed values. 2. 0C to + 70C temperature range only. 3. -55C to + 125C temperature range only. 4. fMAX = 1/tRC, only address inputs are cycling at fMAX, f = 0 means address inputs are not changing. 5.1 mA mA mA 3089 tbl 08 3 IDT6116SA/LA CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS (1) (Continued) VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC - 0.2V 6116SA45 6116LA45 Symbol ICC1 ICC2 ISB ISB1 Parameter Power Com'l. Mil. 6116SA55(3) 6116LA55(3) 6116SA70(3) 6116LA70(3) 6116SA90(3) 6116LA90(3) 6116SA120(3) 6116LA120(3) 6116SA150(3) 6116LA150(3) Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Unit mA Operating Power Supply Current, CS VIL, Outputs Open, VCC = Max., f = 0 SA 80 90 -- 90 -- 90 -- 90 -- 90 -- 90 LA 75 85 -- 85 -- 85 -- 85 -- 85 -- 85 Dynamic Operating Current, CS VIL, VCC = Max., Outputs Open, f = fMAX(4) SA 100 100 -- 100 -- 100 -- 100 -- 100 -- 90 LA 90 95 -- 90 -- 90 -- 85 -- 85 -- 85 Standby Power Supply Current (TTL Level) CS VIH, VCC = Max., Outputs Open, f = fMAX(4) SA 25 25 -- 25 -- 25 -- 25 -- 25 -- 25 LA 20 20 -- 20 -- 20 -- 25 -- 15 -- 15 Full Standby Power Supply Current (CMOS Level), CS V HC, VCC = Max., VIN V HC or VIN VLC, f = 0 SA 2 10 -- 10 -- 10 -- 10 -- 10 -- 10 LA 0.1 0.9 -- 0.9 -- 0.9 -- 0.9 -- 0.9 -- 0.9 NOTES: 1. All values are maximum guaranteed values. 2. 0C to + 70C temperature range only. 3. -55C to + 125C temperature range only. 4. fMAX = 1/tRC, only address inouts are toggling at fMAX, f = 0 means address inputs are not changing. mA mA mA 3089 tbl 09 DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V Typ.(1) Max. VCC VCC Symbol Parameter Test Conditions Min. 2.0V 3.0V 2.0V 3.0V Unit VDR VCC for Data Retention -- 2.0 -- -- -- -- V ICCDR Data Retention Current MIL. -- 0.5 1.5 200 300 A COM'L. -- 0.5 1.5 20 30 -- 0 -- -- -- CS VHC VIN VHC or VLC tCDR(3) Data Deselect to Data Retention Time tR(3) Operation Recovery Time tRC(2) -- -- -- -- ns |ILI| Input Leakage Current -- -- -- 2 2 A NOTES: 1. TA = + 25C 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization, but is not production tested. 5.1 ns 3089 tbl 10 4 IDT6116SA/LA CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES LOW VCC DATA RETENTION WAVEFORM DATA RETENTION MODE V CC V DR 2V 4.5V 4.5V tCDR tR V DR CS V IH V IH 3089 drw 03 AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and 2 3089 tbl 11 5V 5V 480 480 DATAOUT DATA OUT 255 255 30pF* 5pF* 3089 drw 04 3089 drw 05 Figure 1. AC Test Load Figure 2. AC Test Load (for tOLZ, tCLZ, tOHZ, tWHZ, tCHZ & tOW) *Including scope and jig. 5.1 5 IDT6116SA/LA CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (VCC = 5V 10%, All Temperature Ranges) 6116SA15(1) 6116LA15(1) Symbol Parameter Min. 6116SA20 6116LA20 Max. Min. 6116SA25 6116LA25 Max. Min. 6116SA35 6116LA35 Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 15 -- 20 -- 25 -- 35 -- ns tAA Address Access Time -- 15 -- 19 -- 25 -- 35 ns tACS Chip Select Access Time -- 15 -- 20 -- 25 -- 35 ns tCLZ(3) Chip Select to Output in Low-Z 5 -- 5 -- 5 -- 5 -- ns tOE Output Enable to Output Valid -- 10 -- 10 -- 13 -- 20 ns tOLZ(3) Output Enable to Output in Low-Z 0 -- 0 -- 5 -- 5 -- ns tCHZ(3) Chip Deselect to Output in High-Z -- 10 -- 11 -- 12 -- 15 ns tOHZ(3) Output Disable to Output in High-Z -- 8 -- 8 -- 10 -- 13 ns tOH Output Hold from Address Change 5 -- 5 -- 5 -- 5 -- ns tPU(3) Chip Select to Power-Up Time 0 -- 0 -- 0 -- 0 -- ns tPD(3) Chip Deselect to PowerDown Time -- 15 -- 20 -- 25 -- 35 ns 3089 tbl 12 AC ELECTRICAL CHARACTERISTICS (VCC = 5V 10%, All Temperature Ranges) (Continued) Symbol Parameter 6116SA45 6116LA45 6116SA55(2) 6116LA55(2) 6116SA70(2) 6116SA90(2) 6116LA70(2) 6116LA90(2) Min. Max. Min. Max. Min. Max. Min. 6116SA120(2) 6116SA150(2) 6116LA120(2) 6116LA150(2) Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 45 -- 55 -- 70 -- 90 -- 120 -- 150 -- ns tAA Address Access Time -- 45 -- 55 -- 70 -- 90 -- 120 -- 150 ns Chip Select Access Time -- 45 -- 50 -- 65 -- 90 -- 120 -- 150 ns Chip Select to Output in Low-Z 5 -- 5 -- 5 -- 5 -- 5 -- 5 -- ns tOE Output Enable to Output Valid -- 25 -- 40 -- 50 -- 60 -- 80 -- 100 ns tOLZ(3) Output Enable to Output in Low-Z 5 -- 5 -- 5 -- 5 -- 5 -- 5 -- ns tCHZ(3) Chip Deselect to Output in High-Z -- 20 -- 30 -- 35 -- 40 -- 40 -- 40 ns tOHZ(3) Output Disable to Output in High-Z -- 15 -- 30 -- 35 -- 40 -- 40 -- 40 ns tOH Output Hold from Address Change 5 -- 5 -- 5 -- 5 -- 5 -- 5 -- ns tACS tCLZ (3) NOTES: 1. 0C to + 70C temperature range only. 2. -55C to + 125C temperature range only. 3. This parameter guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. 5.1 3089 tbl 13 6 IDT6116SA/LA CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ CYCLE NO. 1(1, 3) tRC ADDRESS tAA tOH OE tOE CS tOHZ (5) tOLZ (5) tACS tCHZ (5) tCLZ (5) DATA VALID DATA OUT ICC tPU V CC Supply Currents ISB tPD 3089 drw 06 TIMING WAVEFORM OF READ CYCLE NO. 2 (1, 2, 4) tRC ADDRESS tAA tOH tOH DATA OUT DATA VALID PREVIOUS DATA VALID 3089 drw 07 TIMING WAVEFORM OF READ CYCLE NO. 3 (1, 3, 4) CS tCLZ (5) tACS tCHZ DATA OUT (5) DATA VALID 3089 drw 08 NOTES: 1. WE is HIGH for Read cycle. 2. Device is continously selected, CS is LOW. 3. Address valid prior to or coincident with CS transition LOW. 4. OE is LOW. 5. Transition is measured 500mV from steady state. 5.1 7 IDT6116SA/LA CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (VCC = 5V 10%, All Temperature Ranges) 6116SA15(1) 6116LA15(1) Symbol Parameter 6116SA20 6116LA20 6116SA25 6116LA25 6116SA35 6116LA35 Min. Max. Min. Max. Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time 15 -- 20 -- 25 -- 35 -- ns tCW Chip Select to End-ofWrite 13 -- 15 -- 17 -- 25 -- ns tAW Address Valid to Endof-Write 14 -- 15 -- 17 -- 25 -- ns tAS Address Set-up Time 0 -- 0 -- 0 -- 0 -- ns tWP Write Pulse Width 12 -- 12 -- 15 -- 20 -- ns tWR Write Recovery Time 0 -- 0 -- 0 -- 0 -- ns tWHZ(3) Write to Output in High-Z -- 7 -- 8 -- 16 -- 20 ns tDW Data to Write Time Overlap 12 -- 12 -- 13 -- 15 -- ns tDH(4) Data Hold from Write Time 0 -- 0 -- 0 -- 0 -- ns tOW(3,4) Output Active from End-of-Write 0 -- 0 -- 0 -- 0 -- ns 3089 tbl 14 AC ELECTRICAL CHARACTERISTICS (VCC = 5V 10%, All Temperature Ranges) 6116SA45 6116LA45 Symbol Parameter 6116SA55(2) 6116LA55(2) Min. Max. Min. Max. 6116SA70(2) 6116LA70(2) Min. Max. 6116SA90(2) 6116LA90(2) 6116SA120(2) 6116SA150(2) 6116LA120(2) 6116LA150(2) Min. Max. Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time 45 -- 55 -- 70 -- 90 -- 120 -- 150 -- ns tCW Chip Select to End of Write 30 -- 40 -- 40 -- 55 -- 70 -- 90 -- ns tAW Address Valid to End of Write 30 -- 45 -- 65 -- 80 -- 105 -- 120 -- ns tAS Address Set-up Time 0 -- 5 -- 15 -- 15 -- 20 -- 20 -- ns tWP Write Pulse Width 25 -- 40 -- 40 -- 55 -- 70 -- 90 -- ns tWR Write Recovery Time 0 -- 5 -- 5 -- 5 -- 5 -- 10 -- ns tWHZ(3) Write to Output in High-Z -- 25 -- 30 -- 35 -- 40 -- 40 -- 40 ns tDW Data to Write Time Overlap 20 -- 25 -- 30 -- 30 -- 35 -- 40 -- ns tDH(4) Data Hold from Write Time 0 -- 5 -- 5 -- 5 -- 5 -- 10 -- ns 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- ns tOW(3,4) Output Active from End of Write NOTES: 3089 tbl 15 1. 0C to +70C temperature range only. 2. -55C to +125C temperature range only. 3. This parameter guaranteed with AC Load (Figure 2) by device characterization, but is not production tested. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operation conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5.1 8 IDT6116SA/LA CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 1, (WE CONTROLLED TIMING) (1, 2, 5, 7) tWC ADDRESS tAW CS (3) tWP(7) tAS tWR tCHZ (6) WE (6) tWHZ DATA OUT PREVIOUS DATA VALID tOW (4) tDW DATA IN (6) DATA (4) VALID tDH DATA VALID 3089 drw 09 TIMING WAVEFORM OF WRITE CYCLE NO. 2, (CS CONTROLLED TIMING) (1, 2, 3, 5, 7) tWC ADDRESS tAW CS tWR tAS (3) tCW WE tDW DATA IN tDH DATA VALID 3089 drw 10 NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. During this period, the I/O pins are in the output state and the input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. 6. Transition is measured 500mV from steady state. 7. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse is the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW. 5.1 9 IDT6116SA/LA CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT 6116 XX XXX X X Device Type Power Speed Package Process/ Temperature Range Blank Commercial (0C to +70C) Military (-55C to + 125C) B Compliant to MIL-STD-883, Class B 5.1 TP P TD D SO Y 300 mil Plastic DIP (P24-1) 600 mil Plastic DIP (P24-2) 300 mil CERDIP (D24-1) 600 mil CERDIP (D24-2) 300 mil Small Outline IC, Gull-Wing Bend (SO24-2) 300 mil SOJ, J-Bend (SO24-4) 15 20 25 35 45 55 70 90 120 150 Commercial Only SA LA Standard Power Low Power Military Only Military Only Military Only Military Only Military Only Speed in nanoseconds 3089 drw 11 10