Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES MARCH 1996
1996 Integrated Device Technology, Inc. 5.1 3089/1
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
The IDT logo is aregistered trademark of Integrated Device Technology, Inc.
FEATURES:
• High-speed access and chip select times
— Military: 20/25/35/45/55/70/90/120/150ns (max.)
— Commercial: 15/20/25/35/45ns (max.)
• Low-power consumption
• Battery backup operation
— 2V data retention voltage (LA version only)
• Produced with advanced CMOS high-performance
technology
• CMOS process virtually eliminates alpha particle
soft-error rates
• Input and output directly TTL-compatible
• Static operation: no clocks or refresh required
• Available in ceramic and plastic 24-pin DIP, 24-pin Thin
Dip and 24-pin SOIC and 24-pin SOJ
• Military product compliant to MIL-STD-833, Class B
DESCRIPTION:
The IDT6116SA/LA is a 16,384-bit high-speed static RAM
organized as 2K x 8. It is fabricated using IDT's high-perfor-
mance, high-reliability CMOS technology.
Access times as fast as 15ns are available. The circuit also
offers a reduced power standby mode. When
CS
goes HIGH,
the circuit will automatically go to, and remain in, a standby
power mode, as long as
CS
remains HIGH. This capability
provides significant system level power and cooling savings.
The low-power (LA) version also offers a battery backup data
retention capability where the circuit typically consumes only
1µW to 4µW operating off a 2V battery.
All inputs and outputs of the IDT6116SA/LA are TTL-
compatible. Fully static asynchronous circuitry is used, requir-
ing no clocks or refreshing for operation.
The IDT6116SA/LA is packaged in 24-pin 600 and 300 mil
plastic or ceramic DIP and a 24-lead gull-wing SOIC, and a 24
-lead J-bend SOJ providing high board-level packing densi-
ties.
Military grade product is manufactured in compliance to the
latest version of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
CS
A0
A10
I/O 0
I/O7
OE
WE
128 X 128
MEMORY
ARRAY
I/O CONTROL
ADDRESS
DECODER
INPUT
DATA
CIRCUIT
CONTROL
CIRCUIT
GND
3089 drw 01
VCC
1
IDT6116SA
IDT6116LA
CMOS STATIC RAM
16K (2K x 8 BIT)
5.1 2
IDT6116SA/LA
CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATINGS (1)
Symbol Rating Commercial Military Unit
Terminal Voltage
VTERM(2) with Respect to GND –0.5 to + 7.0 –0.5 to +7.0 V
Operating
TATemperature 0 to + 70 –55 to +125 °C
Temperature
TBIAS Under Bias –55 to + 125 –65 to +135 °C
Storage
TSTG Temperature –55 to + 125 –65 to +150 °C
Power
PTDissipation 1.0 1.0 W
IOUT DC Output Current 50 50 mA
NOTES: 3089 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed VCC +0.5V.
TRUTH TABLE(1)
Mode
CS
CS OE
OE WE
WE
I/O
Standby H X X High-Z
Read L L H DATAOUT
Read L H H High-Z
Write L X L DATAIN
NOTE: 3089 tbl 02
1. H = VIH, L = VIL, X = Don't Care.
PIN DESCRIPTIONS
A0–A13 Address Inputs
I/O0–I/O7Data Input/Output
CS
Chip Select
WE
Write Enable
OE
Output Enable
VCC Power
GND Ground 3089 tbl 01
CAPACITANCE (TA = +25°C, F = 1.0 MHZ)
Symbol Parameter(1) Conditions Max. Unit
CIN Input Capacitance VIN = 0V 8 pF
CI/O I/O Capacitance VOUT = 0V 8 pF
NOTE: 3089 tbl 03
1. This parameter is determined by device characterization, but is not
production tested.
DIP/SOIC/SOJ
TOP VIEW
3089 drw 02
5
6
7
8
9
10
11
12
GND
1
2
3
4
24
23
22
21
20
19
18
17
P24-2
P24-1
D24-2
D24-1
SO24-2
&
S024-4
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
V
CC
A
9
WE
A
10
I/O
5
I/O
4
OE
16
15
14
13
A
7
A
6
I/O
7
I/O
6
CS
A
8
I/O
2
I/O
3
5.1 3
IDT6116SA/LA
CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
6116SA15(2) 6116SA20 6116SA25 6116SA35
6116LA15(2) 6116LA20 6116LA25 6116LA35
Symbol Parameter Power Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Unit
ICC1 Operating Power Supply SA 105 — 105 130 80 90 80 90 mA
Current,
CS
≤ VIL,
Outputs Open, LA 95 — 95 120 75 85 75 85
VCC = Max., f = 0
ICC2 Dynamic Operating SA 150 — 130 150 120 135 100 115 mA
Current,
CS
≤ VIL,
VCC = Max., LA 140 — 120 140 110 125 95 105
Outputs Open, f = fMAX(4)
ISB Standby Power Supply SA 40 — 40 50 40 45 25 35 mA
Current (TTL Level)
CS
≥ VIH, VCC = Max., LA 35 — 35 45 35 40 25 30
Outputs Open, f = fMAX(4)
ISB1 Full Standby Power SA 2 — 2 10 2 10 2 10 mA
Supply Current
(CMOS Level),
CS
≥ VHC, LA 0.1 — 0.1 0.9 0.1 0.9 0.1 0.9
VCC = Max., VIN ≥ VHC
or VIN ≤ VLC, f = 0
NOTES: 3089 tbl 08
1. All values are maximum guaranteed values.
2. 0°C to + 70°C temperature range only.
3. –55°C to + 125°C temperature range only.
4. fMAX = 1/tRC, only address inputs are cycling at fMAX, f = 0 means address inputs are not changing.
DC ELECTRICAL CHARACTERISTICS (1)
VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V ± 10%
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Grade Temperature GND VCC
Military –55°C to +125°C 0V 5.0V ± 10%
Commercial 0°C to +70°C 0V 5.0V ± 10%
3089 tbl 05
IDT6116SA IDT6116LA
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
MIL. — 10 — 5
|ILI| Input Leakage Current VCC = Max., VIN = GND to VCC COM'L. — 5 — 2 µA
VCC = Max. MIL. — 10 — 5
|ILO| Output Leakage Current
CS
= VIH, VOUT = GND to VCC COM'L. — 5 — 2 µA
VOL Output Low Voltage IOL = 8mA, VCC = Min. — 0.4 — 0.4 V
VOH Output High Voltage IOH = –4mA, VCC = Min. 2.4 — 2.4 — V
3089 tbl 07
RECOMMENDED DC
OPERATING CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 4.5 5.0 5.5(2) V
GND Supply Ground 0 0 0 V
VIH Input High Voltage 2.2 3.5 VCC +0.5 V
VIL Input Low Voltage –0.5(1) — 0.8 V
NOTES: 3089 tbl 06
1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle.
2. VIN must not exceed VCC +0.5V.
5.1 4
IDT6116SA/LA
CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
NOTES: 3089 tbl 10
1. TA = + 25°C
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
(LA Version Only) VLC = 0.2V, VHC = VCC – 0.2V
DC ELECTRICAL CHARACTERISTICS (1) (Continued)
VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V
NOTES: 3089 tbl 09
1. All values are maximum guaranteed values.
2. 0°C to + 70°C temperature range only.
3. –55°C to + 125°C temperature range only.
4. fMAX = 1/tRC, only address inouts are toggling at fMAX, f = 0 means address inputs are not changing.
VCC VCC
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
Typ.(1) Max.
Symbol Parameter Test Conditions Min. 2.0V 3.0V 2.0V 3.0V Unit
VDR VCC for Data Retention — 2.0 — — — — V
ICCDR Data Retention Current MIL. — 0.5 1.5 200 300 µA
CS
≥ VHC COM'L. — 0.5 1.5 20 30
tCDR(3) Data Deselect to Data VIN ≥ VHC or ≤ VLC —0 ——— ns
Retention Time
tR(3) Operation Recovery Time tRC(2) ———— ns
|ILI| Input Leakage Current — — — 2 2 µA
6116SA45 6116SA55(3) 6116SA70(3) 6116SA90(3) 6116SA120(3) 6116SA150(3)
6116LA45 6116LA55(3) 6116LA70(3) 6116LA90(3) 6116LA120(3) 6116LA150(3)
Symbol Parameter Power Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Unit
ICC1 Operating Power Supply SA 80 90 — 90 — 90 — 90 — 90 — 90 mA
Current,
CS
≤ VIL,
Outputs Open, LA 75 85 — 85 — 85 — 85 — 85 — 85
VCC = Max., f = 0
ICC2 Dynamic Operating SA 100 100 — 100 — 100 — 100 — 100 — 90 mA
Current,
CS
≤ VIL,
VCC = Max., LA 90 95 — 90 — 90 — 85 — 85 — 85
Outputs Open, f = fMAX(4)
ISB Standby Power Supply SA 25 25 — 25 — 25 — 25 — 25 — 25 mA
Current (TTL Level)
CS
≥ VIH, VCC = Max., LA 20 20 — 20 — 20 — 25 — 15 — 15
Outputs Open, f = fMAX(4)
ISB1 Full Standby Power SA 2 10 — 10 — 10 — 10 — 10 — 10 mA
Supply Current
(CMOS Level),
CS
≥ VHC, LA 0.1 0.9 — 0.9 — 0.9 — 0.9 — 0.9 — 0.9
VCC = Max., VIN ≥ VHC
or VIN ≤ VLC, f = 0
5.1 5
IDT6116SA/LA
CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOW VCC DATA RETENTION WAVEFORM
Figure 2. AC Test Load
(for tOLZ, tCLZ, tOHZ,
tWHZ, tCHZ & tOW)
Figure 1. AC Test Load
*Including scope and jig.
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
AC Test Load See Figures 1 and 2
3089 tbl 11
5pF*
255
Ω
5V
480
Ω
DATAOUT
3089 drw 05
3089 drw 04
30pF*255
Ω
5V
DATA
OUT
480
Ω
DATA RETENTION MODE
V
CC
CS
t
CDR
4.5V V
DR
≥
2V
V
DR
4.5V
t
R
V
IH
V
IH
3089 drw 03
5.1 6
IDT6116SA/LA
CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
3089 tbl 12
AC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 10%, All Temperature Ranges) (Continued)
6116SA45 6116SA55(2) 6116SA70(2) 6116SA90(2) 6116SA120(2) 6116SA150(2)
6116LA45 6116LA55(2) 6116LA70(2) 6116LA90(2) 6116LA120(2) 6116LA150(2)
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 45 — 55 — 70 — 90 — 120 — 150 — ns
tAA Address Access Time — 45 — 55 — 70 — 90 — 120 — 150 ns
tACS Chip Select Access Time — 45 — 50 — 65 — 90 — 120 — 150 ns
tCLZ(3) Chip Select to Output in 5 — 5 — 5 — 5 — 5 — 5 — ns
Low-Z
tOE Output Enable to Output — 25 — 40 — 50 — 60 — 80 — 100 ns
Valid
tOLZ(3) Output Enable to Output 5 — 5 — 5 — 5 — 5 — 5 — ns
in Low-Z
tCHZ(3) Chip Deselect to Output — 20 — 30 — 35 — 40 — 40 — 40 ns
in High-Z
tOHZ(3) Output Disable to Output — 15 — 30 — 35 — 40 — 40 — 40 ns
in High-Z
tOH Output Hold from 5 — 5 — 5 — 5 — 5 — 5 — ns
Address Change
NOTES: 3089 tbl 13
1. 0°C to + 70°C temperature range only.
2. –55°C to + 125°C temperature range only.
3. This parameter guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
AC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 10%, All Temperature Ranges)
6116SA15(1) 6116SA20 6116SA25 6116SA35
6116LA15(1) 6116LA20 6116LA25 6116LA35
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 15 — 20 — 25 — 35 — ns
tAA Address Access Time — 15 — 19 — 25 — 35 ns
tACS Chip Select Access Time — 15 — 20 — 25 — 35 ns
tCLZ(3) Chip Select to Output in 5 — 5 — 5 — 5 — ns
Low-Z
tOE Output Enable to Output — 10 — 10 — 13 — 20 ns
Valid
tOLZ(3) Output Enable to Output 0 — 0 — 5 — 5 — ns
in Low-Z
tCHZ(3) Chip Deselect to Output — 10 — 11 — 12 — 15 ns
in High-Z
tOHZ(3) Output Disable to Output — 8 — 8 — 10 — 13 ns
in High-Z
tOH Output Hold from 5 — 5 — 5 — 5 — ns
Address Change
tPU(3) Chip Select to Power-Up 0 — 0 — 0 — 0 — ns
Time
tPD(3) Chip Deselect to Power- — 15 — 20 — 25 — 35 ns
Down Time
5.1 7
IDT6116SA/LA
CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2 (1, 2, 4)
TIMING WAVEFORM OF READ CYCLE NO. 1(1, 3)
TIMING WAVEFORM OF READ CYCLE NO. 3 (1, 3, 4)
NOTES:
1.
WE
is HIGH for Read cycle.
2. Device is continously selected,
CS
is LOW.
3. Address valid prior to or coincident with
CS
transition LOW.
4.
OE
is LOW.
5. Transition is measured ±500mV from steady state.
CS
t
ACS
DATA
OUT
t
CLZ (5)
t
CHZ (5)
DATA VALID
3089 drw 08
ADDRESS
t
RC
t
AA
t
OH
t
OH
DATA
OUT
3089 drw 07
PREVIOUS DATA VALID DATA VALID
ADDRESS
OE
CS
t
RC
t
AA
t
OE
t
ACS
DATA
OUT
t
OH
t
OLZ(5)
t
CLZ(5)
t
OHZ (5)
t
CHZ(5)
3089 drw 06
DATA
VALID
t
PD
I
CC
I
SB
t
PU
VCC
Supply
Currents
5.1 8
IDT6116SA/LA
CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
6116SA15(1) 6116SA20 6116SA25 6116SA35
6116LA15(1) 6116LA20 6116LA25 6116LA35
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
WRITE CYCLE
tWC Write Cycle Time 15 — 20 — 25 — 35 — ns
tCW Chip Select to End-of- 13 — 15 — 17 — 25 — ns
Write
tAW Address Valid to End- 14 — 15 — 17 — 25 — ns
of-Write
tAS Address Set-up Time 0 — 0 — 0 — 0 — ns
tWP Write Pulse Width 12 — 12 — 15 — 20 — ns
tWR Write Recovery Time 0 — 0 — 0 — 0 — ns
tWHZ(3) Write to Output — 7 — 8 — 16 — 20 ns
in High-Z
tDW Data to Write Time 12 — 12 — 13 — 15 — ns
Overlap
tDH(4) Data Hold from Write 0 — 0 — 0 — 0 — ns
Time
tOW(3,4) Output Active from 0 — 0 — 0 — 0 — ns
End-of-Write 3089 tbl 14
AC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 10%, All Temperature Ranges)
6116SA45 6116SA55(2) 6116SA70(2) 6116SA90(2) 6116SA120(2) 6116SA150(2)
6116LA45 6116LA55(2) 6116LA70(2) 6116LA90(2) 6116LA120(2) 6116LA150(2)
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
WRITE CYCLE
tWC Write Cycle Time 45 — 55 — 70 — 90 — 120 — 150 — ns
tCW Chip Select to End of 30 — 40 — 40 — 55 — 70 — 90 — ns
Write
tAW Address Valid to End 30 — 45 — 65 — 80 — 105 — 120 — ns
of Write
tAS Address Set-up Time 0 — 5 — 15 — 15 — 20 — 20 — ns
tWP Write Pulse Width 25 — 40 — 40 — 55 — 70 — 90 — ns
tWR Write Recovery Time 0 — 5 — 5 — 5 — 5 — 10 — ns
tWHZ(3) Write to Output — 25 — 30 — 35 — 40 — 40 — 40 ns
in High-Z
tDW Data to Write Time 20 — 25 — 30 — 30 — 35 — 40 — ns
Overlap
tDH(4) Data Hold from Write 0 — 5 — 5 — 5 — 5 — 10 — ns
Time
tOW(3,4) Output Active from 0 — 0 — 0 — 0 — 0 — 0 — ns
End of Write
NOTES: 3089 tbl 15
1. 0°C to +70°C temperature range only.
2. –55°C to +125°C temperature range only.
3. This parameter guaranteed with AC Load (Figure 2) by device characterization, but is not production tested.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operation conditions. Although tDH and tOW values will vary
over voltage and temperature, the actual tDH will always be smaller than the actual tOW.
AC ELECTRICAL CHARACTERISTICS (VCC = 5V ± 10%, All Temperature Ranges)
5.1 9
IDT6116SA/LA
CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, (
WE
WE
CONTROLLED TIMING) (1, 2, 5, 7)
TIMING WAVEFORM OF WRITE CYCLE NO. 2, (
CS
CS
CONTROLLED TIMING) (1, 2, 3, 5, 7)
NOTES:
1.
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW
CS
and a LOW
WE
.
3. tWR is measured from the earlier of
CS
or
WE
going HIGH to the end of the write cycle.
4. During this period, the I/O pins are in the output state and the input signals must not be applied.
5. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in the high-impedance state.
6. Transition is measured ±500mV from steady state.
7.
OE
is continuously HIGH. If
OE
is LOW during a
WE
controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the
I/O drivers to turn off and data to be placed on the bus for the required tDW. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not
apply and the write pulse is the specified tWP. For a
CS
controlled write cycle,
OE
may be LOW with no degradation to tCW.
CS
WE
DATA
IN
t
WC
t
AW
t
CW
t
WR(3)
t
DW
t
DH
t
AS
3089 drw 10
DATA VALID
ADDRESS
ADDRESS
DATA
OUT
CS
WE
DATA
IN
t
WC
t
AW
3089 drw 09
t
AS
t
WHZ(6)
(4)
t
DW
t
DH
(4)
t
OW
t
WR
t
CHZ (6)
t
WP(7)
(6)
PREVIOUS DATA VALID DATA
VALID
DATA VALID
(3)
5.1 10
IDT6116SA/LA
CMOS STATIC RAM 16K (2K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
Blank
B
TP
P
TD
D
SO
Y
15
20
25
35
45
55
70
90
120
150
SA
LA
Commercial (0
°
C to +70
°
C)
Military (-55
°
C to + 125
°
C)
Compliant to MIL-STD-883, Class B
300 mil Plastic DIP (P24-1)
600 mil Plastic DIP (P24-2)
300 mil CERDIP (D24-1)
600 mil CERDIP (D24-2)
300 mil Small Outline IC, Gull-Wing Bend (SO24-2)
300 mil SOJ, J-Bend (SO24-4)
Commercial Only
Military Only
Military Only
Military Only
Military Only
Military Only
Standard Power
Low Power
IDT 6116
Device Type XX
Power XXX
Speed X
Package X
Process/
Temperature
Range
3089 drw 11
Speed in nanoseconds
