Negative-Going VCC Transients
These supervisors are relatively immune to short-
duration, negative-going VCC transients (glitches),
which usually do not require the entire system to shut
down. Resets are issued to the µP during power-up,
power-down, and brownout conditions. The Typical
Operating Characteristics show a graph of the Maximum
VCC Transient Duration vs. Reset Threshold Overdrive,
for which reset pulses are not generated. The graph
was produced using negative-going VCC pulses, start-
ing at the standard monitored voltage and ending below
the reset threshold by the magnitude indicated (reset
threshold overdrive). The graph shows the maximum
pulse width that a negative-going VCC transient can
typically have without triggering a reset pulse. As the
amplitude of the transient increases (i.e., goes farther
below the reset threshold), the maximum allowable pulse
width decreases. Typically, a VCC transient that goes
100mV below the reset threshold and lasts for 20µs or
less will not trigger a reset pulse.
Ensuring a Valid RESET Output Down to
VCC = 0
The MAX6826–MAX6831 are guaranteed to operate
properly down to VCC = 1V. In applications that require
valid reset levels down to VCC = 0, a pulldown resistor to
active-low outputs (push/pull only, Figure 7) and a pullup
resistor to active-high outputs (push/pull only) will ensure
that the reset line is valid while the reset output can no
longer sink or source current. This scheme does not work
with the open-drain outputs of the MAX6828/MAX6831.
The resistor value used is not critical, but it must be small
enough not to load the reset output when VCC is above
the reset threshold. For falling slew rates greater than
1V/s, a 100kW is adequate.
Watchdog Software Considerations
One way to help the watchdog timer monitor software
execution more closely is to set and reset the watchdog
input at different points in the program, rather than pulsing
the watchdog input high-low-high or low-high-low. This
technique avoids a stuck loop, in which the watchdog
timer would continue to be reset inside the loop, keeping
the watchdog from timing out.
Figure 8 shows an example of a flow diagram where the
I/O driving the watchdog input is set high at the begin-
ning of the program, set low at the beginning of every
subroutine or loop, then set high again when the pro-
gram returns to the beginning. If the program should
hang in any subroutine, the problem would quickly be
corrected, since the I/O is continually set low and the
watchdog timer is allowed to time out, causing a reset
or interrupt to be issued. As described in the Watchdog
Input Current section, this scheme results in higher time
average WDI input current than does leaving WDI low
for the majority of the timeout period and periodically
pulsing it low-high-low.
Figure 8. Watchdog Flow Diagram
Figure 7. RESET Valid to VCC = Ground Circuit
START
SET WDI
HIGH
PROGRAM
CODE
SUBROUTINE OR
PROGRAM LOOP
SET WDI LOW
RETURN
MAX6826
MAX6829
VCC
R1
100kΩ
RESET
GND
www.maximintegrated.com Maxim Integrated
│
10
MAX6826-MAX6831 Dual Ultra-Low-Voltage SOT23 µP Supervisors with
Manual Reset and Watchdog Timer