2004 Microchip Technology Inc. Preliminary DS41250A
PIC16F91X
Data Sheet
28/40/44-Pin Flash-Based, 8-Bit
CMOS Microcontrollers with
nanoWatt Technology
DS41250A-page ii Preliminary 2004 Microchip Technology Inc.
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2004 Microchip Technology Inc. Preliminary DS41250A-page 1
PIC16F91X
28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology
High-Performance RISC CPU
• Only 35 instructions to learn:
- All single-cycle instructions except branches
• Operati ng spe ed:
- DC – 20 MHz oscillator/clock input
- DC – 200 ns instruction cycle
• Program Memory Read (PMR) capability
• Interrupt capability
• 8-level deep hardware stack
• Direct, Indirect and Relative Addressing modes
Special Microcontroller Features
• Precision Internal Oscillator:
- Factory calibrated to ±1%
- Software selectable frequency range of
8 MHz to 32 kHz
- Software tunable
- Two-Speed Start-up mode
- Crystal fail detect for critical applic ations
- Clock mode switching during operation for
power saving s
• Power-saving Sleep mode
• Wide operating voltage range (2.0V-5.5V)
• Industri al and Extend ed tem pera t ure range
• Power-on Reset (POR )
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Brown-out Reset (BOR) with software contro l
option
• Enhanced Low-Current Watchdog Timer (WDT)
with on -chip oscillator (software selectable
nominal 268 seconds with full prescaler) with
software enable
• Multiplexed Master Clear with pull-up/input pin
• Programmable code protection
• High-Enduran ce Flash/EEPROM cell:
- 100,000 write Flash end uran ce
- 1,000,000 write EEPROM endurance
- Flash/Data EEPROM retention: > 40 years
Low-Power Features
• Standby Current:
- 1 nA @ 2.0V, typical
• Operating Current:
-8.5µA @ 32 kHz, 2.0V, typical
-100µA @ 1 MHz, 2.0V, typical
• Watchdog Timer Current:
-1µA @ 2.0V, typical
Peripheral Feat ures
• Liquid Cr ystal Display module:
- Up to 24 segment drivers
- Four commons
• Up to 35 I/O pins and 1 input-only pin:
- High-current source/sink for direct LED drive
- Interrupt-on-pin change
- Individually programmable weak pull-ups
• In-Circuit Serial Prog ramming™ (ICSP™) via two
pins
• Analog comparator module with:
- Two analog compar ators
- Programmable on-chip voltage reference
(CVREF) module (% of VDD)
- Comparator inputs and outputs externally
accessible
• A/D Converter:
- 10-bit resolution and up to 8 channels
• Timer0: 8-bit timer/counter with 8-bit
progra mmab le pres caler
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
- Option to use OSC1 and OSC2 as Timer1
oscillator if INTOSCIO or LP mode is
selected
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Addressable Universal Synchronous
Asynchronous Receiver Transmitter (AUSART)
• Up to 2 Capture, Compare, PWM modules:
- 16-bit Capture, max. resolution 12.5 ns
- 16-bit Compare, max. resolution 200 ns
- 10-bit PWM, max. frequency 20 kHz
• Synchronous Serial Port (SSP) with I2C™
PIC16F91X
DS41250A-page 2 Preliminary 2004 Microchip Technology Inc.
Pin Diagrams – PIC16F914/917, 40-Pin
Device
Program
Memory Data Memory I/O 10-bit A/D
(ch)
LCD
(segment
drivers) CCP Timers
8/16-bit
Flash
(words) SRAM
(bytes) EEPROM
(bytes)
PIC16F913 4096 256 256 25 5 16 1 2/1
PIC16F914 4096 256 256 35 8 24 2 2/1
PIC16F916 8192 352 256 25 5 16 1 2/1
PIC16F917 8192 352 256 35 8 24 2 2/1
40-pin PDIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC16F914/917
RE3/MCLR/VPP
RA0/AN0/C1-/SEG12
RA1/AN1/C2-/SEG7
RA2/AN2/C2+/VREF-/COM2
RA3/AN3/C1+/VREF+/SEG15
RA4/C1OUT/T0CK1/SEG4
RA5/AN4/C2OUT/SS/SEG5
RE0/AN5/SEG21
RE1/AN6/SEG22
RE2/AN7/SEG23
VDD
VSS
RA7/OSC1/CLKI/T1OSI
RA6/OSC2/CLKO/T1OSO
RC0/VLCD1
RC1/VLCD2
RC2/VLCD3
RC3/SEG6
RD0/COM3
RD1
RB7/ICSPDAT/ICDDAT/SEG13
RB6/ICSPCLK/ICDCK/SEG14
RB5/COM1
RB4/COM0
RB3/SEG3
RB2/SEG2
RB1/SEG1
RB0/INT/SEG0
VDD
VSS
RD7/SEG20
RD6/SEG19
RD5/SEG18
RD4/SEG17
RC7/RX/DT/SDI/SDA/SEG8
RC6/TX/CK/SCK/SCL/SEG9
RC5/T1CKI/CCP1/SEG10
RC4/T1G/SDO/SEG11
RD3/SEG16
RD2/CCP2
2004 Microchip Technology Inc. Preliminary DS41250A-page 3
PIC16F91X
Pin Diagrams – PIC16F913/916, 28-Pin
28- pin PDIP, SOIC , SSOP
28-pin QFN
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
PIC16F913/916
RE3/MCLR/VPP
RA0/AN0/C1-/SEG12
RA1/AN1/C2-/SEG7
RA2/AN2/C2+/VREF-/COM2
RA3/AN3/C1+/VREF+/COM3/SEG15
RA4/C1OUT/T0CK1/SEG4
RA5/AN4/C2OUT/SS/SEG5
VSS
RA7/OSC1/CLKI/T1OSI
RA6/OSC2/CLKO/T1OSO
RC0/VLCD1
RC1/VLCD2
RC2/VLCD3
RC3/SEG6
RB7/ICSPDAT/ICDDAT/SEG13
RB6/ICSPCLK/ICDCK/SEG14
RB5/COM1
RB4/COM0
RB3/SEG3
RB2/SEG2
RB1/SEG1
RB0/INT/SEG0
VDD
VSS
RC7/RX/DT/SDI/SDA/SEG8
RC6/TX/CK/SCK/SCL/SEG9
RC5/T1CKI/CCP1/SEG10
RC4/T1G/SDO/SEG11
16
2
7
1
3
6
5
4
15
21
19
20
17
18
22
28
26
27
23
24
25
14
8
10
9
13
12
11
PIC16F913/916
RA1/AN1/C2-/SEG7
RA0/AN0/C1-/SEG12
RE3/MCLR/VPP
RB7/ICSPDAT/ICDDAT/SEG13
RB6/ICSPCLK/ICDCK/SEG14
RB5/COM1
RB4/COM0
RC0/VLCD1
RC1/VLCD2
RC2/VLCD3
RC3/SEG6
RC4/T1G/SDO/SEG11
RC5/T1CKI/CCP1/SEG10
RC6/TX/CK/SCK/SCL/SEG9
RA2/AN2/C2+/VREF-/COM2
RA3/AN3/C1+/VREF+/COM3/SEG15
RA4/C1OUT/T0CK1/SEG4
RA5/AN4/C2OUT/SS/SEG5
VSS
RA7/OSC1/CLKI/T1OSI
RA6/OSC2/CLKO/T1OSO
RB3/SEG3
RB2/SEG2
RB1/SEG1
RB0/INT/SEG0
VDD
VSS
RC7/RX/DT/SDI/SDA/SEG8
PIC16F91X
DS41250A-page 4 Preliminary 2004 Microchip Technology Inc.
Pin Diagrams – PIC16F914/917, 44-Pin
44-pin TQFP
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
5
4
PIC16F914/917
NC
RC0/VLCD1
RA6/OSC2/CLKO/T1OSO
RA7/OSC1/CLKI/T1OSI
VSS
VDD
RE2/AN7/SEG23
RE1/AN6/SEG22
RE0/AN5/SEG21
RA5/AN4/C2OUT/SS/SEG5
RA4/C1OUT/T0CK1/SEG4
RC7/RX/DT/SDI/SDA/SEG8
RD4/SEG17
RD5/SEG18
RD6/SEG19
RD7/SEG20
VSS
VDD
RB0/SEG0/INT
RB1/SEG1
RB2/SEG2
RB3/SEG3
NC
NC
RB4/COM0
RB5/COM1
RB6/ICSPCLK/ICDCK/SEG14
RB7/ICSPDAT/ICDDAT/SEG13
RE3/MCLR/VPP
RA0/C1-/AN0/SEG12
RA1/C2-/AN1/SEG7
RA2/AN2/C2+/VREF-/COM2
RA3/AN3/VREF+/C1+/SEG15
RC6/TX/CK/SCK/SCL/SEG9
RC5/T1CKI/CCP1/SEG10
RC4/T1G/SDO/SEG11
RD3/SEG16
RD2/CCP2
RD1
RD0/COM3
RC3/SEG6
RC2/VLCD3
RC1/VLCD2
NC
44-pin QFN
10
11
2
3
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
5
4
PIC16F914/917
RA6/OSC2/CLK0/T1OSO
RA7/OSC1/CLKI/T1OSI
VSS
VSS
NC
VDD
RE2/AN7/SEG23
RE1/AN6/SEG22
RE0/AN5/SEG21
RA5/AN4/C2OUT/SS/SEG5
RA4/C1OUT/T0CK1/SEG4
RC7/RX/DT/SDI/SDA/SEG8
RD4/SEG17
RD5/SEG18
RD6/SEG19
RD7/SEG20
VSS
VDD
VDD
RB0/INT/SEG0
RB1/SEG1
RB2/SEG2
RB3/SEG3
NC
RB4/COM0
RB5/COM1
RB6/ICSPCLK/ICDCK/SEG14
RB7/ICSPDAT/ICDDAT/SEG13
RE3/MCLR/VPP
RA0/AN0/C1-/SEG12
RA1/AN1/C2-/SEG7
RA2/AN2/C2+/VREF-/COM2
RA3/AN3/C1+/VREF+/SEG15
RC6/TX/CK/SCK/SCL/SEG9
RC5/T1CKI/CCP1/SEG10
RC4/T1G/SDO/SEG11
RD3/SEG16
RD2/CCP2
RD1
RD0/COM3
RC3/SEG6
RC2/VLCD3
RC1/VLCD2
RC0/VLDC1
2004 Microchip Technology Inc. Preliminary DS41250A-page 5
PIC16F91X
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Memory O rganization................................................................................................................................................................. 13
3.0 Clock Sources............................................................................................................................................................................ 31
4.0 I/O Ports.............. .................. ........... ................... ................... ................... ................................................................................. 43
5.0 Timer0 Module ................................................................. . ......................................................................................................... 81
6.0 Timer1 Module With Gate Control....................................................................................... ....................................................... 85
7.0 Timer2 Module ................................................................. . ......................................................................................................... 90
8.0 Comparator Module........................................... .... .... .. .... ....... .... .... .. .... ......... .. .... .... .. ................................................................. 93
9.0 Liquid Crystal Display (LCD) Driver Module..................................... .... ....... .... .. .... .... ....... .... .... .. .............................................. 101
10.0 Programmable Low-Voltage Detect (PLVD) Module.......................... .. ........... .. .... .... ......... .... .... .... .......................................... 125
11.0 Addressable Universal Synchronous Async hronous Receiv er Transmitter (USA RT ).............................................................. 127
12.0 Analog-t o-Digital Converter (A/D) Module................................................................................................................................ 143
13.0 Data EEPROM and Flash Program Memory Control....................... .... ........... .... ...... ......... ...... .... ........... ................................. 153
14.0 SS P Module Overview ............................................................................................................................................................. 159
15.0 Capture/Compare/PWM Modules ........ .... .. ......... .... .. .... ....... .... .... .. .... ......... .. .... .... .. ......... .. .... .... .............................................. 177
16.0 Specia l Features of the CPU............ ................... ...................................... ................... ........ .................................................... 185
17.0 Instruction Set Summary.......................................................................................................................................................... 205
18.0 Development Support............................................................................................................................................................... 215
19.0 Electrical Specifications............................................................................................................................................................ 221
20.0 DC and AC Characteristics Graphs and Tables............................. .. .... ......... .... .. .... ......... .... .... .. .... .......................................... 247
21.0 Packagin g In fo rmation................ ................... .................. ................... ................... ................................................................... 249
Appendix A: Data Sheet Revision History............................................ .... .... ......... .... .... .... ......... .... .. .................................................. 259
Appendix B: Migrating From Other PICmicro® Devices ......... ......... .... .... .... ........... .... .... .... ......... .... .... .............................................. 259
Appendix C: Conversion Considerations . .. .. .... .. ....... .... .. .... .. .... ....... .. .... .. .... .. ....... .... .. .... .. ....... .... .. .................................................... 260
Index .................................................................................................................................................................................................. 261
On-line Support.. .... .... ........... ...... .... ........... .... .... ........... .... .... ........... .... ...... .... ........... .... ..................................................................... 269
Systems Information and Upgrade Hot Line...................................................................................................................................... 269
Reader Response.............................................................................................................................................................................. 270
Product Identification System ............................................................................................................................................................ 271
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PIC16F91X
DS41250A-page 6 Preliminary 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Preliminary DS41250A-page 7
PIC16F91X
1.0 DEVICE OVERVIEW
This do cu me n t conta i ns dev ic e spec if i c in f orm at i on fo r
the PIC1 6F91X. Additional information m ay be found in
the “PICmicro® Mid-Range MCU Family Reference
Manual” (DS33023), downloaded from the Microchip
web si te. The Refere nce Ma nual s hould be consi dered
a complementary document to this data sheet and is
highly recommended reading for a better
underst a nding of the dev ice archi tecture and oper atio n
of the peripheral modul es.
The PIC16F91X devices are covered by this data
sheet. It is available in 28/40/44-pin packages.
Figure 1-1 shows a block diagram of the PIC16F913/
916 devic e and Table 1-1 shows the pinout descriptio n.
Figure 1-2 shows a block diagram of the PIC16F914/
917 devic e and Table 1-1 shows the pinout descriptio n.
PIC16F91X
DS41250A-page 8 Preliminary 2004 Microchip Technology Inc.
FIGURE 1-1: PIC16F91 3/916 BLOCK DIAGRAM
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
RB0/INT/SEG0
RB1/SEG1
RB2/SEG2
RB3/SEG3
RB4/COM0
RB5/COM1
RB6/ICSPCLK/ICDCK/SEG14
RB7/ICSPDAT/ICDDAT/SEG13
Flash
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction R eg
Progr am Coun ter
RAM
File
Registers
Direct Addr 7
RAM Addr
9
Addr MUX
Indirect
Addr
FSR Reg
Stat us Reg
MUX
ALU
W Reg
Instruction
Deco de an d
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
PORTA
8
8
8
3
8-Level Stack (13-bit) 256/3 52 byte s
4k/8k x 14
VSS
RA0/AN0/C1-/SEG12
RA1/AN1/C2-/SEG7
RA2/AN2/C2+/VREF-/COM2
RA3/AN3/C1+/VREF+/COM3/SEG1
5
RA4/C1OUT/T0CK1/SEG4
RA5/AN4/C2OUT/SS/SEG5
RA6/OSC2/CLKO/T1OSO
RA7/OSC1/CLKI/T1OSI
INT
Configuration
Internal
Oscillator
VDD
Block
Program Memory Read
PORTC RC0/VLCD1
RC1/VLCD2
RC2/VLCD3
RC3/SEG6
RC4/T1G/SDO/SEG11
RC5/T1CKI/CCP1/SEG10
RC6/TX/CK/SCK/SCL/SEG9
RC7/RX/DT/SDI/SDA/SEG8
PORTE
RE3/MCLR/VPP
(PRM) PORTB
PLVD LCD
Data EEPROM
256 bytes
Comparators Addressable
USART
CCP1 SSP
Timer0 Timer1 Timer2 10-bit A/D
BOR
2004 Microchip Technology Inc. Preliminary DS41250A-page 9
PIC16F91X
FIGURE 1-2: PIC16F91 4/917 BLOCK DIAGRAM
PORTD RD0/COM3
RD1
RD2/CCP2
RD3/SEG16
RD4/SEG17
RD5/SEG18
RD6/SEG19
RD7/SEG20
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
PORTB RB0/INT/SEG0
RB1/SEG1
RB2/SEG2
RB3/SEG3
RB4/COM0
RB5/COM1
RB6/ICSPCLK/ICDCK/SEG14
RB7/ICSPDAT/ICDDAT/SEG1
3
Flash
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction R eg
Progr am Coun ter
RAM
File
Registers
Direct Addr 7
RAM Addr
9
Addr MUX
Indirect
Addr
FSR Reg
Stat us Reg
MUX
ALU
W Reg
Instruction
Deco de an d
Control
Timing
Generation
OSC1/CLKI
OSC2/CLKO
PORTA
8
8
8
3
8-Level Stack (13-bit) 256/3 52 byte s
4k/8k x 14
VSS
RA0/AN0/C1-/SEG12
RA1/AN1/C2-/SEG7
RA2/AN2/C2+/VREF-/COM2
RA3/AN3/C1+/VREF+/SEG15
RA4/C1OUT/T0CK1/SEG4
RA5/AN4/C2OUT/SS/SEG5
RA6/OSC2/CLKO/T1OSO
RA7/OSC1/CLKI/T1OSI
INT
Configuration
Internal
Oscillator
VDD
Block
Program Memory Read
Data EEPROM
256 bytes
PORTC RC0/VLCD1
RC1/VLCD2
RC2/VLCD3
RC3/SEG6
RC4/T1G/SDO/SEG11
RC5/T1CKI/CCP1/SEG10
RC6/TX/CK/SCK/SCL/SEG9
RC7/RX/DT/SDI/SDA/SEG8
PORTE
(PRM)
RE0/AN5/SEG21
RE1/AN6/SEG22
RE2/AN7/SEG23
RE3/MCLR/VPP
PLVD LCD
Comparators Addressable
USART
CCP2 SSP
Timer0 Timer1 Timer2 10-bit A/D
BOR
CCP1
PIC16F91X
DS41250A-page 10 Preliminary 2004 Microchip Technology Inc.
TABLE 1-1: PIC16F91X PINOUT DESCRIPTIONS
Name Function Input
Type Output
Type Description
RA0/AN0/C1-/SEG12 RA0 TTL CMOS General purpose I/O.
AN0 AN — Analog inp ut C hannel 0/Co m parator 1 input – negative.
C1- — AN Comparator 1 negative inp ut .
SEG12 — A N LCD an alog output.
RA1/AN1/C2-/SEG7 RA1 TTL CMOS General purpose I/O.
AN1 AN — Analog inp ut C hannel 1/Co m parator 2 input – negative.
C2- — AN Comparator 2 negative inp ut .
SEG7 — AN LCD analog output .
RA2/AN2/C2+/VREF-/COM2 RA2 TTL CMOS General purpose I/O.
AN2 AN — Analog input C hannel 2/Co m parator 2 in put – positive.
C2+ — AN Comparator 2 positive input .
VREF- AN — Ex tern al Voltage Refer ence – nega tive.
COM2 — AN LCD analog output.
RA3/AN3/C1+/VREF+/COM3(1)/
SEG15 RA3 TTL CMOS General purpose I/O.
AN3 AN — Analog input C hannel 3/Co m parator 1 in put – positive.
C1+ — AN Comparator 1 positive input .
VREF+ AN — External Voltage Refer ence – posit ive.
COM3(1) — AN LCD analog outpu t.
SEG15 — AN LCD analog output.
RA4/C1OUT/T0CK1/SEG4 RA4 TTL CMOS General purpose I/O.
C1OUT — CMOS Comparator 1 out put.
T0CKI ST — Timer0 clock input.
SEG4 — AN LCD analog output .
RA5/AN4/C2OUT/SS/SEG5 RA5 TTL CMOS General purpose I/O.
AN4 AN — Analog input Channel 4.
C2OUT — CMOS Comparator 2 out put.
SS TTL — Slave select input.
SEG5 — AN LCD analog output .
RA6/OSC2/CLKO/T1OSO RA6 TTL CMOS General purpose I/O.
OSC2 — XTAL Crystal/Resonator.
CLKO — CMOS TOSC/4 refer ence clock.
T1OSO — XTAL Timer1 oscillator output.
RA7/OSC1/CLKI/T1OSI RA7 TTL CMOS General purpose I/O.
OSC1 XTAL — Crystal/Resonator.
CLKI ST — Clock input.
T1OSI XTAL — Timer1 oscillato r inpu t.
RB0/INT/SEG0 RB0 TTL CMOS General purpose I/O. Individually enabled pull-up.
INT ST — External interrupt pi n.
SEG0 — AN LCD analog output .
RB1/SEG1 RB1 TTL CMOS General purpose I/O. Ind ividually enabled pull-up.
SEG1 — AN LCD analog output .
Legend: AN = Analog input or o utput CM OS = CMOS co m patible inp ut or ou t put D = Direct
TTL = TTL compatible input ST = Sc hmitt Tr igger input with CMOS levels
HV = High Voltage XTAL = Crystal
Note 1: COM3 is available on R A3 f or the PIC16F913 /9 16 and on RD 0 for the P IC1 6F914/9 17 .
2: Pins available on PIC16F914/917 only.
2004 Microchip Technology Inc. Preliminary DS41250A-page 11
PIC16F91X
RB2/SEG2 RB2 TTL CMOS General purpose I/O. Ind ividually enabled pull-up.
SEG2 — AN LCD analog output .
RB3/SEG3 RB3 TTL CMOS General purpose I/O. Ind ividually enabled pull-up.
SEG3 — AN LCD analog output .
RB4/COM0 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individuall y enabled pull- up.
COM0 — AN LCD analog output.
RB5/COM1 RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individuall y enabled pull- up.
COM1 — AN LCD analog output.
RB6/ICSPCLK/ICDCK/SEG14 RB6 TTL CMOS Gene ral purp o se I/O. Individually controlled interrupt-on-
change. Individuall y enabled pull- up.
ICSPC LK ST — ICSP ™ cl oc k.
ICDCK ST — I CD cl ock I/O.
SEG14 — AN LCD analog output.
RB7/ICSPDAT/ICDDA T/SEG13 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-
change. Individuall y enabled pull- up.
ICSPDAT ST CMOS ICSP Data I/O.
ICDDAT ST CMOS ICD Data I/O.
SEG13 — AN LCD analog output.
RC0/VLCD1 RC0 TTL CMOS General purpose I/O.
VLC D 1 AN — LCD analog input.
RC1/VLCD2 RC1 ST CMOS General purpose I/O.
VLC D 2 AN — LCD analog input.
RC2/VLCD3 RC2 ST CMOS General purpose I/O.
VLC D 3 AN — LCD analog input.
RC3/SEG6 RC3 ST CMOS General purpose I/O.
SEG6 — AN LCD anal og out put.
RC4/T1G/SDO/SEG11 RC4 ST CMOS General purpose I/O.
T1G ST — Timer1 gate input.
SDO — CMOS Serial data output.
SEG11 — AN LCD anal og out put.
RC5/T1CKI/CCP1/SEG10 RC5 ST CMOS General purpose I/O.
T1CKI ST — Timer1 clock input.
CCP1 ST CMOS Capture 1 input/Compare 1 output / PW M 1 out put.
SEG10 — AN LCD analog output.
RC6/TX/CK/SCK/SCL/SEG9 RC6 ST CMOS General purpose I/O.
TX — CMOS U SART asynchro nous seria l tra nsm it .
CK ST C M O S USART synchronous se ri al cl ock.
SCK ST C M O S SPI™ clock.
SCL ST CMOS I2C ™ cl ock.
SEG9 — AN LCD anal og out put.
TABLE 1-1: PIC16F91X PINOUT DESCRIPTIONS (CONTINUED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output D = Direct
TTL = TTL compatible input ST = Sc hmitt Tr igger input with CMOS levels
HV = High Voltage XTAL = Crystal
Note 1: COM3 is available o n R A3 f or the PIC16F913 /9 16 and on RD 0 for the P IC1 6F914/917.
2: Pins available on PIC16F914/917 only.
PIC16F91X
DS41250A-page 12 Preliminary 2004 Microchip Technology Inc.
RC7/RX/DT/SDI/SDA/SEG8 RC7 ST CMOS General purpose I/O.
RX ST — USA RT asy nc hro nous seria l rece iv e.
DT ST CM O S USART synchronous se ri al data.
SDI ST CMOS SPI™ data input.
SDA ST CMOS I2C™ data.
SEG8 — AN LCD anal og out put.
RD0/COM3(1, 2) RD0 ST CMOS General purpose I/O.
COM3 — AN LCD analog output.
RD1(2) RD1 ST CMOS General purpose I/O.
RD2/CCP2(2) RD2 ST CMOS Ge neral purpose I/O.
CCP2 ST CMOS Capture 2 input/Compare 2 output / PW M 2 out put.
RD3/SEG16(2) RD3 ST CMOS General purpose I/O.
SEG16 — AN LCD analog output.
RD4/SEG17(2) RD4 ST CMOS General purpose I/O.
SEG17 — AN LCD analog output.
RD5/SEG18(2) RD5 ST CMOS General purpose I/O.
SEG18 — AN LCD analog output.
RD6/SEG19(2) RD6 ST CMOS General purpose I/O.
SEG19 — AN LCD analog output.
RD7/SEG20(2) RD7 ST CMOS General purpose I/O.
SEG20 — AN LCD analog output.
RE0/AN5/SEG21(2) RE0 ST CMOS Ge neral purpose I/O.
AN5 AN — Analog input Channel 5.
SEG21 — AN LCD analog output.
RE1/AN6/SEG22(2) RE1 ST CMOS Ge neral purpose I/O.
AN6 AN — Analog input Channel 6.
SEG22 — AN LCD analog output.
RE2/AN7/SEG23(2) RE2 ST CMOS Ge neral purpose I/O.
AN7 AN — Analog input Channel 7.
SEG23 — AN LCD analog output.
RE3/MCLR/VPP RE3 ST — Digital input only.
MCLR ST — Mas t er Clea r w/ int er nal pu ll- up.
VPP HV — Programming voltage.
VDD VDD D — Power supply for micro con tro ller .
VSS VSS D — Gr ound reference for micr ocontroll er.
TABLE 1-1: PIC16F91X PINOUT DESCRIPTIONS (CONTINUED)
Name Function Input
Type Output
Type Description
Legend: AN = Analog input or o utput CM OS = CMOS co m patible inp ut or ou t put D = Direct
TTL = TTL compatible input ST = Sc hmitt Tr igger input with CMOS levels
HV = High Voltage XTAL = Crystal
Note 1: COM3 is available on R A3 f or the PIC16F913 /9 16 and on RD 0 for the P IC1 6F914/9 17 .
2: Pins available on PIC16F914/917 only.
2004 Microchip Technology Inc. Preliminary DS41250A-page 13
PIC16F91X
2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
The PIC16F91X has a 13-bit program counter capable
of addressing a 4k x 14 program memory sp ace for the
PIC16F913/914 (0000h-0FFFh) and an 8k x 14 program
memory space for the PIC16F916/917 (0000h-1FFFh).
Accessing a location above the memory boundaries for
the PIC16F913 and PIC16F914 will cause a wrap
around within the first 4k x 14 space. The Reset vector
is at 0000h and the interrupt v ector is at 0004h .
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F913/914
FIGURE 2-2: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F916/917
pc<12:0>
13
0000h
0004h
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
CALL, RETURN
RETFIE, RETLW
Stack Level 2
0005h
On-chip
1FFFh
Program
Memory
Page 0
Page 1
07FFh
0800h
0FFFh
1000h
pc<12:0>
13
0000h
0004h
Stack Lev el 1
Stack Level 8
Reset Vector
Interru pt Vector
CALL, RETURN
RETFIE, RETLW
Stack Level 2
0005h
On-chip
1FFFh
Program
Memory
Page 0
Page 1
Page 2
Page 3
07FFh
0800h
0FFFh
1000h
17FFh
1800h
PIC16F91X
DS41250A-page 14 Preliminary 2004 Microchip Technology Inc.
2.2 Data Memory Organization
The data memory is partitioned into multiple banks,
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP0
and RP1 are bank select bits.
=00:→ Bank 0
=01:→ Bank 1
=10:→ Bank 2
=11:→ Bank 3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function
Registers are the General Purpose Registers,
implemented as static RAM. All implemented banks
contain Special Function Registers. Some frequently
used Special Function Registers from one bank are
mirrored in another bank for code reduction and
quicker access.
2.2. 1 GENERAL PURPOSE REGISTER
FILE
The register file is organized as 256 x 8 in the
PIC16F913/914 and 352 x 8 in the PIC16F916/917.
Each register is accessed either directly or indirectly
through the File Select Register (FSR) (see Section 2.5
“Indirect Addressing, INDF and FSR Registers”).
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Tables 2-1,
2-2, 2-3 and 2-4). These registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
assoc iated with th e “core” are described in this sec tion.
Those related to the operation of the peripheral
features are desc ribed in the se ction of that peripheral
feature.
RP0 RP1 (Status<6:5>)
2004 Microchip Technology Inc. Preliminary DS41250A-page 15
PIC16F91X
FIGURE 2-3: PIC16F913/916 SPECIAL FUNCTION REGISTERS
File File File File
Address Address Address Address
Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h WDTCON 105h 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h LCDCON 107h 187h
08h 88h LCDPS 108h 188h
PORTE 09h TRISE 89h LVDCON 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDATL 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADRL 10Dh EECON2(1) 18Dh
TMR1L 0Eh PCON 8Eh EEDATH 10Eh 18Eh
TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh 18Fh
T1CON 10h OSCTUNE 90h LCDDATA0 110h
General
Purpose
Register(2)
96 Bytes
190h
TMR2 11h ANSEL 91h LCDDATA1 111h
T2CON 12h PR2 92h 112h
SSPBUF 13h SSPADD 93h LCDDATA3 113h
SSPCON 14h SSPSTAT 94h LCDDATA4 114h
CCPR1L 15h WPUB 95h 115h
CCPR1H 16h IOCB 96h LCDDATA6 116h
CCP1CON 17h CMCON1 97h LCDDATA7 117h
RCSTA 18h TXSTA 98h 118h
TXREG 19h SPBRG 99h LCDDATA9 119h
RCREG 1Ah 9Ah LCDDATA10 11Ah
1Bh 9Bh 11Bh
1Ch CMCON0 9Ch LCDSE0 11Ch
1Dh VRCON 9Dh LCDSE1 11Dh
ADRESH 1Eh ADRESL 9Eh 11Eh
ADCON0 1Fh ADCON1 9Fh 11Fh
General
Purpose
Register
96 Bytes
20h
General
Purpose
Register
80 Bytes
A0h
General
Purpose
Register
80 Bytes
120h
EFh 16Fh 1EFh
accesses
70h-7Fh F0h accesses
70h-7Fh 170h accesses
70h-7Fh 1F0h
7Fh FFh 17Fh 1FFh
Bank 0 Bank1 Bank2 Bank3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
2: On the PIC16F913, unimplemented data memory locations, read as ‘0’.
PIC16F91X
DS41250A-page 16 Preliminary 2004 Microchip Technology Inc.
FIGURE 2-4: PIC16F914/917 SPECIAL FUNCTION REGISTERS
File File File File
Address Address Address Address
Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h WDTCON 105h 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h LCDCON 107h 187h
PORTD 08h TRISD 88h LCDPS 108h 188h
PORTE 09h TRISE 89h LVDCON 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDATL 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADRL 10Dh EECON2(1) 18Dh
TMR1L 0Eh PCON 8Eh EEDATH 10Eh 18Eh
TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh 18Fh
T1CON 10h OSCTUNE 90h LCDDATA0 110h
General
Purpose
Register(2)
96 Bytes
190h
TMR2 11h ANSEL 91h LCDDATA1 111h
T2CON 12h PR2 92h LCDDATA2 112h
SSPBUF 13h SSPADD 93h LCDDATA3 113h
SSPCON 14h SSPSTAT 94h LCDDATA4 114h
CCPR2L 15h WPUB 95h LCDDATA5 115h
CCPR2H 16h IOCB 96h LCDDATA6 116h
CCP2CON 17h CMCON1 97h LCDDATA7 117h
RCSTA 18h TXSTA 98h LCDDATA8 118h
TXREG 19h SPBRG 99h LCDDATA9 119h
RCREG 1Ah 9Ah LCDDATA10 11Ah
CCPR2L 1Bh 9Bh LCDDATA11 11Bh
CCPR2H 1Ch CMCON0 9Ch LCDSE0 11Ch
CCPR2CON 1Dh VRCON 9Dh LCDSE1 11Dh
ADRESH 1Eh ADRESL 9Eh LCDSE2 11Eh
ADCON0 1Fh ADCON1 9Fh 11Fh
General
Purpose
Register
96 Bytes
20h
General
Purpose
Register
80 Bytes
A0h
General
Purpose
Register
80 Bytes
120h
EFh 16Fh 1EFh
accesses
70h-7Fh F0h accesses
70h-7Fh 170h accesses
70h-7Fh 1F0h
7Fh FFh 17Fh 1FFh
Bank 0 Bank1 Bank2 Bank3
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
2: On the PIC16F914, unimplemented data memory locations, read as ‘0’.
2004 Microchip Technology Inc. Preliminary DS41250A-page 17
PIC16F91X
TABLE 2-1: PIC16F91X SPECIAL REGISTERS SUMMARY BANK 0
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR/BOR
Reset
Value on
all other
Resets(1)
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
01h TMR0 Timer0 Module’s registe r xxxx xxxx uuuu uuuu
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
03h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
04h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx uuuu uuuu
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
08h PORTD(2) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
09h PORTE — — — —RE3RE2
(2) RE1(2) RE0(2) ---- xxxx ---- uuuu
0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 ---0 0000
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 OSFIF C2IF C1IF LCDIF —LVDIF— CCP2IF 0000 -0-0 0000 -0-0
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu
10h T1CON T1GINV T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
11h TMR2 Timer2 Module Regi ster 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON —— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG USART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
1Bh(2) CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
1Ch(2) CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
1Dh(2) CCP2CON —— CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
1Fh ADCON0 ADFM VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: PIC16F914/917 only.
PIC16F91X
DS41250A-page 18 Preliminary 2004 Microchip Technology Inc.
TABLE 2-2: PIC16F91X SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR/BOR
Reset
Value on
all other
Resets(1)
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical
register) xxxx xxxx xxxx xxxx
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
83h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
84h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
88h TRISD(2) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111
89h TRISE ———— TRISE3(5) TRISE2
(2)
TRISE1
(2)
TRISE0
(2)
---- 1111 ---- 1111
8Ah PCLATH ——— Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 OSFIE C2IE C1IE LCDIE —LVDIE— CCP2IE 0000 -0-0 0000 -0-0
8Eh PCON ———SBOREN——PORBOR ---1 --qq ---u --uu
8Fh OSCCON — IRCF2 IRCF1 IRCF0 OSTS(4) HTS LTS SCS -110 q000 -110 x000
90h OSCTUNE ——— TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu
91h ANSEL ANS7(3) ANS6(3) ANS5(3) ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
92h PR 2 Timer2 Pe riod Reg is ter 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I2 C mode) Address Register 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 0000 0000
95h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111
96h IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- 0000 ----
97h CMCON1 — — — — — — T1GSS C2SYNC ---- --10 ---- --10
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG SPBRG7 SPBRG6 SPBRG5 SPBRG4 SPBRG3 SPBRG2 SPBRG1 SPBRG0 0000 0000 0000 0000
9Ah —Unimplemented — —
9Bh —Unimplemented — —
9Ch CMCON0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000
9Dh VRCON VREN —VRR— VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
9Fh ADCON1 — ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 ---
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: PIC16F 91 4/917 only.
3: PIC16F 914/917 only, f orced ‘0’ on PIC16F 91 3/9 16.
4: The value of the OSTS bit is dependent on the value of the Configuration Word (CONFIG) of the device. See Section 3.0 “Clock
Sources”.
5: Bit is read-only; TRISE = 1 always.
2004 Microchip Technology Inc. Preliminary DS41250A-page 19
PIC16F91X
TABLE 2-3: PIC16F91X SPECIAL REGISTERS SUMMARY BANK 2
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR/BOR
Reset
Value on
all other
Resets(1)
Bank 2
100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
101h TMR0 Timer0 Module’s register xxxx xxxx uuuu uuuu
102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
103h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
104h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
105h WDTCON — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000
106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
107h LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011
108h LCDPS WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 0000 0000 0000 0000
109h LVDCON —— IRVST LVDEN —LVDL2LVDL1LVDL0--00 -100 --00 -100
10Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
10Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
10Ch EEDATL EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDATL1 EEDATL0 0000 0000 0000 0000
10Dh EEADRL EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0 0000 0000 0000 0000
10Eh EEDATH — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 --00 0000
10Fh EEADRH — — — EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---0 0000 ---0 0000
110h LCDDATA0 SEG7
COM0 SEG6
COM0 SEG5
COM0 SEG4
COM0 SEG3
COM0 SEG2
COM0 SEG1
COM0 SEG0
COM0 xxxx xxxx uuuu uuuu
111h LCDDATA1 SEG15
COM0 SEG14
COM0 SEG13
COM0 SEG12
COM0 SEG11
COM0 SEG10
COM0 SEG9
COM0 SEG8
COM0 xxxx xxxx uuuu uuuu
112h LCDDATA2(2) SEG23
COM0 SEG22
COM0 SEG21
COM0 SEG20
COM0 SEG19
COM0 SEG18
COM0 SEG17
COM0 SEG16
COM0 xxxx xxxx uuuu uuuu
113h LCDDATA3 SEG7
COM1 SEG6
COM1 SEG5
COM1 SEG4
COM1 SEG3
COM1 SEG2
COM1 SEG1
COM1 SEG0
COM1 xxxx xxxx uuuu uuuu
114h LCDDATA4 SEG15
COM1 SEG14
COM1 SEG13
COM1 SEG12
COM1 SEG11
COM1 SEG10
COM1 SEG9
COM1 SEG8
COM1 xxxx xxxx uuuu uuuu
115h LCDDATA5(2) SEG23
COM1 SEG22
COM1 SEG21
COM1 SEG20
COM1 SEG19
COM1 SEG18
COM1 SEG17
COM1 SEG16
COM1 xxxx xxxx uuuu uuuu
116h LCDDATA6 SEG7
COM2 SEG6
COM2 SEG5
COM2 SEG4
COM2 SEG3
COM2 SEG2
COM2 SEG1
COM2 SEG0
COM2 xxxx xxxx uuuu uuuu
117h LCDDATA7 SEG15
COM2 SEG14
COM2 SEG13
COM2 SEG12
COM2 SEG11
COM2 SEG10
COM2 SEG9
COM2 SEG8
COM2 xxxx xxxx uuuu uuuu
118h LCDDATA8(2) SEG23
COM2 SEG22
COM2 SEG21
COM2 SEG20
COM2 SEG19
COM2 SEG18
COM2 SEG17
COM2 SEG16
COM2 xxxx xxxx uuuu uuuu
119h LCDDATA9 SEG7
COM3 SEG6
COM3 SEG5
COM3 SEG4
COM3 SEG3
COM3 SEG2
COM3 SEG1
COM3 SEG0
COM3 xxxx xxxx uuuu uuuu
11Ah LCDDATA10 SEG15
COM3 SEG14
COM3 SEG13
COM3 SEG12
COM3 SEG11
COM3 SEG10
COM3 SEG9
COM3 SEG8
COM3 xxxx xxxx uuuu uuuu
11Bh LCDDATA11(2) SEG23
COM3 SEG22
COM3 SEG21
COM3 SEG20
COM3 SEG19
COM3 SEG18
COM3 SEG17
COM3 SEG16
COM3 xxxx xxxx uuuu uuuu
11Ch LCDSE0(3) SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 uuuu uuuu
11Dh LCDSE1(3) SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 uuuu uuuu
11Eh LCDSE2(2,3) SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 0000 0000 uuuu uuuu
11Fh —Unimplemented — —
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: PIC16F914/917 only.
3: This register is only initialized by a POR or BOR reset and is unchanged by other resets.
PIC16F91X
DS41250A-page 20 Preliminary 2004 Microchip Technology Inc.
TABLE 2-4: PIC16F91X SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR/BOR
Reset
Value on
all other
Resets(1)
Bank 3
180h INDF Addressing this location uses contents of FSR to address data memory (not a physical
register) xxxx xxxx xxxx xxxx
181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
182h PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
183h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
184h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
185h —Unimplemented — —
186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
187h —Unimplemented — —
188h —Unimplemented — —
189h —Unimplemented — —
18Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
18Ch EECON1 EEPGD — — — WRERR WREN WR RD ---- x000 ---- q000
18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ----
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2004 Microchip Technology Inc. Preliminary DS41250A-page 21
PIC16F91X
2.2.2.1 Status Register
The Status register, shown in Register 2-1, contains:
• the ari thmetic status of the ALU
• the Reset status
• the bank select bits for data memory (SRAM)
The Status register can be the destination for any
instruction, like any other register. If the Status register
is the destination for an instruction that affects the Z,
DC or C bits, then the write to these three bits is
disabl ed. These bit s are set or clea red according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
Status register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper three
bits and set th e Z bit. Thi s leaves the Statu s regis ter as
‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
S tatus r egister , because these in structions do no t affect
any Status bits. For other instructions not affecting any
Status bits (see Section 17.0 “Instruction Set
Summary”).
REGISTER 2-1: STATUS – STATUS REGISTER (ADDRESS: 03h, 83h, 103h, OR 183h)
Note 1: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD ZDCC
bit 7 bit 0
bit 7 IRP: Registe r Bank Select bit (use d for indirect addressing )
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instr u ction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruct i on
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instru cti ons )(1)
1 = A carry-out from the 4th low-order bit of th e result occurred
0 = No carry-out from the 4th low- order bit of the result
bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with
either the high or low-order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F91X
DS41250A-page 22 Preliminary 2004 Microchip Technology Inc.
2.2.2.2 Option Register
The Option register is a readable and writable register,
which contains various control bits to configure:
• TMR0/WDT prescaler
• External RB0/ INT interrupt
•TMR0
• Weak pull-ups on PORTB
REGISTER 2-2: OPTION_REG – OPTION REGISTER (ADDRESS: 81h OR 181h)
Note: To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT by
setting PSA bit to ‘1’ (OPTION_REG<3>).
See Section 5.4 “Prescaler”.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT/SEG0 pin
0 = Interrupt on falling edge of RB0/INT/SEG0 pin
bit 5 T0CS: TMR0 Clock Sourc e Sele ct bit
1 = Transition on RA4/C1OUT/T0CK1/SEG4 pin
0 = Internal instruction cycle clock (CLKO)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/C1OUT/T0CK1/SEG4 pin
0 = Increment on low-to-high transition on RA4/C1OUT/T0CK1/SEG4 pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Presca ler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
2004 Microchip Technology Inc. Preliminary DS41250A-page 23
PIC16F91X
2.2.2.3 INTCON Register
The INTCON register is a readable and writable
register, which cont ains the various en able and fl ag bits
for TMR0 register overflow, PORTB change and
external RB0/INT/SEG0 pin interrupts.
REGISTER 2-3: INTCON – INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh, or
18Bh)
Note: Interru pt flag bit s are set w hen an interr upt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all inte rrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT/SEG0 External Interrupt Enable bit
1 = Enables the RB0/INT/SEG0 external interrupt
0 = Disables the RB0/INT/SEF0 external interrupt
bit 3 RBIE: PORTB Change Interrupt Enable bit(1)
1 = Enables the PORTB change interrupt
0 = Disables the PORTB change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit(2)
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 reg i ster did not overflow
bit 1 INTF: RB0/INT/SEG0 External Interrupt Flag bit
1 = The RB0/INT/SEG0 external interrupt occurred (must be cleared in software)
0 = The RB0/INT/SEG0 external interrupt did not occur
bit 0 RBIF: PORTB Change Interrupt Flag bit
1 = When at least one of the PORTB <5:0> pins changed state (must be cleared in software)
0 = None of the PORTB <7:4> pins ha ve changed state
Note 1: IOCB register must also be enabled.
2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should
be initialized before clearing T0IF bit.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F91X
DS41250A-page 24 Preliminary 2004 Microchip Technology Inc.
2.2.2.4 PIE 1 Register
The PIE1 regis te r con t ai ns th e in terrupt enable bit s, as
shown in Register 2-1.
REGISTER 2-4: PIE1 – PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
bit 7 EEIE: EE Write Complete Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 5 RCIE: USART Rece iv e Interru pt Enab le bit
1 = Enabled
0 = Disabled
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3 SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Preliminary DS41250A-page 25
PIC16F91X
2.2.2.5 PI E2 Regi st er
The PIE2 regis te r con t ai ns th e in terrupt enable bit s, as
shown in Register 2-5.
REGISTER 2-5: PIE2 – PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS: 8Dh)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0
OSFIE C2IE C1IE LCDIE —LVDIE— CCP2IE
bit 7 bit 0
bit 7 OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 =Disabled
bit 6 C2IE: Comparator 2 Interrupt Enable bit
1 = Enables Comparator 2 interrupt
0 = Disab les Comparator 2 interrupt
bit 5 C1IE: Comparator 1 Interrupt Enable bit
1 = Enables Comparator 1 interrupt
0 = Disab les Comparator 1 interrupt
bit 4 LCDIE: LCD Module Interrupt Enable bit
1 = LCD interrupt is enabled
0 = LCD interrupt is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2 LVDIE: Low Voltage Detect Interrupt Enable bit
1 = Enables LVD Interrupt
0 = Disables LVD Interrupt
bit 1 Unimplemented: Read as ‘0’
bit 0 CCP2IE: CCP2 Interrupt Enable bit (only available in 16F914/917)
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F91X
DS41250A-page 26 Preliminary 2004 Microchip Technology Inc.
2.2.2.6 PIR1 Register
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-6.
REGISTER 2-6: PIR1 – PERIPHERAL INTERRUPT REQUEST REGISTER 1 (ADDRESS: 0Ch)
Note: Interrupt flag bits are set w hen an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are cle ar prior to ena bling
an interrupt.
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
bit 7 EEIF: EE Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation has no t completed or has not started
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = The A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5 RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full (cleared by reading RCREG)
0 = The USART receive buffer is not full
bit 4 TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty (cleared by writing to TXREG)
0 = The USART transmit buffer is full
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The Transmission/Reception is complete (must be cleared in software)
0 = Waiting to Transmit/Receive
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode
Unused in this mode
bit 1 TMR2IF: TM R2 to PR2 Interrupt Flag bit
1 = A TMR2 to PR2 ma tch occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = The TMR1 re gister overflowed (must be cl eared in software)
0 = The TMR1 register did not overflow
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Preliminary DS41250A-page 27
PIC16F91X
2.2.2.7 PIR2 Register
The PIR2 register contains the interrupt flag bits, as
shown in Register 2-7.
REGISTER 2-7: PIR2 – PERIPHERAL INTERRUPT REQUEST REGISTER 2 (ADDRESS: 0Dh)
Note: Interrupt flag bits are set w hen an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are cle ar prior to ena bling
an interrupt.
R/W-0 R/W-0 R-0 R-0 U-0 R/W-0 U-0 R/W-0
OSFIF C2IF C1IF LCDIF —LVDIF— CCP2IF
bit 7 bit 0
bit 7 OSFIF: Oscillator Fail Interrupt Flag bit
1 = System oscilla tor failed, c lock input ha s changed to INT OSC (must be c leared in s oftware)
0 = System clock operating
bit 6 C2IF: Comparator 2 Interrupt Flag bit
1 = Comparator output (C2OUT bit) has changed (must be cleared in software)
0 = Comparator output (C2OUT bit) has not changed
bit 5 C1IF: Comparator 1 Interrupt Flag bit
1 = Comparator output (C1OUT bit) has changed (must be cleared in software)
0 = Comparator output (C1OUT bit) has not changed
bit 4 LCDIF: LCD Module Interrupt bit
1 = LCD has generated an interrupt
0 = LCD has not generated an inter rupt
bit 3 Unimplemented: Read as ‘0’
bit 2 LVDIF: Low Voltage Detect Interrupt Flag bit
1 = LVD has generated an interrupt
0 = LVD has not generated an interrupt
bit 1 Unimplemented: Read as ‘0’
bit 0 CCP2IF: CCP2 Interrupt Flag bit (only available in 16F914/917)
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode
Unused in this mode
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F91X
DS41250A-page 28 Preliminary 2004 Microchip Technology Inc.
2.2.2.8 PCON Regi st er
The Power Control (PCON) register (See Table 17-2)
cont ains flag bits to dif fere ntia te between a:
• Power-on Rese t (POR)
• Brown-out Reset (BO R)
• Watchdog Timer Reset (WDT)
• External MCLR Reset
The PCON register also controls the software en able of
the BOR.
The PCON register bits are shown in Register 2-8.
REGISTER 2-8: PCON – POWER CONTROL REGISTER (ADDRESS: 8Eh)
U-0 U-0 U-0 R/W-1 U-0 U-0 R/W-0 R/W-x
— — — SBOREN ——PORBOR
bit 7 bit 0
bit 7-5 Unimplemented: Read as ‘0’
bit 4 SBOREN: Software BOR Enable bit(1)
1 = BOR enabled
0 = BOR disabled
bit 3-2 Unimplemented: Read as ‘0’
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Powe r-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occu rs)
Note 1: BOREN<1:0> = 01 in the Configur ation Word register for this bit to control the BOR.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Preliminary DS41250A-page 29
PIC16F91X
2.3 PCL and PCLATH
The Program Counter (PC) is 13 bits wide. The low byte
comes from th e PCL register, which is a readabl e and
writable register. The high byte (PC<12:8>) is not
directly rea dable or wr itable and comes from PCLATH.
On any Reset, t he PC is cleared. Figur e 2-5 shows the
two situations for the loading of the PC. The upper
example in Figur e 2-5 show s how the PC is loaded on
a write to PCL (PCLATH<4:0> → PCH). The lower
example in Figure 2-5 shows how the PC is loaded dur-
ing a CALL or GOTO instruction (PCLA TH<4:3> → PCH).
FIGURE 2-5: LOADING OF PC IN
DIFFERENT SITUATIONS
2.3.1 COMPUTED GOTO
A comput ed GOTO is a ccom pli shed by adding a n offset
to the program counter (ADDWF PCL). When perform-
ing a table read using a computed GOTO method, care
should be ex ercise d if th e t able loca tion c rosse s a PCL
memory boundary (each 256-byte block). Refer to the
Application Note AN556, “Implementing a Table Read”
(DS00556).
2.3.2 STACK
The PIC16F91X family has an 8-level x 13-bit wide
hardware stack (see Figures 2-1and 2-2). The stack
space is not part of either program or data space and
the S t ack P ointer i s not readabl e or writ able . The PC is
PUSHed onto the stack when a CALL instruction is
executed or an interrupt causes a branch. The stack is
POPed in th e event of a RETURN, RETLW or a RETFIE
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The st ack operates as a circular buf fer . This means that
after the st ack has been PUSHed ei ght times, th e ninth
push ov erwrit es the v alue tha t was stor ed from th e first
push. The tenth push overw ri t es the second pus h (an d
so on).
2.4 Program Memory Paging
All PIC16F91X devices are capable of addressing a
continuous 8K word block of program memory. The
CALL and GOTO instructions provide only 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALL or GOTO instruction,
the upper 2 bits of the address are provided by
PCLATH<4:3>. When doing a CALL or GOTO instruc-
tion, the us er must ensure that the p a ge s elect bits are
programmed so that the desired program memory
page is addressed. If a return from a CALL instructi on
(or interrupt) is executed, the entire 13-bit PC is popped
off the stack. Therefore, manipulation of the
PCLATH<4:3> bits is not required for the RETURN
instructions (which POPs the address from the stack).
Example 2-1 shows the calling of a subroutine in
page 1 of the program memory. This e xample assu mes
that PCLATH is saved and restored by the Interrupt
Service Routi ne (if interrupts are used).
EXAMPLE 2-1: CALL OF A SUBROUTINE
IN PAGE 1 FROM PAGE 0
PC
12 8 7 0
5PCLATH<4:0>
PCLATH
Instruction wit
h
ALU Result
GOTO, CALL
OPCODE<10:0>
8
PC
12 11 10 0
11
PCLATH<4:3>
PCH PCL
87
2
PCLATH
PCH PCL
PCL a
s
Destinatio
n
Note 1: There are no Status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interr upt add ress.
Note: The contents of the PCLATH register are
unchanged after a RETURN or RETFIE
instruction is executed. The user must
rewrite the contents of the PCLATH regis-
ter for any subsequent subroutine calls or
GOTO instructions.
ORG 0x500
BCF PCLATH,4
BSF PCLATH,3 ;Select page 1
;(800h-FFFh)
CALL SUB1_P1 ;Call subroutine in
: ;page 1 (800h-FFFh)
:
ORG 0x900 ;page 1 (800h-FFFh)
SUB1_P1 : ;called subroutine
;page 1 (800h-FFFh)
:
RETURN ;return to
;Call subroutine
;in page 0
;(000h-7FFh)
PIC16F91X
DS41250A-page 30 Preliminary 2004 Microchip Technology Inc.
2.5 Indirect Addressing, INDF and
FSR Registers
The INDF register is no t a physica l register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR register and the IRP bit
(Status<7>), as shown in Figure 2-6.
A simple pro gram to clear R AM locatio n 20h-2Fh usin g
indirect addressing is shown in Example 2-2.
EXAMPLE 2-2: INDIRECT ADDRESSING
FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC16F91X
MOVLW 0x20 ;initialize pointer
MOVWF FSR ;to RAM
NEXTCLRF INDF ;clear INDF register
INCF FSR ;inc pointer
BTFSS FSR,4 ;all done?
GOTO NEXT ;no clear next
CONTINUE ;yes continue
Note: For memory map detail, see Figures 2-3 and 2-4.
Data
Memory
Indirect AddressingDirect Addressing
Bank Select Locatio n Select
RP1 RP0 6 0
From Opcode IRP File Select Register
70
Bank Select Location Se lect
00 01 10 11 180h
1FFh
00h
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
2004 Microchip Technology Inc. Preliminary DS41250A-page 31
PIC16F91X
3.0 CLOCK SOURCES
3.1 Overview
The PIC16F91X has a wide variety of clock sources
and selection features to allow it to be used in a wide
range of applications while maximizing performance
and minimizing power consumption. Figure 3-1
illustrates a block diagram of the PIC16F91X clock
sources.
Clock sources can be configured from external oscillators,
quartz crystal resonators, ceramic resonators, and
Resistor-Capacitor (RC) circuits. In addition, the system
clock source can b e configured f rom one of tw o internal
oscillators, with a choice of speeds selectable via
software. Additional clock features include:
• Selectable system clock source between external
or internal via software.
• Two-Speed Clock Start-up mode, which
minimizes latency between external oscillator
start-up and code execution.
• Fail-Safe Clock Monitor (FSCM) designed to
detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch to the
Internal Os cillator.
The PIC1 6F91X can be configured in one of eight clock
modes.
1. EC – External clock with I/O on RA6.
2. LP – Low-gain Crystal or Ceramic Resonator
Oscillator mode.
3. XT – Medium-gain Crystal or Ceramic Resonator
Oscillator mode.
4. HS – High-gain Crystal or Ceramic Resonator
mode.
5. RC – External Resistor-Capacitor (RC) with
FOSC/4 output on RA6.
6. RCIO – External Resistor-Capacitor with I/O on
RA6.
7. INTOSC – Internal oscillator with FOSC/4 output
on RA6 and I/O on RA7.
8. INTRCIO – Internal oscillator with I/O on RA6
and RA7.
Clock s ource m odes are configu red by t he FOSC <2:0>
bits in the Configuration Word register (see
Section 16.0 “Special Features of the CPU”). The
internal clock can be generated by two oscillators. The
HFINTOSC is a high-frequency calibrated oscillator.
The LFINTOSC is a low-frequency uncalibrated
oscillator.
FIGURE 3-1: PIC16F91 X SY STEM CLOCK BLOCK DIAGRAM
(CPU and Peripherals)
OSC1
OSC2
Sleep
External Oscillator
LP, XT, HS, RC, RCIO, EC
System Clock
Postscaler
MUX
MUX
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
250 kHz
IRCF<2:0>
111
110
101
100
011
010
001
000
31 kHz
LCD Module
FOSC<2:0>
(Configuration Word)
SCS
(OSCCON<0>)
Internal Oscillator
(OSCCON<6:4>)
Watchdog Timer (WDT)
Fail-Safe Clock Monitor (FSCM)
HFINTOSC
8 MHz
LFINTOSC
31 kHz
Power-up Timer (PWRT)
PIC16F91X
DS41250A-page 32 Preliminary 2004 Microchip Technology Inc.
REGISTER 3-1: OSCCON – OSCILLATOR CONTROL REGISTER (ADDRESS: 8Fh)
U-0 R/W-1 R/W-1 R/W-0 R-q R-0 R-0 R/W-0
— IRCF2 IRCF1 IRCF0 OSTS(1) HTS LTS SCS
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits
000 =31kHz
001 =125kHz
010 =250kHz
011 =500kHz
100 =1MHz
101 =2MHz
110 =4MHz
111 =8MHz
bit 3 OSTS: Oscillator Start-up Time-out Status bit
1 = Device is running from the external system clock defined by FOSC<2:0>
0 = Device is running from the internal system clock (HFINTOSC or LFINTOSC)
bit 2 HTS: HFINTOSC (High Frequency – 8 MHz to 125 kHz) Status bit
1 =HFINTOSC is stable
0 = HFINTOSC is not stable
bit 1 LTS: LFINTOSC (Low Frequency – 31 kHz) Stable bit
1 = LFINTOSC is stable
0 = LFINTOSC is not stable
bit 0 SCS: Syste m Cloc k S ele ct bit
1 = Internal oscillator is used for system clock
0 = Clock source define d by FOSC<2:0>
Note 1: The value of the OSTS bit on device power-up is dependent on the value of the
Configuration Word (CONFIG) of the device. The value of the OSTS bit will be ‘0’
on a de vice Power- on Reset ( POR) or any automatic c lock swit ch, which m ay occur
from Two-Spee d Sta r t-up or Fail -Safe Cl oc k Mo nit or, if the following co ndi tio ns are
true:
OSTS = 0 if:
FOSC<2:0> = 000 (LP) or 001 (XT) or 010 (HS)
and
IESO = 1 or FSCM = 1
(IESO will be enabled automatically if FSCM is enabled)
If any of the above conditions are not met, the value of the OSTS bit will be ‘1’ on
a device POR. See Section 3.6 “Two-Speed Clock Start-up Mode” and
Section 3.7 “Fail-Safe Clock Monitor” for more details.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
q = value depends on condition
2004 Microchip Technology Inc. Preliminary DS41250A-page 33
PIC16F91X
3.2 Clock Source Modes
Clock source modes can be classified as external or
internal.
• Extern al c lock mo des rely on external circuitry for
the clock source. Examples are oscillator mod ules
(EC mode), quartz crystal resonators or ceramic
resonators (LP, XT and HS modes), and
Resistor-Capacitor (RC mode) circuits.
• Internal clock sources are contained internally
within the PIC16F91X. The PIC16F91X has two
internal oscillators: the 8 MHz High-Frequency
Internal Os ci llator (HFINTOSC ) and 31 kHz
Low-Frequency Internal Oscillator (LFINTOSC).
The syste m cl oc k ca n be selected betwee n ex tern al or
inte rnal clock sour ces via t he Syste m Clock Sele ction
(SCS) bit (see Section 3.5 “Clock Switching”).
3.3 External Clock Modes
3.3.1 O SCILLA TOR START-UP TIMER
(OST)
If the PIC16F91X is configured for LP, XT or HS modes,
the Oscillator Start-up Timer (OST) counts 1024 oscil-
lations from the OSC 1 pin, follow ing a Power -on Res et
(POR), and the Power-up T imer (PWRT) has expired (if
configu red ), or a wake -up from Sleep. During th is tim e,
the program counter does not increment and program
execution is suspended. The OST ensures that the
oscillator circuit, using a quartz crystal resonator or
cerami c resona tor , has st arted an d is provid ing a st able
system clock to the PIC16F91X. When switching
between clock sources a delay is required to allow the
new clock to stabilize. These oscillator delays are
shown in Table 3-1.
3.3.1.1 Special Case
An exception to this is when the device is put to Sleep
while the followi ng con di tion s are true:
• LP is the selected primary oscillator mode.
• T1OSCEN = 1 (Timer1 oscillator is enabled).
•SCS = 0 (oscillator mode is defined by
FOSC<2:0>).
• OSTS = 1 (device is running from primary system
clock).
For this case, the OST is not necessary after a wake-up
from Slee p, since T imer1 conti nues to r un duri ng Sleep
and uses the same LP oscillator circuit as its clock
source. For these devices, this case is typically seen
when the LCD module is running during Sleep.
In applic ations where the OSCT UNE register is use d to
shift the FINTOSC frequency, the application should not
expect the FINTOSC frequency to stabilize immediately.
In this case, the frequency may shift gradually toward
the new value. The time for this frequency shift is less
than eight cycles of the base frequency.
Table 3-1 shows exam ples where the oscil lator delay is
invoked.
In order to mi nimize laten cy between externa l oscillator
start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 3.6
“Two-Speed Clock Start-up Mode”).
Note: When the OST is invoked, the WDOG is
held in Reset, because the WDOG ripple
counter is us ed by th e OST to perform the
oscillator delay count. When the OST
count has expired, the WDOG will begin
counting (if enabled).
PIC16F91X
DS41250A-page 34 Preliminary 2004 Microchip Technology Inc.
TABLE 3-1: OSCILLATOR DELAY EXAMPLES
Syste m Clock
Source Frequency Switching From Oscillator Delay
(TOST)Comments
LFIOSC 31 kHz Sleep 10 µs internal delay Following a wake-up from Sleep mode
or POR, an interna l dela y is invok ed to
allow the memory bias to stabilize
before program execution can begin.
HFIOSC 125 kHz-8 MHz Sleep 10 µs internal delay Following a wake-up from Sleep mode
or POR, an interna l dela y is invok ed to
allow the memory bias to stabilize
before program execution can begin.
XT or HS 4-20 MHz INTOSC or Sleep 1024 clock cycles Following a change from INTOSC, an
OST of 1024 cy cl es mu st occ ur.
LP 32 kHz INTOSC or Sleep 1024 clock cycles Following a change from INTOSC, an
OST of 1024 cy cl es mu st occ ur. See
Section 3.3.1.1 “Special Case” for
special case conditions.
LP with T1OSC
enabled 32 kHz Sleep 10 µs internal delay Following a wake-up from Sleep mode,
an internal delay is invoked to allow the
memory bias to stabilize before program
execution can begin. See
Section 3.3.1.1 “Special Case” for
details about this special case.
EC, RC 0-20 MHz Sleep 10 µs internal delay Following a wake-up from Sleep mode
or POR, an interna l dela y is invok ed to
allow the memory bias to stabilize
before program execution can begin.
EC, RC 0-20 MH z LFIOSC 10 µs internal delay Following a switch from a LFIOSC or
POR, an internal delay is invoked to
allow the memory bias to stabilize
before program execution can begin.
2004 Microchip Technology Inc. Preliminary DS41250A-page 35
PIC16F91X
3.3.2 EC MODE
The External Clock (EC) mode allows an externally
generated logic level as the system clock source.
When operating in this mode, an external clock source
is connected to the OSC1 pin and the RA6 pin is
availa ble for general purpose I/O. Figure 3-2 shows th e
pin connections for EC mode.
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC16F91X design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
FIGURE 3-2: EXTERNAL CLOCK (EC)
MODE OPERATION
3.3.3 LP, XT, HS MODES
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
the OSC1 and OSC2 pins (Figures 3-3 and 3-4). The
mode selects a low, medium or high gain setting of the
internal inverter-amplifier to support various resonator
types and speed.
LP Oscillator mode select s the lowest gain setting of the
internal inverter-amplifier . LP mode current consum ption
is the least of the three modes. This mode is bes t suited
to drive resonators with a low drive level specification, for
example, tuning fork type crys tals.
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current c onsumption is the medium of the three mo des.
This mode is best suited to drive resonators with a
medium drive level specification, for example,
low-frequency/AT-cut quartz crystal resonators.
HS Oscillator mode selects the highest gain setting of
the internal inverter-amplifier. HS mode current
consumption is the highest of the three modes. This
mode is best suited for resonators that require a high
drive setting, for example, high-frequency/AT-cut
quartz crystal resonators or ceramic resonators .
Figures 3-3 and 3-4 show typical circuits for quartz
crystal and ceramic resonators, respectively.
RA6/OSC2/CLKO/T1OSO
RA6
Clock
PIC16F91X
Internal
FOSC
FOS C<2:0> = 011
OSC1/ Clock
CLKIN
(External
System)
Note: In the past, the sources for the LP oscilla-
tor and Timer1 oscillator have been sepa-
rate circuits. In this family of devices, the
LP oscillator and Timer1 oscillator use the
same oscillator circuitry. When using a
device config ured for the LP osci llator an d
with T1OSCEN = 1, the source of the
clock for each function comes from the
same oscillator block.
PIC16F91X
DS41250A-page 36 Preliminary 2004 Microchip Technology Inc.
FIGURE 3-3: QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
FIGURE 3-4: CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
Note 1: Quartz crystal characteristics vary
according to type, package and manufac-
turer. The user should consult the
manufacturer data sheets for specifica-
tions and recommended application.
2: Always veri fy os ci lla tor pe rform an ce ov er
the VDD and temperature range that is
expected for the application.
Note 1: A series resistor (RS) may be required fo r
quartz crystals with low drive level.
2: The v alue of RF va ries wit h the osci llator
mode selected (typically between 2 MΩ to
10 MΩ).
3: If using LP mode and T1OSC in enable,
the LP oscilla tor will c ontinue to run during
Sleep.
C1
C2
Quartz
OSC2
RS(1)
OSC1
RF(2)
Sleep(3)
To Int.
Logic
PIC16F91X
Crystal
Note 1: A series resistor (R S) may b e req ui red f or
ceramic resonators with low drive level.
2: The va lue of RF varies with the oscillator
mode sel ected (typically between 2 MΩ to
10 MΩ).
3: An additional parallel feedback resistor
(RP) may be required for proper ceramic
resonator operation (typical value 1 MΩ).
C1
C2
OSC2
RS(1)
OSC1
RF(2)
Sleep
To Int.
Logic
PIC16F91X
RF(3)
Ceramic
Resonator
2004 Microchip Technology Inc. Preliminary DS41250A-page 37
PIC16F91X
3.3.4 EX TERN AL RC MODES
The External Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required. There are two modes, RC and RCIO.
In RC mode, the RC circuit connects to the OSC1 pin.
The OSC2/CLKO pin outputs the RC oscillator
frequency divided by 4. This signal may be used to
provide a clock for external circuitry, synchronization,
calibration, test or other application requirements.
Figure 3-5 shows the RC mode connections.
FIGURE 3-5: RC MODE
In RCIO mode, the RC circuit is connected to the OSC1
pin. The OSC2 pin becomes an additional general
purpose I/O pin. The I/O pin becomes bit 4 of PORTA
(RA4). Figure 3-6 shows the RCIO mode connections.
FIGURE 3-6: RCIO MODE
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT)
values and the operating temperature. In addition to
this, the oscillator frequency will vary from unit to unit
due to normal threshold voltage. Furthermore, the
difference in le ad fram e c apacitance between pac kag e
types w ill also a ffe ct the oscil lation freque ncy o r for low
CEXT values. The user also needs to take into account
variation due to tolerance of external RC components
used.
3.4 Internal Clock Modes
The PIC16F91X has two independent, internal
oscillators that can be configured or selected as the
system clock source.
1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
8 MHz. The frequ ency of t he H FINT OSC can b e
user adjusted ±12% via software using the
OSCTUNE register (Register 3-2).
2. The LFINTOSC (Low-Frequency Internal
Oscillator) is uncalibrated and operates at
approximately 31 kHz.
The sys tem cloc k speed can b e select ed via soft ware
using the Internal Oscillator Frequency Select (IRCF)
bits.
The syste m cl oc k can be se lec ted betw ee n ext ernal or
inte rnal cloc k sources via the S ystem Clo ck Select ion
(SCS) bit (see Section 3.5 “Clock Switching”).
3.4.1 INTOSC AND INTRCIO MODES
The INTOSC and INTRCIO modes configure the inter-
nal oscillators as the system clock source when the
device is programmed using the Oscillator Selection
(FOSC) bits in the Configuration Word register
(Register 16-1).
In INTOSC m ode, the OSC1 pi n is available fo r general
purpose I/O. The OSC2/CLKO pin outputs the selected
internal oscillator frequency divided by 4. The CLKO
signal may be used to provide a clock for external
circuitry, synchronization, calibration, test or other
application requirements.
In INTRCIO mode, the OSC1 and OSC2 pins are
available for general purpose I/O.
3.4.2 HFINTOSC
The High-Fre quency Int ernal Oscil lator (HFINT OSC) is
a factory calibrated 8 MHz internal clock source. The
frequency of the HFINTOSC can be altered
approxi mately ± 12% vi a software using the OSC TUNE
register (Regi ste r 3-2).
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 3-1). One of seven
frequencies can be selected via software using the
IRCF bits (see Section 3.4.4 “Frequency Select Bits
(IRCF)”).
The HFINTOSC is enabled by selecting any frequency
between 8 MHz and 125 kHz (IRCF ≠ 000) as the
system clock source (SCS = 1), or when Two-Speed
Start- up is ena ble d (IESO = 1 and IRCF ≠ 000).
The HF Internal Oscillator (HTS) bit (OSCCON<2>)
indicates whether the HFINTOSC is stable or not.
OSC2/CLKO
CEXT
REXT PIC16F91X
OSC1
FOSC/4
Internal
Clock
VDD
VSS
Recommended values:3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
I/O (OSC2)
CEXT
REXT PIC16F91X
OSC1
RA6
Internal
Clock
VDD
VSS
Recomm ended values:3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
PIC16F91X
DS41250A-page 38 Preliminary 2004 Microchip Technology Inc.
3.4.2.1 OSCTUNE Register
The HFINTOSC is factory calibrated but can be
adjusted in software by writing to the OSCTUNE
register (Register 3-2).
The OSCTUNE register has a tuning range of ±12%.
The default value of the OSCTUNE register is ‘0’. The
value is a 5-bit two’s complement number. Due to
process varia tion, th e mono ton icity and frequen cy ste p
cannot be spe ci fie d.
When the OSCTUNE register is modified, the HFINTOSC
frequency will begin shifting to the new frequency. The
HFINTOSC clock will stabilize within 1 ms. Code
execution continues during this shift. There is no
indication that the shift has occurred.
OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock
Monitor (FSCM) and peripherals, are not af fected by the
change in frequency.
REGISTER 3-2: OSCTUNE – OSCILLATOR TUNING RESISTOR (ADDRESS: 90h)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 TUN<4:0>: Frequenc y Tuning bits
01111 = Maximum frequency
01110 =
•
•
•
00001 =
00000 = Center frequency. Oscillator module is running at the calibrated frequency.
11111 =
•
•
•
10000 = Minimum frequency
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Preliminary DS41250A-page 39
PIC16F91X
3.4.3 LFINTOSC
The Low-Frequency Internal Oscill ator (LFINTOSC) is
an uncalibrated (approximate) 31 kHz internal clock
source.
The output of the LFINTOSC connects to a postscaler
and multiplexer (see Figure 3-1). 31 kHz can be
selected via software using the IRCF bits (see
Section 3.4.4 “Frequency Select Bits (IRCF)”). The
LFINTOSC is also the frequency for the Power-up
Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe
Clock Monitor (FSCM).
The LFINTOSC is enabled by selecting 31 kHz
(IRCF = 000) as the s ystem cloc k sourc e (SCS = 1), or
when any of the following are enabled:
• Two-Speed Start-up (IESO = 1 and IRCF = 000)
• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor (FSCM)
• Selected as LCD module clock source
The LF Internal Oscillator (LTS) bit (OSCCON<1>)
indicates whether the LFINTOSC is stable or not.
3.4.4 FREQUENCY SELECT BITS (IRCF)
The output of the 8 MHz HFINTOSC and 31 kHz
LFINTOSC connect to a postscaler and multiplexer
(see Figure 3-1). The Internal Oscillator Frequency
select bits, IRCF<2:0> (OSCCON<6:4>), select the
frequency output of the internal oscillators. One of eight
frequencies can be selected via software:
•8 MHz
• 4 MHz (Default after Reset)
•2 MHz
•1 MHz
• 500 kHz
• 250 kHz
• 125 kHz
•31 kHz
3.4.5 HF AND LF INTOSC CLOCK
SWITCH TIMING
When switching between the LFINTOSC and the
HFINTOSC, the new oscillator may already be shut
down to sa ve pow er. If this is the case , there is a 10 µs
delay after the IRCF bits are modified before the
frequency selection takes place. The LTS/HTS bits will
reflect the current active status of the LFINTOSC and
the HFINTOSC oscillators. The timing of a frequency
selection is as follows:
1. IRCF bits are modified.
2. If the new clock is shut down, a 10 µs clock
start-up delay is started.
3. Clock switch circuitry waits for a falling edge of
the current clock.
4. CLKO is held low and the clock switch circuitry
waits for a rising edge in the new clock.
5. CLKO is now connected with the new clock.
HTS/LTS bits are updated as required.
6. Clock switch is complete .
If the internal oscillator speed selected is between
8 MHz and 125 kHz, there is no start-up delay before
the new frequency is selected. This is because the old
and the new frequencies are derived from the
HFINTOSC via the postscaler and multiplexer.
3.5 Clock Switching
The system clock source can be switched between
external and internal clock sources via software using
the System C lock Select (SCS) bit.
3.5.1 SYS TEM CLOCK SELECT (SCS) BIT
The System Clock Select (SCS) bit (OSCCON<0>)
selects the system clock source that is used for the
CPU and peripherals.
• When SCS = 0, the system clock source is
determined by configuration of the FOSC<2:0>
bits in the Configuration Word register (CONFIG).
• When SCS = 1, the system clock source is
chosen by the internal oscillator frequency
selected by the IRCF bits. After a Reset, SCS is
always cleared.
Note: Foll owin g any Reset , t he IRC F bit s are s et
to ‘110’ and the frequency selection is set
to 4 MHz. The user can modify the IRCF
bits to select a different frequency. Note: Any automatic clock switch, which may
occur from Two-Speed Start-up or
Fail-Safe Clock Monitor, does not update
the SCS bit. The user can monitor the
OSTS (OSCCON<3>) to determine the
current system clock source.
PIC16F91X
DS41250A-page 40 Preliminary 2004 Microchip Technology Inc.
3.5.2 OSCILLATOR START-UP TIME -OU T
STATUS BIT
The Oscillator Start-up Time-out Status (OSTS) bit
(OSCCON<3>) indicates whether the system clock is
running from the external clock source, as defined by
the FOSC bits, or from the internal clock source. In
particular, OSTS indicates that the Oscillator Start-up
Timer (OST) has timed out for LP, XT or HS modes.
3.6 Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device.
This mode allows the application to wake-up from
Sleep, perform a few instructions using the INTOSC
as the clock source and go back to Sleep without
waiting for the primary oscillator to become stable.
When the PIC16F91X is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) is enabled
(see Section 3.3.1 “Oscillator Start-up Timer
(OST)”). The OST timer will suspend program
execution until 1024 oscillations are counted.
Two-Spe ed Start- up mode minimize s the del ay in cod e
execution by operating from the internal oscillator as
the OST is counting. When the OST count reaches
1024 and the OSTS bit (OSCCON<3 >) is se t, program
execution switches to the external oscillator.
3. 6.1 TWO-SPE ED START-UP MODE
CONFIGURATION
Two-Speed Start-up mode is configured by the
following settings:
• IESO = 1 (CONFIG<10>) Internal/External Switch
Over bit.
•SCS = 0.
• FOSC configured for LP, XT or HS mode .
Two-Speed Start-up mode is entered after:
• Power-on Reset (POR ) and, if enabled, after
PWRT has expired, or
• Wake-up from Sleep.
If the external clock oscillator is configured to be anything
other than LP, XT or HS mode, then Two-Speed Start-up
is disabled. This is because the external clock oscillator
does not require any stabilization time after POR or an
exit from Sleep.
3.6. 2 TWO-SPEED START-UP
SEQUENCE
1. Wake-up from Power-on Reset or Sleep.
2. Instructions begin execution by the internal
oscillator at the frequency set in the IRCF bits
(OSCCON<6:4>).
3. OST enabled to count 1024 clock cycles.
4. OST timed out, wait for falling edge of the
internal oscillator.
5. OSTS is set.
6. System cloc k held lo w until the next fallin g edge
of new clock (LP, XT or HS mode).
7. System clock is switched to external clock
source.
3.6.3 CHE CKING EXTERNAL/I NTERNAL
CLOCK STATUS
Checking the state of the OSTS bit (OSCCON<3>) will
confirm if the PIC16F91X is running from the external
clock source as defined by the FOSC bits in the
Configuration Word (CONFIG) or the internal oscillator.
Note: Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit (OSCCON<3>) to remain
clear.
2004 Microchip Technology Inc. Preliminary DS41250A-page 41
PIC16F91X
FIGURE 3-7: TWO-SPEED START-UP
3.7 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) is designed to
allow the device to continue to operate in the event of
an oscillator failure. The FSCM can detect oscillator
failure at any point after the device has exited a Reset
or Sleep condition and the Oscillator Start-up Timer
(OST) has expired.
FIGURE 3-8: FSCM BLOCK DIAGRAM
The FSCM function is enabled by setting the FCMEN
bit in the Con figuration W ord (CONFIG). It is appl icable
to all external clock options (LP, XT, HS, EC or RC
modes).
In the event of an external clock failure, the FSCM will
set the O SFIF bi t (PIR2< 7>) and g enerate an oscil lator
fail interrupt if the OSFIE bit (PIE2<7>) is set. The
device will then switch the system clock to the internal
oscillator. The system clock will continue to come from
the inte rnal oscillator unless the external clock recovers
and the Fail-Safe condition is exited.
The frequency of the internal oscill ator will depend upon
the value contained in the IRCF bits (OSCCON<6:4>).
Upon entering the Fail-Safe condition, the OSTS bit
(OSCCON<3>) is automatically cleared to reflect that
the internal oscillator is active and the WDT is cleared.
The SCS bit (OSCCON<0>) is not updated. Enabling
FSCM does not affect the LTS bit.
The FSCM sample clock is generated by dividing the
INTOSC clock by 64. This will allow enough time
between FSCM sample clocks for a system clock edge
to occur. Figure 3-8 shows the FSCM block diagram.
On the rising edge of the sample clock, a monitoring
latch ( CM = 0) will be cleared. On a falling edge of the
primary system clock, the monitoring latch will be set
(CM = 1). In th e e ve nt t hat a fal lin g edge of the s ampl e
clock occurs, and the monitoring latch is not set, a clock
failure has been detected. The assigned internal
oscillator is enabled when FSCM is enabled as
reflected by the IRCF.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
0 1 1022 1023
PC PC + 1 PC + 2
TOSTT
INTOSC
OSC1
OSC2
Progra m Count er
System Clock
Primary
LFINTOSC ÷ 64
Oscillator
Clock Clock
Fail
Detector
Clock
Failure
Detected
Note 1: Two-Speed Start-up is automatically
enabled when t he Fail-Safe Clock Monitor
mode is enabled.
2: Primary clocks with a frequency ≤ ~488 Hz
will be considered failed by the FSCM. A
slow starting oscillator can cause an
FSCM interrupt.
PIC16F91X
DS41250A-page 42 Preliminary 2004 Microchip Technology Inc.
3.7.1 FAIL-SAFE CONDITION CLEARING
The Fail-Safe c ondition is cleared after a Reset, the
execution of a SLEEP instruction, or a modification of
the SCS bit. While in Fail-Safe condition, the
PIC16F91X uses the internal oscillator as the system
without exiting the Fail-Safe condition.
The Fail-Safe condition must be cleared before the
OSFIF flag can be cleared.
FIGURE 3-9: FSCM TIMING DIAGRAM
3.7.2 RES E T OR WA KE-UP FROM SLEE P
The FSCM is designed to detect oscillator failure at
any point after the device has exited a Reset or Sleep
condition and the Oscillator Start-up Timer (OST) has
expired. If the external clock is EC or RC mode,
monitoring will begin immediately following these
events.
For LP, XT or HS mode the external oscillator may
require a start-up time considerably longer than the
FSCM sample clock time, a false clock failure may be
detected (see Figure 3-9). To prevent this, the internal
oscillator is automatically configured as the system
clock and functions until the external clock is stable
(the OST has timed out). This is identical to
Two-Speed Start-up mode. Once the external
oscill ato r is st a bl e, the LF INTOSC returns to it s role as
the FSCM source.
.
TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
OSCFIF
CM Output
System
Clock
Output
Sample Clock
Failure
Detected
Oscillator
Failure
Note: The sy stem clock is normally at a much higher frequency than the sample clock. The relative
frequencies in this example have been chosen for clarity.
(Q)
CM Test CM Test CM Test
Note: Due to the wide range of o scillator start-u p
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount o f time, the user shoul d check the
OSTS bit (OSCCON<3>) to verify the
oscillator start-up and system clock
switchover has successfully completed.
Addr Nam e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
8Fh OSCCON — IRCF2 IRCF1 IRCF0 OSTS(2) HTS LTS SCS -110 q000 -110 x000
90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu
2007h(1) CONFIG CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — —
Legend: x = unknown, u = unchanged, — = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Note 1: See Register 16 -1 for operation of all Configuration Word bits.
2: See Register 3-1 for details.
2004 Microchip Technology Inc. Preliminary DS41250A-page 43
PIC16F91X
4.0 I/O PORTS
This dev ic e i nc lud es four 8 -bi t port registers alo ng with
their corresponding TRIS registers and one four bit
port:
• PORTA and TRISA
• PORTB and TRISB
• PORTC and TRISC
• PORTD and TRISD
• PORTE and TRISE
PORTA, PORTB, PORTC and RE3/MCLR/VPP are
impl e me nte d on al l de vi ce s. PO RTD an d RE <2: 0 > ar e
implemented only on the PIC16F914 and PIC16F917.
4.1 PORTA and TRISA Registers
PORTA is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Register 4-2). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., put the
corresponding output driver in a High-impedance mode).
Clearing a TRISA bit (= 0) will make the corresponding
PORTA pin an output (i.e., put the contents of the output
latch on the selected pin). Example 4-1 shows how to
initialize PORTA.
Five o f the p ins o f PORTA c an be con figured as analo g
inputs. These pins, RA5 and RA<3:0>, are configured
as analog inputs on device power-up and must be
reconfigured by the user to be used as I/O’s. This is
done b y w riting the a ppropri ate v alues to the CMCO N0
and ANSEL registers (see Example 4-1).
Reading the PORTA register (Register 4-1) reads the
status of the pins, whereas writing to it will write to the
port latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are rea d, this value is modified and then w ritten
to the port data la tch.
The TRISA register controls the direction of the
PORTA pins, even when they are being used as analog
inputs. The user must ensure the bits in the TRISA
register are maint aine d set when u sing them as an alog
input s. I/O pin s co nfigure d as analo g inpu t alway s rea d
‘0’.
EXAMPLE 4- 1: INITIALIZI NG PORTA
Note 1: The CMCON0 (9Ch) register must be
initialized to configure an analog channel
as a digital input. Pins configured as
analog inputs will read ‘0’.
2: Analog lines that carry LCD signals
(i.e., SEGx, COMy, where x and y are
segment and common identifiers) are
shown as direct connectio ns to the device
pins. The signals are outputs from the
LCD module and may be tri-stated,
depending on the configuration of the
LCD mo dul e.
BCF STATUS,RP0 ;Bank 0
BCF STATUS,RP1 ;
CLRF PORTA ;Init PORTA
BSF STATUS,RP0 ;Bank 1
BCF STATUS,RP1 ;
MOVLW 07h ;Set RA<2:0> to
MOVWF CMCON0 ;digital I/O
CLF ANSEL ;Make all PORTA I/O
MOVLW F0h ;Set RA<7:4> as inputs
MOVWF TRISA ;and set RA<3:0>
; as outputs
BCF STATUS,RP0 ;Bank 0
BCF STATUS,RP1 ;
PIC16F91X
DS41250A-page 44 Preliminary 2004 Microchip Technology Inc.
REGISTER 4-1: PORTA – PORTA REGISTER (ADDRESS: 05h)
REGISTER 4-2: TRISA – PORTA TRI-STATE REGISTER (ADDRESS: 85h)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0
bit 7-0 RA<7:0>: PORTA I/O Pin bits
1 = Port pin is >VIH
0 = Port pin is <VIL
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
bit 7 bit 0
bit 7-0 TRISA<7:0>: PORTA Tri-State Control bits
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Note: TRISA<7:6> always reads ‘1’ in XT, HS, and LP OSC modes.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Preliminary DS41250A-page 45
PIC16F91X
4.1.1 PIN DESCRIPTIONS AND
DIAGRAMS
Each PORTA pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions,
refer to the appropriate section in this data sheet.
4.1.1.1 RA0/AN0/C1-/SEG12
Figure 4-1 shows the di agram f or thi s pin. The R A0 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the A/D
• an analog input for Comparator 1
• an analog output for the LCD
FIGURE 4-1: BLOCK DIAGRAM OF RA0
QD
Q
CK
Data Latch
TRIS Latch
RD TRISA
RD PORTA
Analog Input or
I/O Pin
QD
Q
CK
DQ
EN
TTL
Input Buffer
VDD
To A/ D Converter or Comparator
SEG12
SE12 and LCDEN
SE12 and LCDEN
Data Bus
WR PORTA
WR TRISA
SE12 and LCDEN
PIC16F91X
DS41250A-page 46 Preliminary 2004 Microchip Technology Inc.
4.1.1.2 RA1/AN1/C2-/SEG7
Figure 4-2 shows the di agram for this pi n. The RA 1 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the A/D
• an analog input for Comparator 2
• an analog output for the LCD
FIGURE 4-2: BLOCK DIAGRAM OF RA1
QD
Q
CK
Data Latch
TRIS Latch
RD TRISA
RD PORTA
QD
Q
CK
DQ
EN
To A/D Converter or Comparator
SEG7
Data Bus
WR PORTA
WR TRISA
Analog Input or
I/O Pin
TTL
Input Buffer
VDD
SE7 and LCDEN
SE7 and LCDEN
SE7 and LCDEN
2004 Microchip Technology Inc. Preliminary DS41250A-page 47
PIC16F91X
4.1.1.3 RA2/AN2/C2+/VREF-/COM2
Figure 4-3 shows the di agram f or thi s pin. The R A2 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the A/D
• an analog input for Comparator 2
• a voltage reference input for the A/D
• an analog output for the LCD
FIGURE 4-3: BLOCK DIAGRAM OF RA2
QD
Q
CK
Data Latch
TRIS Latch
RD TRISA
RD PORTA
QD
Q
CK
DQ
EN
To A/D Converter or Comparator
COM2
Data Bus
WR PORTA
WR TRISA
To A/D Module VREF- Input
Analog Input or
I/O Pin
TTL
Input Buffer
VDD
LCDEN and
LMUX<1:0> = 1X
LCDEN and
LMUX<1:0> = 1X
LCDEN and
LMUX<1:0> = 1X
PIC16F91X
DS41250A-page 48 Preliminary 2004 Microchip Technology Inc.
4.1.1.4 RA3/AN3/C1+/VREF+/COM3/SEG15
Figure 4-4 shows the di agram for this pi n. The RA 3 pin
is configurable to function as one of the following:
• a general purpose in put
• an analog input for the A/D
• an analog input from Comparator 1
• a voltage reference input for the A/D
• analog outputs for the LCD
FIGURE 4-4: BLOCK DIAGRAM OF RA3
QD
Q
CK
Data Latch
TRIS Latch
RD TRISA
RD PORTA
VSS
QD
Q
CK
TTL
Input Buffer
To A/D Converter or Comparator
COM3(1) or SEG15
Data Bus
WR PORTA
WR TRISA
To A/D Module VREF+ Input
Note 1: PIC16F913/916 only.
2: For the PIC 16F913/916, the LCDMODE_EN = LCDEN and (SE15 or LMUX<1:0> = 11).
For the PIC16F914/917, the LCDMODE_EN = LCDEN and SE15.
Q
Q
VDD
LCDMODE_EN(2)
Analog Input or
I/O Pin
LCDMODE_EN(2)
DQ
EN
LCDMODE_EN(2)
2004 Microchip Technology Inc. Preliminary DS41250A-page 49
PIC16F91X
4.1.1.5 RA4/C1OUT/T0CK1/SEG4
Figure 4-5 shows the di agram f or thi s pin. The R A4 pin
is configurable to function as one of the following:
• a general purpose I/O
• a digital output from Comparator 1
• a clock input for TMR0
• an analog output for the LCD
FIGURE 4-5: BLOCK DIAGRAM OF RA4
C1OUT
CM<2:0> = 110 or 101
0
1
Schmitt
Trigger
QD
Q
CK
Data Latch
TRIS Latch
RD TRISA
RD PORTA
VSS
VDD
QD
Q
CK
D
Q
EN
T0CKI
Data Bus
WR PORTA
WR TRISA
SEG4
Analog Input or
I/O Pin
TTL
Input Buffer
SE4 and LCDEN
SE4 and LCDEN
SE4 and LCDEN
SE4 and LCDEN
PIC16F91X
DS41250A-page 50 Preliminary 2004 Microchip Technology Inc.
4.1.1.6 RA5/AN4/C2OUT/SS/SEG5
Figure 4-6 shows the di agram for this pi n. The RA 5 pin
is configurable to function as one of the following:
• a general purpose I/O
• a digital output from Comparator 2
• a slave select input
• an analog output for the LCD
• an analog input for the A/D
FIGURE 4-6: BLOCK DIAGRAM OF RA5
AN4
RD TRISA
RD PORTA
D
Q
EN
TTL
Input Buff er
SEG5
SE5 and LCDEN
Data Bus
WR PORTA
WR TRISA
To SS Input
Analog Input or
SE5 and LCDEN
C2OUT
CM<2:0> = 110 or 101
0
1
QD
Q
CK
Data Latch
VSS
VDD
QD
Q
CK
I/O Pin
TRIS Latch
SE5 and LCDEN
2004 Microchip Technology Inc. Preliminary DS41250A-page 51
PIC16F91X
4.1.1.7 RA6/OSC2/CLKO/T1OSO
Figure 4-7 shows the di agram f or thi s pin. The R A6 pin
is configurable to function as one of the following:
• a general purpose I/O
• a crystal/resonator connection
• a clock output
• a TMR1 oscillator connection
FIGURE 4-7: BLOCK DIAGRAM OF RA6
CLKO (FOSC/4)
FOSC = 1x1
RD PORTA
D
Q
EN
TTL
Input Buffer
Data Bus
WR PORTA
WR TRISA
FOSC = 00x, 010 FOSC = 00x, 010
RA6/OSC2/
Oscillator
Circuit
From OSC1
CLKO/T1OSO
Pin
RD TRISA
0
1
QD
Q
CK
Data Latch
VSS
VDD
QD
Q
CK
TRIS Latch
or T1OSCEN or T1OSCEN
PIC16F91X
DS41250A-page 52 Preliminary 2004 Microchip Technology Inc.
4.1.1.8 RA7/OSC1/CLKI/T1OSI
Figure 4-8 shows the di agram for this pi n. The RA 7 pin
is configurable to function as one of the following:
• a general purpose I/O
• a crystal/resonator connection
• a clock input
• a TMR1 oscillator connection
FIGURE 4-8: BLOCK DIAGRAM OF RA7
TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
V alue on all
other
Resets
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx uuuu uuuu
10h T1CON T1GINV T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
1Fh ADCON0 ADFM VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000
81h/181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
91h ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
9Ch CMCON0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000
107h LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011
11Ch LCDSE0(1) SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 uuuu uuuu
11Dh LCDSE1(1) SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note 1: This register is only initialized by a POR or BOR reset and is unchanged by other resets.
QD
Q
CK
Data Latch
TRIS Latch
RD TRISA
RD PORTA
QD
Q
CK
D
Q
EN
TTL
Input Buff er
Data Bus
WR PORTA
WR TRISA
FOSC = 10x FOSC = 10x
RA7/OSC1/
VDD
CLKI/T1OSI
Pin
Oscillator
Circuit
From OSC1
FOSC = 011
2004 Microchip Technology Inc. Preliminary DS41250A-page 53
PIC16F91X
4.2 PORTB and TRISB Registers
PORTB is a general purpose I/O port with similar
functionality as the PIC16 F77. All PORTB pins can have
a weak pull-up feature, and PORTB<7:4> implements an
interrupt-on-input change function.
PORTB is also used for the Serial Flash programming
interface.
EXAMPLE 4- 2: INITIALIZING PORTB
4.3 Additional PORTB Pin Functions
RB<7:6> are used as data and clock signals, respectively ,
for both serial programming and the in-circuit debugger
features on the device. Also, RB0 can be configured as an
external interrupt input.
4.3.1 WEAK PULL-UPS
Each of the POR TB pins has an individually configurable
internal weak pull-up. Control bits WPUB<7:0> enable or
disable each pull-up. Refer to Register 4-6. Each weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disabled on a
Power-on Reset by the RBPU bit (OPTION_REG<7>).
4.3.2 INTERRUPT-ON-CHANGE
Four of the PORTB pins are individually configurable
as an interrupt-on-change pin. Control bits IOCB<7:4>
enable or disable the interrupt function for each pin.
Refer to Register 4-5. The interrupt-on-change feature
is disabled on a Power-on Reset.
For enabled interrupt-on-change pins, the values are
comp ared with the old val ue latch ed on the la st read of
PORTB. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTB Change Interrupt flag
bit (RBIF) in the INTCON register (Register 2-3).
This interrupt can wake the device from Sleep. The user,
in the Interrupt Service Routine, clears the inte rrupt by:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear the flag bit RBIF.
A mism at c h c ond it i on wi ll co nti n ue to s et f lag bi t RB IF.
Reading or writing PORTB will end the mismatch con-
dition and allow flag bit RBIF to be cleared. The latch
holding the last read value is not affected by a MCLR
nor BOR Reset. After these Resets, the RBIF flag will
continue to be set if a mismatch is present.
Note: Analog lines that carry LCD signals
(i.e., SEGx , COMy , whe re x and y are seg-
ment and common identifiers) are shown
as direct connections to the device pins.
The signals are outputs from the LCD
module and may be tri-stated, depending
on the configuration of the LCD module.
BCF STATUS,RP0 ;Bank 0
BCF STATUS,RP1 ;
CLRF PORTB ;Init PORTB
BSF STATUS,RP0 ;Bank 1
BCF STATUS,RP1 ;
MOVLW FFh ;Set RB<7:0> as inputs
MOVWF TRISB ;
BCF STATUS,RP0 ;Bank 0
BCF STATUS,RP1 ;
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF
interrupt flag may not get set. Furthermore,
since a read or write on a port af fects all bits
of that port, care mu st be taken when us ing
multiple pins in Interrupt-on-change mode.
Changes on one pin may not be seen while
servicing changes on another pin.
PIC16F91X
DS41250A-page 54 Preliminary 2004 Microchip Technology Inc.
REGISTER 4-3: PORTB – PORTB REGISTER (ADDRESS: 06h OR 106h)
REGISTER 4-4: TRISB – PORTB TRI-STATE REGISTER (ADDRESS: 86h, 186h)
REGISTER 4-5: IOCB – PORTB INTERRUPT-ON-CHANGE REGISTER (ADDRESS: 96h)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
bit 7 bit 0
bit 7-0 RB<7:0>: PORTB I/O Pin bits
1 = Port pin is >VIH
0 = Port pin is <VIL
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
bit 7 bit 0
bit 7-0 TRISB<7:0>: PORTB Tri-State Control bits
1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output
Note: TRISB<7:6> always reads ‘1’ in XT, HS and LP OSC modes.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
IOCB7 IOCB6 IOCB5 IOCB4 ————
bit 7 bit 0
bit 7-4 IOCB<7:4>: Interrupt-on- change bits
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
bit 3-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Preliminary DS41250A-page 55
PIC16F91X
REGISTER 4-6: WPUB – WEAK PULL-UP REGISTER (ADDRESS: 95h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0
bit 7 bit 0
bit 7-0 WPUB<7:0>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global R BP U must be enabled for individual pu ll-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in Output mode
(TRISB<7:0> = 0).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F91X
DS41250A-page 56 Preliminary 2004 Microchip Technology Inc.
4.3.3 PIN DESCRIPTIONS AND
DIAGRAMS
Each PORTB pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the LCD or interrupts, refer to the appropriate
section in this data sheet.
4.3.3.1 RB0/INT/SEG0
Figure 4-9 shows the di agram for this pi n. The RB 0 pin
is configurable to function as one of the following:
• a general purpose I/O
• an external edge triggered interrupt
• an analog output for the LCD
4.3.3.2 RB1/SEG1
Figure 4-9 shows the di agram for this pi n. The RB 1 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD
4.3.3.3 RB2/SEG2
Figure 4-9 shows the di agram for this pi n. The RB 2 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD
4.3.3.4 RB3/SEG3
Figure 4-9 shows the di agram for this pi n. The RB 3 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD
2004 Microchip Technology Inc. Preliminary DS41250A-page 57
PIC16F91X
FIGURE 4-9: BLOCK DIAGRAM OF RB<3:0>
QD
CK
Data Latch
TRIS Latch
RD TRISB
RD PORTB
QD
CK
D
Q
EN
TTL
Input Buffer
SE<3:0> and LCDEN
Data Bus
WR PORTB
WR TRISB
P
VDD
I/O Pin
VDD
Weak
Pull-up
SE<3:0>
SEG<3:0>
INT(2) Schmitt
Trigger
SE0 and LCDEN
RBPU(1)
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
2: RB0 only.
SE<3:0> and LCDEN
PIC16F91X
DS41250A-page 58 Preliminary 2004 Microchip Technology Inc.
4.3.3.5 RB4/COM0
Figure 4-10 shows the diagram for this pin. The RB4
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LC D
FIGURE 4-10: BLOCK DIAGRAM OF RB4
From other
Set RBIF
RB<7:4> pins
LCDEN
COM0
QD
CK
Data Latch
TRIS Latch
RD TRISB
RD PORTB
QD
CK
TTL
Input Buffer
LCDEN
Data Bus
WR PORTB
WR TRISB
P
VDD
I/O Pin
VDD
Weak
Pull-up
LCDEN
RBPU(1)
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
D
Q
EN
LCDEN
Q1
2004 Microchip Technology Inc. Preliminary DS41250A-page 59
PIC16F91X
4.3.3.6 RB5/COM1
Figure 4-11 shows the diagram for this pin. The RB5
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD
FIGURE 4-11: BLOCK DIAGRAM OF RB5
From other
Set RBIF
RB<7:4> pins RD PORTB
Q3
Q1
COM1
QD
CK
Data Latch
TRIS Latch
RD TRISB
RD PORTB
QD
CK
D
Q
EN
TTL
Input Buffer
Data Bus
WR PORTB
WR TRISB
P
VDD
I/O Pin
VDD
Weak
Pull-up
LCDEN and LMUX<1:0> ≠ 00
RBPU(1)
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and cl ear the RBPU bit.
D
Q
EN
LCDEN and LMUX<1:0> ≠ 00
LCDEN and LMUX<1:0> ≠ 00
LCDEN and LMUX<1:0> ≠ 00
PIC16F91X
DS41250A-page 60 Preliminary 2004 Microchip Technology Inc.
4.3.3.7 RB6/ICSPCLK/ICDCK/SEG14
Figure 4-12 shows the diagram for this pin. The RB6
pin is configurable to function as one of the following:
• a general purpose I/O
• an In-Circuit Serial Programming™ clock
• an ICD clock I/ O
• an analog output for the LCD
FIGURE 4-12: BLOCK DIAGRAM OF RB6
From other
Set RBIF
RB<7:4> pins Q1
RD PORTB
Program Mode/I C D
PGC
QD
CK
Data Latch
TRIS Latch
RD TRISB
RD PORTB
QD
CK
D
Q
EN
TTL
Input Buffer
SE14 and LCDEN
Data Bus
WR PORTB
WR TRISB
P
VDD
I/O Pin
VDD
Weak
Pull-up
SE14 and LCDEN
RBPU(1)
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
D
Q
EN
Prog ram Mode/ICD
SEG14
Schmitt
Trigger Buffer
SE14 and LCDEN
SE14 and LCDEN
2004 Microchip Technology Inc. Preliminary DS41250A-page 61
PIC16F91X
4.3.3.8 RB7/ICSPDAT/ICDDAT/SEG13
Figure 4-13 shows the diagram for this pin. The RB7
pin is configurable to function as one of the following:
• a general purpose I/O
• an In-Circuit Serial Programming™ I/O
• an ICD data I/O
• an analog output for the LCD
FIGURE 4-13: BLOCK DIAGRAM OF RB7
From other
Set RBIF
RB<7:4> pins Q1
RD PORTB
PGD
QD
CK
Data Latch
TRIS Latch
RD TRISB
RD PORTB
QD
CK
D
Q
EN
TTL
Input Buffer
SE13 and LCDEN
Data Bus
WR PORTB
WR TRISB
P
VDD
I/O Pin
VDD
Weak
Pull-up
SE13 and LCDEN
RBPU(1)
Note 1: To enable weak pull-ups, se t the appropriate TRIS bit(s) and clear the RBPU bit.
D
Q
EN
PORT/Program Mode/ICD
SEG13
Schmitt
Trigger Buffer
SE13 and LCDEN
1
0
0
1
PGD DRVEN
PGD
SE13 and LCDEN
Program Mode/ICD
PIC16F91X
DS41250A-page 62 Preliminary 2004 Microchip Technology Inc.
TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
V alue on all
other
Resets
06h/106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h/186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
0Bh/8Bh/
10Bh/18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
95h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111
96h IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- 0000 ----
107h LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011
11Ch LCDSE0(1) SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 uuuu uuuu
11Dh LCDSE1(1) SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.
Note 1: This register is only initialized by a POR or BOR reset and is unchanged by other resets.
2004 Microchip Technology Inc. Preliminary DS41250A-page 63
PIC16F91X
4.4 PORTC and TRISC Registers
PORTC is an 8-bit bidirectional port. PORTC is
multiplexed with several peripheral functions. PORTC
pins have Schmitt T rigger input buffers.
All PORTC pins have latch bits (PORTC register).
They, when written, will modify the contents of the
PORTC latch; thus, modifying the value driven out on
a pin if the corresponding TRISC bit is configured for
output.
EXAMPLE 4- 3: INITIALIZI NG PORTC
REGISTER 4-7: PORTC – PORTC REGISTER (ADDRESS: 07h)
REGISTER 4-8: TRISC – PORTC TRI-STATE REGISTER (ADDRESS: 87h)
Note: Analog lines that carry LCD signals
(i.e., SEGx, VLCDy, where x and y are
segmen t an d LC D b ias v oltage identi fier s)
are shown as direct connections to the
device pins. The signals are outputs from
the LCD module and may be tri-stated,
dependi ng on the config uration of th e LCD
module.
BCF STATUS,RP0 ;Bank 0
BCF STATUS,RP1 ;
CLRF PORTC ;Init PORTC
BSF STATUS,RP0 ;Bank 1
BCF STATUS,RP1 ;
MOVLW FFh ;Set RC<7:0> as inputs
MOVWF TRISC ;
BCF STATUS,RP0 ;Bank 2
BSF STATUS,RP1 ;
CLRF LCDCON ;Disable VLCD<3:1>
;inputs on RC<2:0>
BCF STATUS,RP0 ;Bank 0
BCF STATUS,RP1 ;
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
bit 7 bit 0
bit 7-0 RC<7:0>: PORTC I/O Pin bits
1 = Port pin is >VIH
0 = Port pin is <VIL
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
bit 7 bit 0
bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits
1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin config ured as an output
Note: TRISC<7:6> always read s ‘1’ in XT, HS and LP OSC mo des.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F91X
DS41250A-page 64 Preliminary 2004 Microchip Technology Inc.
4.4.1 PIN DESCRIPTIONS AND
DIAGRAMS
Each PORTC pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the LCD or SSP, refer to the appropriate section
in this data sheet.
4.4.1.1 RC0/VLCD1
Figure 4-14 shows the diagram for this pin. The RC0
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the LCD bias voltage
4.4.1.2 RC1/VLCD2
Figure 4-15 shows the diagram for this pin. The RC1
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the LCD bias voltage
4.4.1.3 RC2/VLCD3
Figure 4-16 shows the diagram for this pin. The RC2
pin is configurable to function as one of the following:
• a general purpo se I/O
• an analog input for the LCD bias voltage
FIGURE 4-14: BLOCK DIAGRAM OF RC0
QD
EN
RD PORTC
VLCD1
RC0 Pin
Schmitt
Trigger
VDD
QD
CK
Data Latch
TRIS Latch
RD TRISC
Data Bus
WR PORTC
WR TRISC
QD
CK
Q
Q
(VLCDEN and LMUX<1:0> ≠ 00)
(VLCDEN and LMUX<1:0> ≠ 00)
2004 Microchip Technology Inc. Preliminary DS41250A-page 65
PIC16F91X
FIGURE 4-15: BLOCK DIAGRAM OF RC1
FIGURE 4-16: BLOCK DIAGRAM OF RC2
QD
EN
RD PORTC
VLCD2
RC1 Pin
Schmitt
Trigger
VDD
QD
CK
Data Latch
TRIS Latch
RD TRISC
Data Bus
WR PORTC
WR TRISC
QD
CK
Q
Q
(VLCDEN and LMUX<1:0> ≠ 00)
(VLCDEN and LMUX<1:0> ≠ 00)
QD
EN
RD PORTC
VLCD3
RC2 Pin
Schmitt
Trigger
VDD
QD
CK
Data Latch
TRIS Latch
RD TRISC
Data Bus
WR PORTC
WR TRISC
QD
CK
Q
Q
VLCDEN
VLCDEN
PIC16F91X
DS41250A-page 66 Preliminary 2004 Microchip Technology Inc.
4.4.1.4 RC3/SEG6
Figure 4-17 shows the diagram for this pin. The RC3
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD
FIGURE 4-17: BLOCK DIAGRAM OF RC3
QD
EN
RD PORTC
SEG6 and LCDEN
RC3 Pin
Schmitt
Trigger
VDD
QD
CK
Data Latch
TRIS Latch
RD TRISC
Data Bus
WR PORTC
WR TRISC
QD
CK
Q
Q
SE6 and LCDEN
SE6 and LCDEN
2004 Microchip Technology Inc. Preliminary DS41250A-page 67
PIC16F91X
4.4.1.5 RC4/T1G/SDO/SEG11
Figure 4-18 shows the diagram for this pin. The RC4
pin is configurable to function as one of the following:
• a general purpose I/O
• a TMR1 gate input
• a serial data output
• an analog output for the LCD
FIGURE 4-18: BLOCK DIAGRAM OF RC4
SDO
PORT/SDO Select
RD PORTC
D
Q
EN
Data Bus
WR PORTC
WR TRISC
RC4 Pin
RD TRISC
1
0
QD
Q
CK
Data Latch
VSS
VDD
QD
Q
CK
TRIS Latch
Schmitt
Trigger
SE11 and LCDEN
Ti me r1 Gate
SEG11 SE11 and LCDEN
PIC16F91X
DS41250A-page 68 Preliminary 2004 Microchip Technology Inc.
4.4.1.6 RC5/T1CKI/CCP1/SEG10
Figure 4-19 shows the diagram for this pin. The RC5
pin is configurable to function as one of the following:
• a general purpose I/O
•a TMR1 clock input
• a Capture input, Compare output or PWM output
• an analog output for the LCD
FIGURE 4-19: BLOCK DIAGRAM OF RC5
CCP1 Data Out
(PORT/CCP1 Select) and CCPMX
RD PORTC
D
Q
EN
Data Bus
WR PORTC
WR TRISC
RC5 Pin
RD TRISC
1
0
QD
Q
CK
Data Latch
VSS
VDD
QD
Q
CK
TRIS Latch
Schmitt
Trigger
SE10 and LCDEN
Timer1 Gate
SEG10 SE10 and LCDEN
2004 Microchip Technology Inc. Preliminary DS41250A-page 69
PIC16F91X
4.4.1.7 RC6/TX/CK/SCK/SCL/SEG9
Figure 4-20 shows the diagram for this pin. The RC6
pin is configurable to function as one of the following:
• a general purpose I/O
• an asynchronous serial output
• a synchronous clock I/O
• a SPI clock I/O
•an I
2C data I/O
• an analog output for the LCD
FIGURE 4-20: BLOCK DIAGRAM OF RC6
TX/CK Data Out
I2C™ Data Out
RD PORTC
D
Q
EN
Data Bus
WR PORTC
WR TRISC
RC6 Pin
RD TRISC
3
1
QD
Q
CK
Data Latch
VSS
VDD
QD
Q
CK
TRIS Latch
Schmitt
Trigger
SE9 and LCDEN
CK/SCL/SCK Input
SEG9 SE9 and LCDEN
0
PORT/SCEN/SSP Mode Select(1)
SCEN or I2C D r ive
Note 1: If all three data output sources are enabled, the following priority order will be used:
• USART dat a
• SSP data
•PORT data
2
SCK Data Out
PIC16F91X
DS41250A-page 70 Preliminary 2004 Microchip Technology Inc.
4.4.1.8 RC7/RX/DT/SDI/SDA/SEG8
Figure 4-21 shows the diagram for this pin. The RC7
pin is configurable to function as one of the following:
• a general purpose I/O
• an asynchronous serial input
• a synchronous serial data I/O
• a SPI data I/O
•an I
2C data I/O
• an analog output for the LCD
FIGURE 4-21: BLOCK DIAGRAM OF RC7
Data Bus
WR PORTC
WR TRISC
QD
EN
RD PORTC
RX/SDI Input
SEG8
0
1
I2C Data Out
Schmitt
Trigger
RC7 Pin
VDD
Data Latch
TRIS Latch
Q
D
Q
CK
Q
D
Q
CK
I2C Drive
SE8 and LCDEN
RD TRISC
PORT/(SCEN or I2C) Select
SCEN/I2C™ Mode Select(1)
DT Data Out
1
0
or SCEN Drive
SE8 and LCDEN
Note 1: If SSP and USAR T ou tput s are bo th enab led, th e USART dat a outpu t will ha ve prio rity over th e
SSP data output. Both SSP and USART data outputs will have priority over the PORT data
output.
2004 Microchip Technology Inc. Preliminary DS41250A-page 71
PIC16F91X
TABLE 4-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
V alue on all
other
Resets
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
10h T1CON T1GINV T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
107h LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011
11Ch LCDSE0(1) SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 uuuu uuuu
11Dh LCDSE1(1) SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not us ed by PORTC.
Note 1: This register is only initialized by a POR or BOR reset and is unchanged by other resets.
PIC16F91X
DS41250A-page 72 Preliminary 2004 Microchip Technology Inc.
4.5 PORTD and TRISD Registers
PORTD is an 8-bit port with Schmitt Trigger input buffers.
Each pin is ind ividual ly c onfigured as an input or output.
PORTD is only available on the PIC16F914 and
PIC16F917.
EXAMPLE 4- 4: INITIALIZI NG PORTD
REGISTER 4-9: PORTD – PORTD REGISTER (ADDRESS: 08h)
REGISTER 4-10: TRISD – PORTD TRI-STATE REGISTER (ADDRESS: 88h)
Note: Analog lines that carry LCD signals
(i.e., SEGx , COMy , whe re x and y are seg-
ment and common identifiers) are shown
as direct connections to the device pins.
The signals are outputs from the LCD
module and may be tri-stated, depending
on the configuration of the LCD module.
BCF STATUS,RP0 ;Bank 0
BCF STATUS,RP1 ;
CLRF PORTD ;Init PORTD
BSF STATUS,RP0 ;Bank 1
BCF STATUS,RP1 ;
MOVLW FFh ;Set RD<7:0> as inputs
MOVWF TRISD ;
BCF STATUS,RP0 ;Bank 0
BCF STATUS,RP1 ;
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
bit 7 bit 0
bit 7-0 RD<7:0>: PORTD I/O Pin bits
1 = Port pin is >VIH
0 = Port pin is <VIL
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
bit 7 bit 0
bit 7-0 TRISD<7:0>: PORTD Tri-State Control bits
1 = PORTD pin configured as an input (tri-stated)
0 = PORTD pin configured as an output
Note: TRISD<7:6> always reads ‘1’ in XT, HS and LP OSC modes.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Preliminary DS41250A-page 73
PIC16F91X
4.5.1 PIN DESCRIPTIONS AND
DIAGRAMS
Each PORTD pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the comparator or the A/D, refer to the
appropriate section in this data sheet.
4.5.1.1 RD0/COM3
Figure 4-22 shows the diagram for this pin. The RD0
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the A/D
4.5.1.2 RD1
Figure 4-23 shows the diagram for this pin. The RD1
pin is configurable to function as one of the following:
• a general purpose I/O
4.5.1.3 RD2/CCP2
Figure 4-24 shows the diagram for this pin. The RD2
pin is configurable to function as one of the following:
• a general purpose I/O
• a Capture input, Compare output or PWM output
4.5.1.4 RD3/SEG16
Figure 4-25 shows the diagram for this pin. The RD3
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD
4.5.1.5 RD4/SEG17
Figure 4-25 shows the diagram for this pin. The RD4
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD
4.5.1.6 RD5/SEG18
Figure 4-25 shows the diagram for this pin. The RD5
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD
4.5.1.7 RD6/SEG19
Figure 4-25 shows the diagram for this pin. The RD6
pin is configurable to function as one of the following:
• a general purpo se I/O
• an analog output for the LCD
4.5.1.8 RD7/SEG20
Figure 4-25 shows the diagram for this pin. The RD7
pin is configurable to function as one of the following:
• a general purpo se I/O
• an analog output for the LCD
PIC16F91X
DS41250A-page 74 Preliminary 2004 Microchip Technology Inc.
FIGURE 4-22: BLOCK DIAGRAM OF RD0
FIGURE 4-23: BLOCK DIAGRAM OF RD1
Data Bus
WR PORTD
WR TRISD
QD
EN
RD PORTD
COM3
Schmitt
Trigger
RD0 Pin
VDD
Data Latch
TRIS Latch
Q
D
Q
CK
Q
D
Q
CK
LCDEN and LMUX<1:0> = 11
RD TRISD
LCDEN and
LMUX<1:0> = 11
Data Bus
WR PORTD
WR TRISD
QD
EN
RD PORTD
Schmitt
Trigger
RD1 Pin
VDD
Data Latch
TRIS Latch
Q
D
Q
CK
Q
D
Q
CK
RD TRISD
2004 Microchip Technology Inc. Preliminary DS41250A-page 75
PIC16F91X
FIGURE 4-24: BLOCK DIAGRAM OF RD2
FIGURE 4-25: BLOCK DIAGRAM OF RD<7:3>
Data Bus
WR PORTD
WR TRISD
QD
EN
RD PORTD
CCP2 Input
0
1
(PORT/CCP2 Select) and CCPMX
CCP2 Data Out
Schmitt
Trigger
RD2 Pin
VDD
Data Latch
TRIS Latch
Q
D
Q
CK
Q
D
Q
CK
RD T R I S D
Data Bus
WR PORTD
WR TRISD
QD
EN
RD PORTD
SEG<20:16>
RD<7:3> Pin
VDD
Data Latch
TRIS Latch
Q
D
Q
CK
Q
D
Q
CK
SE<20:16> and LCDEN
RD T R I S D Schmitt
Trigger
SE<20:16> and LCDEN
PIC16F91X
DS41250A-page 76 Preliminary 2004 Microchip Technology Inc.
TABLE 4-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
V alue on all
other
Resets
08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
1Dh(2) CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
88h TRISD(2) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111
107h LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011
11Eh LCDSE2(1,2) SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 0000 0000 uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.
Note 1: This register is only initialized by a POR or BOR reset and is unchanged by other resets.
2: PIC16F914/917 only.
2004 Microchip Technology Inc. Preliminary DS41250A-page 77
PIC16F91X
4.6 PORTE and TRISE Registers
PORT E is a 4-bit port with Schmitt T rigger input buf fers.
RE<2:0> are individually configured as inputs or out-
puts. RE3 is only available as an input if MCLRE is ‘0’
in Confi g uration Word (Register 16-1) .
RE<2:0> are only available on the PIC16F914 and
PIC16F917.
EXAMPLE 4- 5: INITIALIZI NG PORTE
REGISTER 4-11: PORTE – PORTE REGISTER (ADDRESS: 09h)
REGISTER 4-12: TRISE – PORTE TRI-STATE REGISTER (ADDRESS: 89h)
Note: Analog lines that carry LCD signals
(i.e., SEGx, where x are segment identifi-
ers) are shown as direct connections to
the device pins. The signals are outputs
from the LCD module and may be
tri-stated, depending on the configuration
of the LCD module.
BCF STATUS,RP0 ;Bank 0
BCF STATUS,RP1 ;
CLRF PORTE ;Init PORTE
BSF STATUS,RP0 ;Bank 1
BCF STATUS,RP1 ;
MOVLW 0Fh ;Set RE<3:0> as inputs
MOVWF TRISE ;
CLRF ANSEL ;Make RE<2:0> as I/O’s
BCF STATUS,RP0 ;Bank 0
BCF STATUS,RP1 ;
U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x
———— RE3 RE2 RE1 RE0
bit 7 bit 0
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 RE<3:0>: PORTE I/O Pin bits
1 = Port pin is >VIH
0 = Port pin is <VIL
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
U-0 U-0 U-0 U-0 R-1 R/W-1 R/W-1 R/W-1
———— TRISE3 TRISE2 TRISE1 TRISE0
bit 7 bit 0
bit 7-4 Unimplemented: Read as ‘0’
bit 3 TRISE3: Data Direction bit. RE3 is always an input, so this bit always reads as a ‘1’
bit 2-0 TRISE<2:0>: Data Direction bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F91X
DS41250A-page 78 Preliminary 2004 Microchip Technology Inc.
4.6.1 PIN DESCRIPTIONS AND
DIAGRAMS
Each PORTE pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the comparator or the A/D, refer to the
appropriate section in this data sheet.
4.6.1.1 RE0/AN5/SEG21
Figure 4-26 shows the diagram for this pin. The RE0
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the A/D
• an analog output for the LCD
4.6.1.2 RE1/AN6/SEG22
Figure 4-26 shows the diagram for this pin. The RE1
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the A/D
• an analog output for the LCD
4.6.1.3 RE2/AN7/SEG23
Figure 4-26 shows the diagram for this pin. The RE2
pin is configurable to function as one of the following:
• a general purpo se I/O
• an analog input for the A/D
• an analog output for the LCD
4.6.1.4 RE3/MCLR/VPP
Figure 4-27 shows the diagram for this pin. The RE3
pin is configurable to function as one of the following:
• a digital input only
• as Master C lear Reset with weak pull-up
• a programming voltage reference input
FIGURE 4-26: BLOCK DIAGRAM OF RE<2:0>
Data Bus
WR PORTE
WR TRISE
QD
EN
RD PORTE
SEG<23:21>
Schmitt
Trigger
RE<2:0> Pin
VDD
Data Latch
TRIS Latch
Q
D
Q
CK
Q
D
Q
CK
Analog Mode or
RD TRISE
AN<7:5>
SE<23:21> an d LCDEN
SE<23:21> an d LCDEN
2004 Microchip Technology Inc. Preliminary DS41250A-page 79
PIC16F91X
FIGURE 4-27: BLOCK DIAGRAM OF RE3/MCLR/VPP
TABLE 4-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on all
other
Resets
09h PORTE — — — — RE3 RE2 RE1 RE0 ---- xxxx ---- uuuu
1Fh ADCON0 ADFM VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000
89h TRISE — — — —TRISE3
(3) TRISE2(2) TRISE1(2) TRISE0(2) ---- 1111 ---- 1111
91h ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
107h LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011
11Eh LCDSE2(1,2) SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 0000 0000 uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not us ed by PORTC.
Note 1: This register is only initialized by a POR or BOR reset and is unchanged by other resets.
2: PIC16F914/917 only.
3: Bit is read only; TRISE = 1 always.
DQ
EN
HV Detect
MCLR Filter(1)
RE3/MCLR/VPP
RE Po r t
MCLR cir cuit
Programm ing mode
Data Bus
RE TRIS
MCLRE
Note 1: The MCLR filter is bypassed in Emulatio n mode.
HV
Buffer
Schmitt Trigger
HV
Buffer
Schmitt Trigger
PIC16F91X
DS41250A-page 80 Preliminary 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Preliminary DS41250A-page 81
PIC16F91X
5.0 TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 5-1 is a bloc k diagram o f the T imer0 mod ule and
the prescaler shared with the WDT.
5.1 Timer0 Operat ion
Timer mode is selected by clearing the T0CS bit
(OPTION_REG<5>). In Timer mode, the Timer0
module will increment every instruction cycle (without
prescal er). If TMR0 is written , the incre ment is inhibite d
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 registe r.
Counter mode is selected by setting the T0CS bit
(OPTION_REG<5>). In this mode, the Timer0 module
will increment either on every rising or falling edge of pin
RA4/C1OUT/T0CKI/SEG4. The incrementing edge is
determined by the source edge (T0SE) control bit
(OPTION_REG<4>). Clearing the T0SE bit selects the
rising edge.
5.2 Timer0 Interrupt
A Timer0 interrupt is generated when the TMR0
register timer/counter overflows from FFh to 00h. This
overflow sets the T0IF bit (INTCON<2>). The interrupt
can be masked by cl eari ng the T0IE bit (INTCO N<5 >).
The T0IF bit must be cleared in softwa re by the T i mer0
module Interrupt Service Routine before re-enabling
this interrupt. The Timer0 interrupt cannot wake the
proce ssor from Sle ep, since the timer i s s hu t off during
Sleep.
FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Note: Additional information on the Timer0
module is available in the “PICmicro®
Mid-Range MCU Family Reference
Manual” (DS33023).
Note: Counter mode has specific external clock
requirements. Additional information on
these requirements is available in the
“PICmicro® Mid-Range MCU Family
Refere nce M anual” (DS33023).
T0CKI
T0SE
pin
CLKO
TMR0
Watchdog
Timer
WDT
Time-out
PS<2:0>
WDTE
Data Bus
Set Flag bit T0IF
on Overflow
T0CS
Note 1: T0SE, T0CS, PSA and PS<2:0> are bits in the Option register; WDTPS<3:0> are bits in the WDTCON register.
0
1
0
1
0
1
SYNC 2
Cycles
8
8
8-bit
Prescaler
0
1
(= FOSC/4)
PSA
PSA
PSA
16-bit
Prescaler 16
WDTPS<3:0>
31 kHz
INTOSC
SWDTEN
PIC16F91X
DS41250A-page 82 Preliminary 2004 Microchip Technology Inc.
5.3 Using Tim er0 with an External
Clock
When no prescaler is used, the external clock input is the
same as the prescaler output. The synchronization of
T0CKI, with the internal phase clocks, is accomplished by
sampling the prescaler output on the Q2 and Q4 cycles of
the internal phase clocks. Therefore, it is necessary for
T0CKI to be high for at least 2 T OSC (and a small RC delay
of 20 ns) and low for at least 2 T OSC (and a small RC delay
of 20 ns). Refer to the electrical specification of the
desired device.
REGISTER 5-1: OPTION_REG – OPTION REGISTER (ADDRESS: 81h OR 181h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU: PORT B Pull-up Enable bit
1 = PORTB pull-ups are d isabled
0 = PORTB pull-ups are enabled by individual port latch values in WPUA register
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT/SEG0 pin
0 = Interrupt on falling edge of RB0/INT/SEG0 pin
bit 5 T0CS: TMR0 Clock Sourc e Sele ct bit
1 = Transition on RA4/C1OUT/T0CKI/SEG4I pin
0 = Internal instruction cycle clock (CLKO)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/C1OUT/T0CKI/SEG4 pin
0 = Increment on low-to-high transition on RA4/C1OUT/T0CKI/SEG4 pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Presca ler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Note 1: A dedicated 16-bit WDT postscaler is available for the PIC16F91X. See
Section 16.6 “Watchdog Timer (WDT)” for more information.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate(1)
2004 Microchip Technology Inc. Preliminary DS41250A-page 83
PIC16F91X
5.4 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. For simplicity, this counter will be referred to as
“prescaler” throughout this data sheet. The prescaler
assignment is controlled in software by the control bit
PSA (OPTION_REG<3>). Clearing the PSA bit will
assign the prescaler to Timer0. Prescale values are
selectable via the PS<2:0> bits (OPTION_REG<2:0>).
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions w riting
to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1, x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer.
5.4.1 SW ITCHIN G PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software control
(i.e., it can be changed “on-the-fly” during program
execution). To avoid an unintended device Reset, the
following instruction sequence (Example 5-1 and
Example 5-2) must be executed when changing the
prescaler assignment from Timer0 to WDT.
EXAMPLE 5-1: CHANGING PRESCALER
(TIMER0 →WDT)
To change prescaler from the WDT to the TMR0
module , use the se quence sh own in Exa mple 5-2. This
preca ution mus t be tak en even if the WDT is dis abled.
EXAMPLE 5-2: CHANGING PRESCALER
(WDT →TIMER0)
TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0
BCF STATUS,RP0 ;Bank 0
CLRWDT ;Clear WDT
CLRF TMR0 ;Clear TMR0 and
; prescaler
BSF STATUS,RP0 ;Bank 1
MOVLW b’00101111’ ;Required if desired
MOVWF OPTION_REG ; PS2:PS0 is
CLRWDT ; 000 or 001
;
MOVLW b’00101xxx’ ;Set postscaler to
MOVWF OPTION_REG ; desired WDT rate
BCF STATUS,RP0 ;Bank 0
CLRWDT ;Clear WDT and
; prescaler
BSF STATUS,RP0 ;Bank 1
MOVLW b’xxxx0xxx’ ;Select TMR0,
; prescale, and
; clock source
MOVWF OPTION_REG ;
BCF STATUS,RP0 ;Bank 0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
01h TMR0 T i mer0 Module register xxxx xxxx uuuu uuuu
0Bh/10Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
81h OPTION_REG RBPUINTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
Legend: - = Unimplemented locations, read as ‘ 0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.
PIC16F91X
DS41250A-page 84 Preliminary 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Preliminary DS41250A-page 85
PIC16F91X
6.0 TIMER1 MODULE WITH GATE
CONTROL
The PIC16F91X has a 16-bit timer. Figure 6-1 shows
the basic block diagram of the Timer1 module. Timer1
has the follow i ng feat ures :
• 16-bit timer/counter (TMR1H:TMR1L)
• Readable and writable
• Internal or external clock selection
• Synchronous or asynchronous operation
• Interrupt-on-overflow from FFFFh to 0000h
• Wake-up upon overflow (Asynchronous mode)
• Optional external enable input
- Selectable gate source: T1G or C2 output
(T1GSS)
- Selectable gate polarity (T1GINV)
• Op tional LP oscil lator
The Timer1 Control register (T1CON), shown in
Register 6-1, is used to enable/disable Timer1 and
select the various features of the Timer1 module.
FIGURE 6-1: TIMER1 ON THE PIC16F91X BLOCK DIAGRAM
Note: Additional information on timer modules is
available in the “PICmicro® Mid-Range MCU
Family Reference Manual” (DS33023).
TMR1H TMR1L
LP OSC
T1SYNC
T1CKPS<1:0> Sleep Input
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
Clock Input
2
OSC1/T1OSI
OSC2/T1OSO
Set Flag bit
TMR1IF on
Overflow TMR1(1)
TMR1ON
T1GE
TMR1ON
T1GE
FOSC = 000
T1OSCEN
FOSC = x00 1
0
C2OUT
T1GSS
T1GINV
To C2 Comparator Module
TMR1 Clock
Note 1: Timer1 increments on the rising edge.
2: ST Buffer is low-power type when using LP oscillator or high-speed type when using T1CKI.
RC4/T1G/
1
0
RC5/T1CKI/
T1CS
(2)
Clear on special
event trigger
SDO/SEG11
CCP1/SEG10
PIC16F91X
DS41250A-page 86 Preliminary 2004 Microchip Technology Inc.
6.1 Timer1 Modes of Operation
Timer1 can operate in one of three modes:
• 16-bit timer with prescaler
• 16-bit synchronous counter
• 16-bit asynchronous counter
In Timer mode, Timer1 is incremented on every
instruction cycle. In Counter mode, Timer1 is incremented
on the rising edge of the external clock input T1CKI. In
addition, the Counter mode clock can be synchronized to
the microcontroller system clock or run asynchronously.
In th e Ti mer1 modu le, the m odule cl ock can b e gated
by the T imer1 g ate, whi ch can be select ed as ei ther the
T1G pin or Comparator 2 output.
If an external clock oscillator is needed (and the
microcontroller is using the INTOSC without CLKO),
Timer1 can use the LP oscillator as a clock source.
6.2 Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 Interrupt Flag bit (PIR1<0>) is se t. To
enable the interrupt on rollo ver , you m ust set th ese bits :
• Timer1 Interrupt Enable bit (PIE1<0>)
• PEIE bit (INTCON<6>)
• GIE bit (INTCON<7>)
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
6.3 Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits
(T1CON<5:4>) control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write
to TMR1H or TMR1L.
6.4 Timer1 Gate
Timer1 gate source is software configurable to be the
T1G pin or th e ou tput of C omparator 2. This all ow s the
device to directly time external events using T1G or
analog events using Comparator 2. See CMCON1
(Register 8-2) for selecting the Timer1 gate source.
This feature can simplify the software for a Delta-Sigma
A/D converter and many other applications. For more
information on Delta-Sigma A/D converters, see the
Microchip web site (www.microchip.com).
Timer1 gate can be inverted using the T1GINV bit
(T1CON< 7>), wh ether it origin ates from th e T1G pin or
Comparator 2 output. This configures Timer1 to
measure either the active-high or active-low time
between events.
FIGURE 6-2: TIMER1 INCREMENTING EDGE
Note: In Counter mode, a falling edge must be
registered by the counter prior to the first
incr em enti ng ris ing edge.
Note: The T MR1H:TTMR1L register p air and the
TMR1IF bit should be cleared before
enabling interrupts.
Note: T1GE bit (T1CON<6>) must be set to use
either T1G or C2OUT as the Timer1 gate
source. See Register 8-2 for more
information on selecting the Timer1 gate
source.
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be regi stered by the counter prior to the first incrementing
rising edge of the clock.
2004 Microchip Technology Inc. Preliminary DS41250A-page 87
PIC16F91X
REGISTER 6-1: T1CON – TIMER1 CONTROL REGISTER (ADDRESS: 10h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
T1GINV T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
bit 7 T1GINV: Timer1 Gate Invert bit(1)
1 = Timer1 gate is inverted
0 = Timer1 gate is not inverted
bit 6 T1GE: Timer1 Gate Enable bit(2)
If TMR1ON = 0:
This bit is ignored.
If TMR1ON = 1:
1 = Timer1 gate is enabled
0 = Timer1 gate is disabled
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale Value
10 = 1:4 Prescale Value
01 = 1:2 Prescale Value
00 = 1:1 Prescale Value
bit 3 T1OSCEN: LP Oscillator Enable Control bit
If INTOSC without CLKO oscilla tor is ac tiv e:
1 = LP oscillator is enabled for Timer1 clock
0 = LP oscillator is off
Else:
This bit is ignored.
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from RC5/T1CKI/CCP1/SEG10 pin or T1OSC (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Note 1: T1GINV bit inve rts the Timer1 gate logic, regardless of source.
2: T1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS
bit (CMCON1<1>), as a Timer1 gate source.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F91X
DS41250A-page 88 Preliminary 2004 Microchip Technology Inc.
6.5 Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during Sleep and can
generate an interrupt-on- overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 6.5.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
6.5.1 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TM R1L, while the timer is running
from an external asynchronous clock, will ensure a
valid read (taken care of in hardware). However, the
user shoul d keep i n mind that r eadi ng the 16-bit time r
in two 8-b it va lu es i t self, poses cert a in pro bl em s, s inc e
the timer may overflow between the reads.
For write s, it is re commend ed that the us er simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may pro duce an
unpredictable value in the timer registe r.
Reading the 16-bit value requires some care.
Examples in the “PICmicro® Mid-Range MCU Family
Referenc e Manual” (DS33023) show how to read and
write Time r1 when i t is ru nning in Asy nchron ous mod e.
6.6 TIMER1 OSCILLATOR
To minimize the multiplexing of peripherals on the I/O
ports, the dedicated TMR1 oscillator, which is normally
used for TMR1 real time clock applications, is eliminated.
Instead, the TMR1 module can enable the LP oscillator.
If the microcontroller is programmed to run from
INTOSC with no CLKO or LP oscillator:
1. Setting the T1OSCEN bit to ‘1’ will enable the
LP oscillator to clock TMR1 while the microcon-
troller is clocked from either the INTOSC or LP
oscillator. Note that the T1OSC and LP oscilla-
tors share the same circuitry. Therefore, when
LP os ci lla tor i s s el ec ted and T1O SC i s e nab le d,
both the microcontroller and the Timer1 module
share the same clock source.
2. Sleep mode does not shut off the LP oscillator
operation (i.e., if the INTOSC oscillator runs the
microcontroller, and T1OSCEN = 1 (TMR1 is
running from the LP oscillator), then the LP
oscillator will continue to run during Sleep mode.
In all oscillator modes except for INTOSC with no
CLKOUT and LP, the T1OSC enable option is unavail-
able and is ignored.
6.7 Resetting Time r1 Us ing a CCP
Trigger Output
If the CCP 1 or CCP2 mo dule is config ured in C ompa re
mode to generate a “special event trigger”
(CCP1M<3:0> = 1011), this signal will reset Timer1.
T imer 1 must be c onfigured fo r either T ime r or Synch ro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of operation, the CCPRxH:CCPRxL register
pair effectively becomes the period register for Timer1.
Note: The ANSEL (91h) and CMCON0 (9Ch)
register s must be ini tialized to conf igure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
Note: When INTOSC without CLKO oscillator is
selected and T1OSCEN = 1, the LP
oscillator will run continuously independent
of the TMR1ON bit.
Note: The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit, TMR1IF (PIR1<0 >).
2004 Microchip Technology Inc. Preliminary DS41250A-page 89
PIC16F91X
6.8 Resetting of Timer1 Register Pair
(TMR1H , TMR1 L)
TMR1H an d TMR1L reg isters are not rese t to 00h on a
POR, or any other Reset, except by the CCP1 and
CCP2 special event triggers.
T1CON register is reset to 00h on a Power-on Reset,
or a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other Resets, the register
is unaffected.
6.9 Timer1 Operat ion During Sleep
Timer1 can only operate during Sleep when setup in
Asynch ronous Counter mode. In this mode, an ext ernal
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
• Timer1 must be on (T1CON<0>)
• TMR1IE bit (PIE1<0>) must be set
• PEIE bit (INTCON<6>) must be set
The device will wake-up on an overflow. If the GIE bit
(INTCON<7>) is set, the device wil l wake -up an d jum p
to the Interrupt Service Rout ine (0004h) on an overflow .
If the GIE bit is clear, execution will continue with the
next instruction.
TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER1
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
0Bh/
8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Eh TMR1L Holding register for the Least Significant B yt e of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON T1GINV T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
1Ah CMCON1 — — — — — —T1GSSC2SYNC ---- --10 ---- --10
8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
PIC16F91X
DS41250A-page 90 Preliminary 2004 Microchip Technology Inc.
7.0 TIMER2 MODULE
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
• 8-bit perio d register (PR2)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match with PR2
Timer2 has a control register shown in Register 7-1.
TMR2 can be shut-off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Figure 7-1 is a simplified block diagram of the Timer2
module. The prescaler and postscaler selection of
Timer2 are controlled by this register.
7.1 Timer2 Operation
Timer2 can be used as the PWM time base for the
PWM mode of the CCP module. The TMR2 register is
readable and writable, and is cleared on any device
Reset. The i npu t clo ck (FOSC/4) has a prescale option
of 1:1, 1:4 or 1:16, selected by control bits T2CKPSx
(T2CON<1:0>). The match output of TMR2 goes
through a 4-bit postscaler (which gives a 1:1 to 1:16
scaling inclusive) to generate a TMR2 interrupt (latched
in flag bit TMR2IF, (PIR1<1>)).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• A write to the TMR2 register
• A write to the T2CON register
• Any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset, or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 7-1: T2CON – TIMER2 CONTROL REGISTER (ADDRESS: 12h)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6-3 TOUTPS<3:0>: Timer2 Output Postscale Select bits
0000 =1:1 Postscale
0001 =1:2 Postscale
•
•
•
1111 =1:16 Postscale
bit 2 TMR2ON: Timer2 On bit
1 =Timer2 is on
0 =Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Pr escale Select bits
00 =Prescaler is 1
01 =Prescaler is 4
1x =Prescaler is 16
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Preliminary DS41250A-page 91
PIC16F91X
7.2 Timer2 Interrupt
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
7.3 Timer2 Output
The output of TMR2 (before the post scaler) is fed to the
SSP module, which optionally uses it to generate the
shift clock.
FIGURE 7-1: TIMER2 BLOCK DIAGRAM
TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER2
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
0Bh/
8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
11h TMR2 Holding register for the 8-b i t TMR2 register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
92h PR2 Timer2 Period register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Ti mer2 module.
Comparator
TMR2 Sets F lag
TMR2
Output(1)
Reset
Postscaler
Prescaler
PR2
2
FOSC/4
1:1 to 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
TOUTPS<3:0>
T2CKPS<1:0>
Note 1: TMR2 regis ter ou tput c an be softwa re sel ected by the SSP mod ule as a b aud cloc k.
PIC16F91X
DS41250A-page 92 Preliminary 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Preliminary DS41250A-page 93
PIC16F91X
8.0 COMPARATOR MODULE
The comparator module contains two analog
comparators. The inputs to the comparators are
multiplexed with I/O port pins RA<3:0>, while the outputs
are multiplexed to pins RA<5:4>. An on-chip Comparator
Voltage Reference (CVREF) can also be applied to the
inputs of the comparators.
The CMCON0 register (Register 8-1) controls the
comparator input and output multiplexers. A block
diagram of the various comparator configurations is
shown in Figure 8-3.
REGISTER 8-1: CMCON0 – COMPARA TOR CONFIGURA TION REGISTER (ADDRESS: 9Ch)
R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0
bit 7 bit 0
bit 7 C2OUT: Comparator 2 Output bit
When C2INV = 0;
1 =C2 V
IN+ > C2 VIN-
0 =C2 V
IN+ < C2 VIN-
When C2INV = 1;
0 =C2 V
IN+ > C2 VIN-
1 =C2 V
IN+ < C2 VIN-
bit 6 C1OUT: Comparator 1 Output bit
When C1INV = 0;
1 =C1 V
IN+ > C1 VIN-
0 =C1 V
IN+ < C1 VIN-
When C1INV = 1;
0 =C1 V
IN+ > C1 VIN-
1 =C1 V
IN+ < C1 VIN-
bit 5 C2INV: Comparator 2 Output Inversion bit
1 = C2 Output in verted
0 = C2 Output no t inverted
bit 4 C1INV: Comparator 1 Output Inversion bit
1 = C1 Output in verted
0 = C1 Output no t inverted
bit 3 CIS: Comparator Input Switch bit
When CM<2:0> = 010:
1 =C1 V
IN- connects to RA3/AN3/C1+/VREF+/SEG15
C2 VIN- connects to RA2/AN2/C2+/VREF-/COM2
0 =C1 V
IN- connects to RA0/AN0/C1-/SEG12
C2 VIN- connects to RA1/AN1/C2-/SEG7
When CM<2:0> = 001:
1 =C1 V
IN- connects to RA3/AN3/C1+/VREF+/SEG15
0 =C1 V
IN- connects to RA0/AN0/C1-/SEG12
bit 2-0 CM<2:0>: Comparator Mode bits(1)
See Figure 8-3 for comparator modes and CM<2:0> bit settings.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry,
weak pull ups, and interrupt-on-change if available. The corresponding TRIS bit
must be se t to Input mode in order to allow external control of the volt age on the pin.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F91X
DS41250A-page 94 Preliminary 2004 Microchip Technology Inc.
8.1 Compara tor Operat ion
A single comparator is shown in Figure 8-1 along with
the relationship between the analog input levels and
the digit al ou tput. When the an alog input a t VIN+ is less
than the analog input VIN-, the output of the comp arator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 8-1 represent
the uncertainty due to input offsets and response time.
The polarity of the comparator output can be inverted
by setting the CxINV bits (CMCON0<5:4>). Clearing
CxINV results in a non-inverted output. A complete
table showing the output state versus input conditions
and the polarity bit is shown in Table 8-1.
TABLE 8-1: OUTPUT STATE VS. INPUT
CONDITIONS
FIGURE 8-1: SINGLE COMPARATOR
8.2 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 8-2. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. Th e analog input, th erefore, must be betw een
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum source impedance of 10 kΩ is recommended
for the analog sources. Any external component
conne cted to an anal og in put pin , suc h as a capaci tor
or a Zener diode, should have very little leakage.
FIGURE 8-2: ANALOG INPUT MODEL
Note: To use CIN+ and CIN- pins as analog
inputs, the appropriate bits must be
programmed in the CMCON0 (9Ch)
register.
Input Conditions CINV CxOUT
VIN- > VIN+00
VIN- < VIN+01
VIN- > VIN+11
VIN- < VIN+10
V
IN–
V
IN+
O
utput
–
+
VIN+
VIN-Output
Output
VIN+
VIN-
VA
Rs < 10K
AIN CPIN
5 pF
VDD
VT = 0.6V
VT = 0.6V
RIC
Leakage
±500 nA
Vss
Legend: CPIN= Input Capacitance
VT= Threshold Voltage
ILEAKAGE= Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS= Source Impedance
VA = Analog Voltage
2004 Microchip Technology Inc. Preliminary DS41250A-page 95
PIC16F91X
8.3 Comparator Configuration
There are eight modes of operation for the comparators.
The CMCON0 register is used to select these modes.
Figure 8-3 shows the eight possible modes.
If the Comparator mode is changed, the comparator
output level may not be valid for the specified mode
change delay shown in Section 19.0 “Electrical
Specifications”.
FIGURE 8-3: COMPARATOR I/O OPERATING MODES
Note: Compara tor in terr upts sh ould be dis abled
during a Comparator mode change.
Otherwise, a false interrupt may occur.
C1
RA0/AN0/ VIN-
VIN+
RA3/AN3/ Off (Read as ‘0’)
Comparators Reset (POR Default Value)
A
A
CM<2:0> = 000
C2
RA1/AN1/ VIN-
VIN+
RA2/AN2/ Off (Read as ‘0’)
A
A
C1
VIN-
VIN+C1OUT
Two Independent Comparators
A
A
CM<2:0> = 100
C2
VIN-
VIN+C2OUT
A
A
C1
VIN-
VIN+C1OUT
Two Common Reference Comparators
A
D
CM<2:0> = 011
C2
VIN-
VIN+C2OUT
A
A
C1
VIN-
VIN+Off (Read as ‘0’)
One Independent Comparator
D
D
CM<2:0> = 101
C2
VIN-
VIN+C2OUT
A
A
C1
VIN-
VIN+Off (Read as ‘0’)
Comparators Off
D
D
CM<2:0> = 111
C2
VIN-
VIN+Off (Read as ‘0’)
D
D
C1
VIN-
VIN+C1OUT
Four Inputs Multiplexed to Two Comparators
A
A
CM<2:0> = 010
C2
VIN-
VIN+C2OUT
A
A
From CVREF Module
CIS = 0
CIS = 1
CIS = 0
CIS = 1
C1
VIN-
VIN+C1OUT
Two C ommon Reference Co mparators with Outputs
A
CM<2:0> = 110
C2
VIN-
VIN+C2OUT
A
A
A = Analog Input, port reads ze ros always. D = Digital Input. CIS (CMCON0<3>) i s the Comparator In put Swi tch
.
C1
VIN-
VIN+C1OUT
Three Inputs Multiplexed to Two Comparators
A
A
CM<2:0> = 001
C2
VIN-
VIN+C2OUT
A
A
CIS = 0
CIS = 1
Legend:
RA4
RA5
RA5
C1-/SEG12
C1+/VREF+/SEG15
RA0/AN0/
C1-/SEG12
RA3/AN3/
C1+/VREF+/SEG15
C2-/SEG7
C2+/VREF-/COM2
RA1/AN1/
C2-/SEG7
RA2/AN2/
C2+/VREF-/COM2
RA0/AN0/
C1-/SEG12
RA3/AN3/
C1+/VREF+/SEG15
RA1/AN1/
C2-/SEG7
RA2/AN2/
C2+/VREF-/COM2
RA0/AN0/
C1-/SEG12
RA3/AN3/
C1+/VREF+/SEG15
RA1/AN1/
C2-/SEG7
RA2/AN2/
C2+/VREF-/COM2
RA0/AN0/
C1-/SEG12
RA1/AN1/
C2-/SEG7
RA2/AN2/
C2+/VREF-/COM2
RA0/AN0/
C1-/SEG12
RA3/AN3/
C1+/VREF+/SEG15
RA1/AN1/
C2-/SEG7
RA2/AN2/
C2+/VREF-/COM2
RA0/AN0/
C1-/SEG12
RA3/AN3/
C1+/VREF+/SEG15
RA1/AN1/
C2-/SEG7
RA2/AN2/
C2+/VREF-/COM2 RA2/AN2/
C2+/VREF-/COM2
RA1/AN1/
C2-/SEG7
RA3/AN3/
C1+/VREF+/SEG15
RA0/AN0/
C1-/SEG12
PIC16F91X
DS41250A-page 96 Preliminary 2004 Microchip Technology Inc.
FIGURE 8-4: MODIFIED COMPARATOR C1 OUTPUT BLOCK DIAGRAM
FIGURE 8-5: COMPARATOR C2 OUTPUT BLOCK DIAGRAM
DQ
EN
To C1OUT pin
RD CMCON
Set C1IF bit
MULTIPLEX
DQ
EN
CL
Port Pins
NReset
To D a ta Bu s
C1INV
RD CMCON
C2SYNC
DQ
EN
To C2OUT pin
RD CMCON
Set C2IF bit
MULTIPLEX
DQ
EN
CL
Port Pins
RD CMCON
Reset
To D a ta Bu s
C2INV
DQ
EN TMR1
clock source(1)
0
1
To TMR1
Note 1: Comparator 2 output is latched on falling edge of T1 clock source.
2004 Microchip Technology Inc. Preliminary DS41250A-page 97
PIC16F91X
REGISTER 8-2: CMCON1 – COMP ARATOR CONFIGURATION REGISTER (ADDRESS: 97h)
8.4 Comparator Outputs
The comparator outputs are read through the
CMCON0 register. These bits are read-only. The
comparator outputs may also be directly output to the
RA4 and RA5 I/O pins. When enabled, multiplexers in
the output path of the RA4 and RA5 pins will switch
and the output of each pin will be the unsynchronized
output of the comparator. The uncertainty of each of
the comparators is related to the input offset voltage
and the response time given in the specifications.
Figure 8-4 and Figure 8-5 show the output block
diagram for Comparator 1 and 2.
The TRIS bits will still function as an output
enable/disable for the RA4 and RA5 pins while in this
mode.
The polarity of the comparator outputs can be changed
using the C1INV and C2INV bits (CMCON0<5:4>).
Timer1 gate source can be configured to use the T1G
pin or Comparator 2 output as selected by the T1GSS
bit (CMCON1<1>). This feature can be used to time
the duration or interval of analog events. The output of
Comparator 2 can also be synchronized with Timer1
by setting the C2SYNC bit (CMCON1<0>). When
enabled, the output of Comparator 2 is lat ched on the
falling edge of Timer1 clock source. If a prescaler is
used with Timer1, Comparator 2 is latched after the
prescaler . To prevent a race condition, the C omparator
2 output is latched on the falling edge of the Timer1
clock source and T imer1 increments on the rising edge
of its clock source. See (Figure 8-5), Comparator 2
Block Diagram and (Figure 6-1), Timer1 Block
Diagram for more information.
It is recommended to synchronize Comparator 2 with
Timer1 by setting the C2SYNC bit when Comparator 2
is used as the Timer1 gate source. This ensures Timer1
does not miss an increment if Comparator 2 changes
during an inc rement.
8.5 Comparator Interrupt s
The comparator interrupt flags are set whenever there is
a change in the output value of its respective comparator .
Software will need to maintain information about the
sta tus of the output bi ts, a s read from CMCON0< 7:6>, t o
determine the act ual change that has occurred. The CxIF
bits , PIR2<6:5 >, ar e the Comp arat or Inte rrupt fl ags. Th is
bit must be reset in software by clearing it to ‘0’. Si nc e it
is al so po ssi bl e t o w rit e a ‘1’ to this register, a simulated
interrupt may be initiated.
The CxIE bits (PIE2<6:5>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupts. In
addition, the GIE bit must also be set. If any of these
bits are cleared, th e interrupt is n ot enabled, th ough the
CxIF bit s will still be se t if an interru pt condi tion occ urs.
The use r , in the Interru pt Service Routi ne, can clear th e
interr upt in the foll owin g man ner:
a) Any read or write of CMCON0. This will end the
mismatch condition.
b) Clear flag bit CxIF
A mismatch condition will continue to set flag bit CxIF.
Readi ng CMCON0 will end the mis match condi tion and
allow flag bits CxIF to be cleared.
U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0
—————— T1GSS C2SYNC
bit 7 bit 0
bit 7-2: Unimplemented: Read as ‘0’
bit 1 T1GSS: Timer1 Gate Source Select bit
1 = Timer1 gate source is T1G pin (RC4 must be configured as digital input)
0 = Timer1 gate source is Comparator 2 Output
bit 0 C2SYNC: Comparator 2 Synchronize bit
1 = C2 output synchronized with falling edge of Timer1 clock
0 = C2 output not synchronized with Timer1 clock
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: If a change in the CMCON0 register
(CxOUT) should occur when a read
operatio n is being executed (start of the Q2
cycle), th en the CxIF (PI R2<6:5>) interru pt
flag may not get set.
PIC16F91X
DS41250A-page 98 Preliminary 2004 Microchip Technology Inc.
8.6 Comparator Reference
The com parator m od ule al so allows the se lec tio n of an
internally generated voltage reference for one of the
comparator inputs. The VRCON register, Register 8-3,
controls the voltage reference module shown in
Figure 8-6.
8.6.1 CONFIGURING THE VOLTAGE
REFERENCE
The voltage reference can output 32 distinct voltage
levels; 16 in a high range and 16 in a low range.
The follow ing equati on determines the output volt ages:
EQUATION 8-1:
8.6.2 VOLTAGE REFERENCE
ACCURACY/ERROR
The ful l range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on th e
top and bottom of the resistor ladder network
(Figure 8-6) keep CVREF from approaching VSS or
VDD. The exception is when the module is disabled by
clearin g the VREN b it (VRCON<7> ). When disa bled,
the reference voltage is VSS when VR<3:0> = 0000.
This allows the comparators to detect a zero-crossing
and not con sume CVREF module current.
The volt age reference is VDD derived and theref ore, the
CVREF output changes with fluctuations in VDD. The
tested absolute accuracy of the comparator voltage
reference can be found in Section 19.0 “Electrical
Specifications”.
FIGURE 8-6: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VRR = 1 (low range): CVREF = (VR3:VR0/24) x VDD
VRR = 0 (high range):
CVREF = (VDD/4) + (VR3:VR0 x VDD/32)
VRR
8R
VR<3:0>
16-1 Analog
8RRR RR
CVREF to
16 Stages
Comparator
Input
VREN
VDD
MUX
2004 Microchip Technology Inc. Preliminary DS41250A-page 99
PIC16F91X
8.7 Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output is ensured to have a valid level. If
the internal reference is changed, the maximum delay
of the internal voltage reference must be considered
when using the comparator outputs. Otherwise, the
maximum delay of the comparators should be used
(Table 19-10).
8.8 Operation During Sleep
The comparators and voltage reference, if enabled
before entering Sleep mode, remain active during
Sleep. Thi s results in highe r Sleep currents than shown
in the power-down specifications. The additional
current consumed by the comparator and the voltage
reference is shown separately in the specifications. To
minim ize power consum ption whil e in Sleep mode, tu rn
off the comparator, CM<2:0> = 111, and voltage
reference, VRCON<7> = 0.
While the comparator is enabled during Sleep, an
interrupt will wake-up the device. If the GIE bit
(INTCON<7>) is set, the device will jump to the inter-
rupt vector (0004h), and if clear, continues execution
with the next instruction. If the device wakes up from
Sleep, the contents of the CMCON0, CMCON1 and
VRCON registers are not affected.
8.9 Effects of a Reset
A device Reset forces the CMCON0, CMCON1 and
VRCON registers to their Reset states. This forces the
comparator module to be in the Comparator Reset
mode, CM< 2:0> = 000 and the voltage reference to its
off state. Thus, all potential inputs are analog inputs
with the comparator and voltage reference disabled to
consume the smallest current possible.
PIC16F91X
DS41250A-page 100 Preliminary 2004 Microchip Technology Inc.
REGISTER 8-3: VRCON – VOL TAGE REFERENCE CONTROL REGISTER (ADDRESS: 9Dh)
TABLE 8-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
VREN —VRR— VR3 VR2 VR1 VR0
bit 7 bit 0
bit 7 VREN: CVREF Enable bit
1 = CVREF circuit powered on
0 = CVREF circuit powered down, no IDD drain and CVREF = VSS.
bit 6 Unimplemented: Read as ‘0’
bit 5 VRR: CVREF Range Selection bit
1 = Low range
0 = High range
bit 4 Unimplemented: Read as ‘0’
bit 3-0 VR<3:0>: CVREF value selection 0 ≤ VR<3:0> ≤ 15
When VRR = 1: CVREF = (VR<3:0>/24) * VDD
When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
0Bh/8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Dh PIR2 OSFIF C2IF C1IF LCDIF —LVDIF —CCP2IF 0000 -0-0 0000 -0-0
9Ch CMCON0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000
1Ah CMCON1 —————— T1GSS C2SYNC ---- --10 ---- --10
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
8Dh PIE2 OSFIE C2IE C1IE LCDIE —LVDIE—CCP2IE 0000 -0-0 0000 -0-0
99h VRCON VREN —VRR— VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the comparator or Comparator Voltage
Refere nce mo dule .
2004 Microchip Technology Inc. Preliminary DS41250A-page 101
PIC16F91X
9.0 LIQUID CRYSTAL DISPLAY
(LCD) DRIVER MODULE
The Liquid Crystal Display (LCD) driver module generates
the timing control to drive a static or multiplexed LCD
panel. In the P IC16F914/917 devices (PI C16F914/917) ,
the module drives the panels of up to four commons and
up to 24 segments and in the PIC16F913/916 devices
(PIC16F913 /916), the module drives t he panels of up to
four commons and up to 16 segments. It also provides
control of the LCD pixel data.
The LCD driver module supports:
• Direc t driving of LCD panel
• Three LCD clock sources with selecta ble prescaler
• Up to four commons :
- Static
- 1/2 multiplex
- 1/3 multiplex
- 1/4 multiplex
• Up to 24 (in PIC16F914/917 devices)/16 (in
PIC16F913/916 devices) segments
• Static, 1/2 or 1/3 LCD Bias
The module has 32 registers:
• LCD Control Register (LCDCON)
• LCD Phase Register (LCDPS)
• Three LCD Segment Enable Registers
(LCDSE<2:0>)
• 24 LCD Data Registers (LCDDATA<11:0>)
The LCDCON register, shown in Register 9-1, controls
the operation of the LCD driver module. The LCDPS
register, shown in Register 9-2, configures the LCD
clock source prescaler and the type of waveform;
T ype-A or T ype-B. The LCDSE<2:0> registers c onfigure
the functions of the port pins:
• LCDSE0 SE<7:0>
• LCDSE1 SE<15:8>
• LCDSE2 SE<23:16>
As an example, LCDSEn is detailed in Register 9-3.
Once the module is initialized for the LCD panel, the
individual bits of the LCDDATA<11:0> registers are
cleared/set to represent a clear/dark pixel,
respectively:
• LCDDATA0 SEG7COM 0:SEG0COM0
• LCDDATA1 SEG15COM0:SEG8COM0
• LCDDATA2 SEG23COM0:SEG16COM0
• LCDDATA3 SEG7COM 1:SEG0COM1
• LCDDATA4 SEG15COM1:SEG8COM1
• LCDDATA5 SEG23COM1:SEG16COM1
• LCDDATA6 SEG7COM 2:SEG0COM2
• LCDDATA7 SEG15COM2:SEG8COM2
• LCDDATA8 SEG23COM2:SEG16COM2
• LCDDATA9 SEG7COM 3:SEG0COM3
• LCDDATA10 SEG15COM3:SEG8COM3
• LCDDATA11 SEG23COM3:SEG 16COM3
As an example, LCDDATAx is detailed in Register 9-4 .
Once the module is configured, the LCDEN
(LCDCON <7>) bit is used to enable or dis able the LCD
module . The LC D p an el c an als o op erate during Sleep
by clearing the SLPEN (LCDCON<6>) bit.
Note: The LCDSE2 register is not implemented
in PIC16F913/916 devices.
Note: Writing into the registers LCDDATA2,
LCDDATA5, LCDDATA8 and LCDDATA11
in PIC16F913/916 devices will not affect the
status of any pixel and these registers can
be used as General Purpose Registers.
PIC16F91X
DS41250A-page 102 Preliminary 2004 Microchip Technology Inc.
FIGURE 9-1: LCD DRIVER MODULE BLOCK DIAGRAM
COM<3:0>
Clock Source
Timing Cont rol
Data Bus
Select and
Prescaler
LFINTOSC/32
FOSC/8192
T10CKI/32
96
to
24
MUX
SEG<23:0>
To I/O Pads(1)
To I/O Pads(1)
LCDCON
LCDPS
LCDSEn
12 x 8
(= 4 x 24)
LCDDATAx
Registers
Note 1: These are not directly connected to the I/O pads. See Section 4.0 “I/O Ports ” for more de tail.
2004 Microchip Technology Inc. Preliminary DS41250A-page 103
PIC16F91X
REGISTER 9-1: LCDCON – LIQUID CRYSTAL DISPLAY CONTROL REGISTER (ADDRESS: 107h)
R/W-0 R/W-0 R/C-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1
LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0
bit 7 bit 0
bit 7 LCDEN: LCD Driv er Enable bit
1 = LCD driver module is enabled
0 = LCD driver module is disabled
bit 6 SLPEN: LCD Driver Enable in Sleep mode bit
1 = LCD driver module is disabled in Sleep mode
0 = LCD driver module is enabled in Sleep mode
bit 5 WERR: LCD Write Failed Error bit
1 = LCDDATAx register written while LCDPS<WA> = 0 (must be cleared in software)
0 = No LCD write error
bit 4 VLCDEN: LCD Bias Voltage Pins Enable bit
1 = VLCD pins are enabled
0 = VLCD pins are disabled
bit 3-2 CS<1:0>: Clock Sourc e Select bits
00 = FOSC/8192
01 = T13CKI (Timer1)/32
1x = INTOSC (31.25 kHz)/32
bit 1-0 LMUX<1:0>: Comm ons Select bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
C = Only clearable bit ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
LMUX<1:0> Multiplex Maximum Number
of Pixels
(PIC16F913/916)
Maximum Number
of Pixels
(PIC16F914/917) Bias
00 Static (COM0) 16 48 Static
01 1/2 (COM <1: 0>) 32 96 1/2 or 1/3
10 1/3 (COM <2: 0>) 48 144 1/2 or 1/3
11 1/4 (COM<3: 0>) 60(1) 192 1/3
Note 1: On PIC16F913/916 devic es , CO M 3 a nd SEG1 5 a r e s ha red on one pin, limiting the
device from driving 64 pixels.
PIC16F91X
DS41250A-page 104 Preliminary 2004 Microchip Technology Inc.
REGISTER 9-2: LCDPS – LCD PRESCALER SELECT REGISTER (ADDRESS: 108h)
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
WFT BIASMD LCDA WA LP3 LP2 LP1 LP0
bit 7 bit 0
bit 7 WFT: Waveform Type Select bit
1 = Type-B waveform (phase changes on each frame boundary)
0 = Type-A waveform (phase changes within each common type)
bit 6 BIASMD: Bias Mode Select bit
When LMUX<1:0> = 00:
0 = Static Bias mode (do not set this bit to ‘1’)
When LMUX<1:0> = 01:
1 = 1/2 Bias mode
0 = 1/3 Bias mode
When LMUX<1:0> = 10:
1 = 1/2 Bias mode
0 = 1/3 Bias mode
When LMUX<1:0> = 11:
0 = 1/3 Bias mode (do not set this bit to ‘1’)
bit 5 LCDA: LCD Active Status bit
1 = LCD driver module is active
0 = LCD driver module is inactive
bit 4 WA: LCD Write Allo w Status bit
1 = Write into the LCDDATAx registers is allo wed
0 = Wri te into the LCDDATAx registers is not allowed
bit 3-0 LP<3:0>: LCD Prescaler Select bits
1111 = 1:16
1110 = 1:15
1101 = 1:14
1100 = 1:13
1011 = 1:12
1010 = 1:11
1001 = 1:10
1000 = 1:9
0111 = 1:8
0110 = 1:7
0101 = 1:6
0100 = 1:5
0011 = 1:4
0010 = 1:3
0001 = 1:2
0000 = 1:1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Preliminary DS41250A-page 105
PIC16F91X
REGISTER 9-3: LCDSEn – LCD SEGMENT REGISTERS (ADDRESS: 11Ch, 11Dh, OR 11Eh)
REGISTER 9-4: LCDDAT Ax – LCD DATA REGISTERS (ADDRESS: 110h-119h, 11Ah, 11Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEn SEn SEn SEn SEn SEn SEn SEn
bit 7 bit 0
bit 7-0 SEn: Segment Enable bits
1 = Segment function of the pin is enabled
0 = I/O function of the pin is enabled
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEGx-
COMy SEGx-
COMy SEGx-
COMy SEGx-
COMy SEGx-
COMy SEGx-
COMy SEGx-
COMy SEGx-
COMy
bit 7 bit 0
bit 7-0 SEGx-COMy: Pixel On bits
1 = Pixel on ( dark)
0 = Pixel off (clear)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F91X
DS41250A-page 106 Preliminary 2004 Microchip Technology Inc.
9.1 LCD Clock Source Selection
The LCD driver module has 3 possible clock sources:
•F
OSC/8192
• T13CKI-Clock/32
• INTOSC/32
The first clock source is the system clock divided by
8192 (FOSC/8192). This divider ratio is chosen to
provide about 1 kHz output when the system clock is
8 MHz. The divider is not programmable. Instead, the
LCD prescaler bits, LCDPS<3:0>, are used to set the
LCD frame clock rate.
The second clock source is the Timer1 oscillator/32.
This also gives about 1 kHz when a 32.768 kHz crystal
is used with the Timer1 oscillator. To use the Timer1
oscillator as a clock source, the T1OSCEN
(T1CON< 3>) bit sh oul d be set.
The third clock source is a 31.25 kHz internal RC
oscillator/32 (LFINTOSC), which provides app roximately
1 kHz output.
The second and third clock sources may be used to
continue running the LCD while the processor is in
Sleep.
Using the bits, CS<1:0> (LCDCON<3:2>), any of these
clock sources can be selected.
9.1.1 LCD PRESCALER
A 16-bit counter is available as a prescaler for the LCD
cloc k. The p rescal er is n ot di rectly readab le or w ritable;
its value is set by the LP<3 :0> bit s (LC DPS<3:0>), which
determ in e the prescal er as si gn m en t a nd pr es ca le ratio.
The prescale values from 1:1 through 1:16.
9.2 LCD Bias Types
The LCD driver module can be configured into three
bias types:
• Static Bias (2 voltage levels: VSS and VDD)
• 1/2 Bias (3 voltage levels: VSS, 1/2 VDD and VDD)
• 1/3 Bias (4 voltage levels: VSS, 1/3 VDD, 2/3 VDD
and VDD)
This module uses an external resistor ladder to
generate the L CD bias voltages.
The exte rnal resistor ladder shoul d be connect ed to the
Bias 1 pin, Bias 2 pin, Bias 3 pin and VSS. The Bias 3
pin should also be connected to VDD.
Figure 9-2 shows the proper way to connect the
resistor ladder to the Bias pins.
FIGURE 9-2: LCD BIAS RESISTOR LADDER CONNECTION DIAGRAM
Note: VLCD pins used to supply LCD bias
voltage are enabled on power-up (POR)
and must be disabled by the user by
clearing LCDCON<4>, the VLCDEN bit,
(see Register 9-1).
VLCD 3
VLCD 2
VLCD 1
VLCD 0(1)
To
LCD
Driver
Connections for External R-ladder
10 kΩ*10 kΩ*10 kΩ*
LCD Bias 2 L CD Bias 1
LCD Bias 3
* These values are provided for design guidance only and should be optimized for the application by the
designer.
Note 1: Internal connection.
VSS
Static
Bias 1/2 Bias 1/3 Bias
VLCD 0VSS VSS VSS
VLCD 1 —1/2 VDD 1/3 V DD
VLCD 2 —1/2 VDD 2/3 V DD
VLCD 3VDD VDD VDD
10 kΩ*10kΩ*VSS
VDD*
VDD*
VDD*
Static Bias
1/2 Bias
1/3 Bias
2004 Microchip Technology Inc. Preliminary DS41250A-page 107
PIC16F91X
9.3 LCD Multiplex Types
The LCD driver module can be configured into four
multiplex types:
• Static (only COM0 used)
• 1/2 multiplex (COM0 and COM1 are used)
• 1/3 multiplex (COM0, COM1 and COM2 are used)
• 1/4 multiplex (all COM0, COM1, COM2 and COM3
are used)
The LMUX<1:0> setting decides the function of RB5,
RA2 or either RA3 or RD0 pins (see Table 9-1 for
details).
If the pin is a digital I/O, the corresponding TRIS bit
controls the data direction. If the pin is a COM drive,
then the TRIS setting of that pin is overridden.
TABLE 9-1: PORTC<2:0> FUNCTION
9.4 Segment Enables
The LCDSEn registers are used to select the pin
function for each segment pin. The selection allows
each pin to operate as either an LCD segment driver or
as one of the pin’ s alte rnate fun ction s. To configure the
pin as a segment pin, the corresponding bits in the
LCDSEn registers must be set to ‘1’.
If the pin is a digital I/O, the corresponding TRIS bit
controls the data direction. Any bit set in the LCDSEn
registers overrides any bit settings in the corresponding
TRIS register.
9.5 Pixel Control
The LCDDATAx registers contain bits which define the
state of each pixel. Each bit defines one unique pixel.
Register 9-4 shows the correlation of each bit in the
LCDDATAx registers to the respective common and
segment signals.
Any L CD pix el lo catio n not b eing used f or dis play can
be used as general purpose RAM.
9.6 LCD Frame Frequency
The rat e at which the CO M and SEG out puts c hange is
called the LCD frame frequency.
TABLE 9-2: FRAME FREQUENCY
FORMULAS
TABLE 9-3: APPROXIMATE FRAME
FREQUENCY (IN Hz) USING
FOSC @ 8 MHz, TIMER1 @
32.768 kHz OR INTOSC
Note: On a Power-on Reset, the LMUX<1:0>
bits are ‘11’.
LMUX
<1:0> RA3/RD0(1) RA2 RB5
00 Digit al I/O Digital I/O Digital I/O
01 Digital I/O Digital I/O COM1 Driver
10 Digital I/O COM2 Driver COM1 Driver
11 COM3 Driver COM2 Driver COM1 Driver
Note 1: RA3 for PIC16F913/916, RD0 for
PIC16F914/917
Note: On a Power-on Reset, these pins are
configured as digital I/O.
Multiplex Frame Fr equency =
Stat ic Clock source/(4 x 1 x (LP<3:0> + 1))
1/2 Clock source/(2 x 2 x (LP<3:0> + 1))
1/3 Clock source/(1 x 3 x (LP<3:0> + 1))
1/4 Clock source/(1 x 4 x (LP<3:0> + 1))
Note: Clock source is FOSC/8192, T1OSC/32 or
LFINTOSC/32.
LP<3:0> Static 1/2 1/3 1/4
2 85 85 114 85
364648564
451516851
543435743
637374937
732324332
PIC16F91X
DS41250A-page 108 Preliminary 2004 Microchip Technology Inc.
FIGURE 9-3: LCD CLOCK GENERATION
CS<1:0>
T1OSC 32 kHz
Crystal Osc.
LFINTOSC
Nom FRC = 31.25 kHz
STAT
DUP
TRIP
QUAD
÷4
LMUX<1:0>
4-bit Prog Presc ÷1, 2, 3, 4
Ring Counter
LMUX<1:0>
COM0
COM1
COM2
COM3
÷8192
FOSC
÷2
÷32
÷32 LP<3:0>
(LCDCON<3:2>) (LCDCON<1:0>)
(LCDCON<1:0>)
(LCDPS<3:0>)
2004 Microchip Technology Inc. Preliminary DS41250A-page 109
PIC16F91X
FIGURE 9-4: LCD SEGMENT MAPPING WORKSHEET
LCD
Function COM0 COM1 COM2 COM3 Pin No. PORT Alternate
Functions
LCDDATAx
Address LCD
Segment LCDDATAx
Address LCD
Segment LCDDATAx
Address LCD
Segment LCDDATAx
Address LCD
Segment 28/40-pin
SEG0 LCDDATA0, 0 LCDDATA3, 0 LCDDATA6, 0 LCDDATA9, 0 21/33 RB0 INT
SEG1 LCDDATA0, 1 LCDDATA3, 1 LCDDATA6, 1 LCDDATA9, 1 22/34 RB1
SEG2 LCDDATA0, 2 LCDDATA3, 2 LCDDATA6, 2 LCDDATA9, 2 23/35 RB2
SEG3 LCDDATA0, 3 LCDDATA3, 3 LCDDATA6, 3 LCDDATA9, 3 24/36 RB3
SEG4 LCDDATA0, 4 LCDDATA3, 4 LCDDATA6, 4 LCDDATA9, 4 6/6 RA4 C1OUT/T0CKI
SEG5 LCDDATA0, 5 LCDDATA3, 5 LCDDATA6, 5 LCDDATA9, 5 7/7 RA5 C2OUT/AN4/SS
SEG6 LCDDATA0, 6 LCDDATA3, 6 LCDDATA6, 6 LCDDATA9, 6 14/18 RC3
SEG7 LCDDATA0, 7 LCDDATA3, 7 LCDDATA6, 7 LCDDATA9, 7 3/3 RA1 AN1
SEG8 LCDDATA1, 0 LCDDATA4, 0 LCDDATA7, 0 LCDDATA10, 0 18/26 RC7 RX/DT/SDI/SDA
SEG9 LCDDATA1, 1 LCDDATA4, 1 LCDDATA7, 1 LCDDATA10, 1 17/25 RC6 TX/CK/SCK/SCL
SEG10 LCDDATA1, 2 LCDDATA4, 2 LCDDATA7, 2 LCDDA TA10, 2 16/24 RC5 T1CKI/CCP1
SEG11 LCDDATA1, 3 LCDDATA4, 3 LCDDATA7, 3 LCDDATA10, 3 15/23 RC4 T1G/SDO
SEG12 LCDDATA1, 4 LCDDATA4, 4 LCDDATA7, 4 LCDDATA10, 4 2/2 RA0 AN0
SEG13 LCDDATA1, 5 LCDDATA4, 5 LCDDATA7, 5 LCDDATA10, 5 28/40 RB7 ICSPDAT/ICDDAT
SEG14 LCDDATA1, 6 LCDDATA4, 6 LCDDATA7, 6 LCDDATA10, 6 27/39 RB6 ICSPCK/ICDCK
SEG15 LCDDATA1, 7 LCDDATA4, 7 LCDDATA7, 7 LCDDATA10, 7 5/5 RA3 AN3/VREF+
SEG16 LCDDATA2, 0 LCDDATA5, 0 LCDDATA8, 0 LCDDATA11, 0 -/26 RD3
SEG17 LCDDATA2, 1 LCDDATA5, 1 LCDDATA8, 1 LCDDATA11, 1 -/27 RD4
SEG18 LCDDATA2, 2 LCDDATA5, 2 LCDDATA8, 2 LCDDATA11, 2 -/28 RD5
SEG19 LCDDATA2, 3 LCDDATA5, 3 LCDDATA8, 3 LCDDATA11, 3 -/29 RD6
SEG20 LCDDATA2, 4 LCDDATA5, 4 LCDDATA8, 4 LCDDATA11, 4 -/30 RD7
SEG21 LCDDATA2, 5 LCDDATA5, 5 LCDDATA8, 5 LCDDATA11, 5 -/8 RE0 AN5
SEG22 LCDDATA2, 6 LCDDATA5, 6 LCDDATA8, 6 LCDDATA11, 6 -/9 RE1 AN6
SEG23 LCDDATA2, 7 LCDDATA5, 7 LCDDATA8, 7 LCDDATA11, 7 -/10 RE2 AN7
PIC16F914/917 only.
PIC16F91X
DS41250A-page 110 Preliminary 2004 Microchip Technology Inc.
9.7 LCD Waveform Generation
LCD waveforms are generated so that the net AC
volt age across the d ark p ixe l sh ould b e max imized an d
the net AC voltage across the clear pixel should be
minim ized. The n et DC vo ltage a cross any pixel sh ould
be zero.
The COM signal represents the time slice for each
common, while the SEG contains the pixel data.
The pixel signal (COM-SEG) will have no DC compo-
nent and it can take only one of the two rms values. The
higher rms value will create a dark pixel and a lower
rms value will create a clear pixel.
As the number of commons increases, the delta
between the two rms values decreases. The delta
represents the maximum contrast that the display can
have.
The LCDs can be driven by two types of waveform:
Type-A and Type-B. In Type-A waveform, the phase
changes within ea ch common ty pe, wherea s in Type-B
waveform, the phase changes on each frame
boundary. Thus, Type-A waveform maintains 0 VDC
over a single frame, whereas Type-B waveform takes
two frames.
Figure 9-5 through Figure 9-15 provide waveforms for
static, half-multiplex, one-third-multiplex and
quarter-multiplex drives for Type-A and Type-B
waveforms.
FIGURE 9-5: TYPE-A/TYPE-B WAVEFORMS IN ST ATIC DRIVE
Note 1: If Sleep has to be executed with LCD
Sleep enabled (LCDCON<SLPEN> is
‘1’), then care must be taken to execute
Sleep only when VDC on all the pixels is
‘0’.
2: When the LCD clock s ource is FOSC/8192,
if Sleep is executed, irrespective of the
LCDCON<SLPEN> setting, the LCD goes
into Sleep. Thus, t ake care to see tha t VDC
on all pixels is ‘0’ when Sleep is executed .
V1
V0
COM0
SEG0
COM0-SEG0
COM0-SEG1
SEG1
V1
V0
V1
V0
V0
V1
-V1
V0
1 Frame
COM0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
2004 Microchip Technology Inc. Preliminary DS41250A-page 111
PIC16F91X
FIGURE 9-6: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
-V2
-V1
V2
V1
V0
-V2
-V1
COM0
COM1
SEG0
SEG1
COM0-SEG0
COM0-SEG1
1 Frame
COM1
COM0
SEG0
SEG1
SEG2
SEG3
PIC16F91X
DS41250A-page 112 Preliminary 2004 Microchip Technology Inc.
FIGURE 9-7: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
-V2
-V1
V2
V1
V0
-V2
-V1
COM0
COM1
SEG0
SEG1
COM0-SEG0
COM0-SEG1
COM1
COM0
SEG0
SEG1
SEG2
SEG3
2 Frames
2004 Microchip Technology Inc. Preliminary DS41250A-page 113
PIC16F91X
FIGURE 9-8: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
-V3
-V2
-V1
V3
V2
V1
V0
-V3
-V2
-V1
COM0
COM1
SEG0
SEG1
COM0-SEG0
COM0-SEG1
1 Frame
COM1
COM0
SEG0
SEG1
SEG2
SEG3
PIC16F91X
DS41250A-page 114 Preliminary 2004 Microchip Technology Inc.
FIGURE 9-9: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
-V3
-V2
-V1
V3
V2
V1
V0
-V3
-V2
-V1
COM0
COM1
SEG0
SEG1
COM0-SEG0
COM0-SEG1
COM1
COM0
SEG0
SEG1
SEG2
SEG3
2 Frames
2004 Microchip Technology Inc. Preliminary DS41250A-page 115
PIC16F91X
FIGURE 9-10: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
-V2
-V1
V2
V1
V0
-V2
-V1
COM0
COM1
COM2
SEG0
SEG1
COM0-SEG0
COM0-SEG1
1 Frame
COM2
COM1
COM0
SEG0
SEG1
SEG2
SEG2
PIC16F91X
DS41250A-page 116 Preliminary 2004 Microchip Technology Inc.
FIGURE 9-11: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
V2
V1
V0
-V2
-V1
V2
V1
V0
-V2
-V1
COM0
COM1
COM2
SEG0
SEG1
COM0-SEG0
COM0-SEG1
2 Frames
COM2
COM1
COM0
SEG0
SEG1
SEG2
2004 Microchip Technology Inc. Preliminary DS41250A-page 117
PIC16F91X
FIGURE 9-12: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
-V3
-V2
-V1
V3
V2
V1
V0
-V3
-V2
-V1
COM0
COM1
COM2
SEG0
SEG1
COM0-SEG0
COM0-SEG1
1 Frame
COM2
COM1
COM0
SEG0
SEG1
SEG2
SEG2
PIC16F91X
DS41250A-page 118 Preliminary 2004 Microchip Technology Inc.
FIGURE 9-13: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
-V3
-V2
-V1
V3
V2
V1
V0
-V3
-V2
-V1
COM0
COM1
COM2
SEG0
SEG1
COM0-SEG0
COM0-SEG1
2 Frames
COM2
COM1
COM0
SEG0
SEG1
SEG2
2004 Microchip Technology Inc. Preliminary DS41250A-page 119
PIC16F91X
FIGURE 9-14: TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
-V3
-V2
-V1
V3
V2
V1
V0
-V3
-V2
-V1
COM0
COM1
COM2
COM3
SEG0
SEG1
COM0-SEG0
COM0-SEG1
COM3
COM2
COM1
COM0
1 Frame
SEG0
SEG1
PIC16F91X
DS41250A-page 120 Preliminary 2004 Microchip Technology Inc.
FIGURE 9-15: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
-V3
-V2
-V1
V3
V2
V1
V0
-V3
-V2
-V1
COM0
COM1
COM2
COM3
SEG0
SEG1
COM0-SEG0
COM0-SEG1
COM3
COM2
COM1
COM0
2 Frames
SEG0
SEG1
2004 Microchip Technology Inc. Preliminary DS41250A-page 121
PIC16F91X
9.8 LCD Interrupts
The LCD timing generation provides an interrupt that
defines the LCD frame timing. This interrupt can be
used to co ord ina te the writing of the pi xe l data with the
start of a new frame. Writing pixel data at the frame
boundary allows a visual ly crisp transit ion of the image.
This in terrupt c an als o be us ed to s ynchroni ze externa l
event s to the LCD.
A new frame is defined to begin at the leading edge of
the COM0 common signal. The interrupt will be set
immediately after the LCD controller completes
accessing all pixel data required for a frame. This will
occur at a fixed interval before the frame boundary
(TFINT), as shown in Figure 9-16. The LCD controller
will begin to access data for the next frame within the
interval f r om th e i nte rrup t to when the con troll er be gin s
to access data after the interrupt (TFWR). New data
must be written within TFWR, as this is when the LCD
controller will begin to access the data for the next
frame.
When the LCD driver is running with Type-B waveforms
and the LMUX<1:0> bits are not equal to ‘00’, there are
some additional issues that must be addressed. Since
the DC voltage on th e pix el t a kes two fr ames t o mai nt ai n
zero volts, the pixel data must not change between
subsequent frames. If the pixel data were allowed to
change, the waveform for the odd frames would not
necessarily be the complement of the waveform
generated in the even frames and a DC component
would be introduced into the panel. Therefore, when
using Type- B wave form s, the user m ust sy nch roniz e the
LCD pixel updates to occur within a subframe after the
frame in ter rupt.
To correctly sequence writing while in Type-B, the
interrupt will only occur on complete phase intervals. If the
user attempts to write when the write is disabled, the
WERR (LCDCON<5>) bit is set.
FIGURE 9-16: WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY CYCLE DRIVE
(EXAMPLE – TYPE-B, NON-ST ATIC)
Note: The interrupt is not generated when the
T ype-A waveform is selected and when the
Type-B with no multiplex (static) is
selected.
Frame
Boundary Frame
Boundary
LCD
Interrupt
Occurs
Controller Accesses
Next Frame Data
TFINT
TFWR
TFWR =TFRAME/2*( LMUX<1:0> + 1) + TCY/2
TFINT =(TFWR/2 – (2 TCY + 40 ns)) →minimum = 1.5(TFRAME/4) – (2 TCY + 40 ns)
(TFWR/2 – (1 TCY + 40 ns)) →maximum = 1.5(TFRAME/4) – (1 TCY + 40 ns)
Frame
Boundary
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
COM0
COM1
COM2
COM3
2 Frames
PIC16F91X
DS41250A-page 122 Preliminary 2004 Microchip Technology Inc.
9.9 Operation During Sleep
The LC D modul e can o perate d uring Sl eep. Th e se lec-
tion is controlled by bit SLPEN (LCDCON<6>). Setting
the SLPEN bit allows the LCD module to go to Sleep.
Clearing the SLPEN bit allows the module to continue
to operate during Sleep.
If a SLEEP instruction is executed and SLPEN = 1, the
LCD module will cease all functions and go into a very
low current consumption mode. The module will stop
operation immediately and drive the minimum LCD
voltage on both segment and common lines.
Figure 9-17 shows this operation.
To ensure that no DC component is introduced on the
pane l, the SLEEP instruction sh ould be executed imme-
diately after a LCD frame boundary. The LCD interrupt
can be used to determine the frame boundary. See
Section 9.8 “LCD Interrupts” for the formulas to
calculate the delay.
If a SLEEP instruction is executed and SLPEN = 0, the
module will continue to display the current contents of
the LCDDATA registers. To allow the module to
continue operation while in Sleep, the clock source
must be either the LFINTOSC or T1OSC external
oscillator. While in Sleep, the LCD data cannot be
changed. The LCD module current consumption will
not decrease in this mode; however, the overall
consumption of the device will be lower due to shut
down of the core and other peripheral functions.
Table 9-4 shows the status of the LCD module during
a Sleep while using each of the three available clock
sources:
TABLE 9-4: LCD MODULE STATUS
DURING SLEEP
Clock Source SLPEN Operation
During Sleep?
T1OSC 0Yes
1No
LFINTOSC 0Yes
1No
FOSC/4 0No
1No
Note: The LFINTOSC or external T1OSC
oscillator must be used to operate the LCD
module during Sleep.
2004 Microchip Technology Inc. Preliminary DS41250A-page 123
PIC16F91X
FIGURE 9-17: SLEEP ENTRY/EXIT WHEN SLPEN = 1 OR CS<1:0> = 00
SLEEP Instruction Execution Wake-up
2 Frames
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
V3
V2
V1
V0
COM0
COM1
COM2
SEG0
PIC16F91X
DS41250A-page 124 Preliminary 2004 Microchip Technology Inc.
9.10 Configuring the LCD Module
The following is the sequ enc e of s teps to config ure th e
LCD mo dul e.
1. Select the frame clock prescale using bits
LP<3:0> (LCDPS<3:0>).
2. Configure the appropriate pins to function as
segment drivers using the LCDSEn registers.
3. Configure the LCD module for the following
using the LCDCON register:
-Multiplex and Bias mode, bits LMUX<1:0>
-Timing source, bits CS<1:0>
-Sleep mode, bit SLPEN
4. Write initial values to pixel data registers,
LCDDATA0 through LCDDATA11.
5. Clear LCD Inter rupt F lag, LCDIF (PIR2<4 >) and
if desired, enable the interrupt by setting bit
LCDIE (PIE2<4>).
6. Enable bias voltage pins (VLCD<3:1>) by
setting VLCDEN (LCDCO N<4>).
7. Enable the LCD module by setting bit LCDEN
(LCDCON<7>).
TABLE 9-5: REGISTERS ASSOCIATED WITH LCD OPERATION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
10h T1CON T1GINV T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
0Bh/8Bh/
10Bh/18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Dh PIR2 OSFIF C2IF C1IF LCDIF — LVDIF —CCP2IF 0000 -0-0 0000 -0-0
8Dh PIE2 OSFIE C2IE C1IE LCDIE —LVDIE —CCP2IE 0000 -0-0 0000 -0-0
107h LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011
108h LCDPS WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 0000 0000 0000 0000
110h LCDDATA0 SEG7
COM0 SEG6
COM0 SEG5
COM0 SEG4
COM0 SEG3
COM0 SEG2
COM0 SEG1
COM0 SEG0
COM0 xxxx xxxx uuuu uuuu
111h LCDDATA1 SEG15
COM0 SEG14
COM0 SEG13
COM0 SEG12
COM0 SEG11
COM0 SEG10
COM0 SEG9
COM0 SEG8
COM0 xxxx xxxx uuuu uuuu
112h LCDDATA2(2) SEG23
COM0 SEG22
COM0 SEG21
COM0 SEG20
COM0 SEG19
COM0 SEG18
COM0 SEG17
COM0 SEG16
COM0 xxxx xxxx uuuu uuuu
113h LCDDATA3 SEG7
COM1 SEG6
COM1 SEG5
COM1 SEG4
COM1 SEG3
COM1 SEG2
COM1 SEG1
COM1 SEG0
COM1 xxxx xxxx uuuu uuuu
114h LCDDATA4 SEG15
COM1 SEG14
COM1 SEG13
COM1 SEG12
COM1 SEG11
COM1 SEG10
COM1 SEG9
COM1 SEG8
COM1 xxxx xxxx uuuu uuuu
115h LCDDATA5(2) SEG23
COM1 SEG22
COM1 SEG21
COM1 SEG20
COM1 SEG19
COM1 SEG18
COM1 SEG17
COM1 SEG16
COM1 xxxx xxxx uuuu uuuu
116h LCDDATA6 SEG7
COM2 SEG6
COM2 SEG5
COM2 SEG4
COM2 SEG3
COM2 SEG2
COM2 SEG1
COM2 SEG0
COM2 xxxx xxxx uuuu uuuu
117h LCDDATA7 SEG15
COM2 SEG14
COM2 SEG13
COM2 SEG12
COM2 SEG11
COM2 SEG10
COM2 SEG9
COM2 SEG8
COM2 xxxx xxxx uuuu uuuu
118h LCDDATA8(2) SEG23
COM2 SEG22
COM2 SEG21
COM2 SEG20
COM2 SEG19
COM2 SEG18
COM2 SEG17
COM2 SEG16
COM2 xxxx xxxx uuuu uuuu
119h LCDDATA9 SEG7
COM3 SEG6
COM3 SEG5
COM3 SEG4
COM3 SEG3
COM3 SEG2
COM3 SEG1
COM3 SEG0
COM3 xxxx xxxx uuuu uuuu
11Ah LCDDATA10 SEG15
COM3 SEG14
COM3 SEG13
COM3 SEG12
COM3 SEG11
COM3 SEG10
COM3 SEG9
COM3 SEG8
COM3 xxxx xxxx uuuu uuuu
11Bh LCDDATA11(2) SEG23
COM3 SEG22
COM3 SEG21
COM3 SEG20
COM3 SEG19
COM3 SEG18
COM3 SEG17
COM3 SEG16
COM3 xxxx xxxx uuuu uuuu
11Ch LCDSE0(3) SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 uuuu uuuu
11Dh LCDSE1(3) SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 uuuu uuuu
11Eh LCDSE2(2,3) SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 0000 0000 uuuu uuuu
Legend: x = unknown , u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the LCD module.
Note 1: These pins may be configured as port pins, depending on the oscillator mode selected.
2: PIC16F 91 4/917 only.
3: This register is only initialized by a POR or BOR reset and is unchanged by other resets.
2004 Microchip Technology Inc. Preliminary DS41250A-page 125
PIC16F91X
10.0 PROGRAMMABLE
LOW-VOLTAGE DETECT
(PLVD) MODULE
The Programmable Low-Voltage Detect module is an
interrupt driven supply level detection. The voltage
detection monitors the internal power supply.
10.1 Voltage Trip Points
The PIC16F91X device supports eight internal PLVD
trip points. See Register 10-1 for available PLVD trip
point voltages.
10.1.1 PLVD CALIBRATION
The PIC16F91X stores the PLVD calibration values in
fuses located in the Calibration Word 2 (2009h). The
Calibration Word 2 is not erased when using the spec-
ified bulk erase sequence in the “PIC16F91X Memory
Programm ing Specific ation” (DS41244) and thus, does
not require reprogramming.
REGISTER 10-1: LVDCON – LOW-VOLTAGE DETECT CONTROL REGISTER (ADDRESS: 109h)
TABLE 10-1: REGISTERS ASSOCIATED WITH PROGRAMMABLE LOW-VOLTAGE DETECT
U-0 U-0 R-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
——IRVSTLVDEN— LVDL2 LVDL1 LVDL0
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5 IRVST: Internal Reference Voltage Stable Status Flag bit
1 = Indicates that the PLVD is stable and PLVD interrupt is reliable
0 = Indicates that the PLVD is not stable and PLVD interrupt should not be enabled
bit 4 LVDEN: Low-Voltage Detect Power Enable bit
1 = Enables PLVD, powers up PLVD circuit and supporting reference circuitry
0 = Disables PLVD, powers down PLVD and supporting circuitry
bit 3 Unimplemented: Read as ‘0’
bit 2-0 LVDL<2:0>: Low-Voltage Detection Limit bits (nominal values)
111 = 4.5V
110 = 4.2V
101 = 4.0V
100 = 2.3V (default)
011 = 2.2V
010 = 2.1V
001 = 2.0V
000 = 1.9V(1)
Note 1: Not tested and below minimum VDD.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Addres s Name Bit 7 Bit 6 B i t 5 B it 4 Bit 3 B it 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all othe r
Resets
0Bh/8Bh/
10Bh/18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Dh PIR2 OSFIF C2IF C1IF LCDIF —LVDIF—CCP2IF 0000 -0-0 0000 -0-0
8Dh PIE2 OSFIE C2IE C1IE LCDIE —LVDIE—CCP2IE 0000 -0-0 0000 -0-0
109h LVDCON — — IRVST LVDEN — LVDL2 LVDL1 LVDL0 --00 -100 --00 -100
Legend: x = unk nown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the PLVD module.
PIC16F91X
DS41250A-page 126 Preliminary 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Preliminary DS41250A-page 127
PIC16F91X
11.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial
Communications Interface or SCI.) The USART can be
configured as a full-duplex asynchronous system that
can communicate with peripheral devices, such as
CRT terminals and personal computers, or it can be
configured as a half-duplex synchronous system that
can co mmun icate with periph eral de vice s, such as A/D
or D/A integrated circuits, serial EEPROMs, etc.
The USART can be configured in the following modes:
• Asynchronous (full-duplex)
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex)
Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be
set in order to configure pins RC6/TX/CK/SCK/SCL/SEG9
and RC7/RX/DT/SDI/SDA/SEG8 as the Universal
Synchronous Asynchro nous Recei ver T r ansmi tter.
The USART module also has a multi-processor
communic ation capability using 9-bit address detection.
REGISTER 11-1: TXST A – TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN SYNC — BRGH TRMT TX9D
bit 7 bit 0
bit 7 CSRC: Cloc k Sourc e Sele ct bit
Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transm it Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in Sync mode.
bit 4 SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 Unimplemented: Read as ‘0’
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of Transmit Data, can be Parity bit
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F91X
DS41250A-page 128 Preliminary 2004 Microchip Technology Inc.
REGISTER 11-2: RCST A – RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
bit 7 SPEN(1): Serial Port Enable bit
1 = Serial port enabled (configures RC7/RX/DT/SDI/SDA/SEG8 and
RC6/TX/CK/SCK/SCL/SEG9 pins as serial port pins)
0 = Serial port disabled
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1 = Enables single r ecei ve
0 = Disables single receive
This bit is cleared after reception is complete
Synchronous mode – Slav e:
Don’t care.
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address de tection, en ables interrup t and loa d of the receive bu ffer when RSR<8>
is set
0 = Disables address detection, all bytes are received and ninth bi t can be used as parity bit
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of Received Data (can be parity bit but must be calculated by user firmware)
Note 1: CCP2CON used for PIC16F914/917 only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Preliminary DS41250A-page 129
PIC16F91X
11.1 USART Baud Rate Generator
(BRG)
The BRG supports both the Asynchronous and
Synchronous modes of the USART. It is a dedicated
8-bit bau d rate generato r . The SPBRG register con trols
the period of a free running 8-bit timer. In
Asynchronous mode, bit BRGH (TXSTA<2>) also
controls the baud rate. In Synchronous mode, bit
BRGH is ignored. Table 11-1 shows the formula for
computation of the baud rate for different USART
modes which only apply in Master mode (internal
clock).
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculate d
using the formula in Table 11-1. From this, the error in
baud rate can be determined.
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
becaus e the FOSC/(16 (X + 1)) equatio n can reduce the
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
11.1.1 SAMPLING
The data on the RC7/RX/DT/SDI/SDA/SEG8 pin is
sampled three times by a majority detect circuit to
determine if a high or a low level is present at the RX
pin.
TABLE 11-1: BAUD RATE FORMULA
TABLE 11-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed)
0
1(Asy nc hron ous) Baud Ra te = FOSC/(64 (X + 1))
(Synchronous) Baud Rate = FOSC/(4 (X + 1)) Baud Rate = FOSC/(16 (X + 1))
N/A
Legend: X = value in SPBRG (0 to 255)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
PIC16F91X
DS41250A-page 130 Preliminary 2004 Microchip Technology Inc.
TABLE 11-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
BAUD
RATE
(K)
FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz
KBAUD %
ERROR
SPBRG
value
(decimal) KBAUD %
ERROR
SPBRG
value
(decimal) KBAUD %
ERROR
SPBRG
value
(decimal)
0.3------- --
1.2 1.221 1.75 255 1.202 0.17 207 1.202 0.17 129
2.4 2.404 0.17 129 2.404 0.17 103 2.404 0.17 64
9.6 9.766 1.73 31 9.615 0.16 25 9.766 1.73 15
19.2 19.531 1.72 15 19.231 0.16 12 19.531 1.72 7
28.8 31.250 8.51 9 27.778 3.55 8 31.250 8.51 4
33.6 34.722 3.34 8 35.714 6.29 6 31.250 6.99 4
57.6 62.500 8.51 4 62.500 8.51 3 52.083 9.58 2
HIGH 1.221 - 255 0.977 - 255 0.610 - 255
LOW 312.500 - 0 250.000 - 0 156.250 - 0
BAUD
RATE
(K)
FOSC = 4 MHz FOSC = 3.6864 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal) KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3 0.300 0 207 0.3 0 191
1.2 1.202 0.17 51 1.2 0 47
2.4 2.404 0.17 25 2.4 0 23
9.6 8.929 6.99 6 9.6 0 5
19.2 20.833 8.51 2 19.2 0 2
28.8 31.250 8.51 1 28.8 0 1
33.6 - - - - - -
57.6 62.500 8.51 0 57.6 0 0
HIGH 0.244 - 255 0.225 - 255
LOW 62.500 - 0 57.6 - 0
TABLE 11-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
BAUD
RATE
(K)
FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz
KBAUD %
ERROR
SPBRG
value
(decimal) KBAUD %
ERROR
SPBRG
value
(decimal) KBAUD %
ERROR
SPBRG
value
(decimal)
0.3---------
1.2---------
2.4 - - - - - - 2.441 1.71 255
9.6 9.615 0.16 129 9.615 0.16 103 9.615 0.16 64
19.2 19.231 0.16 64 19.231 0.16 51 19.531 1.72 31
28.8 29.070 0.94 42 29.412 2.13 33 28.409 1.36 21
33.6 33.784 0.55 36 33.333 0.79 29 32.895 2.10 18
57.6 59.524 3.34 20 58.824 2.13 16 56.818 1.36 10
HIGH 4.883 - 255 3.906 - 255 2.441 - 255
LOW 1250.000 - 0 1000.000 0 625.000 - 0
BAUD
RATE
(K)
FOSC = 4 MHz FOSC = 3.6864 MHz
KBAUD
%
ERROR
SPBRG
value
(decimal) KBAUD
%
ERROR
SPBRG
value
(decimal)
0.3------
1.2 1.202 0.17 207 1.2 0 191
2.4 2.404 0.17 103 2.4 0 95
9.6 9.615 0.16 25 9.6 0 23
19.2 19.231 0.16 12 19.2 0 11
28.8 27.798 3.55 8 28.8 0 7
33.6 35.714 6.29 6 32.9 2.04 6
57.6 62.500 8.51 3 57.6 0 3
HIGH 0.977 - 255 0.9 - 255
LOW 250.000 - 0 230.4 - 0
2004 Microchip Technology Inc. Preliminary DS41250A-page 131
PIC16F91X
11.2 USART Asynchronous Mode
In this mode, the USART uses standard
Non-Return-to-Zero (NRZ) format (one Start bit, eight
or nine data bits and one Stop bit). The most common
data format is 8 bits. An on-chip, dedicated, 8-bit Baud
Rate Generator can be used to derive standard baud
rate frequencies from the oscillator. The USART
transmits and receives the LSb first. The transmitter
and receiver are functionally independent but use the
same data format and baud rate. The baud rate
generato r produces a cloc k, either x16 or x6 4 o f the bit
shift rate, depending on bit BRGH (TXSTA<2>). Parity
is not supported by the hardware, but can be
implemented in software (and stored as the ninth data
bit). Asynchronous mode is stopped during Sleep.
Asynchronous mode is sele cted by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the
following important elements:
• Baud Rate Ge nerator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
11.2.1 USART ASYNCHRONOUS
TRANSMITTER
The USART transmitter block diagram is shown in
Figure 11-1. The heart of th e transmitter is the T ransmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer, TXREG.
The TXREG register is loaded with data in software.
The TSR register is not loaded until the Stop bit has
been transmitted from the previous load. As soon as
the Stop bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG regi ster transfers the data to the TSR register
(occurs in one TCY), t he TXRE G regi ste r is empt y a nd
flag bit, TXIF (PIR1<4>), is set. This interrupt can be
enabled/disabled by setting/clearing enable bit, TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will re set o nly when ne w dat a i s loaded into the
TXREG register . While flag bit TXIF indicates the status
of the TXREG register , another bit, TRMT (TXSTA<1>),
shows the status of the TSR register. Status bit TRMT
is a read-only bit which is set when the TSR register is
empty. No interrupt logic is tied to this bit so the user
has to poll this bit in order to determine if the TSR
register is empty.
Transmission is enabled by setting enable bit, TXEN
(TXSTA<5>). The act ual transmission will not occur until
the TXREG register has been loaded with data and the
Baud Rate Gener ator (BRG) has produced a shift clock
(Figure 11-2). The transmission can also be started by
first loading the TX REG register and then set ting enable
bit TXEN. Normally , when transmission is first started, the
TSR register is empty. At that point, transfer to the
TXREG register will result in an immediate transfer to
TSR, resulting in an empty TXREG. A back-to-back
transfer is thus possible (Figure 1 1-3). Clearing enable bit
TXEN during a transmission wil l cau se the transmi ssion
to be aborted and will reset the transmitter . As a result, the
RC6/TX/CK/SCK/SCL/SEG9 pin will revert to
high-impedance.
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG reg-
ister. This is because a data write to the TXREG regis-
ter can resu lt in an immediate tra nsfer of the dat a to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit may be loaded in the TSR
register.
When setting up an Asynchronous Transmission,
follow these steps:
1. Initialize the SPBRG re gister for the appropria te
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 11.1 “USART Baud
Rate Generator (BRG)”).
2. Enable the asy nch ron ous seri al port by clearin g
bit SYNC and s e tting bit SPEN.
3. If interrupt s are desired, then set enable bit TXIE.
4. If 9-bit transmission is desired, then set transmit
bit TX9.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts
transmission).
8. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit T XIF is set when en able bit TXEN
is set. TXIF is cle ared by load ing TXR EG.
PIC16F91X
DS41250A-page 132 Preliminary 2004 Microchip Technology Inc.
FIGURE 11-1: USART TRANSMIT BLOCK DIAGRAM
FIGURE 11-2: ASYNCHRONOUS MASTER TRANSMISSION
FIGURE 11-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
TXIF
TXIE
Interrupt
TXEN Baud Rate CLK
SPBRG
Baud Rate Generator TX9D
MSb LSb
Data Bus
TXREG Register
TSR Register
(8) 0
TX9
TRMT SPEN
RC6/TX/CK/SCK/
Pin Buffer
and Control
8
• • •
SCL/SEG9 pin
Word 1 Stop Bit
Word 1
Transmit Shift Reg
Start Bit B it 0 Bit 1 Bit 7/8
Write to TXREG Word 1
BRG Output
(Shift Clock)
RC6/TX/CK/
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SCK/SCL/ SEG9
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
RC6/TX/CK/
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1 Word 2
Word 1 Word 2
Start Bit Stop Bit Start Bit
Trans mit Shift Reg.
Word 1 Word 2
Bit 0 Bit 1 Bit 7/8 Bit 0
Note: This timing diagram shows two consecutive transmissions.
SCK/SCL/SEG9
2004 Microchip Technology Inc. Preliminary DS41250A-page 133
PIC16F91X
TABLE 11-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Addr e s s Name Bit 7 Bit 6 Bit 5 B it 4 Bit 3 Bit 2 B it 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG USART Transmit Register 0000 0000 0000 0000
8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unk nown, - = unimplemented locations read as ‘0’. Shade d cells are not used for asynchronous transmission.
PIC16F91X
DS41250A-page 134 Preliminary 2004 Microchip Technology Inc.
11.2.2 USART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 11-4.
The data is received on the
RC7/RX/DT/SDI/SDA/SEG8 pin and drives the data
recovery block. The data recovery block is actually a
high-speed shifter, operating at x16 times the baud
rate; whereas the main receive serial shifter operates
at the bit rate or at FOSC.
Once Asynchronous mode is selected, reception is
enabled by setti ng bit CRE N (RCSTA<4>).
The heart of the receiver is the Receive (Serial) Shift
Register (RSR). After sampling the Stop bit, the
received data in the RSR is transferred to the RCREG
register (if it is empty). If the transfer is complete, flag
bit, R CIF (PI R 1<5> ), i s se t. T he actual interr upt ca n b e
enabled/disabled by setting/clearing enable bit, RCIE
(PIE1<5>). Flag bit RCIF is a read-only bit which is
cleared by the hardware. It i s cleared when the RCREG
register has been read and is empty. The RCREG is a
double-buffered register (i.e., it is a two-deep FIFO). It
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of
the Stop bit of the third byte, if the RC REG register is
still full, the Overrun Error bit, OERR (RCSTA<1>), will
be set. The word in the RSR will be lost. The RCREG
register can be read twice to retrieve the two bytes in
the F IFO. Ov er ru n bi t OE RR ha s to b e cl ear e d in s of t -
ware. Th is is done by resetting the re ceive logi c (CREN
is cleared and then set). If bit OERR is set, transfers
from the RSR register to th e RCREG register are inhib-
ited and n o further dat a will be received. It is , therefor e,
essential to clear error bit OERR if it is set. Framing
error bit, FERR (RCSTA<2>), is set if a Stop bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG will load bits RX9D and FERR with new
values , the refo re, it is essential for the user to re ad th e
RCSTA re gis ter bef ore reading the RCREG register in
order not to los e t he old FERR and RX9D i nform at ion .
When setting up an Asynchronous Reception, follow
these steps:
1. Initialize the SPBRG re gister for the appropria te
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 11.1 “USART Baud
Rate Generator (BRG)”).
2. Enable the asy nch ron ous seri al port by clearin g
bit SYNC and s e tting bit SPEN.
3. If interrupts are desired, then set enable bit
RCIE.
4. If 9-bit reception is desired, then set bit RX9.
5. Enable the reception by setting bit CREN.
6. Flag bit RCI F wi ll b e se t w he n rec ept ion is com -
plete an d an interru pt will be generate d if enabl e
bit RCIE is set.
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit CREN.
10. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
2004 Microchip Technology Inc. Preliminary DS41250A-page 135
PIC16F91X
FIGURE 11-4: USART RECEIVE BLOCK DIAGRAM
FIGURE 11-5: ASYNCHR ON OUS RECEPTION
TABLE 11-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receive Dat a Regis ter 0000 0000 0000 0000
8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unk nown, - = unimplemented locations read as ‘0’. Shade d cells are not used for asynchronous reception.
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT/
Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR Register
MSb LSb
RX9D RCREG Register FIFO
Interrupt RCIF
RCIE Data Bus
8
÷64
÷16
or Stop Start
(8) 710
RX9
• • •
FOSC
SDI/SDA/SEG8
Start
bit bit 7/8
bit 1bit 0 bit 7/ 8 bit 0Stop
bit
Start
bit Start
bit
bit 7/8 Stop
bit
RX (pin)
Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG Word 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word,
causing the OERR (Overrun Error) bit to be set.
PIC16F91X
DS41250A-page 136 Preliminary 2004 Microchip Technology Inc.
11.2.3 SETTING UP 9-BIT MODE WITH
ADDR ES S DET E CT
When setting up an Asynchronous Reception with
address detect enabled:
• Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH.
• Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
• If interrupts are desired, then set enable bit RCIE.
• Set bit RX9 to enable 9-bit reception.
• Set ADDEN to enable address detect.
• Enable the reception by setting enable bit CREN.
• Flag bit RCIF will be set when reception is
complete, and an interrupt will be generated if
enable bit RCIE was set.
• Read the RCSTA register to get the ninth bit and
determine if any error occurred during reception.
• Read the 8-bit received data by reading the
RCREG register to determine if the device is
being addressed.
• If any error occurred, clear the error by clearing
enable bit CREN.
• If the device has been addressed, clear the
ADDEN bi t to al low da t a b yte s an d address bytes
to be read into the receive buf fer and int errupt the
CPU.
FIGURE 11-6: USART RECEIVE BLOCK DIAGRAM
x64 B aud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT
Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR Register
MSb LSb
RX9D RCREG Register FIFO
Interrupt RCIF
RCIE Data Bus
8
÷ 64
÷ 16
or Stop Start(8) 7 10
RX9
• • •
RX9
ADDEN
RX9
ADDEN
RSR<8>
Enable
Load of
Receive
Buffer
8
8
FOSC
SDI/SDA/SEG8
2004 Microchip Technology Inc. Preliminary DS41250A-page 137
PIC16F91X
FIGURE 11-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
FIGURE 11-8: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
TABLE 11-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Start
bit bit 1bit 0 bit 8 bit 0Stop
bit
Start
bit bit 8 Stop
bit
RC7/RX/DT/
Load RSR
Read
RCIF
Word 1
RCREG
Bit 8 = 0, Data Byte Bit 8 = 1, Address Byte
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)
because ADDEN = 1.
SDI/SDA/SEG8
Start
bit bit 1bit 0 bit 8 bit 0Stop
bit
Start
bit bit 8 Stop
bit
Load RSR
Read
RCIF
Word 1
RCREG
Bit 8 = 1, Address Byte Bit 8 = 0, Data Byte
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)
because ADDEN was not updated and still = 0.
RC7/RX/DT/
SDI/SDA/SEG8
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all othe r
Resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
99h SPB RG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unk nown, - = unimplemented locations read as ‘0’. Shade d cells are not used for asynchronous reception.
PIC16F91X
DS41250A-page 138 Preliminary 2004 Microchip Technology Inc.
11.3 USART Synchronous
Master Mode
In Sync hronous Ma ster mode, the data is transmi tted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting dat a,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit, SYNC (TXSTA<4>). In
additio n, enabl e bit, SPEN (RCSTA<7>), is set in ord er
to configure the RC6/TX/CK/SCK/SCL/SEG9 and
RC7/RX/DT/SDI/SDA/SEG8 I/O pins to CK (cl ock) and
DT (data) lines, respectively. The Master mode indi-
cates that the processor transmits the master clock on
the CK li ne. Th e M as ter m ode is e nte red by se tti ng bi t,
CSRC (TXSTA<7>).
11.3.1 USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 1 1-6. The h eart of the trans mitter is the T ransm it
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new da ta from the TXREG (if available). Once the
TXREG regi ster transfers the data to the TSR register
(occurs in one TCYCLE), the TXREG i s empt y and in ter-
rupt bit, TXIF (PIR1<4>), is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will re set o nly when ne w dat a i s loaded into the
TXREG register . While flag bit TXIF indicates the status
of the TXREG register , another bit, TRMT (TXSTA<1>),
shows the status of the TSR register. TRMT is a
read-only bit which is set when the TSR is empty. No
interrupt logic is tied to this bit so the user has to poll
this bit in order to determine if the TSR register is
empty. The TSR is not mapped in data memory so it is
not available to the user.
Transmission is enabled by setting enable bit, TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The fir st data bit will be shifte d out on the next av ailable
rising edge of the clock on the CK line. Data out is
stab le around the fal ling edge of the sync hronous cloc k
(Figure 11-9). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 11-10). This is advant age ous when s low
baud rate s are selec ted, since th e BRG is kep t in Reset
when bits TXEN, CREN and SREN are clear. Setting
enable bit TXEN will start the BRG, creating a shift
clock immediately. Normally, when transmission is first
started, the TSR register is empty, so a transfer to the
TXREG regi ster will result in an immediate transfer to
TSR, resulting in an empty TXREG. Back-to-back
transfers are possible.
Clearing enable bit TXEN during a transmission will
cause the tra nsm is s ion to be ab orte d a nd will reset th e
transmitter. The DT and CK pins will revert to
high-impedance. If either bit CREN or bit SREN is set
during a transmission, the transmission is aborted and
the DT pin reverts to a high-impedance state (for a
reception). The CK pin will remain an output if bit CSRC
is se t (inte rnal c lock ). The transm itter logic , how ever, i s
not reset, although it is disconnected from the pins. In
order to reset the transmitter, the user has to clear bit
TXEN. If b it SREN is set (to inte rrupt an on-goi ng trans-
mission and receive a single word), then after the sin-
gle word is received, bit SREN will be cleared and the
serial port will revert back to transmitting, since bit
TXEN is still set. The DT line will immediately switch
from High-Impedance Receive mode to transmit and
start driving. To avoid this , bit TXEN should be cleared.
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit sh ould be set and the ninth bi t should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was writt en befo re writ ing the “new” T X9D,
the “present” value of bit TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initialize the SPBRG re gister for the appropria te
baud rate (Section 11.1 “USART Baud Rate
Generator (BRG)”).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired , set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. S tart transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
2004 Microchip Technology Inc. Preliminary DS41250A-page 139
PIC16F91X
TABLE 11-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
FIGURE 11-9: SYNCHRONOUS TRANSMISSION
FIGURE 11-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
Addr e s s Nam e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B it 0 Valu e on:
POR, BOR
Value on
all othe r
Resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h T XR EG US ART Transmit Data Regist er 0000 0000 0000 0000
8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unk nown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
bit 0 bit 1 bit 7
Word 1
Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
bit 2 bit 0 bit 1 bit 7
RC6/TX/CK/
Write to
TXREG reg
TXIF bit
(Int errupt Flag )
TXEN bit ‘
1
’ ‘
1
’
Word 2
TRMT bit
Write Word 1 Write Word 2
Note: Sync Master mode; SPBRG = 0. Continuous transmission of two 8-bit words.
SCK/SCL/SEG9
RC7/RX/DT/
SDI/SDA/SEG8
RC7/RX/DT/SDI/SDA/SEG8
RC6/TX/CK/SCK/SCL/SEG9
Write to
TXREG Reg
TXIF bit
TRMT bit
bit 0 bit 1 bit 2 bit 6 bit 7
TXEN b it
PIC16F91X
DS41250A-page 140 Preliminary 2004 Microchip Technology Inc.
11.3.2 USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either enable bit, SREN
(RCSTA<5>), or enable bit, CREN (RCSTA<4>). Data
is sampled on the RC7/RX/DT/SDI/SDA/SEG8 pin on
the falling edge of the clock. If enable bit SREN is set,
then only a s ing le w ord is received. If ena ble bit CRE N
is set, the reception is continuous until CREN is
cleared. If both bits are set, CREN takes precedence.
After clocking the last bit, the received data in the
Receive Shift Register (RSR) is transferred to the
RCREG register (if it is empty). When the transfer is
complete, interrupt flag b it, RCIF (PIR1<5>), is set. The
actual interrupt can be enabled/disabled by set-
ting/cl earing enabl e bit, RCIE (PIE1<5> ). Flag bit RC IF
is a rea d-only bit wh ich i s reset b y the hardw are. In this
case, it is reset when the RCREG register has been
read and is empty. The RCREG is a double-buffered
register (i.e., it is a two -deep FIFO). It is possible for two
bytes of data to be received and transferred to the
RCREG FIFO and a third byte to begin shifting into the
RSR register. On the clocking of the last bit of the third
byte, if the RCREG register is still full, then Overrun
Error bit, OERR (RCSTA<1>), is set. The word in the
RSR will be lost. The RCREG register can be read
twice to retrieve the two bytes in the FIFO. Bit OERR
has to be c lea red in s oftwa r e (by cl eari ng b it CR EN) . If
bit OERR is se t, transfers from th e RSR to the RCREG
are inhibited so it is essential to clear bit OERR if it is
set. The ninth receive bit is buffered the same way as
the receive data. Reading the RCREG register will load
bit RX9D with a new value, therefore, it is essential for
the user to read the RCSTA register before reading
RCREG in order not to lose the old RX9D information.
When sett ing up a Synchronous Master Reception:
1. Initialize the SPBRG re gister for the appropria te
baud rate (Section 11.1 “USART Baud Rate
Generator (BRG)”).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt fla g bit RCIF will be se t when receptio n
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 11-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Address Name Bit 7 Bit 6 B it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unk nown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
2004 Microchip Technology Inc. Preliminary DS41250A-page 141
PIC16F91X
FIGURE 11-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
11.4 USART Synchronous Slave Mode
Synchronous Slave mode dif fers from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK/SCK/SCL/SEG9 pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in Sleep mode.
Slave mode is entered by clearing bit, CSRC
(TXSTA<7>).
11.4.1 USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes is identica l, except in the cas e of the Slee p mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from Sleep and if the global interrupt is
enabled , the p rog ram wil l bran ch to the in terrupt
vector (0004h).
When setting up a Synchronous Slave Transmission,
follow these steps:
1. Enable the synchronou s slave s erial port by se t-
ting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmis si on is des ired , then set bi t TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. S tart transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
CREN bit
RC7/RX/DT/
RC6/TX/CK/
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q2 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
‘
0
’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘
0
’
Q1Q2Q3Q4
SDI/SDA/SEG8
SCK/SCL/SEG9
PIC16F91X
DS41250A-page 142 Preliminary 2004 Microchip Technology Inc.
TABLE 11-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
11.4.2 USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep
mode. Bit SREN is a “don't care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP inst ruction , then a wor d m ay be receiv ed d uring
Sleep. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enabl e bit RCIE bit is set , the interrupt gene rated
will wake the chip from Sleep. If the global interrupt is
enabled , the pro gram wil l branc h to the interru pt vec tor
(0004h).
When setting up a Synchronous Slave Reception,
follow these steps:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit R X9.
4. To enable reception, set enable bit CREN.
5. Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 11-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Addr e s s Na m e Bit 7 Bit 6 Bit 5 Bi t 4 B i t 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG USA RT Trans mit Data Register 0000 0000 0000 0000
8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah RCREG USART Receive Data Regis ter 0000 0000 0000 0000
8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
2004 Microchip Technology Inc. Preliminary DS41250A-page 143
PIC16F91X
12.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The analog-to-digital converter (A/D) allows conversion of
an analog input signal to a 10-bit binary representation of
that signal. The PIC16F91X has up to eight analog inputs,
multiplexed into on e sample and ho ld circuit. The outpu t
of the sample and hold is connected to the input of the
converter. The converter generates a binary result via
successive approximation and stores the result in a 10-bit
register. Th e vol tage ref eren ce used in the conversion is
software selectable to either VDD o r a voltage applied by
the V REF pin. Figure 12-1 shows the block diagram of the
A/D on the PIC16F91X.
FIGURE 12-1: A/D BLOCK DIAGRAM
RA0/AN0/C1-/SEG12
A/D
RA1/AN1/C2-/SEG7
RA2/AN2/C2+/VREF-/COM2
RA5/AN4/C2OUT/SS/SEG5
VDD
VREF+
ADON
GO/DONE
VCFG0 = 1
VCFG0 = 0
CHS<2:0>
ADRESH ADRESL
10
10
ADFM
VSS
RE0/AN5/SEG21(1)
RE1/AN6/SEG22(1)
RE2/AN7/SEG23(1)
RA4/C1OUT/T0CK1/SEG4
VCFG1 = 1
VCFG1 = 0
VREF-
Note 1: These channels are only available on PIC16F914/917 devices.
PIC16F91X
DS41250A-page 144 Preliminary 2004 Microchip Technology Inc.
12.1 A/D Configuration and Operation
There are three registers available to control the
functionality of the A/D module:
1. ANSEL (Register 12-1)
2. ADCON0 (Register 12-2)
3. ADCON1 (Register 12-3)
12.1.1 ANALOG PORT PINS
The ANS<7:0> bits (ANSEL<7:0>) and the TRIS bits
control the operation of the A/D port pins. Set the
corresponding TRIS bits to set the pin output driver to
it s high-imp edance st ate. Likewi se, set the correspond-
ing ANSEL bit to disable the digital input buffer.
12.1.2 CHANNEL SELECTION
There are up to eight analog channels on the PIC16F91X,
AN<7:0>. The CHS<2:0> bits (ADCON0<4:2>) control
which channel is connected to the sample and hold
circuit.
12.1.3 VOLTAGE REFERENCE
There are two options for each reference to the A/D
converter , V REF+ a nd VREF-. V REF+ can be connected to
either VDD or an externally applied vol tage. Alternatively ,
VREF- can be connected to either VSS or an externally
applied voltage. VCFG<1:0> bits are used to select the
reference source.
12.1.4 CONVERSION CLOCK
The A/D conversion cycle requires 11 TAD. The source
of the conversion clock is software selectable via the
ADCS bits (ADCON1<6:4>). There are seven possible
clock options:
•F
OSC/2
•F
OSC/4
•FOSC/8
•FOSC/16
•F
OSC/32
•FOSC/64
•FRC (dedicated internal oscillator)
For correct conversion, the A/D conversion clock
(1/TAD) mu st be select ed to ensu re a minimum TAD of
1.6 µs. Table 12-1 shows a few TAD calculations for
selected frequencies.
TABLE 12-1: TAD vs. DEVICE OPERATING FREQUENCIES
Note: Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
A/D Clock Source (TAD) Device Frequ ency
Operation ADCS<2:0> 20 MHz 5 MHz 4 MHz 1.25 MHz
2 TOSC 000 100 ns (2) 400 ns(2) 500 ns(2) 1.6 µs
4 TOSC 100 200 ns (2) 800 ns(2) 1.0 µs(2) 3.2 µs
8 TOSC 001 400 ns (2) 1.6 µs2.0 µs6.4 µs
16 TOSC 101 800 ns(2) 3.2 µs4.0 µs12.8 µs(3)
32 TOSC 010 1.6 µs6.4 µs8.0 µs(3) 25.6 µs(3)
64 TOSC 110 3.2 µs12.8 µs(3) 16.0 µs(3) 51.2 µs(3)
A/D RC x11 2-6 µs(1,4) 2-6 µs(1,4) 2-6 µs(1,4) 2-6 µs(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The A/D RC source has a typical TAD time of 4 µs for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the
conversion will be perf ormed during Sleep.
2004 Microchip Technology Inc. Preliminary DS41250A-page 145
PIC16F91X
12.1.5 STARTING A CONVERSION
The A/D conversion is initiated by setting the
GO/DONE bi t ( ADCO N0< 1>). Wh en t he c onv ers ion is
complete, the A/D module:
• Clears the GO/DONE bit
• Sets the ADIF flag (PIR1<6 >)
• Generates an interrupt (if enabled)
If the conversion must be aborted, the GO/DONE bit
can be cleared in software. The ADRESH:ADRESL
register s wil l not be u pdated with the p ar tiall y comple te
A/D conversion sample. Instead, the
ADRESH:ADRESL registers wi ll re t ain th e va lue of the
previous conversion. After an aborted conversion, a
2T
AD delay is required before another acquisition can
be initiated. Following the delay, an input acquisition is
automatically sta rted on the se lec t ed chann el .
FIGURE 12-2: A/D CONVERSION TAD CYCLES
12.1.6 CONVERSION OUTPUT
The A/D con version can be supp lied in two forma ts: left
or right shifted. The ADFM bit (ADCON0<7>) controls
the output format. Figure 12-3 shows the output
formats.
FIGURE 12-3: 10-BIT A/D RESULT FORMAT
Note: The GO/DONE bit shou ld not be set in th e
same instru ction that turns on the A/D.
TAD1TAD2 TAD3TAD4TAD5 TAD6 TAD7 TAD8TAD9
Set GO/DONE bit
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
b9 b8 b7 b6 b5 b4 b3 b2
TAD10 TAD11
b1 b0
TCY TO TAD
Conversion Starts
ADRESH and ADRESL registers are loaded,
GO/DONE bit is cleared,
ADIF bit is set,
Holding Capacitor is Connected to Analog Input
ADRESH ADRESL
(ADFM = 0)MSB LSB
bit 7 bit 0 bit 7 bit 0
10-bit A/D Result Unimplement ed: Read as ‘0’
(ADFM = 1)MSB LSB
bit 7 bit 0 bit 7 bit 0
Unimplemented: Read as ‘0’10-bit A/D Result
PIC16F91X
DS41250A-page 146 Preliminary 2004 Microchip Technology Inc.
REGISTER 12-1: ANSEL – ANALOG SELECT REGISTER (ADDRESS: 91h)
REGISTER 12-2: ADCON0 – A/D CONTROL REGISTER (ADDRESS: 1Fh)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
ANS7(2) ANS6(2) ANS5(2) ANS4 ANS3 ANS2 ANS1 ANS0
bit 7 bit 0
bit 7-0: ANS<7:0>: Analog Select bits(2)
Select between analog or digital function on pins AN<7:0>, respectively.
1 = Analog input. Pin is as signed as analog input.(1)
0 = Digital I/O. Pin is assigned to port or special function.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry,
weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit
must be se t to Input mode in order to allow external control of th e voltage on th e pin.
2: ANS<7:5> on PIC16F914/917 only; forced ‘0’ on PIC16F913/916.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
bit 7 ADFM: A/D Result Formed Select bit
1 = Right justified
0 = Left justified
bit 6 VCFG1: Voltage Reference bit
1 = VREF- p i n
0 = VSS
bit 5 VCFG0: Voltage Reference bit
1 = VREF+ pin
0 = VDD
bit 4-2 C H S<2 :0 >: Analog Channel Select bits
000 = Channel 00 (AN0)
001 = Channel 01 (AN1)
010 = Channel 02 (AN2)
011 = Channel 03 (AN3)
100 = Channel 04 (AN4)
101 = Channel 05 (AN5)
110 = Channel 06 (AN6)
111 = Channel 07 (AN7)
bit 1 GO/DONE: A/D Conversion Status bit
1 = A/D conver si on cycle in progress. Set ting this bit starts an A/D co nversion c ycl e.
This bit is automatica lly cleared by har dware when the A/D conversio n has complet ed.
0 = A/D conver si on completed/ not in progre ss
bit 0 A D O N: A /D Convers ion Status bit
1 = A/D converter module is operating
0 = A/D conver t er is shut off and con sumes n o ope rating curr ent
Legend:
R = Readable bit W = Writable bi t U = Unimplemen te d bi t , read as ‘0’
- n = Value at POR ‘ 1’ = Bi t is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Preliminary DS41250A-page 147
PIC16F91X
REGISTER 12-3: ADCON1 – A/D CONTROL REGISTER 1 (ADDRESS: 9Fh)
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— ADCS2 ADCS1 ADCS0 ————
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits
000 =F
OSC/2
001 =F
OSC/8
010 =F
OSC/32
x11 =F
RC (clock derived from a dedicated internal oscillator = 500 kHz max)
100 =F
OSC/4
101 =F
OSC/16
110 =F
OSC/64
bit 3-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F91X
DS41250A-page 148 Preliminary 2004 Microchip Technology Inc.
12.1.7 CONFIGURING THE A/D
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversi on is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine sample time, see S ection 19.0 “Electrical
Specifications”. After this sample time has elapsed, the
A/D conversion can be started.
These s te p s sh ou ld be followed f or an A/D convers io n:
1. Configure the A/D module:
• Configure analog/digital I/O (ANSEL)
• Configure voltage reference (ADCON0)
• Select A/D input channel (ADCON0)
• Select A/D con ve rsi on cl ock (ADCO N 1)
• Turn on A/D module (ADCON0)
2. Configure A /D interrupt (if desired):
• Clear ADIF bit (PIR1<6>)
• Set ADIE bit (PIE1<6>)
• Set PEIE and GIE bits (I NTCON<7 :6>)
3. Wait the required acquisition time.
4. Start conversion:
• Set GO/DONE bit (ADCON0<1>)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
(with interrupts disabled); OR
• Waiting for the A/D interrupt
6. Read A/D Result register pair
(ADRESH:ADRESL); clear bit ADIF if required.
7. For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition st arts.
EXAMPLE 12-1: A/D CONVERSION
;This code block configures the A/D
;for polling, Vdd reference, R/C clock
;and RA0 input.
;
;Conversion start and wait for complete
;polling code included.
;
BSF STATUS,RP0 ;Bank 1
MOVLW B’01110000’ ;A/D RC clock
MOVWF ADCON1
BSF TRISA,0 ;Set RA0 to input
BSF ANSEL,0 ;Set RA0 to analog
BCF STATUS,RP0 ;Bank 0
MOVLW B’10000001’ ;Right, Vdd Vref, AN0
MOVWF ADCON0
CALL SampleTime ;Wait min sample time
BSF ADCON0,GO ;Start conversion
BTFSC ADCON0,GO ;Is conversion done?
GOTO $-1 ;No, test again
MOVF ADRESH,W ;Read upper 2 bits
MOVWF RESULTHI
BSF STATUS,RP0 ;Bank 1
MOVF ADRESL,W ;Read lower 8 bits
MOVWF RESULTLO
2004 Microchip Technology Inc. Preliminary DS41250A-page 149
PIC16F91X
12.2 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allow ed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 12-4. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance va rie s over the dev ice vol tag e
(VDD), see Figure 12-4. The maximum recom-
mended impedance for analog sources is 10 kΩ.
As the impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
To calculate the minimum acquisition time,
Equation 12-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 st eps for the A/D). The
1/2 LSb err or is the ma ximu m error allo wed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the “PICmicro® Mid-Range MCU Family Reference
Manual” (DS33023).
EQUATION 12-1: ACQUISITION TIME
TACQ Amplifier Settling Time Hold Capacitor Charging Time Temperature Co efficient++=
TAMP TCTCOFF++=
2µs TCTemperature - 25°C()0.05µs/°C()[]++=
TCCHOLD RIC RSS RS++() ln(1/2047)–=
10pF 1k
Ω
7k
Ω
10k
Ω
++()– ln(0.0004885)=
1.37
=µs
TACQ 2µS1.37µS50°C- 25°C()0.05µS/°C()[]++=
4.67µS=
VAPPLIED 1e
Tc–
RC
---------
–
VAPPLIED 11
2047
------------
–
=
VAPPLIED 11
2047
------------
–
VCHOLD=
VAPPLIED 1e
TC–
RC
----------
–
VCHOLD=
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD charge response to VAPPLIED
;combin ing [1] and [2]
Wher e CHOLD is charged to within 1/2 lsb:
Solving for TC:
Therefore:
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin
leakage specification.
PIC16F91X
DS41250A-page 150 Preliminary 2004 Microchip Technology Inc.
FIGURE 12-4: ANALOG INPUT MODEL
12.3 A/D Operation During Sleep
The A/D converter module can operate during Sleep.
This requires the A/D clock source to be set to the
internal oscillator. When the RC clock source is
selected, the A/D waits one instruction before starting
the co nve rsion . This allo ws the SLEEP instruc tion t o b e
execut ed, thus eliminating muc h of the switchin g noise
from the conversion. When the conversion is complete,
the GO/DONE bit is cleared and the result is loaded
into the ADRESH:ADRESL registers. If the A/D
interr upt is enabled, the device awakens from Sleep. If
the GIE b it (INTCON< 7>) is se t, the progr am count er is
set to the interrupt vector (0004h). If GIE is clear, the
next instruction is executed. If the A/D interrupt is not
enabled, the A/D module is turned off, although the
ADON bit remains set.
When the A/D clock source is something other than
RC, a SLEEP instruction causes the present conversion
to be aborted, and the A/D module is turned off. The
ADON bit remains set.
FIGURE 12-5: A/D TRANSFER FUNCTION
CPIN
VA
RSANx
5 pF
VDD
VT = 0.6V
VT = 0.6V I LEAKAGE
RIC ≤ 1k
Sampling
Switch
SS RSS
CHOLD
= DAC capacitance
VSS
6V
Sampling Switch
5V
4V
3V
2V
567891011
(kΩ)
VDD
= 10 pF
± 500 nA
Legend: CPIN
VT
I LEAKAGE
RIC
SS
CHOLD
= Input Capacitanc e
= Threshold Voltage
= Leakage current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacit ance (from DAC)
various junctions
RSS
3FFh
3FEh
A/D Output
3FDh
3FCh
004h
003h
002h
001h
000h
Full-Scale
3FBh
1/2 LSB Ideal
Zero-Scale Zero-Scale
Transition
VREF
1/2 LSB Ideal
Transition Center of
Full-Scale Code
1 LSB Ideal
Full-Scale Range
Analog I nput
2004 Microchip Technology Inc. Preliminary DS41250A-page 151
PIC16F91X
12.4 Effects of Reset
A device Reset forces all registers to their Reset state.
Thus, the A/D module is turned off and any pending
conversion is aborted. The ADRESH:ADRESL
registers are unchanged.
TABLE 12-2: SUMMARY OF A/D REGISTERS
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
05h/
105h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx uuuu uuuu
09h PORTE — — — —RE3RE2 RE1 RE0 ---- xxxx ---- uuuu
0Bh/
8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
1Eh ADRESH Most Significant 8 bits of the left justified A/D result or 2 bits of the right justified result xxxx xxxx uuuu uuuu
1Fh ADCON0 ADFM VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
89h TRISE — — — — TRISE3 TRISE2 TRISE1 TRISE0 ---- 1111 ---- 1111
8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
91h ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
9Eh ADRESL Least Significant 2 bits of the left justified A/D result or 8 bits of the right justified result xxxx xxxx uuuu uuuu
9Fh ADCON1 — ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 ----
Legend: x = unknown , u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for A/D module.
PIC16F91X
DS41250A-page 152 Preliminary 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Preliminary DS41250A-page 153
PIC16F91X
13.0 DATA EEPROM AND FLASH
PROGRAM MEMORY
CONTROL
Data EEPROM memory is readable and writable and
the Flash program memory is readable during normal
operation (full VDD range). These memories are not
directly m ap ped i n the register fi le s p ac e. Ins tead, they
are indirectly addressed through the Special Function
Registers. There are six SFRs used to access these
memories:
• EECON1
• EECON2
• EEDATL
• EEDATH
• EEADRL
• EEADRH
When interfacing the data memory block, EEDATL
holds the 8-bit data for read/write, and EEADRL holds
the address of the EE data location being accessed.
This device has 256 bytes of data EEPROM with an
address range from 0h to 0FFh.
When interfacing the program memory block, the
EEDATL and EEDATH registers form a 2-byte word
that holds the 14-bit data for read, and the EEADRL
and EEADRH registers form a 2-byte word that holds
the 13-bit address of the EEPROM location being
acces sed. This de vice has 4k and 8k words of progra m
EEPROM with an address range from 0h-0FFFh and
0h-1FFFh. The program memory allows one word
reads.
The EEPROM dat a memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write).
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge p ump rated to op erate over the v oltage ran ge of
the devi ce for byte or word operations.
When the device is code-protected, the CPU may
continue to read and write the data EEPROM memory
and r ead th e p rogr am m emor y. Wh en c ode -pro tec ted ,
the device programmer can no longer access data or
program memory .
Additional information on the data EEPROM is
available in the “PICmicro® Mid-Range MCU Family
Reference Manual” (DS33023).
13.1 EEADRL and EEADRH Registers
The EEADRL and EEADRH registers can address up
to a maximu m of 256 bytes of dat a EEPROM or up to a
maximum of 8k words of program EEPROM.
When selecting a program address value, the MSB of
the address is written to the EEADRH register and the
LSB is wri tten to the EEADRL regi st er. When selecting
a data address value, only the LSB of the address is
written to the EEADR L register.
13.1.1 EECON1 AND EECON2 REGISTERS
EECON1 is the control register for EE memory
accesses.
Control bit EEPGD determines if the access will be a
program or data memory access. When clear, as it is
when reset, any subsequent operations will operate on
the dat a memory . Wh en set, any subsequent ope rations
will operate on the program memory. Program memory
can only be read.
Control bits RD and WR initiate read and write,
resp ec ti v el y. Th es e bi ts cann o t be cl ear e d, onl y s et , in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prev ents the accidental, premature
termination of a write operation.
The WREN bit, when set, w ill allow a write opera tion to
data EEPROM. On power-up, the WREN bit is clear.
The WRERR bit is set when a write operation is
interrupted by a MCLR or a WDT Time-out Reset
during normal operation. In these situations, following
Reset, the user can check the WRERR bit and rewrite
the location. The data and address will be unchanged
in the EEDATL and EEADRL registers.
Interrupt flag bit EEIF (PIR1<7>), is set when write is
complete. It must be cleared in the software.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the data EEPROM write sequence.
PIC16F91X
DS41250A-page 154 Preliminary 2004 Microchip Technology Inc.
REGISTER 13-1: EEDATL – EEPROM DATA LOW BYTE REGISTER (ADDRESS: 10Ch)
REGISTER 13-2: EEADRL – EEPROM ADDRESS LOW BYTE REGISTER (ADDRESS: 10Dh)
REGISTER 13-3: EEDATH – EEPROM DATA HIGH BYTE REGISTER (ADDRESS: 10Eh)
REGISTER 13-4: EEADRH – EEPROM ADDRESS HIGH BYTE REGISTER (ADDRESS: 10Fh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDATL1 EEDATL0
bit 7 bit 0
bit 7-0 EEDATL<7:0>: Byte value to Write to or Read from data EEPROM bits or to Read from program memory
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = V alue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0
bit 7 bit 0
bit 7-0 EEADRL<7:0>: Specifies one of 256 locations for EEPROM Read/Write Operation bits or low byte for
program memory reads
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = V alue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0
bit 7 bit 0
bit 5-0 EEDATH<5:0>: Byte value to Write to or Read from data EEPROM bits or to Read from program memory
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = V alue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0
bit 7 bit 0
bit 4-0 EEADRH<4:0>: Specifies one of 256 locations for EEPROM Read/Write Operation bits or high bits for
program memory reads
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = V alue at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Preliminary DS41250A-page 155
PIC16F91X
REGISTER 13-5: EECON1 – EEPROM CONTROL REGISTER 1 (ADDRESS: 18Ch)
R/W-0 U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD — — — WRERR WREN WR RD
bit 7 bit 0
bit 7 EEPGD: Program/Data EEPROM Select bit
1 = A ccesses program mem ory
0 = Accesses data memory
bit 6-4 Unimplemented: Read as ‘0’
bit 3 WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during
normal operation or BOR Reset)
0 = The write operation completed
bit 2 WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
bit 1 WR: Write Control bit
EEPGD = 1:
This bit is ignored
EEPGD = 0:
1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only be
set, not cleared, in software.)
0 = Write cycle to the data EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates a memory read (RD is cleared in hardware. The RD bit can only be set, not cleared, in
software.)
0 = D oes not initiate an memory read
Legend:
S = Bit can only be set
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F91X
DS41250A-page 156 Preliminary 2004 Microchip Technology Inc.
13.1.2 READING THE DATA EEPROM
MEMORY
To read a data memory location, the user must write the
address to the EEADRL register, clear the EEPGD
control bit (EECON1<7>), and then set control bit RD
(EECON1<0>). The data is available in the very next
cycle, in the EEDATL register; th eref ore, it can be read
in the ne xt ins tructi on. EED ATL will hold thi s val ue unti l
another read or until it is written to by the user (during
a write operation).
EXAMPLE 13-1: DATA EEPROM READ
13.1.3 WRITING TO THE DATA EEPROM
MEMORY
To write an EEPROM data location, the user must first
write the add res s to t he EEADRL re gis ter a nd th e da ta
to the EEDATL register. Then the user must follow a
specific sequence to initiate the write for each byte.
The write will not initiate if the sequen ce described below
is not followed exactly (write 55h to EECON2, write AAh
to EECON2, then set WR bit) for each byte. Interrupts
should be disabled during this code segment.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit wil l not af fect this wri te cycle. The WR bit wil l
be inhib ited from bei ng set u nle ss the WR EN bit i s set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
The steps to write to EEPROM data memory are:
1. If step 10 is not implemented, chec k the WR bit
to see if a write is in progress.
2. Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.
3. Write the 8-bit data value to be programmed in
the EEDATA register.
4. Clear the EEPGD bit to point to EEPROM data
memory.
5. Set the WREN bit to en able program operations.
6. Disable interrupts (if enabled).
7. Execute the special five instruction sequence:
• W rite 55h to EECON2 i n two steps (first to W ,
then to EECON2)
• Write AAh to EECON2 in two steps (first to
W, then to EECON2)
• Set t he WR bit
8. Enable interrupts (if using interrupts).
9. Clear the WREN bit to disable program
operations.
10. At the completion of the write cycle, the WR bit
is cleared and the EEIF interrupt flag bit is set.
(EEIF must be cleared by firmware.) If step 1 is
not implemented, then firmware should check
for EEIF to be set, or WR to clear, to i ndicate th e
end of the program cycle .
EXAMPLE 13-2: DATA EEPROM WRITE
BSF STATUS,RP1 ;
BCF STATUS,RP0 ; Bank 2
MOVF DATA_EE_ADDR,W ; Data Memory
MOVWF EEADR ; Address to read
BSF STATUS,RP0 ; Bank 3
BCF EECON1,EEPGD ; Point to Data
; memory
BSF EECON1,RD ; EE Read
BCF STATUS,RP0 ; Bank 2
MOVF EEDATA,W ; W = EEDATA
BSF STATUS,RP1 ;
BSF STATUS,RP0
BTFSC EECON1,WR ;Wait for write
GOTO $-1 ;to complete
BCF STATUS,RP0 ;Bank 2
MOVF DATA_EE_ADDR,W;Data Memory
MOVWF EEADR ;Address to write
MOVF DATA_EE_DATA,W;Data Memory Value
MOVWF EEDATA ;to write
BSF STATUS,RP0 ;Bank 3
BCF EECON1,EEPGD ;Point to DATA
;memory
BSF EECON1,WREN ;Enable writes
BCF INTCON,GIE ;Disable INTs.
MOVLW 55h ;
MOVWF EECON2 ;Write 55h
MOVLW AAh ;
MOVWF EECON2 ;Write AAh
BSF EECON1,WR ;Set WR bit to
;begin write
BSF INTCON,GIE ;Enable INTs.
BCF EECON1,WREN ;Disable writes
Required
Sequence
2004 Microchip Technology Inc. Preliminary DS41250A-page 157
PIC16F91X
13.1.4 READING THE FLASH PROGRAM
MEMORY
To read a program memory location, the user must
write two bytes of the address to the EEADRL and
EEADRH registers, set the EEPGD control bit
(EECON1<7>), and then set control bit RD
(EECON1<0>). Once the read control bit is set, the
program memory Flash controller will use the second
instruction cycle to read the data. This causes the
second instruction immediately following the
“BSF EECON1,RD” instruct ion to be ig nor ed. The da ta
is available in the very next cycle, in the EEDATL and
EEDATH registers; therefore, it can be read as two
bytes in the following instructions. EEDATL and
EEDATH registe rs will hold this valu e until ano ther read
or until it is written to by the user (during a write
operation).
EXAMPLE 13-3: FLASH PROGRAM READ
Note 1: The two instructions following a program
memory read are required to be NOP’s.
This prevents the user from executing a
two-cycle instruction on the next
instruction after the RD bit is set.
2: If the WR bit is set when EEPGD = 1, it
will be immediately reset to ‘0’ and no
operation will take place.
BSF STATUS, RP1 ;
BCF STATUS, RP0 ; Bank 2
MOVLW MS_PROG_EE_ADDR;
MOVWF EEADRH ; MS Byte of Program Address to read
MOVLW LS_PROG_EE_ADDR;
MOVWF EEADR ; LS Byte of Program Address to read
BSF STATUS, RP0 ; Bank 3
BSF EECON1, EEPGD ; Point to PROGRAM memory
BSF EECON1, RD ; EE Read
;NOP
NOP ; Any instructions here are ignored as program
; memory is read in second cycle after BSF EECON1,RD
;BCF STATUS, RP0 ; Bank 2
MOVF EEDATA, W ; W = LS Byte of Program EEDATA
MOVWF DATAL ;
MOVF EEDATH, W ; W = MS Byte of Program EEDATA
MOVWF DATAH ;
Required
Sequence
PIC16F91X
DS41250A-page 158 Preliminary 2004 Microchip Technology Inc.
FIGURE 13-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION
TABLE 13-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
0Bh/8Bh/
10Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
10Ch EEDATL EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDATL1 EEDATL0 0000 0000 0000 0000
10Dh EEADRL EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0 0000 0000 0000 0000
10Eh EEDATH — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 --00 0000
10Fh EEADRH — — — EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---0 0000 ---0 0000
18Ch EECON1 EEPGD — — — WRERR WREN WR RD ---- x000 ---- q000
18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ----
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by data EEPROM module.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
BSF EECON1,RD
execut ed her e INSTR(PC + 1)
executed here Forced NOP
execut ed her e
PC
PC + 1 EEADRH,EEADRL PC+3 PC + 5
Flash ADDR
RD bit
EEDATH,EEDATL
P C + 3 PC + 4
INSTR (PC + 1)
INSTR(PC - 1)
executed here INSTR(PC + 3)
executed here INSTR(PC + 4)
executed here
Flas h Data
EEDATH
EEDATL
register
EERHLT
INSTR (PC) INSTR (PC + 3) INSTR (PC + 4)
2004 Microchip Technology Inc. Preliminary DS41250A-page 159
PIC16F91X
14.0 SSP MODULE OVERVIEW
The Synchronous Serial Port (SSP) module is a serial
inter fac e us ed to c om muni cate with other peri phe ral or
microc ontroll er devic es. Thes e periph eral devi ces ma y
be serial EEPROMs, shift registers, display drivers,
A/D converters, etc. The SSP module can operate in
one of two modes:
• Serial Peripheral Interface (SPI™)
• Inter-Integrated Circuit (I2 C™)
An overview of I2C operations and additional information
on the SSP module can be found in the “PICmicro®
Mid-Range MCU Fa mily Reference Manual” (DS33023).
Refer to Application Note AN578, “Use of the SSP
Module in the Multi-Master Environment” (DS00578).
14.1 SPI Mode
This section c ontains register definitions and operational
characteristics of the SPI module. Additional information
on the SPI module can be found in the “PICmicro®
Mid-Range MCU Fa mily Reference Manual” (DS33023).
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. To accomplish
communication, typically three pins are used:
• Serial Data Out (SDO) – RC4/T1G/SDO/SEG11
• Serial Data In (SDI) – RC7/RX/DT/SDI/SDA/SEG8
• Serial Clock (SCK) – RC6/TX/CK/SCK/SCL/SEG9
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Se lect (SS) – RA5/AN4/C2OUT/SS/SEG5
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the
following to be speci fied:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the cloc k input)
• Clock Polarity (idle state of SCK)
• Clock edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
PIC16F91X
DS41250A-page 160 Preliminary 2004 Microchip Technology Inc.
REGISTER 14-1: SSPSTAT – SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF
bit 7 bit 0
bit 7 SMP: SPI™ Data Input Sample Phase bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time (Microwire)
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
I2 C™ mode:
This bit must be maintained clear
bit 6 CKE: SPI Clock Edge Select bit
SPI mode, CKP = 0:
1 = Data transmitted on rising edge of SCK (Microwire alternate)
0 = Data transmitted on falling edge of SCK
SPI mode, CKP = 1:
1 = Data transmitted on falling edge of SCK (Microwire default)
0 = Data transmitted on rising edge of SCK
I2 C mode:
This bit must be maintained clear
bit 5 D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit (I2C mode only)
This bit is cl eared when the SSP module is disabled, or when the Start bit is detected last.
SSPEN is cleared.
1 = Indicates that a Stop bit has been detected last (this bit is ‘ 0’ on Reset)
0 = Stop bit was not detected last
bit 3 S: Start bit (I2C mode only)
This bit is cl eared when the SSP module is disabled, or when the Stop bit is detected last.
SSPEN is cleared.
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
bit 2 R/W: Read/Write bit Information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid f rom
the address match to the ne xt Start bit, Stop bit or ACK bit.
1 = Read
0 = Write
bit 1 UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2 C mode only):
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Preliminary DS41250A-page 161
PIC16F91X
REGISTER 14-2: SSPCON – SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
bit 7 WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting th e previou s word (must b e cleared
in software)
0 = No collision
bit 6 SSPOV: Receiv e Overflow Indicator bit
In SPI™ mode:
1 = A new byte is rece ived while the SSPBUF reg ister is still holdin g the previou s data. In case of
overflow , the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read
the SSPBUF, even if only transmitting data, to avoid setting overflow . In Master mode, the over-
flow bit is not set since each new reception (and transmission) is initiated by writing to the SSP-
BUF re gist er.
0 = No overflow
In I2 C™ mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t
care” in Transmit mode. SSPO V m ust be cleare d in soft war e in ei ther mo de.
0 = No overflow
bit 5 SSPEN: Synch ronous Serial Por t Enable bit
In SPI mode:
1 = Enables seria l port and config ur es SC K, SDO, and SD I as se rial port pins
0 = Disables serial port and configures th ese pins as I/O port pins
In I2 C mode:
1 = Enables the ser ia l por t and configures the SDA and SC L pi ns as serial port pi ns
0 = Disables serial port and configures th ese pins as I/O port pins
In both m odes, whe n enabled, these pins m ust be properl y con f ig ur ed as input or out put.
bit 4 CKP: C l o ck Polarity Select bit
In SPI mode:
1 = Idle state for clo ck i s a high level (Microwire default)
0 = Idle state for clock is a low level (Microwire alternate)
In I2 C mode:
SCK release con t rol
1 = Enable cloc k
0 = Holds clo ck low (clock stretch ). (Used to ensure data setup time.)
bit 3-0 SSPM<3:0>: Syn chronous Ser ial P or t Mode Select bits
0000 = SPI Master mode, clock = FOSC/4
0001 = SPI Master mode, clock = FOSC/16
0010 = SPI Master mode, clock = FOSC/64
0011 = SPI Master mode, cl ock = TMR2 output / 2
0100 = SPI Slave mode, clock = SC K pin. SS pin co nt ro l enabled.
0101 = SPI Slave mode, clock = SC K pin. SS pin co nt ro l disabled. SS can be used as I/O pin.
0110 = I2C Slav e m od e, 7-b it ad dr ess
0111 = I2C Slav e m od e, 10- bit addr ess
1011 = I2C Firmware Controlled Master mode (slave idle)
1110 = I2C Slav e m ode, 7-bit ad dr ess w ith Start and Stop bit inter r upts e nabled
1111 = I2C Slav e m ode, 10-bit addr es s w i th Start and Stop bit interr upts enabled
Legend:
R = Readable bit W = Writable bi t U = Unimplemen te d bi t , read as ‘0’
- n = Value at POR ‘ 1’ = Bi t is set ‘0’ = Bit is cleared x = Bit is unknown
PIC16F91X
DS41250A-page 162 Preliminary 2004 Microchip Technology Inc.
FIGURE 14-1: SSP BLOCK DIAGRAM
(SPI MODE)
To enable the serial port, SSPEN bit (SSPCON<5>)
must be set. To reset or reconfigure SPI mode:
• Clear bit SSPEN
• Re-initialize the SSPCON register
• Set SSPEN bit
This configures the SDI, SDO, SCK and SS pins as
serial port pins. For the pins to behave in a serial port
functio n, they mu st have their dat a direc tion bits (in the
TRISC register) appropriately programmed. This is:
• SDI must have TRISC<7> set
• SDO must have TRISC<4> cleared
• SCK (Master mode) must have TRISC<6>
cleared
• SCK (Slave mode) must have TRISC<6> set
• SS must have TRISA<5> set.
.
Read Write
Internal
Data Bus
RC7/RX/
RC4/T1G/
RA5/AN2/
RC6/TX/CK/
SSPSR reg
SSPBUF reg
SSPM<3:0>
bit 0 Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 Outpu
t
TCY
Prescaler
4, 16, 64
TRISC<6>
2
Edge
Select
2
4
SCL/
Peripheral OE
SDA/SEG8
DT/SDI/
SDO/SEG11
C2OUT/SS/
SEG5
SCK/
SEG9
Note 1: When the SPI is in Slave mode with SS
pin control enabled (SSPCON<3:0> =
0100), the SP I modul e will re set if th e SS
pin is set to VDD.
2: If the SPI is used in Slave mode with
CKE = 1, then the SS pin control must b e
enabled.
3: When the SPI is in Slave mode with SS pin
control enabled (SSPCON<3:0> = 0100),
the state of the SS pin can affect the state
read back from the TRISC<4> bit. The
peripheral OE signa l from the SSP module
into PORTC controls the state that is read
back from the TRISC<4> bit (see
Section 19.4 “DC Characteristics:
PIC16F91X-I (Industrial), PIC16F91X-E
(Extended)” for information on PORTC).
If read-modify-write instructions, such as
BSF, are performed on the TRISC register
while the SS pin is high, this will cau se the
TRISC<4> bit to be set, thus disabling the
SDO output.
2004 Microchip Technology Inc. Preliminary DS41250A-page 163
PIC16F91X
14.2 Operation
When initializing the SPI, several options need to be
specif ied. This is done by progra mming the ap propriate
control bits (SSPCON<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the cloc k input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The SSP consists of a transmit/receive shift register
(SSPS R) and a buffer re gist er (S SP BUF) . T he SSP SR
shifts the data i n and out of the device, MS b first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the eight bits of
data have been received, that byte is moved to the
SSPBUF register. Then, the Buffer Full detect bit, BF
(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
read ing t he dat a tha t wa s j ust rec ei ved . An y w rite to the
SSPBUF register during transmission/reception of data
will be ign ored an d th e w rite co llisi on d ete ct bi t, WC OL
(SSPCON<7>), will be set. User software must clear the
WCOL bit so that it can be determined if the following
write(s) to the SSPBUF register completed successfully .
When the application software is expecting to receive
valid da ta, the SSPBUF shoul d be read before th e next
byte o f dat a t o transfe r is written to t he SSPBUF. Buffer
Full bit, BF (SSPSTAT<0>), indicates when SSPBUF
has been loaded with the receiv ed data (transmission
is complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally, the SSP interrupt is used to
determine when the transmission/reception has com-
pleted. T he SSPBUF must be rea d and/or written. If the
interrupt method is not going to be used, then software
polling can be d one to ensure that a write collision d oes
not occur. Example 14-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
The SSPSR is n ot directly reada ble or wri table and can
only be ac cessed by addressing the SSPBUF register.
Additionally, the SSP Status register (SSPSTAT)
indicates the various status conditions.
EXAMPLE 14-1: LOADING THE SSPBUF (SSPSR) REGISTER
LOOP BTFSS SSPSTAT, BF ;Has data been received(transmit complete)?
BRA LOOP ;No
MOVF SSPBUF, W ;WREG reg = contents of SSPBUF
MOVWF RXDATA ;Save in user RAM, if data is meaningful
MOVF TXDATA, W ;W reg = contents of TXDATA
MOVWF SSPBUF ;New data to xmit
PIC16F91X
DS41250A-page 164 Preliminary 2004 Microchip Technology Inc.
14.3 Enabling SPI I/O
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pin s. For the pins t o behave as the serial p ort fun c-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed. That is:
• SDI is a uto matically con trol led by the SPI module
• SDO must have TRISC<5> bit cleared
• SCK (Master mode) must have TRISC<3> bit
cleared
• SCK (Slave mode) must have TRISC<3> bit set
•SS
must ha ve TRISC<4> bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
14.4 Typical Connect ion
Figure 14-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their
programmed clock edge and latched on the opposite
edge of the clock. Both processors should be
programmed to the same Clock Polarity (CKP), then
both controllers would send and receive data at the
same tim e. Whet her the dat a is meaningful (or dummy
data) depends on the application software. This leads
to three scenarios for data transmission:
• Master sends data – Slave sends dummy d ata
• Master sends data – Slave s ends data
• Master sends dummy data – Slave sen ds data
FIGURE 14-2: SPI™ MASTER/SLAVE CONNECTION
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
Processor 1
SCK
SPI™ Master SSPM<3:0> = 00xxb
Serial Input Buf fe r
(SSPBUF)
Shift Register
(SSPSR)
LSb
MSb
SDI
SDO
Processor 2
SCK
SPI™ Slave SSPM<3:0> = 010xb
Serial Clock
2004 Microchip Technology Inc. Preliminary DS41250A-page 165
PIC16F91X
14.5 Master Mode
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 14-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF registe r is written to. If the SPI is
only going to receive, the SDO output could be
disabled (programmed as an input). The SSPSR
register will conti nue to shift i n the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and Status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
The clock pola rity is selected by appropriately program-
ming the CKP bi t (SSPCON<4>). This then, would giv e
waveforms for SPI communication as shown in
Figure 14-3, Figure 14-5 and Figure 14-6, where the
MSB is t rans m itted first. In Master mo de, the SPI clock
rate (bit rate) is user programmable to be one of the
following:
•F
OSC/4 (or TCY)
•FOSC/16 (or 4 • TCY)
•F
OSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 40 MHz) of
10 Mbps.
Figure 14-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
dat a is shown.
FIGURE 14-3: SPI™ MODE WAVEFORM (MASTER MODE)
SCK
(CKP = 0
SCK
(CKP = 1
SCK
(CKP = 0
SCK
(CKP = 1
4 Clock
Modes
Input
Sample
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
bit 7 bit 0
SDI
SSPIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 1)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
(CKE = 0)
(CKE = 1)
Next Q4 Cycle
after Q2↓
PIC16F91X
DS41250A-page 166 Preliminary 2004 Microchip Technology Inc.
14.6 Slave Mode
In Slave m ode , the dat a is transmitted and r ece iv ed a s
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
14.7 Slave Select Synchronization
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode wit h SS pin control ena bled
(SSPCON<3:0> = 04h). The pin must not be drive n low
for the SS pin to function as an input. The data latch
must be high. When the SS pin is l ow , transm ission an d
receptio n are enab led and the SDO pin is driven. When
the SS pin goes high, the SDO pin is no longer driven,
even if in the middle of a transmitted byte, and
becomes a floating output. External pull-up/pull-down
resistors may be desirable, depending on the applica-
tion.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an in put. This d isables transmissi ons from th e SDO.
The SDI can always be left as an input (SDI function)
since it can not cre ate a bus con f li ct .
FIGURE 14-4: SLAVE SYNCHRONIZATION WAVEFORM
Note 1: When the SPI is in Slave mode with SS pin
control enabled ( SSPCON<3:0> = 0100),
the SPI module will reset if the SS pin is set
to VDD.
2: If the SPI is us ed in Slave Mo de with CK E
set, then the SS pin control must be
enabled.
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7
SDO bi t 7 bit 6 bit 7
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
bit 0
bit 7 bit 0
Next Q4 Cycle
after Q2↓
2004 Microchip Technology Inc. Preliminary DS41250A-page 167
PIC16F91X
FIGURE 14-5: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
FIGURE 14-6: SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Optional
Next Q4 Cycle
after Q2↓
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI
bit 7 bit 0
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SSPIF
Interrupt
(SMP = 0)
CKE = 1)
CKE = 1)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
Not Optional
Next Q4 Cycle
after Q2↓
PIC16F91X
DS41250A-page 168 Preliminary 2004 Microchip Technology Inc.
14.8 Sleep Operation
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal mode, the module will continue to trans-
mit/r eceive data.
In Slave m ode , th e SP I Transm it/ R ece ive Sh ift register
operat es asy nchron ously to the devi ce. Th is al lows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been receiv ed, the SSP interrupt
flag bit will be set and if enabled, will w ake the device
from Sleep.
14.9 Effects of a Reset
A Reset disables the SSP module and terminates the
current transfer.
14.10 Bus Mode Compatibility
Table 14-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 14-1: SPI™ BUS MODES
There is also a SMP bit w hich co ntrols whe n the dat a is
sampled.
TABLE 14-2: REGISTERS ASSOCIATED WITH SPI™ OPERATION
Standard SPI™
Mode Terminology
Control Bits State
CKP CKE
0, 0 0 1
0, 1 0 0
1, 0 1 1
1, 1 1 0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all othe r
Resets
0Bh,8Bh.
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = un implemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.
2004 Microchip Technology Inc. Preliminary DS41250A-page 169
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14.11 SSP I2 C Operation
The SSP module in I2C mode, fully implements all
slave functions, except general call support, and pro-
vides interrupts on Start and Stop bits in hardware to
facilitate firmware implementations of the master func-
tions. Th e SSP mod ule imple ment s the st andard m ode
specifications, as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the
RC6/TX/CK/SCK/SCL/SEG9 pin, which is the clock
(SCL), and the RC7/RX/DT/SDI/SDA/SEG8 pin, which
is the data (SDA).
The SSP mod ule fun ctions a re enabl ed by settin g SSP
enable bit SSPEN (SSPCON<5>).
FIGURE 14-7: SSP BLOCK DIAGRAM
(I2 C™ MODE)
The SSP module has five registers for the I2C operation,
which are listed below.
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Rece ive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly
accessible
• SSP Address Register (SSPADD)
The SSPCON register allows control of the I2C
operation. Four mode selection bits (SSPCON<3:0>)
allow one of the following I2C modes to be selected:
•I
2C Slave mode (7-bit address)
•I
2C Slave mode (10-bit address)
•I
2C Slave mode (7-bit add res s), with Sta rt and
Stop bit interrupts enabled to support Firmware
Master mode
•I
2C Slave mode (10-bit address), with Start and
Stop bit interrupts enabled to support Firmware
Master mode
•I
2C Start and Stop bit interrupts enabled to sup-
port Firmware Master mode; Slave is idle
Selection of any I2C mode with the SSPEN bit set
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits. Pull-up resistors must be
provide d external ly to the SCL and SD A pins for proper
operation of the I2C module.
Additional information on SSP I2C operation can be
found in the “PICmicro® Mid-Range MCU Family
Reference Manual” (DS33023).
14.12 Slave Mode
In Slave mod e, the SCL and SDA pin s must be config-
ured as input s (TRISC<7 :6> set). The SSP module will
override the input state with the output data when
required (slave -tran smit ter).
When an add ress is match ed, or the da t a trans fer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse, and
then load the SSPBUF reg is ter wi th th e re ceive d valu e
currently in the SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK pulse. They include (either
or both):
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
b) The overf low bit SSPOV (SSPCON<6>) was set
before the transfer was received.
In this case, the SS PSR r egister val ue is no t loa ded int o
the SSPBUF, but bit SSPI F (PIR1<3>) is set. Table 14-3
shows the results of when a data transfer byte is received,
given the status of bits BF and SSPOV. The shaded cells
show the conditio n where user soft ware did not p roperly
clear the overflow condition. Flag bit BF is cleared by
reading the SSPBUF register, while bit SSPOV is cleared
through software.
The SCL clock input must have a minimum high and
low for proper operation. For high and low times of the
I2C specification, as well as the requirements of the
SSP module, see Se ction 19.0 “Electrical Specific a-
tions”.
Read Write
SSPSR reg
Match Detect
SSPADD reg
Start and
Stop bit Detect
SSPBUF reg
Internal
Data Bus
Addr Match
Set, Rese t
S, P bits
(SSPSTAT reg
)
RC6/TX/
RC7/
Shift
Clock
MSb
RX/DT/ LSb
SDI/
CK/SCK/
SCL/SEG9
SDA/
SEG8
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DS41250A-page 170 Preliminary 2004 Microchip Technology Inc.
14.12.1 ADDRESSING
Once the SSP module has been enabled, it waits for a
Start condition to occur. Following the Start condition,
the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following ev ents occur:
a) The SSPSR register value is loaded into the
SSPBUF register.
b) The buffer full bit, BF is set.
c) An ACK pulse is generated.
d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) on the falling
edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave (Figure 14-8). The five Most
Significant bits (MSbs) of the first address byte specify
if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must
specify a write so the slave device will receive the
second address byte. For a 10-bit address, the first
byte w ould equ al ‘1111 0 A9 A8 0’, where A9 and
A8 are the two MSbs of the address.
The sequence of events fo r 10-bit address is as follows,
with steps 7-9 for slave-transm itter:
1. Receive first (high) byte of address (bits SSPIF,
BF and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
5. Update t he SSPADD registe r wi th the first (high)
byte of a ddre ss ; if match releases SCL li ne, this
will clear bit UA.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive repeated Start condition.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
TABLE 14-3: DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received SSPSR → SSPBUF Generate ACK
Pulse
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
BF SSPOV
00 Yes Yes Yes
10 No No Yes
11 No No Yes
0 1 No No Yes
Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
2004 Microchip Technology Inc. Preliminary DS41250A-page 171
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14.12.2 RECEPTION
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleare d. The re ceived ad dress is loa ded in to
the SSPBUF register.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or b it SSPOV (SSPCON<6>) is set. This is an e rror
condition due to the user’s firmware.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
FIGURE 14-8: I2 C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
P
9
8
7
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1SDA
SCL 123456789123456789123
4
Bus Master
terminates
transfer
Bit SSPOV is set because the SSPBUF register is still full.
Cleared in software
SSPBUF register is read
ACK Receiving Data
Receiving Data D0
D1
D2
D3D4
D5
D6D7
ACK
R/W = 0
Receiving Ad dr ess
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
ACK
ACK is not sent.
PIC16F91X
DS41250A-page 172 Preliminary 2004 Microchip Technology Inc.
FIGURE 14-9: I2C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S123456789 123456789 12345 789 P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7 D6D5D4D3 D1D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Clear ed in softwar e
D2
6
(PIR1<3>) Cleared in software
Receive Second Byte of Address
Clear ed by hard w ar e
when SSPADD is updated
with low byte of address
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating
that the SSPADD needs to
be updated
UA is set indicating
that SSPA DD needs to
be updated
Cleared by hardware when
SSPADD is updated with high
byte of address
SSPBUF is written
with contents of SSPSR Dummy read of SSPBUF
to clear BF flag
ACK
CKP
12345 789
D7 D6 D5 D4 D3 D1 D0
Receive Data Byte
Bus maste
r
terminates
transfer
D2
6
ACK
Cleared in software Cleared in software
SSPOV (SSPCON<6>)
SSPOV is set
because SSPBUF is
still full. ACK is not sen
t.
(CKP does not reset to ‘0’ when SEN = 0)
Clock is held low until
update of SSPADD has
taken place
2004 Microchip Technology Inc. Preliminary DS41250A-page 173
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14.12.3 TRANSMISSION
When the R/W bit of the incoming address by te is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin
RC6/TX/CK/SCK/SCL/SEG9 is held low. The transmit
data must be loaded into the SSPBUF register, which
also loads the SSPSR register. Then, pin
RC6/TX/CK/SCK/SCL/SEG9 should be enabled by
setting bit CKP (SSPCON<4>). The master must mon-
itor the SCL pin prior to asserting another clock pulse.
The slave devices may be holding off the master by
stretching the clock. The eight data bits are shifted out
on the falling edge of the SCL input. This ensures that
the SDA signal is valid during the SCL high time
(Figure 14-10).
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the s tatus
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
the dat a tran sfer is com plete. When th e ACK is latched
by the slave, the slave logic is reset (resets SSPSTAT
register) an d the slave then moni tors for another occur-
rence of the S tart bit. If the SDA line was lo w (ACK), the
transmit data must be loaded into the SSPBUF register ,
which also loads the SSPSR register. Then pin
RC6/TX/CK/SCK/SCL/SEG9 should be enabled by
setting bit CKP.
FIGURE 14-10 : I2 C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Transmitting DataR/W = 1Receiving Ad dr ess
123456789 123456789 P
Cleared in software
SSPBUF is written in software From SSP Interrupt
Service R out i ne
Set bit after writing to SSPB UF
SData in
sampled SCL held low
while CPU
responds to SSPIF
(the SSPBUF must be written to
before the CKP bit can be set)
PIC16F91X
DS41250A-page 174 Preliminary 2004 Microchip Technology Inc.
FIGURE 14-11: I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S123456789 123456789 12345 789 P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 1 1 1 1 0 A8
R/W = 1
ACK
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
Bus master
terminates
transfer
A9
6
(PIR1<3>)
Receive Second Byte of Address
Cleared by hardwa re w hen
SSPADD is updated with
low byte of address
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating
that the SSPADD
needs to be update d
UA is set indicating
that SSPADD needs
to be updated
Cleared by hardware when
SSPADD is updated with high
byte of address
SSPBUF is written
with contents of Dummy read of SSPBUF
to clear BF flag
Receive First Byte of Address
12345 789
D7 D6 D5 D4 D3 D1 ACK
D2
6
Transmitting Data Byte D0
Dummy read of SSPBUF
to clear BF flag
Sr
Cleared in software
Write of SSPBUF
initiates transmit
Clear ed in softwar e
Comple tion of
clears BF flag
CKP (SSPCON<4>)
CKP is set in software
CKP is automatically cleared in hardware
Clock is held low until
update of SSPADD has
taken place
data transmission
Clock is held low until
CKP is set to ‘1’
BF flag is clear
third address sequence
at the end of the
holding SCL low
SSPSR
2004 Microchip Technology Inc. Preliminary DS41250A-page 175
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14.13 Master Mode
Master mode of operation is supported in firmware
using interrupt generation on the detection of the Start
and S t op conditio ns. The S top (P) and S t art (S) bits are
cleared from a Reset or when the SSP module is dis-
abled. The Stop (P) and Start (S) bits will toggle based
on the St art and Stop conditions. C ontrol of the I 2C bus
may be t aken whe n the P bit is set or th e bus is idle an d
both the S and P bits are clear.
In Master mode, the SCL and SDA lines are manipu-
lated by cleari ng the c orresp onding TRISC<6 :7> bit(s ).
The output level is always low, irrespective of the
value(s ) i n PO R T C <6:7 >. So w h en tran sm itti ng da t a, a
‘1’ data bit must have the TRISC<7 > bi t s et (i npu t) an d
a ‘0’ data bi t mus t have the TRI S C<7> bi t c le ared (o ut-
put). The same scenario is true for the SCL line with the
TRISC<6> bit. Pull-up resistors must be provided
externally to the SCL and SDA pins for proper opera-
tion of the I2C module.
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP Interrupt will occur if
enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
Master mode of operation can be done with either the
Slave mode idle (SSPM<3:0> = 1011), or with the
Slave active. When both Master and Slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
14.14 Multi-master Mode
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions, allows the
determination of when the bus is free. The Stop (P)
and Sta r t ( S) bi t s are c lea red from a R eset or when the
SSP module is disabled. The Stop (P) and Start (S)
bits will toggle based on the Start and Stop conditions.
Control of the I2 C bus may be taken when bit P
(SSPSTAT<4>) is set, or the bus is idle and both the S
and P bits clear. When the bus is busy, enabling the
SSP Interr upt will gen erat e th e in terru pt wh en the S top
conditi on occ urs .
In Multi-Master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low
level is present, the device needs to release the SDA
and SCL lines (set TRISC<6:7>). There are two
stages where this arbitration can be lost, these are:
• Address Transfer
• Data Transfer
When the slave logic is enabled, the slave continues
to receive. If arbitration was lost during the address
transfer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be gener-
ated. If arbitration was lost during the data transfer
stage, the device will need to re-transfer the data at a
later time.
14.14.1 CLOCK SYNCHRONIZATION AND
THE CKP BIT
When the CKP bit is cleared, the SCL output is forced
to ‘0’; however, setting the CKP bit will not assert the
SCL outpu t low until the SCL outpu t is already sample d
low. Therefore, the CKP bit will not assert the SCL line
until an external I2C master device has already
asserted the SCL line. The SCL output will remain low
until the CKP bit is set and all other devices on the I2C
bus have deasserted SCL. Thi s ensures that a write to
the CKP bit will not violate the minimum high time
requirement for SCL (see Figure 14-12).
PIC16F91X
DS41250A-page 176 Preliminary 2004 Microchip Technology Inc.
FIGURE 14-12: CLOCK SYNCHRONIZATION TIMING
TABLE 14-4: REGISTERS ASSOCIATED WITH I2 C™ OPERATION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
13h SSP BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
87h TRISC PO RTC Data Direction Register 1111 1111 1111 1111
93h SSPADD Sync hronous Ser ial Port (I2C™ mode) Addre ss Regist er 0000 0000 0000 0000
94h SSPSTAT SMP(1) CKE(1) D/A PSR/WUA BF 0000 0000 0000 0000
Legend: x = unk nown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by SSP module in
I2C mode.
Note 1: Maintain these bi ts clear in I2C mode.
SDA
SCL
DX-1DX
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON
CKP
Master device
deasserts clock
Master device
asserts clock
2004 Microchip Technology Inc. Preliminary DS41250A-page 177
PIC16F91X
15.0 CAPTURE/COMPARE/PWM
MODULES
Each Capture/Compare/PWM (CCP) module contains
a 16-bit register which can operate as a:
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cy cle register
Both the CCP1 and CCP2 modules are identical in
operatio n, with th e except ion being the operation of the
special event trigger. Table 15-1 and Table 15-2 show
the resources and interactions of the CCP module(s).
In the following sections, the operation of a CCP mod-
ule is described with respect to CCP1. CCP2 operates
the same as CCP1, except where noted.
CCP1 Mo dul e:
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is
generated by a compare match and will reset Timer1.
CCP2 Mo dul e:
Capture/Compare/PWM Register2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. The special event trigger is
generated by a compare match and will reset Timer1
and start an A/D conversion (if the A/D module is
enabled).
Additional information on CCP modules is available in
the “PICmicro® Mid-Range MCU Family Reference
Manual” (DS33023) and in Application Note AN594,
“Using the CCP Modules” (DS00594).
TABLE 15-1: CCP MODE - TIMER
RESOURCES REQUIRED
TABLE 15-2: INTERACTION OF TWO CCP MODULES
CCP Mode Timer Resource
Capture Timer1
Compare Timer1
PWM Timer2
CCPx Mode CCPy Mode Interaction
Capture Capture Same TMR1 time base
Capture Compare The compare should be configured for the special event trigger, which clears TMR1
Compare Compare The compare(s) should be configured for the special event trigger, which clears TMR1
PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt)
PWM Capture None
PWM Compare None
PIC16F91X
DS41250A-page 178 Preliminary 2004 Microchip Technology Inc.
REGISTER 15-1: CCP1CON – CCP2CON(1) REGISTER (ADDRESS: 17h/1Dh)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0
bit 7-6 Unimplemented: Re ad as ‘0’
bit 5-4 CCPxX:CCPxY: PWM Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0 CCPxM<3:0>: CCPx Mode Select bits
0000 = Capture/Compare/PWM disabl ed (resets CCPx module)
0100 = Capture mode, every falling e dge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit is set)
1001 = Compare mode, clear output on match (CCPxIF bit is set)
1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is
unaffected)
1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected);
CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module
is enabled)
11xx =PWM mode
Note 1: CCP2CON used for PIC16F914/917 only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Preliminary DS41250A-page 179
PIC16F91X
15.1 Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of th e TMR1 r egister wh en an event occurs
on pin RC5/T1CKI/CCP1/SEG10. An event is defined
as one of the following:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
The type of event is configured by control bits
CCP1M<3:0> (CCPxCON<3:0>). When a capture is
made, the interrupt request flag bit CCP1IF (PIR1<2>)
is set. The interrupt flag must be cleared in software. If
another capture occurs before the value in register
CCPR1 is read, the old captured va lue is overwritten by
the new value.
15.1.1 CCP PIN CONFIGURATION
In Capture mode, the RC5/T1CKI/CCP1/SEG10 pin
should be configured as an input by setting the
TRISC< 2> bit.
FIGURE 15-3: CAPTURE MODE
OPERATION BLOCK
DIAGRAM
15.1.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode, or Synchro-
nized Counter mode, for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture ope ration may not work.
15.1.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF, following any such
change in operati ng mode.
15.1.4 CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M<3:0>. Whenever the CCP module is turned
off, or the CCP module is not in Capture mode, the
prescaler counter is cleared. Any Reset will clear the
prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleare d, therefore , the first cap ture may be from
a non-zero prescaler. Example 15-1 shows the recom-
mended method for switching between capture pre-
scalers . This example also clears the prescaler co unter
and will not generate the “false” interrupt.
EXAMPLE 15-1: CHANGIN G BETWEEN
CAPTURE PRESCALERS
Note: If the RC5/T1CKI/CCP1/SEG10 pin is
configu red as an output, a wr ite to the port
can cause a cap ture cond itio n.
CCPR1H CCPR1L
TMR1H TMR1L
Set Flag bit CCP1IF
(PIR1<2>)
Capture
Enable
Qs CCP1CON<3:0>
RC5/T1CKI/
Prescaler
÷ 1, 4, 16
and
edge detect
pin
CCP1/SEG10
CLRF CCP1CON ; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load the W reg with
; the new prescaler
; move value and CCP ON
MOVWF CCP1CON ; Load CCP1CON with this
; value
PIC16F91X
DS41250A-page 180 Preliminary 2004 Microchip Technology Inc.
15.2 Compare Mode
In C ompare mo de, t he 16- bit CC PR1 re gist er va lue is
constantly compared against the TMR1 register pair
value. When a match occurs, the
RC5/T1C KI/ CCP1 /SEG 10 pin is:
• Driven high
•Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M<3:0> (CCP1CON<3:0>). At the same
time, interrupt flag bit CCP1IF is set.
FIGURE 15-4: COMPARE MODE
OPERATION BLOCK
DIAGRAM
15.2.1 CCP PIN CONFIGURATION
The user m ust configur e the RC5/T1CKI/CC P1/SEG10
pin as an output by clearing the TRISC<2> bit.
15.2.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode, or Synchro-
nized Counter mode, if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
15.2.3 SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen, the
RC5/T1CKI/CCP1/SEG10 pin is not affected. The
CCPIF bit is set, causing a CCP interrupt (if enabled).
15.2.4 SPECIAL EVENT TRIGGER
In this mod e, an internal hardw are trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 regi ste r pai r. T his allo ws t he C CPR 1 reg ist er t o
ef fectively b e a 16-bit progra mmable pe riod registe r for
Timer1.
The special event trigger output of CCP2 resets the
TMR1 regis ter pair and starts an A/D co nv ersi on (if the
A/D module is enabled).
Note: Clearing the CCP1CON register will force
the RC5/T1CKI/CCP1/SEG10 compare
output la tch to the de fault low lev el. This is
not the PORTC I/O data latch.
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
QS
ROutput
Logic
Special Event Trigger
Set Flag bit CCP1IF
(PIR1<2>)
Match
RC5/T1CKI/
TRISC<2> CCP1CON<3:0>
Mode Select
Output Enab le
pin
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
CCP1/SEG10
Note: The special event trigger from the
CCP1and CCP2 modules will not set inter-
rupt flag bit TMR1IF (PIR1<0>).
2004 Microchip Technology Inc. Preliminary DS41250A-page 181
PIC16F91X
15.3 PWM Mode (PWM)
In Pulse Width Modulation mode, the CCPx pin pro-
duces up to a 10-bit resolution PWM output. Since the
RC5/T1CKI/CCP1/SEG10 pin is multiplexed with the
PORTC data latch, the TRISC<2> bit must be cleared
to make the RC5/T1CKI/CCP1/SEG10 pin an output.
Figure 15-5 shows a simplified block diagram of the
CCP module in PWM mo de.
For a ste p-by-step proc edure on how t o set up the CC P
module for PWM operation, see Section 15.3.3
“Setup for PWM Operation”.
FIGURE 15-5: SIMPLIFIED PWM BLOCK
DIAGRAM
A PWM output (Figure 15-6) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 15-6: PWM OUTP UT
15.3.1 PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
PWM period = (PR2) + 1] • 4 • TOSC •
(TMR 2 pr e sc ale value)
PWM frequency is defined as 1 / [PWM period].
When TM R2 is equal to PR2, t he following three event s
occur on the next increment cycle:
•TMR2 is cleared
• The RC5/T1CKI/CCP1/SEG10 pin is set (excep-
tion: if PWM duty cycle = 0%, the
RC5/T1CKI/CCP1/SEG10 pin will not be set)
• The PWM duty cycle is latched from C CPR1L into
CCPR1H
15.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10- b i t re so l uti on is av ai l ab le. T he CC PR 1 L c ontai ns
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM duty cycle =(CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to dou ble buf fer th e PWM duty cycle. Thi s doubl e
buffering is essential for glitch-free PWM operation.
When t he CCP R1H an d 2-bit latch match T MR2, con-
catenate d with an in terna l 2-b it Q clo ck , or 2 bits of the
TMR2 pres caler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the formula:
Note: Clearing the CCP1CON register will force
the CCP1 PWM o utpu t latch to the defau lt
low level. This is not the PORTC I/O data
latch.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(1)
RQ
S
Duty Cycle Registers CCP1CON<5:4>
Clear Time r,
CCP1 pin and
latch D.C.
TRISC<2>
RC5/T1CKI/
Note 1: The 8-b it timer is concatenate d with 2-bit internal Q
clock, or 2 bits of the pr esca ler, to create 10-bit time
base.
CCP1/SEG10
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR 2
Note: The Timer2 postscaler (see Section 7.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
Note: If the PWM d uty c ycle v alu e i s lon ger tha n
the PWM period, the
RC5/T1CKI/CCP1/SEG10 pin will not be
cleared.
PWM Resolution
FOSC
FPWM TMR2 Prescaler×
-------------------------------------------------------------
log
2()log
--------------------------------------------------------------------------- bits=
PIC16F91X
DS41250A-page 182 Preliminary 2004 Microchip Technology Inc.
15.3.3 SETUP FOR PWM OPERA TIO N
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM pe riod by writing to the PR2
register.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the R C5 / T1C KI / CC P1/ SE G1 0 pi n an ou t -
put by clearing the TRISC<2> bit.
4. Set the TMR2 prescale value and enable T imer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
TABLE 15-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
TABLE 15-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFFh 0xFFh 0xFFh 0x3Fh 0x1Fh 0x17h
Maximum Resolution (bits) 10 10 10 8 7 5.5
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Valu e on
all other
Resets
0Bh,8Bh,
10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 OSFIF C2IF C1IF LCDIF —LVDIF — CCP2IF 0000 -0-0 0000 - 0-0
8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 OSFIE C2IE C1IE LCDIE —LVDIE — CCP2IE 0000 -0-0 0000 -0-0
87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
0Eh TMR1L Holding Regist er for the Leas t Signi fic ant Byt e of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Regist er for the Most Sign ificant Byte of t he 16-bit TMR1 Re gister xxxx xxxx uuuu uuuu
10h T1CON T1GINV T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuu u
15h CCPR1L Capture/Comp are/ PWM Registe r1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Comp are/ PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 000 0 --00 0000
1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 000 0
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
2004 Microchip Technology Inc. Preliminary DS41250A-page 183
PIC16F91X
TABLE 15-3: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR,
BOR
Value on
all oth er
Resets
0Bh,8Bh,
10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 OSFIF C2IF C1IF LCDIF —LVDIF —CCP2IF0000 -0-0 0000 -0-0
8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 00 00 0000 0000 0000
8Dh PIE2 OSFIE C2IE C1IE LCDIE —LVDIE —CCP2IE0000 -0-0 0000 -0-0
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
11h TMR2 T i m er 2 M o du l e ’s Re gi st er 0000 0000 0000 0000
92h PR2 Timer2 Module’s Period Register 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON —— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON —— CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 -- 00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.
PIC16F91X
DS41250A-page 184 Preliminary 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Preliminary DS41250A-page 185
PIC16F91X
16.0 SPECIAL FEATURES OF THE
CPU
The PIC16F91X has a host of features intended to
maximize system reliability, minimize cost through
elimination of external components, provide power
saving features and offer code protection.
These features are:
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Oscillator Selection
• Sleep
• Code Protection
• ID Locations
• In-Circuit Serial Programming
The PIC16F91X has two timers that offer necessary
delays on power-up. One is the Oscillator Start-up
Timer (O ST), intende d to keep t he chi p in Res et un til
the crystal oscillator is stable. The other is the
Power-up T imer (PWRT), which provides a fixed delay
of 64 ms (nominal) on power-up only, designed to
keep the part in Reset while the power supply
stabilizes. There is als o circu itry to re set the devi ce if
a brown-out occurs, which can use the Power-up
Timer to provide at least a 64 ms Reset. With these
three functions-on-chip, most applications need no
external Reset circuitry.
The Sleep mode is des igned to of fer a very l ow-c urrent
Power-down mode. The user can wake-up from Sleep
through:
•External Reset
• Watchdog Timer Wake-up
• An interrupt
Several oscillator options are also made available to
allow the p art to f it th e a ppl ic ati on. The INTOSC optio n
saves system cost, while the LP crystal option saves
power. A set of configuration bits are used to select
various option s (see Register 16-1).
PIC16F91X
DS41250A-page 186 Preliminary 2004 Microchip Technology Inc.
16.1 Configuration Bits
The configuration bits can be programmed (read as
‘0’), or left unpro grammed (r ead as ‘1’) to select various
device configurations as shown in Register 16-1.
These bits are mapped in program memory location
2007h.
REGISTER 16-1: CONFIG – CONFIGURATION WORD (ADDRESS: 2007h)
Note: Address 2007h is beyond the user
program memory space. It belongs to the
special configuration memory space
(2000h-3FFFh), which can be accessed
only during programming. See
“PIC16F91X Memory Programming
Specification” (DS41244) for more
information.
—DEBUGFCMEN IESO BOREN1 BOREN0 CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0
bit 13 bit 0
bit 13 Unimplemented: Read as ‘1’
bit 12 DEBUG: In-Circuit Debugger Mode bit
1 = In-Circuit Debugger disabled, RB6/ICSPCLK/ICDCK/SEG14 and RB7/ICSPDAT/ICDDAT/SEG13 are general purpose I/O pins
0 = In-Circuit Debugger enabled, RB6/ICSPCLK/ICDCK/SEG14 and RB7/ICSPDAT/ICDDAT/SEG13 are dedicated to the debugger
bit 11 FCMEN: Fail-Safe Clock Monitor Enabled bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
bit 10 IESO: Internal External Switchover bit
1 = Internal External Switchover mode is enabled
0 = Internal External Switchover mode is disabled
bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits(1)
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit (PCON<4>)
00 = BOR disabled
bit 7 CPD: Data Code Protection bit(2)
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
bit 6 CP: Code Protection bit(3)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 5 MCLRE: RB3/MCLR/VPP pin function select bit(4)
1 = RB3/MCLR/VPP pin function is MCLR
0 = RB3/MCLR/VPP pin function is digital input, MCLR internally tied to VDD
bit 4 PWRTE: Pow er-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 3 WDTE: W atchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled and can be enabled by SWDTEN bit (WDTCON<0>)
bit 2-0 FOSC<2:0>: Oscillator Selection bits
111 = RC oscillator: CLKO function on RA6/OSC2/CLKO/T1OSO pin, RC on RA7/OSC1/CLKI/T1OSI
110 = RCIO oscillator: I/O function on RA6/OSC2/CLKO/T1OSO pin, RC on RA7/OSC1/CLKI/T1OSI
101 = INTOSC oscillator: CLKO function on RA6/OSC2/CLKO/T1OSO pin, I/O function on RA7/OSC1/CLKI/T1OSI
100 = INTOSCIO oscillator: I/O function on RA6/OSC2/CLKO /T1OS O pin, I/O func tion on RA 7 /OSC1/CLK I/T1OSI
011 = EC: I/O function on RA6/OSC2/CLKO/T1OSO pin, CLKI on RA7/OSC1/CLKI/T1OSI
010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKO/T1OSO and RA7/OSC1/CLKI/T1OSI
001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKO/T1OSO and RA7/OSC1/CLKI/T1OSI
000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKO/T1OSO and RA7/OSC1/CLKI/T1OSI
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire data EEPROM will be erased when the code protection is turned off.
3: The entire program memory will be erased when the code protection is turned off.
4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
2004 Microchip Technology Inc. Preliminary DS41250A-page 187
PIC16F91X
16.2 Reset
The PIC16F91X differentiates between various kinds of
Reset:
a) P ower-on Reset (PO R)
b) WDT Reset during normal operation
c) WDT Reset during Sleep
d) MCLR Reset during normal operation
e) MCLR Reset during Sleep
f) Brown-out Reset (BOR)
Some regi sters a re not af fected in any Rese t conditio n;
their st at us is un kn ow n o n PO R and un ch anged in any
other Reset. Most other registers are reset to a “Reset
state” on:
• Power-on Reset
•MCLR
Reset
•MCLR Reset during Sleep
•WDT Reset
• Brown-out Reset (BO R)
They are not affected by a WDT wake-up since this is
viewed as the resump tion of normal opera tion . T O an d
PD bits are set or cleared differently in different Reset
situations, as indicated in Table 16-2. These bits are
used in software to determine the nature of the Reset.
See Table 16-5 for a full description of Reset states of
all registers.
A simplif ied block diagra m of the On-Chip Rese t Circu it
is sh own in Figure 16-1 .
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 19.0 “Electrical
Specifications” for pulse width specifications.
FIGURE 16-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External
Reset
MCLR/VPP pin
VDD
OSC1/
WDT
Module
VDD Rise
Detect
OST/PWRT
LFINTOSC
WDT
Time-out
Power-on Reset
OST
10-bit Ripple Counter
PWRT
Chip_Reset
11-bit Ripple Counter
Reset
Enable OST
Enable PWRT
SLEEP
Brown-out(1)
Reset SBOREN
BOREN
CLKI pin
Note 1: Refer to the Configuration Word register (Register 16-1).
PIC16F91X
DS41250A-page 188 Preliminary 2004 Microchip Technology Inc.
16.3 Power-on Reset
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper
operation. To take advantage of the POR, simply
connect the MCLR pin through a resistor to VDD. This
will eliminate external RC components usually needed
to create Power-on Reset. A maximum rise time for
VDD is required . See Section 19.0 “Elec trical Specifi-
cations” for details. If the BOR is enabled, the maxi-
mum rise time specification does not apply. The BOR
circuit ry will keep th e device in Reset u ntil VDD reache s
VBOR (see Section 16.3.3 “Brown-Out Reset
(BOR)”).
When the device starts normal operation (exits the
Reset condition), device operating parameters
(i.e., voltage, frequency, temperature, etc.) must be
met to ensure operation. If these conditions are not
met, the device must be held in Reset until the operat-
ing conditions are met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
16.3.1 MCLR
PIC16 F 91 X has a n oi se fi l t er in th e MC LR Rese t path.
The filter will de tect and ignore small pu lses .
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from early devices of this family.
Volt ages app li ed to the p in that ex ceed i ts s pecif icatio n
can resu lt in both MCLR Resets and excessiv e c urre nt
bey ond t h e de v ic e sp e ci fic at i on du ri ng th e ESD ev e nt .
For this rea son, Microc hip recomme nds that the MC LR
pin no long er be tied direc tly to VDD. The use of an RC
network, as sh own in Figure 16-2, is suggested.
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
clear e d, MC LR is internally tied to VDD and an internal
weak pull-up is enabled for the MCLR pin. In-Circuit
Serial Programming is not affected by selecting the
internal MCLR option.
FIGURE 16-2: RECOMMENDED MCLR
CIRCUIT
16.3.2 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from the 31 kHz
LFINTOSC oscillator. For more information, see
Section 3.4 “Internal Clock Modes” . The ch ip is ke pt
in Reset as long as PWRT is active. The PWRT delay
allows the VDD to rise to an acceptable level. A config-
uration bit, PWRTE, can disable (if set) or enable (if
cleared or programmed) the Power-up Timer. The
Power-up Timer should be enabled when Brown-out
Reset is enabled, although it is not required.
The Power-up Timer delay will vary from chip-to-chip
and vary due to:
•V
DD variation
• Temperature variation
• Process variation
See DC parameters for details (Section 19.0
“Electrical Specifications”).
Note: The POR circuit does not produce an
internal Reset when VDD declines. To
re-enable the POR, VDD must reach Vss
for a minimum of 100 µs.
VDD PIC16F91X
MCLR
R1
1kΩ (or greater)
C1
0.1 µF
(optional, not critical)
2004 Microchip Technology Inc. Preliminary DS41250A-page 189
PIC16F91X
16.3.3 BROWN-OUT RESET (BOR)
The BOREN0 and BOREN1 bits in the Configuration
Word register selects one of four BOR modes. Two
modes have been added to a llow softw are or hardwa re
control of the BOR enable. When BOREN<1:0> = 01,
the SBOREN bit (PCON<4>) enables/disables the
BOR allowing it to be controlled in software. By select-
ing BORE N<1:0>, the BO R is automa tically disabled in
Sleep to conserve power and enabled on wake-up. In
this mode, the SBOREN bit is disabled. See
Register 16-1 for the configuration word definition.
If VDD falls below VBOR for greater than parameter
(TBOR) (see Section 19.0 “Electrical Specifica-
tions”), the Brown-out situation will reset the device.
This will occur regardless of VDD slew rate. A Reset is
not insured to occur if VDD falls below VBOR for less
than para meter (TBOR).
On any Rese t (Power-on, Brown-out Reset, Watchdog
T imer , et c.), the ch ip will remai n in Reset until VDD rises
above VBOR (see Figure 16-3). The Power-up Timer
will no w be invoked , if enable d and will kee p the chip in
Reset an additional 64 ms.
If VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-u p Timer will be re-initialized. Onc e VDD
rises above VBOR, the Power-up Timer will execute a
64 ms Reset.
16.3.4 BOR CALIBRAT ION
The PIC16F91X stores the BOR calibration values in
fuses located in the Calibration Word (2008h). The
Calibration Word is not erased when using the speci-
fied bulk erase sequence in the “PIC16F91X Memory
Programm ing Specific ation” (DS41244) and thus, does
not require reprogramming.
FIGURE 16-3: BROWN-OUT SITUATIONS
Note: The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word.
Address 2008h is beyond the user program memory
space. It belongs to the special configuration memory
space (2000h-3FFFh), which can be accessed only
during programming. See “PIC16F91X Memory
Programming Specification” (DS41244) for more
information.
64 ms(1)
VBOR
VDD
Internal
Reset
VBOR
VDD
Internal
Reset 64 ms(1)
< 64 ms
64 ms(1)
VBOR
VDD
Internal
Reset
Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.
PIC16F91X
DS41250A-page 190 Preliminary 2004 Microchip Technology Inc.
16.3.5 TIME-OUT SEQUENCE
On power- up, the t ime-out sequ ence is a s follows: first,
PWR T time- out is invo ked aft er POR has expire d, then
OST is ac tiv ate d aft er the PWRT time-out has exp ire d.
The tot a l time -ou t wil l vary bas ed on os ci llator configu-
ration and PWRTE bit stat us. For exampl e, in EC mode
with PWRT E bit erased (PWR T di sa ble d), there will be
no time -out at all. Figure 16-4, Figure 16-5 and Figure
16-6 depict time-out sequences. The device can exe-
cute code from the INTOSC while OST is active, by
enablin g Two- Speed St art-up o r Fail-Safe Mo nitor (se e
Section 3.6.2 “Two-Speed Start-up Sequence” and
Section 3.7 “Fail-Safe Clock Monitor”).
Since the time-outs oc cur from the POR pulse, if MCLR
is kept low lon g enough, the time-out s will expire. Then,
bringing MCLR high will begin execution immediately
(see Figure 16-5). This is useful for testing purposes or
to synchronize more than one PIC16F91X device
operating in parallel.
Table 16-5 shows the Reset conditions for some
special registers, while Table 16-5 shows the Reset
conditions for all the registers.
16.3.6 POWER CONTROL (PCON)
REGISTER
The Power C ontro l (PCON) re gister (address 8Eh) ha s
two Status bits to indicate what type of Reset that last
occurred.
Bit 0 is BOR (Brown-out). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
indicating tha t a Brown-ou t has occurred. The BOR Sta-
tus bit is a “don’t care” and is not necessarily predictable
if the brown-out circuit is disabled (BOREN<1:0> = 00
in the Con fi g ura ti o n Word regist er).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaf fec ted oth erwise. T he user m ust write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., VDD may have
gone too low).
For more inf ormation, see Section 16.3.3 “Brown-Out
Reset (BOR)”.
TABLE 16-1: TIME-OUT IN VARIOUS SITUATIONS
TABLE 16-2: PCON BITS AND THEIR SIGNIFICANCE
TABLE 16-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Oscillator Configuration Power-up Brown-out Reset Wake-up
from Sleep
PWRTE = 0PWRTE = 1PWRTE = 0PWRTE = 1
XT, HS, LP(1) TPWRT + 1024
• TOSC 1024 • TOSC TPWRT + 1024
• TOSC 1024 • TOSC 1024 • TOSC
RC, EC, INTOSC TPWRT —TPWRT ——
Note 1: LP mode with T1O SC disa ble d.
POR BOR TO PD Condition
0u11Power-on Re set
1011Brown-out Reset
uu0uWDT Reset
uu00WDT Wake-up
uuuuMCLR Reset during normal operation
uu10MCLR Reset during Sleep
Legend: u = unchanged, x = unknown
Address Na m e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets(1)
03h STATUS IRP RP1 RPO TO PD ZDC C0001 1xxx 000q quuu
8Eh PCON — — — SBOREN ——PORBOR --01 --qq --0u --uu
Legend: u = unc hanged, x = unknown, — = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are
not used by BOR.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Tim er Res et during normal operation.
2004 Microchip Technology Inc. Preliminary DS41250A-page 191
PIC16F91X
FIGURE 16-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1
FIGURE 16-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2
FIGURE 16-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD): CASE 3
TPWRT
TOST
VDD
MCLR
Internal POR
PWRT T ime-out
OST Time-out
Internal Reset
VDD
MCLR
Internal POR
PWRT Tim e-out
OST Time-out
Internal Reset
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
Internal POR
PWRT Tim e-out
OST Time-out
Internal Reset
PIC16F91X
DS41250A-page 192 Preliminary 2004 Microchip Technology Inc.
TABLE 16-4: INITIALIZATION CONDITION FOR REGISTERS
Register Address Power-on
Reset
•MCLR Reset
•WDT Reset
•Brown-out Reset(1)
•Wake-up from Sleep
through interrupt
•Wake-up from Sleep
through WDT time-out
W—xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h/80h/
100h/180h xxxx xxxx xxxx xxxx uuuu uuuu
TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h/82h/
102h/182h 0000 0000 0000 0000 PC + 1(3)
STATUS 03h/83h/
103h/183h 0001 1xxx 000q quuu(4) uuuq quuu(4)
FSR 04h/84h/
104h/184h xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 05h xxxx xxxx 0000 0000 uuuu uuuu
PORTB 06h/106h xxxx xxxx 0000 0000 uuuu uuuu
PORTC 07h xxxx xxxx 0000 0000 uuuu uuuu
PORTD 08h xxxx xxxx 0000 0000 uuuu uuuu
PORTE 09h ---- xxxx ---- 0000 ---- uuuu
PCLATH 0Ah/8Ah/
10Ah/18Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 0Bh/8Bh/
10Bh/18Bh 0000 000x 0000 000x uuuu uuuu(2)
PIR1 0Ch 0000 0000 0000 0000 uuuu uuuu(2)
PIR2 0Dh 0000 -0-0 0000 -0-0 uuuu -u-u
TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 10h 0000 0000 uuuu uuuu uuuu uuuu
TMR2 11h 01-0 0-00 01-0 0-00 uu-u u-uu
T2CON 12h -000 0000 -000 0000 -uuu uuuu
SSPBUF 13h xxxx xxxx xxxx xxxx uuuu uuuu
SSPCON 14h 0000 0000 0000 0000 uuuu uuuu
CCPR1L 15h 0000 0000 0000 0000 uuuu uuuu
CCPR1H 16h 0000 0010 0000 0010 uuuu uuuu
CCP1CON 17h 000x 000x 000x 000x uuuu uuuu
RCSTA 18h ---0 1000 ---0 1000 ---u uuuu
TXREG 19h 0000 0000 0000 0000 uuuu uuuu
RCREG 1Ah 0000 0000 0000 0000 uuuu uuuu
CCP2CON 1Dh --00 0000 --00 0000 --uu uuuu
ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu
Legend: u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
4: See Table 16-5 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All ot her Resets will cause bit 0 = u.
2004 Microchip Technology Inc. Preliminary DS41250A-page 193
PIC16F91X
ADCON0 1Fh 0000 0000 0000 0000 uuuu uuuu
OPTION_REG 81h/181h 1111 1111 1111 1111 uuuu uuuu
TRISA 85h 1111 1111 1111 1111 uuuu uuuu
TRISB 86h/186h 1111 1111 1111 1111 uuuu uuuu
TRISC 87h 1111 1111 1111 1111 uuuu uuuu
TRISD 88h 1111 1111 1111 1111 uuuu uuuu
TRISE 89h 1111 1111 1111 1111 uuuu uuuu
PIE1 8Ch 0000 0000 0000 0000 uuuu uuuu
PIE2 8Dh 0000 0000 0000 0000 uuuu uuuu
PCON 8Eh --01 --0x --0u --uu(1,5) --uu --uu
OSCCON 8Fh -110 q000 -110 x000 -uuu uuuu
OSCTUNE 90h ---0 0000 ---u uuuu ---u uuuu
ANSEL 91h 1111 1111 1111 1111 uuuu uuuu
PR2 92h 1111 1111 1111 1111 1111 1111
SSPADD 93h 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 94h 0000 0000 0000 0000 uuuu uuuu
WPUB 95h 1111 1111 1111 1111 uuuu uuuu
IOCB 96h 0000 ---- 0000 ---- uuuu ----
CMCON1 97h ---- --10 ---- --10 ---- --uu
TXSTA 98h 0000 -010 0000 -010 uuuu -uuu
SPBRG 99h 0000 0000 0000 0000 uuuu uuuu
CMCON0 9Ch 0000 0000 0000 0000 uuuu uuuu
VRCON 9Dh 0-0- 0000 0-0- 0000 u-u- uuuu
ADRESL 9Eh xxxx xxxx uuuu uuuu uuuu uuuu
ADCON1 9Fh -000 ---- -000 ---- -uuu ----
WDTCON 105h ---0 1000 ---0 1000 ---u uuuu
LCDCON 107h 0001 0011 0001 0011 uuuu uuuu
LCDPS 108h 0000 0000 0000 0000 uuuu uuuu
LVDCON 109h --00 -100 --00 -100 --uu -uuu
EEDATL 10Ch 0000 0000 0000 0000 uuuu uuuu
EEADRL 10Dh 0000 0000 0000 0000 uuuu uuuu
EEDATH 10Eh --00 0000 0000 0000 uuuu uuuu
EEADRH 10Fh ---0 0000 0000 0000 uuuu uuuu
LCDDATA0 110h xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA1 111h xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA2 112h xxxx xxxx uuuu uuuu uuuu uuuu
Legend: u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
4: See Table 16-5 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All ot her Resets will cause bit 0 = u.
TABLE 16-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Register Address Power-on
Reset
•MCLR Reset
•WDT Reset
•Brown-out Reset(1)
•Wake-up from Sleep
through interrupt
•Wake-up from Sleep
through WDT time-out
PIC16F91X
DS41250A-page 194 Preliminary 2004 Microchip Technology Inc.
TABLE 16-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
LCDDATA3 113h xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA4 114h xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA5 115h xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA6 116h xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA7 117h xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA8 118h xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA9 119h xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA10 11Ah xxxx xxxx uuuu uuuu uuuu uuuu
LCDDATA11 11Bh xxxx xxxx uuuu uuuu uuuu uuuu
LCDSE0 11Ch 0000 0000 uuuu uuuu uuuu uuuu
LCDSE1 11Dh 0000 0000 uuuu uuuu uuuu uuuu
LCDSE2 11Eh 0000 0000 uuuu uuuu uuuu uuuu
EECON1 18Ch x--- x000 u--- q000 u--- uuuu
Legend: u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
4: See Table 16-5 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All ot her Resets will cause bit 0 = u.
TABLE 16-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Register Address Power-on
Reset
•MCLR Reset
•WDT Reset
•Brown-out Reset(1)
•Wake-up from Sleep
through interrupt
•Wake-up from Sleep
through WDT time-out
Condition Program
Counter Status
Register PCON
Register
Power-on Reset 000h 0001 1xxx --01 --0x
MCLR Reset during normal operation 000h 000u uuuu --0u --uu
MCLR Reset during Sleep 000h 0001 0uuu --0u --uu
WDT R eset 000h 0000 uuuu --0u --uu
WDT Wake-up PC + 1 uuu0 0uuu --uu --uu
Brown-out Reset 000h 0001 1uuu --01 --10
Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu --uu --uu
Legend: u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’.
Note 1: When the w ake-up is due to an interrupt and Gl obal Interrup t Enable bit, G IE, is set, the PC is loade d with
the interrupt vector (0004h) after execution of PC + 1.
2004 Microchip Technology Inc. Preliminary DS41250A-page 195
PIC16F91X
16.4 Interrupts
The PIC16F91X has multiple sources of interrupt:
• External Inte rrup t RB0/INT/SEG0
• TMR0 Overfl ow Interru pt
• PORTB Change Interrupts
• 2 Comparator Interrupts
• A/D Interrupt
• Timer1 Overflow Interrupt
• EEPROM Data Write Interrupt
• Fail-Safe Clock Monitor Interrupt
• LCD Interrupt
• PLVD Interrupt
• USART Receive and Transmit interrupts
• CCP1 and CCP2 Interrupts
• TMR2 Interrupt
The Interrup t Control (INTCON) register and Peripheral
Interrupt Request 1 (PIR1) register record individual
interrupt requests in flag bits. The INTCON register
also has individual and global interrupt enable bits.
A Global Interrupt Enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in the
INTCON register and PIE1 register. GIE is cleared on
Reset.
The Return from Interrupt instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, wh ich
re-enable s unm as ke d inte rrupts.
The following interrupt flags are contained in the
INTCON register:
• INT Pin Interrupt
• PORTB Change Interrupt
• TMR0 Overfl ow Interru pt
The per ipheral interrupt fl ags are co ntaine d in the sp ecial
registers, PIR1 and PIR2. The corresponding interrupt
enable bit are contained in the special registers, PIE1
and PIE2.
The follow ing interrupt flags are contained in the PIR1
register:
• EEPROM Data Write Interrupt
• A/D Interrupt
• USART Receive and Transmit Interrupts
• Timer1 Overflow Interrupt
• CCP1 Interrupt
• SSP Interrupt
The following interrupt flags are contained in the PIR2
register:
• Fail- Safe Clock Monitor Interrupt
• Comparator 1 and 2 Interrupts
• LCD Interrupt
• PLVD Interrupt
• CCP2 Interrupt
When an interrupt is serviced:
• The GIE is c lea red t o di sa ble any fu rthe r int errup t.
• The return address is pushed onto the stac k.
• The PC is loaded with 0004h.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 16-8). The latency is the same for one or
two-cycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
For additional information on Timer1, A/D or data
EEPROM modules, refer to the respective peripheral
section.
Note 1: Individual interrupt flag bits are set,
regardless of the status of their
corresponding mask bit or the GIE bit.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts, which were
ignored, are still pending to be serviced
when the GIE bit is set again.
Note: The ANSEL (91h) and CMCON0 (9Ch)
registers must be initialized to configure
an analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
Also, if a LCD output function is active on
an external interrupt pin, that interrupt
function will be disabled.
PIC16F91X
DS41250A-page 196 Preliminary 2004 Microchip Technology Inc.
16.4.1 RB0/INT/S EG0 INTER RUPT
External interrupt on RB0/INT/SEG0 pin is edge-trig-
gere d; eith er rising if the I NTEDG b it (OPTIO N<6>) is
set, or falling, if the INTEDG bit is clear. When a valid
edge appears on the RB0/INT/SEG0 pin, the INTF bit
(INTCON<1>) is set. This interrupt can be disabled by
clear ing th e INTE control bit (IN TCON<4> ). The I NTF
bit must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The
RB0/INT/SEG0 interrupt can wake-up the processor
from Sleep if the INTE bit was set prior to going into
Sleep. The st atus of the GIE b it dec ides wh ether or n ot
the proces sor branches to the inter rupt vector follow ing
wake-up (0004h). See Section 16.7 “Power-Down
Mode (Sleep)” for details on Sleep and Figure 16-10
for timing of wake-up from Sleep through
RB0/INT/SEG0 int errupt.
16.4.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
the T0IF (INTCON<2>) bit. The interrupt can be
enabled/disabled by setting/clearing T0IE
(INTCON<5>) bit. Se e Section 5.0 “Timer0 Module”
for operation of the Timer0 module.
16.4.3 PORTB INTERRUPT
An input change on PORTB change sets the RBIF
(INTCON<0>) bit. The interrupt can be
enabled/disabled by setting/clearing the RBIE
(INTCON<3>) bit. Plus, individual pins can be config-
ured through the IOCB register.
FIGURE 16-7: INTERRUPT LOGIC
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF
interrupt flag may not get set.
TMR1IF
TMR1IE
C1IF
C1IE
TMR0IF
TMR0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake-up (If in Sleep mode)
Inte rr u p t to CPU
PEIF
EEIE
EEIF
ADIF
ADIE
IOC-RB4
IOCB4
IOC-RB5
IOCB5
IOC-RB6
IOCB6
IOC-RB7
IOCB7
CCP2IF
CCP2IE
OSFIF
OSFIE
C2IF
C2IE
CCP1IF
CCP1IE
*
SSPIE
SSPIF
RCIF
RCIE
TXIF
TXIE
LCDIF
LCDIE
LVDIF
LVDIE
TMR2IF
TMR2IE
*Only available on the PIC16F914/917.
2004 Microchip Technology Inc. Preliminary DS41250A-page 197
PIC16F91X
FIGURE 16-8: INT PIN INTERRUPT TIMING
TABLE 16-6: SUMMARY OF INTERRUPT REGISTERS
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
Resets
0Bh,
8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 OSFIF C2IF C1IF LCDIF —LVDIF — CCP2IF 0000 -0-0 0000 -0-0
8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 OSFIE C2IE C1IE LCDIE —LVDIE — CCP2IE 0000 -0-0 0000 -0-0
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cell s are not us ed by the inte rrup t modu le.
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
OSC1
CLKO(3)
INT pin
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency
PC PC + 1 PC + 1 0004h 0005h
Inst (0004h) Inst (0005h)
Dummy Cycl e
Inst (PC) Inst (PC + 1)
Inst (PC - 1) Inst (0004h)
Dummy Cycl e
Inst ( PC)
—
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interru pt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycl e time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKO is available only in INTOS C and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 19.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
(1) (2)
(4)
(5)
(1)
PIC16F91X
DS41250A-page 198 Preliminary 2004 Microchip Technology Inc.
16.5 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W and Status
registers). This must be implemented in software.
Since the lower 16 bytes of all banks are common in the
PIC16F91X (see Figure 2-3), temporary holding
registers, W_TEMP and STATUS_TEMP, should be
placed in here. These 16 locations do not require
banking and therefore, make it easier to context save
and restore. The same code shown in Example 16-1
can be used to:
• Store the W register
• Store the Status register
• Execute the ISR code
• Restore the Status (and Bank Select Bit register)
• Restore the W register
EXAMPLE 16-1: SAVING STATUS AND W REGISTERS IN RAM
Note: The PIC16F91X n ormally d oes not require
saving the PCLATH. However, if
computed GOTO’s are u sed in the ISR and
the main code, the PCLATH must be
saved and restored in the ISR.
MOVWF W_TEMP ;Copy W to TEMP register
SWAPF STATUS,W ;Swap status to be saved into W
CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
:
:(ISR) ;Insert user code here
:
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into Status register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W
2004 Microchip Technology Inc. Preliminary DS41250A-page 199
PIC16F91X
16.6 Watchdog Timer (WDT)
For PIC16F91X, the WDT has been modified from
previous PIC16F devices. The new WDT is code and
functionally compatible with previous PIC16F WDT
modul es a n d ad ds a 1 6 - bi t p r es ca l er to t he W D T. T h is
allow s the user to have a scaled value for the WDT and
TMR0 at the same time . In addition, the WDT time-out
value c an be extend ed to 268 se conds. WDT is cleared
under certain conditions described in Table 16-7.
16.6.1 WDT OSCILLAT OR
The WDT derives its time base from the 31 kHz
LFINTOSC. The LTS bit does not reflect that the
LFINTOSC is enabled.
The va lue of WDTCON is ‘---0 1000’ on all Resets.
This gives a nominal time base of 16 ms, which is
compatible with the time base generated with previous
PIC16F microcontroller versions.
A new prescaler has been added to the path between
the INTOSC and the multiplexers used to select the
path for the WDT. This prescaler is 16 bits and can be
programmed to divide the INTOSC by 32 to 65536,
giving the WDT a nominal range of 1 ms to 268s.
16.6.2 WDT CONTROL
The WDTE bit is located in the Configuration Word
register. When set, the WDT runs continuously.
When the WDTE bi t in the Configuratio n Word re gister
is set, t he SWDTEN bit (WDTC ON<0>) ha s no effect.
If WDTE is c le ar, th en th e SWDT EN bi t ca n be us ed to
enable a nd disable the WDT. Setting th e bit will enable
it and clearing the bit will disable it.
The PSA and PS<2:0> bits (OPTION_REG) have the
same function as in previous versions of the PIC16F
family of microcontrollers. See Section 5.0 “Timer0
Module” for more information.
FIGURE 16-9: WATC HDOG TIMER BLOCK DIAGRAM
Note: When the Oscillator Start-up Timer (OST)
is invoked, the WDT is held in Reset,
bec ause the WD T Ri pple C ounte r i s us ed
by the OST to perform the oscillator delay
count. When the OST count has expired,
the WDT will begin counting (if enabled).
TABLE 16-7: WDT STATUS
Conditions WDT
WDTE = 0
Cleared
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST
31 kHz
PSA
16-bit WDT Prescaler
From TMR0 Clock Source
Prescaler(1)
8
PS<2:0>
PSA
WDT Time-out
To TMR0
WDTPS<3:0>
WDTE from Configuration Word register
1
1
0
0
SWDTEN from WDTCON
LFINTOSC Clock
Note 1: This is the shared Timer0/WDT prescaler . See Section 5.4 “Prescaler” for more information.
PIC16F91X
DS41250A-page 200 Preliminary 2004 Microchip Technology Inc.
REGISTER 16-2: WDTCON – W ATCHDOG TIMER CONTROL REGISTER (ADDRESS: 105h)
TABLE 16-8: SUMMARY OF WATCHDOG TIMER REGISTERS
U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0
— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN
bit 7 bit 0
bit 7-5 Unimplemented: Read as ‘0’
bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits
Bit Value = Prescale Rate
0000 = 1:32
0001 = 1:64
0010 = 1:128
0011 = 1:256
0100 = 1:512 (Reset value)
0101 = 1:1024
0110 = 1:2048
0111 = 1:4096
1000 = 1:8192
1001 = 1:16384
1010 = 1:32768
1011 = 1:65536
1100 = reserved
1101 = reserved
1110 = reserved
1111 = reserved
bit 0 SWDTEN: Software Enable or Disable the Watchdog Timer bit(1)
1 = WDT is turned on
0 = WDT is turned off (Reset value)
Note 1: If WDTE configuration bit = 1, then WDT is always enabled, irrespective of this
control bit. If WDTE c onfi guratio n bit = 0, then i t is p ossib le to turn WDT on/off wi th
this control bit.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
18h WDTCON — — — WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
2007h(1) CONFIG CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 16-1 for operation of all Configuration Word register bits.
2004 Microchip Technology Inc. Preliminary DS41250A-page 201
PIC16F91X
16.7 Power-Down Mode (Sleep)
The Power-down mode is entered by executing a
SLEEP instruction.
If the Watchdog Timer is enabled:
• WDT will be cleared but keeps running.
•PD
bit in the Status register is cleared.
•TO
bit is set.
• Oscillator driver is turned off.
• I/O ports maintain the status they had before
SLEEP was executed (driving high, low or
high-impedance).
For lowest current consumption in this mode, all I/O
pins should be either at VDD or VSS, with no external
circuitry drawing current from the I/O pin, and the
comparators and CVREF should be disabled. I/O pins
that are high-impedance inputs should be pulled high
or low ex ternally to avoid switching currents caused b y
floating inputs. The T0CKI input should also be at VDD
or VSS for lowest current consumption. The
contribution from on-chip pull-ups on PORTB should be
considered.
The MCLR pin must be at a logic high level.
16.7.1 WAKE-UP FROM SLEEP
The devi ce can wake -up from Sleep through one of th e
following events:
1. External Re set input on MCLR pin.
2. Watchdog Timer wake-up (if WDT was
enabled).
3. Interrupt from RB0/INT/SEG0 pin, PORTB
change or a peripheral interrupt.
The firs t event wi ll cause a devic e Reset. The two latter
events are considered a continuation of program
execution. The TO and PD bits in the Status register
can be used to determine the cause of device Reset.
The PD bit, whic h is se t on power -up, is cl eare d wh en
Sleep is invoked. TO bit is cleared if WDT wake-up
occurred.
The follo wing periph eral interrupt s can wake the device
from Sleep:
1. TMR1 Interrupt. T imer1 must be operatin g as an
asynchronous counter.
2. EUSART Receive Interrupt
3. A/D conversion (when A/D clock source is RC)
4. EEPROM write operation completion
5. Comparator output changes state
6. Interrupt-on-change
7. External Interrupt from INT pin
Other peripherals cannot generate interrupts since
during Sleep, no on-chip clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up thro ugh an interrupt event, the co rres pon din g
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (dis abled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction, then branches to the interrupt
address (0004h). In cases where the execution of the
instruction following SLEEP is not desirable, the user
should hav e a NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the so urce of wake-up.
16.7.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and inte rrupt fla g bit s et, one of the fo llow ing wil l occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will
comple te as a NOP. Therefore, the WDT an d WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
• If the interrupt occurs during or after the
execution of a SLEEP instructio n, the dev ic e will
immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. The refore, the WDT and WDT pres caler
and pos tsc aler (if enable d) wi ll be c leared , the T O
bit will be set and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine w hether a SLEEP instr uctio n executed , test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instru ction
should be executed before a SLEEP instru ction.
Note: It should be noted that a Reset generated
by a WDT time-out does not drive MCLR
pin low.
Note: If the g lobal interrup ts a re disa bled (G IE is
cleared ), but any interrup t source has bo th
it s interrupt enabl e bit and the corres pond-
ing interrupt flag bits set, the device will
immediately wake-up from Sleep. The
SLEEP instruction is comple tely executed.
PIC16F91X
DS41250A-page 202 Preliminary 2004 Microchip Technology Inc.
FIGURE 16-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1(1)
CLKO(4)
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
PC PC + 1 PC + 2
Inst(PC) = Sleep
Inst(PC - 1)
Inst(PC + 1)
Sleep
Processor in
Sleep
Interrupt Latency(3)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Dummy Cycle
PC + 2 0004h 0005h
Dummy Cycle
TOST(2)
PC + 2
Note 1: XT, HS or LP Oscillator mode assume d.
2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes.
3: GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execut i on will cont i nue in-lin e.
4: CLKO is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
2004 Microchip Technology Inc. Preliminary DS41250A-page 203
PIC16F91X
16.8 Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out usin g ICSP for verific ation purposes.
16.9 ID Locations
Four memo ry locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are
readable and writable during Program/Verify mode.
Only the Least Significant 7 bits of the ID locations are
used.
16.10 In-Ci rcuit Serial Programming
The PIC16F91X microcontrollers can be serially
progra mmed w hile in t he en d app licati on c ircuit. This i s
simply done with tw o lines for cl ock and data and thre e
other lines for:
• power
• ground
• programming voltage
This allows customers to manufacture boards with
unprogrammed devices and then program the micro-
controller just before shipping the product. This also
allows the mos t recent firmware or a custom firmware
to be programmed.
The device is placed into a Program/Verify mode by
holding the RB7/ICSPDAT/ICDDAT/SEG13 and
RB1/SEG1 pins low, while raising the MCLR (VPP) pin
from VIL to VIHH. See “PIC16F91X Memory Programming
Specification” (DS41244) for more information.
RB7/ICSPDAT/ICDDAT/SEG13 becomes the
programming data and RB6/ICSPCLK/ICDCK/SEG14
becomes the programming clock. Both
RB7/ICSPDAT/ICDDAT/SEG13 and
RB6/ICSPCLK/ICDCK/SEG14 are Schmitt Tr igger inputs
in this mode.
After Reset, to place the device into Program/Verify
mode, th e Pr ogram Cou nte r (P C) i s at l oca tio n 00h . A
6-bit command is then supplied to the device.
Depending on the command, 14 bits of program data
are then supplied to or from the device, depending on
whether the command was a load or a read. For
comple te d et a ils of s eri al p r ogr am mi ng, p lea se refe r to
the “PIC16F91X Memory Programming Specification”
(DS41244).
A typical In-Circuit Serial Programming connection is
shown in Figure 16-11.
FIGURE 16-11: TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
Note: The entire data EEPROM and Flash
program memory will be erased when the
code protection is turned off. See the
“PIC16F91X Memory Programming
Specification” (DS41244) for more infor-
mation. External
Connector
Signals
To Normal
Connections
To Normal
Connections
PIC16F91X
VDD
VSS
RE3/MCLR/VPP
RB6/ICSPCLK/
RB7/ICSPDATA/
+5V
0V
VPP
CLK
Data I/O
* * *
*
* Isolation devices (as required)
ICDCK/SEG14
ICDDAT/SEG13
PIC16F91X
DS41250A-page 204 Preliminary 2004 Microchip Technology Inc.
16.11 In-Circuit Debugger
The PIC16F91X-ICD can be used in any of the pack-
age types. The device will be mounted on the target
application board, which in turn has a 3 or 4 wire con-
nec tion to the ICD tool .
When the debug bit in the Configuration Word
(CONFIG<12>) is programmed to a ‘0’, the In-Circuit
Debug ger fun ct ion ali ty is enabled. This funct ion allo ws
simple debugging functions when used with MPLAB®
ICD 2. When the microcontroller has this feature
enabled, some of the resources are not available for
general use. See Table 16-9 for more detail.
For more information, see “Using MPLAB® ICD 2”
(DS51265), available on Microchip’s web site
(www.microchip.com).
16.11.1 ICD PINOUT
The devices in the PIC16F91X family carry the
circuitry for the In-Circuit Debugger on-chip and on
existing device pins. This eliminates the need for a
sepa rate di e or p acka ge for th e ICD d evice . The pi nout
for the ICD device is the same as the devices (see
Section 1.0 “Device Overview” for complete pinout
and pin descriptions). Table 16-9 shows the location
and function of the ICD related pins on the 28 and 40
pin devices.
TA BLE 16-9: PIC16F91X-ICD PIN DESCRIPTIONS
Note: The user’s application must have the
circuitry required to support ICD
functionality. Once the ICD circuitry is
enabled, normal device pin functions on
RB6/ICSPCLK/ICDCK/SEG14 and
RB7/ICSPDAT/ICDDAT/SEG13 will not be
usable. The ICD circuitry uses these pins for
communication with the ICD2 external
debugger.
Pin (PDIP) Name Type Pull-up Description
PIC16F914/917 PIC16F913/916
40 28 ICDDATA TTL — In Circuit Debugger Bidirectional data
39 27 ICDCLK ST — In Circuit Debugger Bidirectional clock
11MCLR / VPP HV — Programming voltage
11,32 20 VDD P—
12,31 8,19 VSS P—
Legend: TTL = TTL input bu ffer, ST = Schmitt Trigger input buffer, P = Power, HV = High Voltage
2004 Microchip Technology Inc. Preliminary DS41250A-page 205
PIC16F91X
17.0 INSTRUCTION SET SUMMARY
The PIC16F91X instruction set is highly orthogon al and
is comprised of three basic categories:
•Byte-oriented operations
•Bit-oriented operations
•Literal and cont rol operations
Each PIC16 instruction is a 14-bit word divided into an
opcode, which specifi es the instruction type and one or
more operands, which further specify the operation of
the instruction. The formats for each of the categories
is presented in Figure 17-1, while the various opcode
fields are sum m ariz ed in Table 17-1.
Table 17-2 lists the instructions recognized by the
MPASMTM assembler. A complete description of each
instruction is also available in the “PICmicro®
Mid-Range MCU Family Reference Manual”
(DS33023).
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The desti nation designator specifies where the result of
the operation is to be placed. If ‘d’ is zer o , t he r e su lt is
placed in the W re gister . If ‘ d’ is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the
operatio n, whi le ‘f’ re pre sen t s t he ad dres s o f the file i n
which the bit is located.
For literal and control operations, ‘k’ represents an
8-bit or 11-bit constant, or literal value.
One instr uction cycle co nsists of four os cillator periods ;
for an oscillator frequency o f 4 MHz, t his gives a normal
instruction execution time of 1 µs. All instructions are
executed within a single instruction cycle, unless a
conditional test is true, or the program counter is
change d as a result of an instruction. When this occurs,
the execution takes two instruction cycles, with the
second cycle executed as a NOP.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
17.1 READ-MODIFY-WRITE
OPERATIONS
Any instruction that specifies a file register as part of
the instruction performs a Read-Modi fy-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion, or the destination designator ‘d’. A read operation
is performe d on a register even if the instruction writes
to that register.
For exam pl e, a CLRF G PIO in st ruc tion will read G P IO,
clear all the data bits, then write the result back to
GPIO. This example w ould have the unintended result
of clearing the condition that set the GPIF flag.
TABLE 17-1: OPCODE FIELD
DESCRIPTIONS
Note: To maintain upward compatibility with
future products, do not use the OPTION
and TRIS instructions.
Field Description
fRegister file address (0x00 to 0x 7F)
WWorking register (accumulator)
bBit address within an 8-bit file register
kLiteral field, constant data or label
xDon’t care location (= 0 or 1).
The asse mbler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
dDestination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
PC Program Counter
TO Time-out bit
PD Power-down bit
PIC16F91X
DS41250A-page 206 Preliminary 2004 Microchip Technology Inc.
FIGURE 17-1: GENERAL FORMAT FOR
INSTRUCTIONS
Byte-orie nted file register operations
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operati ons
13 10 9 7 6 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (l i te ra l )
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
General
CALL and GOTO instructions only
2004 Microchip Technology Inc. Preliminary DS41250A-page 207
PIC16F91X
TABLE 17-2: PIC16F91X INSTRUCTION SET
Mnemonic,
Operands Description Cycles 14-B it Opcod e Status
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
-
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f thr ough Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1, 2
1, 2
2
1, 2
1, 2
1, 2, 3
1, 2
1, 2, 3
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Sk ip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1, 2
1, 2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Wat chdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return fro m interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a f unct ion of itself (e.g., MOVF GPIO, 1), the value used will be that value pr esent
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PICmicro® Mid-Range MCU
Family Reference Manual” (DS33023).
PIC16F91X
DS41250A-page 208 Preliminary 2004 Microchip Technology Inc.
17.2 Instruction Descriptions
ADDLW Add Literal and W
Syntax: [ label ] ADDLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) + k → (W)
Status Affected: C, DC, Z
Description: The contents of the W register
are added to the eight-bit literal ‘k’
and the result is placed in the W
register.
ADDWF Add W and f
Syntax: [ label ] ADDWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) + (f) → (destination)
Status Affected: C, DC, Z
Desc ription: Add the conten ts of the W regis ter
with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W registe r . I f
‘d’ is ‘1’, the result is stored back
in register ‘f’.
ANDLW AND Litera l with W
Syntax: [ label ] ANDLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .AND. (k) → (W)
Status Affected: Z
Description: The contents of W register are
AND’ed with the eight-bit literal
‘k’. The result is place d in the W
register.
ANDWF AND W with f
Syntax: [ label ] ANDWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .AND. (f) → (destination)
Status Affected: Z
Description: AND the W register with register
‘f’. If ‘d’ is ‘0’, the resu lt is stored in
the W register. If ‘d’ is ‘1’, the
result is sto r ed bac k in regi ste r ‘f’.
BCF Bit Clear f
Syntax: [ label ] BCF f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: 0 → (f<b>)
Status Affected: None
Description: Bit ‘b’ in register ‘f’ is cleared.
BSF Bit Set f
Syntax: [ label ] BSF f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: 1 → (f<b>)
Status Affected: None
Description: Bit ‘b’ in register ‘f’ is set.
BTFSC Bit Test, Skip if Clear
Syntax: [ label ] BTFSC f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation: skip if (f<b>) = 0
Status Affected: None
Descr iption: If bit ‘b’ in regi ster ‘f’ is ‘1’, the next
instructi on is ex ecuted.
If bit ‘b’, in register ‘f’, is ‘0’, the
next instruction is discarded, and
a NOP is ex ecuted instead , making
this a two-cycle instruction.
2004 Microchip Technology Inc. Preliminary DS41250A-page 209
PIC16F91X
BTFSS Bit Test f, Skip if Set
Syntax: [ label ] BTFSS f,b
Operands: 0 ≤ f ≤ 127
0 ≤ b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Desc ription: If bit ‘b’ in register ‘f’ is ‘0’ , the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next
inst ruc tion is di sc ard ed and a NOP
is exec ute d ins te ad, m ak in g thi s a
two-cycle instruction.
CALL Call Subroutine
Syntax: [ label ] CALL k
Operands: 0 ≤ k ≤ 2047
Operation: (PC)+ 1→ TOS ,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Status Affected: None
Description: Call Subroutine. First, return
address (PC + 1) is pushed onto
the stack. The eleven-bit
immediate address is loaded into
PC bits <10:0>. The upper bits of
the PC are loa ded from PC LATH.
CALL is a two-cycle instruction.
CLRF Clear f
Syntax: [ label ] CLRF f
Operands: 0 ≤ f ≤ 127
Operation: 00h → (f)
1 → Z
Status Affected: Z
Desc ript ion : The conten t s of regi ste r ‘f’ are
cleared and the Z bit is set.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h → (W)
1 → Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z)
is set.
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Status Affected: TO, PD
Description: CLRWDT instruction resets the
W atchdog T imer . It also resets the
prescaler of the WDT.
Status bits TO and PD are set.
COMF Complement f
Syntax: [ label ] COMF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) → (destination)
Status Affected: Z
Description: The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’,
the result is stored back in
register ‘f’.
DECF Decrement f
Syntax: [ label ] DECF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - 1 → (destination)
Status Affected: Z
Description: Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
PIC16F91X
DS41250A-page 210 Preliminary 2004 Microchip Technology Inc.
DECFSZ Decrement f, Skip if 0
Syntax: [ label ] DECFSZ f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - 1 → (destination);
skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are
decremen ted. If ‘ d’ is ‘ 0’, the res ult
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘ 0’, then a NOP is
executed instead, making it a
two-cycle instruction.
GOTO Go to Address
Syntax: [ label ] GOTO k
Operands: 0 ≤ k ≤ 2047
Operation: k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Status Affected: None
Description: GOTO is an unconditional branch.
The e le ven -bi t im me dia t e v al ue i s
loaded into PC bits <10:0>. The
upper bi ts of PC are loaded from
PCLATH<4:3>. GOTO is a
two-cycle instruction.
INCF Increment f
Syntax: [ label ] INCF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) + 1 → (destination)
Status Affected: Z
Description: The contents of register ‘f’ are
incremen ted. If ‘d’ is ‘0’, the res ult
is place d in the W regi ste r. If ‘ d’ i s
‘1’, the result is placed back in
register ‘f’.
INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCFSZ f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) + 1 → (destination),
skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘0’, a NOP is executed
instead, making it a two-cycle
instruction.
IORLW Inclusive OR Literal with W
Syntax: [ label ] IORLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .OR. k → (W)
Status Affected: Z
Descr iption: The c ontents of the W regis ter are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .OR. (f) → (destination)
Status Affected: Z
Description: Inclusive OR the W register with
register ‘f ’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
2004 Microchip Technology Inc. Preliminary DS41250A-page 211
PIC16F91X
MOVF Move f
Syntax: [ label ] MOVF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) → (dest)
Status Affected: Z
Encoding: 00 1000 dfff ffff
Desc ript ion : The conten t s of regi ste r ‘f’ is
moved to a destination dependent
upon the status of ‘d’. If ‘d’ = 0,
destin ation is W re gister. If ‘d’ = 1,
the destination is file register ‘f’
itself. ‘d’ = 1 is useful to test a file
register since status flag Z is
affected.
Words: 1
Cycles: 1
Example MOVF FSR, 0
After Instruction
W= value in FSR
register
Z= 1
MOVLW Move Literal to W
Syntax: [ label ] MOVLW k
Operands: 0 ≤ k ≤ 255
Operation: k → (W)
Status Affected: None
Encoding: 11 00xx kkkk kkkk
Description: The eight bit literal ‘k’ is loaded
into W register. The “don’t cares”
will assemble as ‘0’s.
Words: 1
Cycles: 1
Example MOVLW 0x5A
After Instruction
W = 0x5A
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Operands: 0 ≤ f ≤ 127
Operation: (W) → (f)
Status Affected: None
Encoding: 00 0000 1fff ffff
Description: Move data from W register to
register ‘f’.
Words: 1
Cycles: 1
Example MOVWF OPTION
Before Inst ruction
OPTION= 0xFF
W = 0x4F
After Instruction
OPTION= 0x4F
W = 0x4F
NOP No Oper atio n
Syntax: [ label ] NOP
Operands: None
Operation: No operation
Status Affected: None
Encoding: 00 0000 0xx0 0000
Description: No operation.
Words: 1
Cycles: 1
Example NOP
PIC16F91X
DS41250A-page 212 Preliminary 2004 Microchip Technology Inc.
RETFIE Return from Interrupt
Syntax: [ label ] RETFIE
Operands: None
Operation: TOS → PC,
1 → GIE
Status Affected: None
Encoding: 00 0000 0000 1001
Description: Return from Interrupt. Stack is
POPed an d Top-of-S tac k (TOS) is
loaded in the PC. Interrupts are
enabled by setting Global
Interrupt Enable bit, GIE
(INTCON<7>). This is a two-cycle
instruction.
Words: 1
Cycles: 2
Example RETFIE
After Interrupt
PC = TOS
GIE = 1
RETLW Return with Literal in W
Syntax: [ label ] RETLW k
Operands: 0 ≤ k ≤ 255
Operation: k → (W);
TOS → PC
Status Affected: None
Encoding: 11 01xx kkkk kkkk
Description: The W register is loaded with the
eight bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
Words: 1
Cycles: 2
Example
TABLE
CALL TABLE ;W contains table
;offset value
• ;W now has table
value
•
•
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
•
•
•
RETLW kn ; End of table
Before Inst ruction
W = 0x07
After Instruction
W = value of k8
RETURN Return from Subroutine
Syntax: [ label ] RETURN
Operands: None
Operation: TOS → PC
Status Affected: None
Description: Return from subroutine. The stack
is POPed an d the top of th e s t a ck
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
2004 Microchip Technology Inc. Preliminary DS41250A-page 213
PIC16F91X
RLF Rotate Left f through Carry
Syntax: [ label ] RLF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: See description below
Status Affected: C
Encoding: 00 1101 dfff ffff
Description: The contents of register ‘f’ are
rotated one bit to the left through
the Carry Flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
Words: 1
Cycles: 1
Example RLF REG1,0
Before Instruction
REG1 = 1110 0110
C=0
After Instruction
REG1 = 1110 0110
W = 1100 1100
C=1
RRF Rotate Right f through Carry
Syntax: [ label ] RRF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: See description below
Status Affected: C
Desc ript ion : The contents of register ‘f’ are
rotat ed one bit to the r ight throug h
the Carry Flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the resu lt is place d
back in register ‘f’.
Register fC
Register fC
SLEEP
Syntax: [ label ] SLEEP
Operands: None
Operation: 00h → WDT,
0 → WDT prescaler,
1 → TO,
0 → PD
Status Affected: TO, PD
Descripti on: The power-down Status bit, PD is
cleared. Time-out Status bit, TO
is set. Watchdog Timer and its
prescaler are cleared.
The processor is put into Sleep
mode with the oscillator stopped.
SUBLW Subtract W from Literal
Syntax: [ label ] SUBLW k
Operands: 0 ≤ k ≤ 255
Operation: k - (W) → (W)
Status Affected: C, DC, Z
Description: The W register is subtracted (2’s
complement method) from the
eight-bit literal ‘k’. The result is
placed in the W register.
SUBWF Subtract W from f
Syntax: [ label ] SUBWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - (W) → (destination)
Status Affected: C, DC, Z
Description: Subtract (2’s complement method)
W register from register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
PIC16F91X
DS41250A-page 214 Preliminary 2004 Microchip Technology Inc.
SWAPF Swap Nibbles in f
Syntax: [ label ] SWAPF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Status Affected: None
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in the W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
XORLW Exclusive OR Literal with W
Syntax: [ label ] XORLW k
Operands: 0 ≤ k ≤ 255
Operation: (W) .XOR. k → (W)
Status Affected: Z
Description: The contents of the W register
are XOR’ed with the eight-bit
literal ‘k’. The result is placed in
the W register.
XORWF Exclusive OR W with f
Syntax: [ label ] XORWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (W) .XOR. (f) → (destination)
Status Affected: Z
Descrip tion: Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
2004 Microchip Technology Inc. Preliminary DS41250A-page 215
PIC16F91X
18.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full ran ge of hardware a nd softwa re develo pment to ols:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C17 and MPLAB C18 C Compilers
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB C30 C Compiler
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
- MPLAB dsPIC30 Software Simulator
•Emulators
- MPLAB ICE 2000 In -Circuit Emulator
- MPLAB ICE 4000 In -Circuit Emulator
• In-Circuit Debugger
- MPLAB ICD 2
• Device Progra mmers
-PRO MATE
® II Universal Device Progr a mm er
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM.netTM De monstration Board
- PICDEM 2 Plus Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 4 Demonstration Board
- PICDEM 17 Demonstration Board
- PICDEM 18R Demonstration Board
- PICDEM LIN Demonstration Board
- PICDEM USB Demonstration Board
• Evaluation Kits
-K
EELOQ® Secur ity ICs
- P ICDEM MSC
-microID
® RFID
-CAN
- PowerSmart® Battery Management
-Analog
18.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
based application that contains:
• An interface to deb ugging tools
- simulator
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor with color coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Exten si ve on-l in e help
The MPLAB IDE allows you to :
• Edit your sour ce fil es (either assembly or C)
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools
(automatically updates all project information)
• Debug us ing :
- source files (as sembl y or C)
- mixed assembly and C
- machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve whe n upgrading to tools with increasin g flexibi lity
and power.
18.2 MPASM Assembler
The MPASM assembler is a full-featured, universal
macro assembler for all PICmicro MCUs.
The MPASM assembler generates relocatable object
files for the MPLINK object linker, Intel® standard hex
files, M AP files to detail memory u sage and symbol re f-
erence, a bsolute LST files that contain source lines and
generated machine code and COFF files for
debugging.
The MPASM assembler features include:
• Integration into MPLAB IDE projects
• User de fined m acros to strea mline asse mbly cod e
• Condit ion al as sem bl y for multi-purpose source
files
• Directi ves that allow complete control over the
assembly p rocess
PIC16F91X
DS41250A-page 216 Preliminary 2004 Microchip Technology Inc.
18.3 MPLAB C17 and MPLAB C18
C Compilers
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI C compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol info rmation tha t is optimized to the MPLAB IDE
debugger.
18.4 MPLINK Object Linker/
MPLIB Object Librari an
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB object librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file , only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement , deletion and extr action
18.5 MPLAB C30 C Compiler
The MPLAB C30 C compiler is a full-featured, ANSI
compliant, optimizing compiler that translates standard
ANSI C programs into dsPIC30F assembly language
source. The compiler also supports many command
line options and language extensions to take full
adv antage of the dsPIC 30F dev ice ha rdwar e capab ili-
ties and afford fine control of the compiler code
generator.
MPLAB C30 is distributed with a complete ANSI C
standard library. All library functions have been vali-
dated an d c on form to the ANSI C li brary standard. The
library includes functions for string manipulation,
dynamic memory allocation, data conversion, time-
keepin g and math func tions (trigonome tric, expone ntial
and hyperbolic). The compiler provides symbolic
information for high-level source debugging with the
MPLAB IDE.
18.6 MPLAB ASM30 Assembler, Linker
and Librarian
MPLAB ASM30 assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 compiler uses the
assembler to produce it’s object file. The assembler
generates relocatable object files that can then be
archived or lin ked with other relocatable object files and
arch ives to c rea te an e xecu tabl e fil e. N otabl e fe atu res
of the assembler include:
• Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich dire cti ve set
• Flexible macro language
• MPLAB IDE compatib ility
18.7 MPLAB SIM Software Simulator
The MPLAB SIM sof tware simulat or allows code deve l-
opment in a PC hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or use r de fined key p ress, to any pin. The exec u-
tion can be performed in Single-Step, Execute Until
Break or Trace mode.
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and MPLAB C18
C Compilers, as well as the MPASM assembler. The
software simulator offers the flexibility to develop and
debug code outside of the laboratory environment,
making it an excellent, economical software
development tool.
18.8 MPLAB SIM30 Software Simulator
The MPLAB SIM30 software simulator allows code
develop ment in a PC hosted en vironment by simulating
the dsPIC30F series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any of the pins.
The MPLAB SIM30 simulator fully supports symbolic
debugging using the MPLAB C30 C Compiler and
MPLAB ASM30 assembler . The simulator runs in either
a Command Line mode for automated tasks, or from
MPLAB IDE. This high-speed simulator is designed to
debug, analyze and optimize time intensive DSP
routines.
2004 Microchip Technology Inc. Preliminary DS41250A-page 217
PIC16F91X
18.9 MPLAB ICE 2000
High-Performance Universal
In-Circui t Emu lator
The MPLAB ICE 2000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers. Software control of the
MPLAB ICE 2000 in-circuit emulator is advanced by
the MPLAB Integrated Development Environment,
which all ows ed iting, b uildin g, do wnlo ading and sourc e
debuggi ng from a singl e envi ronm en t.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitor-
ing feat ures. Interc hangeabl e proces sor modul es allow
the system to be easily reconfigured for emulation of
different processors. The universal architec ture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLAB ICE 2000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
18.10 MPLAB ICE 4000
High-Performance Universal
In-Circui t Emu lator
The MPLAB ICE 4000 universal in-circuit emulator is
intended to provide the product development engineer
with a co mplete micro controller de sign tool se t for high-
end PICm icro microcontrollers. Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment, which
allows editing, building, downloading and source
debuggi ng from a singl e envi ronm en t.
The MPLAB ICD 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high-speed perfor-
mance for dsPIC30F and PIC18XXXX devices. Its
advanc ed emulator fe atures inc lude complex t riggering
and timing, up to 2 Mb of emulation memory and the
ability to view variables in real-time.
The MPLAB ICE 4000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
18.11 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash
PICmicro MCUs and can be used to develop for these
and other PICmicro microcontrollers. The MPLAB
ICD 2 utilizes the in-circuit debugging capability built
into the Flash devices. This feature, along with
Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM)
protocol , offe rs cost ef fective i n-circuit Flash debug ging
from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by setting
breakpoints, single-stepping and watching variables,
CPU status and peripheral registers. Running at full
speed enables testing hardware and applications in
real-tim e. MPLAB ICD 2 also serves as a devel opment
programmer for selected PICmicro devices.
18.12 PRO MATE II Universal Device
Programmer
The PRO MATE II is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maxi mum reli abili ty. It features
an LCD display for instructions and error messages
and a modular detachable socket assembly to support
various package types. In Stand-Alone mode, the
PRO MATE II device programmer can read, verify and
program PICmicro devices without a PC connection. It
can also set code protection in this mode.
18.13 MPLAB PM3 Device Programmer
The MPLAB PM3 is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maxi mum reli abili ty. It features
a large LCD display (128 x 64) for menus and error
messages and a modular detachable socket assembly
to support various package types. The ICSP™ cable
assembly is included as a standard item. In Stand-
Alone mode , the M PLAB PM3 devi ce pr ogra mmer ca n
read, verify and program PICmicro devices without a
PC connection. It can also set code protection in this
mode. M PLAB PM3 con nects t o the host PC via an RS-
232 or USB cable. MPLAB PM3 has high-speed com-
munications and optimized algorithms for quick pro-
gramming of large memory devices and incorporates
an SD/ MMC card fo r file s torage an d secure d ata a ppli-
cations.
PIC16F91X
DS41250A-page 218 Preliminary 2004 Microchip Technology Inc.
18.14 PICSTART Plus Development
Programmer
The PICSTART Plus development programmer is an
easy-to-use, low-cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Inte grated Dev elopmen t En vironme nt so ftware makes
using the programmer simple and efficient. The
PICSTART Plus development programmer supports
most PICmicro devices up to 40 pins. Larger pin count
devices, such as the PIC16C92X and PIC17C76X,
may be supported with an adapter socket. The
PICSTART Plus development programmer is CE
compliant.
18.15 PICDEM 1 PICmicro
Demonstration Board
The PICDEM 1 demo nstrat ion boa rd demo nstrate s the
capabilities of the PIC16C5X (PIC16C54 to
PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,
PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All
necessary hardware and software is included to run
basic demo programs. The sample microcontrollers
provi d ed wi t h the P IC DE M 1 de mo ns t rat i on b oar d c an
be pro gramme d with a PRO MATE II devic e progra m-
mer or a PICSTART Plus development programmer.
The PICDE M 1 demonstrati on board can be conne cted
to the MPLAB ICE in-circuit emulator for testing. A
proto type area extends the ci rcuitry for a dditio nal appli-
cation components. Features include an RS-232
interface, a potentiometer for simulated analog input,
push button switches and eight LEDs.
18.16 PICDEM.net Internet/Ethernet
Demonstration Board
The PICDEM.net demonstration board is an Internet/
Ethernet demonstration board using the PIC18F452
microcontroller and TCP/IP firmware. The board
supports any 40-pin DIP device that conforms to the
standard pinout used by the PIC16F877 or
PIC18C452. This kit features a user friendly TCP/IP
stack, web server with HTML, a 24L256 Serial
EEPROM for Xmodem download to web pages into
Serial EEPROM, ICSP/MPLAB ICD 2 interface con-
nector, an Ethernet interface, RS-232 interface and a
16 x 2 LCD display. Also included is the book and
CD-ROM “TCP/IP Lean, Web Servers for Embedded
Systems,” by J eremy Ben tham
18.17 PICDEM 2 Plus
Demonstration Board
The PICDEM 2 Plus demonstration board supports
many 18, 28 and 40-pin microcontrollers, including
PIC16F87X and PIC18FXX2 devices. All the neces-
sary ha rdware and s oftware is included to run the dem-
onstration programs. The sample microcontrollers
provided with the PICDEM 2 demonstration board can
be programmed with a PRO MATE II device program-
mer, PICSTART Plus development programmer, or
MPLAB ICD 2 with a Universal Programmer Adapter.
The MPLAB I CD 2 and MPLAB ICE in-circuit emul ators
may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area extends the
circuitry for additional application components. Some
of the features include an RS-232 interface, a 2 x 16
LCD display , a piezo speaker, an on-board temperature
sensor, four LEDs and sample PIC18F452 and
PIC16F877 Flash microcontrollers.
18.18 PICDEM 3 PIC16C92X
Demonstration Board
The PICDEM 3 demonstration board supports the
PIC16C923 and PIC16C924 in the PLCC package. All
the necessary hardware and softwa re is included to run
the demonstration programs.
18.19 PICDEM 4 8/14/18-Pin
Demonstration Board
The PICDEM 4 can be used to demonstrate the capa-
bilities of the 8, 14 and 18-pin PIC16XXXX and
PIC18XXXX MCUs, including the PIC16F818/819,
PIC16F87/88, PIC16F62XA and the PIC18F1320
family of microcontrollers. PICDEM 4 is intended to
showcase the many features of these low pin count
parts, including LIN and Motor Control using ECCP.
Special provisions are made for low-power operation
with the supercapacitor circuit and jumpers allow on-
board hardware to be disabled to eliminate current
draw in this mode. Included on th e demo board are pro-
visions for Crystal, RC or Canned Oscillator modes, a
five volt regulator for use with a nine volt wall adapter
or battery, DB-9 RS-232 interface, ICD connector for
programming via ICSP and development with MPLAB
ICD 2, 2 x 16 liquid crystal display , PCB footprints for H-
Bridge motor driver, LIN transceiver and EEPROM.
Also included are: header for expansion, eight LEDs,
four potentiometers, three push buttons and a proto-
typing are a. Inc lud ed with the kit is a PIC16F627A and
a PIC18F1 320. Tutorial fir mwar e is inc luded along wi th
the User’s Guide.
2004 Microchip Technology Inc. Preliminary DS41250A-page 219
PIC16F91X
18.20 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. A pro-
gramme d sample i s included. The PR O MA TE I I device
programmer, or the PICSTART Plus development pro-
gramme r , can be used to reprogram the device for user
tailored application development. The PICDEM 17
demonstration board supports program download and
execution from external on-board Flash memory. A
generous proto typ e area is av ailab le for user hardw are
expansion.
18.21 PICDEM 18R PIC18C601/801
Demonstration Board
The PICDEM 18R demonstration board serves to assist
development of the PIC18C601/801 family of Microchip
microcontrollers. It provides hardware implementation
of both 8-bit Multiplexed/Demultiplexed and 16-bit
Memory modes. The board includes 2 Mb external
Flash memory and 128 Kb SRAM memory, as well as
serial EEPROM, allowing access to the wide range of
memory types supported by the PIC18C601/801.
18.22 PICDEM LIN PIC16C43X
Demonstration Board
The pow erfu l LI N hard w are a nd s of tw are kit includes a
series of boards and three PICmicro microcontrollers.
The small footprint PIC16C432 and PIC16C433 are
used as slaves in the LIN communication and feature
on-board LIN transceivers. A PIC16F874 Flash
microcontroller serves as the master. All three micro-
controllers are programmed with firmware to provide
LIN b us communication.
18.23 PICkitTM 1 Flash Starter Kit
A complete “development system in a box”, the PICkit
Flash Starter Kit includes a convenient multi-section
board for p rogramming, evaluation a nd development of
8/14-pin Flash PIC® microcontrollers. Powered via
USB, the board operates un der a simple Windows GUI.
The PICkit 1 Starter Kit includes the User’s Guide (on
CD ROM), PICkit 1 tutorial software and code for
various applications. Also included are MPLAB® IDE
(Integrated Development Environment) software,
software and hardware “Tips ‘n Tricks for 8-pin Flash
PIC® Microcontrollers” Handbook and a USB interface
cable. Supports all current 8/14-pin Flash PIC
microcontrollers, as well as many future planned
devices.
18.24 PICDEM USB PIC16C7X5
Demonstration Board
The PICDEM U SB Demo ns trati on Board sho w s o f f th e
capabilities of the PIC16C745 and PIC16C765 USB
microcontrollers. This board provides the basis for
future USB products.
18.25 Evaluation and
Programming Tools
In additio n to the PICDEM seri es of circuits, Microchip
has a line of evaluation kits and demonstration software
for the se products.
•K
EELOQ evaluation and prog ram mi ng too ls for
Microchip’s HCS Secure Data Products
• CAN developers kit for automo tive network
applications
• Analog design boards and filter design software
• PowerSmart bat tery charging evaluation/
calibration kits
•IrDA
® development kit
• microID development and rfLabTM development
software
• SEEVAL® designer kit for memory ev al uat ion an d
endurance calculations
• PICDEM MSC demo boards for Switching mode
power supply, high-power IR driver, delta sigma
ADC and flow rate sensor
Check the Microchip web page and the latest Product
Selector Guide for the complete list of demonstration
and evaluation kits.
PIC16F91X
DS41250A-page 220 Preliminary 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Advance Informa tion DS41250A-page 221
PIC16F91X
19.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings(†)
Ambient temperature under bias..........................................................................................................-40° to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Volt a ge on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V
Volt a ge on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V
Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) ...............................................................................................................................800 mW
Maximum curr ent out of VSS pin .....................................................................................................................300 mA
Maximum curr ent into VDD pin........................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)................................................................................................................±20 mA
Output clamp cur rent, IOK (Vo < 0 or Vo >VDD)..........................................................................................................±20 mA
Maximum output current sunk by any I/O pin....................................................................................................25 mA
Maximum output current sourced by any I/O pin ..............................................................................................25 mA
Maximum current sunk by PORTA, PORTB and PORTE(2) (combined).........................................................200 mA
Maximum current sourced by PORTA, PORTB and PORTE(2) (combined) ...................................................200 mA
Maximum current sourced PORTA and PORTC (combined)..........................................................................200 mA
Maximum current sunk by PORTA and PORTC (combined)..........................................................................200 mA
Note 1: Power dissi pa tion is c alcul ated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL).
2: PORTD and PORTE are not implemented in PIC16F913/916 devices.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100 Ω should be used when appl ying a “low” l evel to the MCLR pin, rather than
pulling this pin direct ly to VSS.
PIC16F91X
DS41250A-page 222 Advance Information 2004 Microchip Technology Inc.
FIGURE 19-1: PIC16F91X VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C
5.5
2.0
3.5
2.5
0
3.0
4.0
4.5
5.0
4
Frequency (MHz)
VDD
(Volts)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
81612 2010
2004 Microchip Technology Inc. Advance Informa tion DS41250A-page 223
PIC16F91X
19.1 DC Characteristics: PIC16F91X -I (Industrial) PIC16F91X -E (Extended)
DC CHARACTERISTICS Standard Operating Conditi ons (unle ss otherw is e stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No. Sym Characteristic Min Typ† Max Units Conditions
D001
D001C
D001D
VDD Supply Voltage 2.0
3.0
4.5
—
—
—
5.5
5.5
5.5
V
V
V
FOSC < = 4 MHz:
FOSC < = 10 MHz
FOSC < = 20 MHz
D002 VDR RAM Data Retention
Voltage(1) 1.5* — — V Device in Sleep mode
D003 VPOR VDD Start Voltage to
ensure internal Power-on
Reset signal
—VSS —VSee Section 16.3 “Power-on Reset” for
details.
D004 SVDD VDD Rise Rate to ensure
internal Power-on Reset
signal
0.05* — — V/ms See Section 16.3 “Power-on Reset” for
details.
D005 VBOR Brown-out Reset —2.1— V
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
PIC16F91X
DS41250A-page 224 Advance Information 2004 Microchip Technology Inc.
19.2 DC Characteristics: PIC 16F91X-I (Industrial)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No. Device Char ac teri s tics Min Typ† Max Units Conditions
VDD Note
D010 Supply Current (IDD)(1, 2) —12TBDµA2.0FOSC = 32 kHz
LP Oscillator mode
—18TBDµA3.0
—35TBDµA5.0
D011 — 110 TBD µA2.0F
OSC = 1 MHz
XT Oscill ator mode
—190TBDµA3.0
—330TBDµA5.0
D012 — 220 TBD µA2.0F
OSC = 4 MHz
XT Oscill ator mode
—370TBDµA3.0
— 0.6 TBD mA 5.0
D013 — 70 TBD µA2.0F
OSC = 1 MHz
EC Oscillator mode
—140TBDµA3.0
—260TBDµA5.0
D014 — 180 TBD µA2.0F
OSC = 4 MHz
EC Oscillator mode
—320TBDµA3.0
— 500 TBD µA5.0
D015 — TBD TBD µA2.0F
OSC = 31 kHz
INTOSC mode
—TBDTBDµA3.0
—TBDTBDmA 5.0
D016 — 340 TBD µA2.0F
OSC = 4 MHz
INTOSC mode
—500TBDµA3.0
— 0.8 TBD mA 5.0
D017 — 180 TBD µA2.0F
OSC = 4 MHz
EXTRC mode
—320TBDµA3.0
—580TBDµA5.0
D018 — 2.1 TBD mA 4.5 FOSC = 20 MHz
HS Oscillator mode
— 3.0 TBD mA 5.0
D020 Power-down Base
Current (IPD)(4) —1.0TBDµA 2.0 WDT , BOR, Comparators, VREF and
T1OSC disabled
—0.4TBDµA3.0
—2.9TBDµA5.0
Legend: TBD = To Be Determined
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The tes t cond itions for al l IDD mea surem ent s in a ctive opera tion m ode are : OSC 1 = e xternal square w ave ,
from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabl ed.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loa din g an d s w itc hi ng ra te, os cil la tor ty pe , in tern al code execut ion p a ttern an d te mp erature, also have
an impact on the current consumption.
3: The peri pheral cu rren t is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peri pheral ∆ current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
2004 Microchip Technology Inc. Advance Informa tion DS41250A-page 225
PIC16F91X
D021 — 0.3 TBD µA 2.0 WDT Current
—1.8TBDµA3.0
—8.4TBDµA5.0
D022 — 58 TBD µA 3.0 BOR Current
—75TBDµA5.0
D023 — 3.3 TBD µA 2.0 Comparator Cu rrent(3)
—6.1TBDµA3.0
—11.5TBDµA5.0
D024 — 58 TBD µA2.0CV
REF Current
—85TBDµA3.0
—138TBDµA5.0
D025 — 4.0 TBD µA 2.0 T1OSC Current
—4.6TBDµA3.0
—6.0TBDµA5.0
D026 — 1.2 TBD nA 3.0 A/D Current
—0.0022TBD µA5.0
D024 — 58 TBD µA2.0CV
REF Current
—85TBDµA3.0
—138TBDµA5.0
D025 — 4.0 TBD µA 2.0 T1OSC Current
—4.6TBDµA3.0
—6.0TBDµA5.0
D026 — 1.2 TBD nA 3.0 A/D Current
—0.0022TBD µA5.0
19.2 DC Characteristics: PIC 16F91X-I (Industrial) (Continued)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param
No. Device Char ac teri s tics Min Typ† Max Units Conditions
VDD Note
Legend: TBD = To Be Determined
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The tes t cond itions for al l IDD mea surem ent s in a ctive opera tion m ode are : OSC 1 = e xternal square w ave ,
from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin load in g an d s w itc hi ng ra te, os cil la tor ty pe , in ternal code exe cut ion p a ttern an d te mp erature, also hav e
an impact on the current consumption.
3: The peri pheral cu rren t is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peri pheral ∆ current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
PIC16F91X
DS41250A-page 226 Advance Information 2004 Microchip Technology Inc.
19.3 DC Characteristics: PIC16F91X-E (Extended)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +125°C for extended
Param
No. Device Characteristics Min Typ† Max Units Conditions
VDD Note
D010E Supply Current (IDD)(1, 2) —9TBDµA2.0FOSC = 32 k Hz
LP Oscillator mode
—18TBDµA3.0
—35TBDµA5.0
D011E — 110 TBD µA2.0F
OSC = 1 MHz
XT Oscillator mode
— 190 TBD µA3.0
— 330 TBD µA5.0
D012E — 220 TBD µA2.0F
OSC = 4 MHz
XT Oscillator mode
— 370 TBD µA3.0
— 0.6 TBD mA 5.0
D013E — 70 TBD µA2.0F
OSC = 1 MHz
EC Oscillator mode
— 140 TBD µA3.0
— 260 TBD µA5.0
D014E — 180 TBD µA2.0F
OSC = 4 MHz
EC Oscillator mode
— 320 TBD µA3.0
— 580 TBD µA5.0
D015E — TBD TBD µA2.0F
OSC = 31 kHz
INTOSC mode
—TBDTBDµA3.0
—TBDTBDmA5.0
D016E — 340 TBD µA2.0F
OSC = 4 MHz
INTOSC mode
— 500 TBD µA3.0
— 0.8 TBD mA 5.0
D017E — 180 TBD µA2.0F
OSC = 4 MHz
EXTRC mode
— 320 TBD µA3.0
— 580 TBD µA5.0
D018E — 2.1 TBD mA 4.5 FOSC = 20 MHz
HS Oscillator mode
— 2.4 TBD mA 5.0
Legend: TBD = To Be Determined
† Data in ‘T yp’ colu mn is at 5. 0V, 25°C unles s otherwise st ated. Thes e param eters are fo r design gu idance on ly
and are not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabl ed.
2: The supp ly cu rrent is mainly a fun cti on of th e op erating voltage and frequen cy. Other fa cto rs, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
3: The peri pheral cu rren t is the sum of the base IDD or IPD and the additional current consumed when this
periphera l is ena ble d. The periph eral ∆ current can be determined by subtracting the base IDD or IPD current
from this limit. Max value s should be used w hen calculating total current consumption.
4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
2004 Microchip Technology Inc. Advance Informa tion DS41250A-page 227
PIC16F91X
D020E Power-dow n Base
Current (IPD)(4) — 0.00099 TBD µA 2.0 WDT, B OR, Comparators, VREF and
T1OSC di sabled
— 0.0012 TBD µA3.0
— 0.0029 TBD µA5.0
D021E — 0.3 TBD µA 2.0 WDT Current
—1.8TBDµA3.0
—8.4TBDµA5.0
D022E — 58 TBD µA 3.0 BOR Cu r r ent
— 109 TBD µA5.0
D023E — 3.3 TBD µA 2.0 Compara tor Curren t(3)
—6.1TBDµA3.0
—11.5TBDµA5.0
D024E — 58 TBD µA2.0CV
REF Current
—85TBDµA3.0
— 138 TBD µA5.0
D025E — 4.0 TBD µA 2 .0 T1OSC Current
—4.6TBDµA3.0
—6.0TBDµA5.0
D026E — 0.0012 TBD µA 3.0 A/D Current(3)
— 0.0022 TBD µA5.0
19.3 DC Characteristics: PIC16F91X-E (Extended) (Continued)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +125°C for extended
Param
No. Device Characteristics Min Typ† Max Units Conditions
VDD Note
Legend: TBD = To Be Determined
† Data in ‘T yp’ colu mn is at 5. 0V, 25°C unles s otherwise stated . These p aramete rs are fo r design gu idance on ly
and are not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supp ly cu rrent is mainly a fun cti on of th e op era t ing vo lt a ge and frequency. Other fa cto rs, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
3: The peri pheral cu rren t is the sum of the base IDD or IPD and the additional current consumed when this
periphera l is ena ble d. The periph eral ∆ current can be determined by subtracting the base IDD or IPD current
from this limit. Max value s should be used w hen calculating total current consumption.
4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
PIC16F91X
DS41250A-page 228 Advance Information 2004 Microchip Technology Inc.
19.4 DC Characteristics: PIC16F91X-I (Industrial), PIC16F91X-E (Extended)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industr ial
-40°C ≤ TA ≤ +125°C for extended
Param
No. Sym Characteristic Min Typ† Max Units Conditions
VIL Input Low Voltage
I/O port:
D030 with TTL buffer Vss — 0.8 V 4.5V ≤ VDD ≤ 5.5V
D030 A Vss — 0.15 VDD V Otherwise
D031 w ith Sc hm i tt Trigger buffer Vss — 0.2 VDD V Entire range
D032 MCLR, OSC1 (RC mode) VSS — 0.2 VDD V
D033 OSC1 (XT and LP modes)(1) VSS —0.3V
D033A OSC1 (HS mode)(1) VSS — 0.3 VDD V
D034 I2C ™ m ode VSS —0.3VDD VEntire VDD Range
VIH Input High Voltage
I/O port: —
D040
D040A with TTL buffer 2.0
(0.25 VDD +
0.8)
—
—VDD
VDD V
V4.5V ≤ VDD ≤ 5.5V
Otherwise
D041 with Schm itt Trigger buffer 0.8 VDD —VDD V Entire range
D042 MCLR 0.8 V DD —VDD V
D043 OSC1 (XT and LP modes) 1.6 — VDD V(Note 1 )
D043A OSC1 (HS mode) 0.7 VDD —VDD V(No te 1)
D043B OSC1 ( R C mo de) 0.9 VDD —VDD V
D044 I2C mode 0.7VDD —VDD VEntire VDD Range
D070 IPUR PORTB Weak Pull-u p C ur r ent 50* 250 400* µAVDD = 5.0V, VPIN = VSS
IIL Input Leakag e Cur re nt (2)
D060 I/O port — ± 0.1± 1µAVSS ≤ VPIN ≤ VDD,
Pin at high -im pe dance
D061 MCLR(3) —± 0.1± 5µAVSS ≤ VPIN ≤ VDD
D063 OSC1 — ± 0.1± 5µAVSS ≤ VPIN ≤ VDD, XT, HS and
LP OSC configuration
VOL Output Low Voltage
D080 I/O port — — 0.6 V IOL = 8.5 m A, VDD = 4.5V (Ind . )
D083 OSC2/ CLKO (RC mode) — — 0.6 V IOL = 1.6 m A, V DD = 4.5V (Ind.)
IOL = 1.2 mA, VDD = 4.5V (Ext.)
VOH Output High Voltage
D090 I/O port VDD – 0.7 — — V I OH = -3.0 mA, VDD = 4.5V (In d .)
D092 OSC2/C LKO ( R C m ode) VDD – 0.7 — — V IOH = -1.3 mA, VDD = 4.5V (In d .)
IOH = - 1. 0 mA , V DD = 4.5V (Ext.)
* These para m et er s ar e characterized but not tested.
† Data in ‘Typ’ colu m n i s at 5.0 V, 25°C unless oth er w i se sta te d. These paramet er s ar e f or d esi gn guidanc e onl y
and ar e not teste d.
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger in put. It is not recommended to use an
external clock in RC mode.
2: Nega tive current is def i ned as curren t s our ced by the pin.
3: The lea kage current on the MCLR pi n i s str ongly dependent on th e app l ie d voltage level. The specifie d le vels
repre sent norm al operating con d itions. Higher leakag e current may be measured at different in put vol tag es.
2004 Microchip Technology Inc. Advance Informa tion DS41250A-page 229
PIC16F91X
Capacitive Loading Specs
on Output Pins
D100 COS
C2 OSC2 pin — — 15* pF In XT, HS and LP modes
when ex ternal clock i s used to
drive OSC1
D101 CIO All I/O pins — — 50* pF
Data EEPROM Memory
D120 EDByte Endurance 100K 1M — E/W -40°C ≤ TA ≤ +85°C
D120A EDByte Endurance 10K 100K — E/W +85°C ≤ TA ≤ +125°C
D121 VDRW VDD for Read/Write VMIN — 5.5 V Using EECON1 to read/write
VMIN = Minimum operating
voltage
D122 TDEW Erase/Write Cycle Time — 5 6 m s
D123 TRETD Characteristic Retention 40 — — Year Provided no other specifica-
tions are violated
D124 TREF Number of Total Erase/Write
Cycl es bef ore Refres h (2) 1M 10M — E/W -40°C ≤ TA ≤ +85°C
Program Flash Memory
D130 EPCell Endurance 10K 100K — E/W -40°C ≤ TA ≤ +85°C
D130A EDCell Endurance 1K 10K — E/W +85°C ≤ TA ≤ +125°C
D131 VPR VDD for Read VMIN —5.5VVMIN = Minimum operating
voltage
D132 VPEW VDD for Erase/Write 4.5 — 5.5 V
D133 TPEW Erase/Write cycle time — 2 2.5 m s
D134 TRETD Characteristic Retention 40 — — Year Provided no other specifica-
tions are violated
19.4 DC Characteristics: PIC16F91X-I (Industrial), PIC16F91X-E (Extended) (Continued)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No. Sym Characteristic Min Typ† Max Units Conditions
* These para m et er s ar e characterized but not tested.
† Data in ‘Typ’ colu m n i s at 5.0 V, 25°C unless oth er w i se sta te d. These paramet er s ar e f or d esi gn guidanc e onl y
and ar e not teste d.
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger in put. It is not recommended to use an
external clock in RC mode.
2: Nega tive current is def i ned as curren t s our ced by the pin.
3: The lea kage current on the MCLR pi n i s str ongly dependent on th e app l ie d voltage level. The specif ied le vels
repre sent norm al operating con d itions. Higher leakag e current may be measured at different in put vol tag es.
PIC16F91X
DS41250A-page 230 Advance Information 2004 Microchip Technology Inc.
19.5 Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
FIGURE 19-2: LOAD CONDITIONS
1. TppS2ppS
2. TppS
TF Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKO rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppe rcase letters and their meanings :
SFFall PPeriod
HHigh RRise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
V
DD
/2
C
L
R
L
Pin Pin
V
SS
V
SS
C
L
RL= 464Ω
CL= 50 pF for all pins
15 pF for OSC2 output
Load Cond ition 1 Load Condition 2
Legend:
2004 Microchip Technology Inc. Advance Informa tion DS41250A-page 231
PIC16F91X
19.6 AC Characteristics: PIC 16F91X (Industrial, Extended)
FIGURE 19-3: EXTERNAL CLOCK TIMING
TABLE 19-1: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions (unless otherw ise stated)
Operating Temperature -40°C ≤ TA ≤ +125°C
Param
No. Sym Characteristic Min Typ† Max Units Conditions
FOSC External CL KI Frequency(1) DC — 37 kHz LP Oscill ator mode
DC — 4 MHz XT Oscillator mode
DC — 20 MHz HS Oscillator mode
DC — 20 MHz EC Oscillator mode
Osci lla tor Freq uen cy(1) 5 — 37 kHz LP Oscillator mode
—4 —MHzINTOSC mode
DC — 4 MHz RC Oscillator mode
0.1 — 4 MHz XT Oscillator mode
1 — 20 MHz HS Oscillator mode
1T
OSC External CLKI Period(1) 27 — ∞µs LP Oscill ator mode
50 — ∞ns HS Osci llator mode
50 — ∞ns EC Osci llator mode
250 — ∞ns XT Oscillator mode
Oscillator Perio d(1) 27 200 µs LP Oscillator mode
—250 — nsINTOSC mode
250 — — ns RC Oscillator mode
250 — 10,000 ns XT Oscillator mode
50 — 1,00 0 ns HS Oscillator mode
2T
CY Instructi on Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC
3 TosL,
TosH External CLKI (OSC1) High
External CLKI Low 2* — — µs LP oscillator, TOSC L/H duty cycle
20* — — n s HS osci lla tor, TOSC L/H d uty cycle
100 * — — n s XT oscillat or, TOSC L/H duty cycle
4TosR,
TosF External CLKI Rise
External CLKI Fall — — 50* ns LP oscillator
— — 25* ns XT oscillator
— — 15* ns HS oscillator
* These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: Instruction cycle p eriod (TCY) equals four times the input oscillator time base period. All specified values
are based on charac teri za tion data for that particular osci lla tor typ e unde r st andard operating condi tion s
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at ‘min’
values with an external clock applied to OSC1 pin. When an external clock input is used, the ‘max’ cycle
time limit is ‘DC’ (no clock) for all devices.
OSC1
CLKO
Q4 Q1 Q2 Q3 Q4 Q1
1
2
3344
PIC16F91X
DS41250A-page 232 Advance Information 2004 Microchip Technology Inc.
TABLE 19-2: PRECISION INTERNAL OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C ≤ TA ≤ +125°C
Param
No. Sym Characteristic Freq.
Tolerance Min Typ† Max Units Conditions
F10 FOSC Internal Calibrated
INT OS C Freq uen cy (1) ±1% — 8.00 TBD MHz VDD and Temperature TBD
±2% — 8.00 TBD MHz 2.5V ≤ VDD ≤ 5.5V
0°C ≤ TA ≤ +8 5°C
±5% — 8.00 TBD MHz 2.0V ≤ VDD ≤ 5.5V
-40°C ≤ TA ≤ +85°C (Ind.)
-40°C ≤ TA ≤ +125°C (Ext.)
F14 TIOSC
ST Oscillator Wake-up from
Sleep Start- up Time* ——TBDTBDµsVDD = 2.0V, -40°C to +85°C
——TBDTBDµsV
DD = 3.0V, -40°C to +85°C
——TBDTBDµsVDD = 5.0V, -40°C to +85°C
Legend: TBD = To Be Determined
* These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to
the device as possible. 0.1 uF and 0.01 uF values in parallel are recommended.
2004 Microchip Technology Inc. Advance Informa tion DS41250A-page 233
PIC16F91X
FIGURE 19-4: CLKO AND I/O TIMING
TABLE 19-3: CLKO AND I/O TIMING REQUIREMENTS
Standard Operating Conditions (unless otherw ise stated)
Operating Temperature -40°C ≤ TA ≤ +125°C
Param
No. Sym Characteristic Min Typ† Max Units Conditions
10* TOSH2CKLOSC1↑ to CLOUT↓ — 75 200 ns (Note 1)
11* TOSH2CKHOSC1↑ to C LOUT↑ — 75 200 ns (Note 1)
12* TCKR CLKO Rise Time — 35 100 ns (Note 1)
13* TCKF CLKO Fall Time — 35 100 ns (Note 1)
14* TCKL2IOVCLKO↓ to Port Out Valid — — 0.5 TCY + 20 ns (Note 1)
15* TIOV2CKH Port In Valid before CLKO↑ TOSC + 200 ns — — ns (Note 1)
16* TCKH2IOI Port In Hold after CLKO↑ 0 — — ns (Note 1)
17* TOSH2IOVOSC1↑ (Q1 cycle) to Po rt Out Valid — 50 150* ns
——300ns
18* TOSH2IOIOSC1↑ (Q2 cycle) to Port
Input Invalid (I/O in hold time) 3.0-5.5V 100 — — ns
2.0-5.5V 200 — — ns
19* TIOV2OSH Port Input Va lid to OSC1↑
(I/O in setup time) 0——ns
20* TIOR Port Output Rise Time 3.0-5.5V — 10 40 ns
2.0-5.5V — — 145
21* TioF Port Output Fall Time 3.0-5.5V — 1 0 40 ns
2.0-5.5V — — 145
22* Tinp INT Pin High or Low Time 25 — — ns
23* Trbp PORTA change INT high or low time TCY ——ns
* These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKO output is 4 x TOSC.
OSC1
CLKO
I/O pin
(Input)
I/O pin
(Output)
Q4 Q1 Q2 Q3
10
13
14
17
20, 21
22
23
19 18
15
11
12
16
Old Value New Value
PIC16F91X
DS41250A-page 234 Advance Information 2004 Microchip Technology Inc.
FIGURE 19-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
FIGURE 19-6: BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O pins
34
BVDD
Reset (due to BOR)
VDD
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
64 ms Time-out(1)
35
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word is programmed to ‘0’.
2004 Microchip Technology Inc. Advance Informa tion DS41250A-page 235
PIC16F91X
TABLE 19-4: RESET, WATCHDOG T IMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Standard Operating Conditions (unless otherw ise stated)
Operating Temperature -40°C ≤ TA ≤ +125°C
Param
No. Sym Characteristic Min Typ† Max Units Conditions
30 TMCLMCLR Pulse Width (low ) 2
11 —
18 —
24 µs
ms VDD = 5V, -40°C to +85°C
Extended temperature
31 TWDT Watchdog Timer Time-out
Period (No Prescaler) 10
10 17
17 25
30 ms
ms VDD = 5V, -40°C to +85°C
Extended temperature
32 TOST Oscillation Start-up Timer
Period — 1024 TOSC ——TOSC = OSC1 period
33* TPWRT Power-up Timer Period 28*
TBD 64
TBD 132*
TBD ms
ms VDD = 5V, -40°C to +85°C
Extended Temperature
34 TIOZ I/O High-impedance from
MCLR Low or Watchdog Timer
Reset
——2.0µs
BVDD Brown-out Reset Voltage 2.025 — 2.175 V
35 TBOR Brown-out Reset P u lse Width 100* — — µsVDD ≤ BVDD (D005 )
Legend: TBD = To Be Determined
* These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
PIC16F91X
DS41250A-page 236 Advance Information 2004 Microchip Technology Inc.
FIGURE 19-7: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 19-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
41* TT0L T0CKI Low Pulse Width N o Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
42* TT0P T0CKI Period Greater of:
20 or TCY + 40
N
— — ns N = prescale
valu e (2 , 4 , ...,
256)
45* TT1H T1CKI High
Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Synchronous,
with Prescaler 3.0-5.5V 15 — — ns
2.0-5.5V 25 — — ns
Asynchronous 3.0-5.5V 30 — — ns
2.0-5.5V 50 — — ns
46* TT1L T1CKI Low
Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Synchronous,
with Prescaler 3.0-5.5V 15 — — ns
2.0-5.5V 25 — — ns
Asynchronous 3.0-5.5V 30 — — ns
2.0-5.5V 50 — — ns
47* TT1P T1CKI Input
Period Synchronous 3.0-5.5V Greater of:
30 or TCY + 40
N
— — ns N = prescale
value (1, 2, 4, 8)
2.0-5.5V 50 or TCY + 40
N ——ns
Asynchronous 3.0-5.5V 60 — — ns
2.0-5.5V 100 — — ns
FT1 Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN) DC — 200* kHz
48 TCKEZTMR1 Delay from external clock edge to timer
increment 2 TOSC*—7 TOSC*—
* Thes e parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
T0CKI
T1CKI
40 41
42
45 46
47 48
TMR0 o r
TMR1
2004 Microchip Technology Inc. Advance Informa tion DS41250A-page 237
PIC16F91X
FIGURE 19-8: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 19-6: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 19-9: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 19-7: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C ≤ TA ≤ +125°C
Param.
No. Symbol Characteristic Min Max Units Conditions
120 TCKH2DTV SYNC XMIT (Master and Slave)
Clock high to data-out valid 3.0-5.5V — 80 ns
2.0-5.5V — 100 ns
121 TCKRF Clock out rise time and fall time
(Master mo de) 3.0-5.5V — 45 ns
2.0-5.5V — 50 ns
122 TDTRF Data-out rise time and fall time 3.0-5.5V — 45 ns
2.0-5.5V — 50 ns
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C ≤ TA ≤ +125°C
Param.
No. Symbol Characteristic Min Max Units Conditions
125 TDTV2CKL SYNC RCV (Master and Slave)
Data-hold before CK ↓ (DT hold time) 10 — ns
126 TCKL2DTL Data-hold after CK ↓ (DT hold time) 15 — ns
Note: Refer to Figu re 19- 2 for l oad condi tions.
121 121
120 122
RC6/TX/CK
RC7/RX/DT/
SCK/SCL/SEG9
SDI/SDA/SEG8
Note: Refer to Figure 19-2 for load conditions.
125
126
RC6/TX/CK
SCK/SCL/SEG9
RC7/RX/DT/
SDI/SDA/SEG8
PIC16F91X
DS41250A-page 238 Advance Information 2004 Microchip Technology Inc.
FIGURE 19-10: CAPTURE/COMPARE/PWM TIMINGS
TABLE 19-8: CAPTURE/COMPARE/PWM REQUIREMENTS
Param.
No. Sym Characteristic Min Typ† Max Units Conditions
50* TCCL CCP1
input low tim e No Prescaler 0.5TCY + 5 — — ns
With Presca ler 3.0-5.5V 10 — — ns
2.0-5.5V 20 — — ns
51* TCCHCCP1
input high time No Prescaler 0.5TCY + 5 — — ns
With Presca ler 3.0-5.5V 10 — — ns
2.0-5.5V 20 — — ns
52* TCCPCCP1 input period 3TCY + 40
N— — ns N = prescale
value (1,4 or 16)
53* TCCR CCP 1 output fall time 3. 0-5. 5V — 10 25 ns
2.0-5.5V — 25 50 ns
54* TCCF CCP1 output fall time 3. 0-5.5V — 10 25 ns
2.0-5.5V — 25 45 ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
Note: Refer to Figure 19-2 for load conditions.
(Capture mode )
50 51
52
53 54
CCP1/CCP2
(Compare mode)
CCP1/CCP2
2004 Microchip Technology Inc. Advance Informa tion DS41250A-page 239
PIC16F91X
TABLE 19-9: COMPARATOR SPECIFICATIONS
TABLE 19-10: COMP ARATOR VOLTAGE REFERENCE SPECIFICATIONS
TABLE 19-11: PIC16F91X PLVD CHARACTERISTICS:
Comparator Specifications Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +125°C
Sym Characteristics Min Typ Max Units Comments
VOS Input Offset Voltage — ±5.0 ±10 mV
VCM Input Common Mode Vol tage 0 — VDD – 1.5 V
CMRR Common Mode Rejection Ratio +55* — — db
TRT Response Time(1) — 150 400* ns
TMC2COV Comparator Mode Change to
Output Valid —— 10* µs
* These parameters are characterized but not tested.
Note 1: Respons e time mea sured w ith on e comp arator i nput at (VDD – 1. 5)/2 wh ile the other in put trans itions from
VSS to VDD – 1.5V.
Voltage Reference Specifications Standard Operating Conditions (unless otherwise stated)
Operating temperature -40° C ≤ TA ≤ +125°C
Sym. Characteristics Min Typ Max Units Comments
Resolution —
—VDD/24*
VDD/32 —
—LSb
LSb Low Range (VRR = 1)
High Range (VRR = 0)
Absolute Accuracy —
——
—±1/4*
±1/2* LSb
LSb Low Range (VRR = 1)
High Range (VRR = 0)
Unit Resistor Value (R) — 2K* — Ω
Settling Time(1) ——10*µs
* These parameters are characterized but not tested.
Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from ‘0000’ to ‘1111’.
DC Character ist ics Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C ≤ TA ≤ +125°C
Operating Voltage VDD Range 2.0V-5.5V
Sym. Characteristic Min Typ† Max Units Conditions
VPLVD PLVD
Voltage LVDL<2:0> = 000 TBD 1.9 TBD V
TBD TBD 2.0 TBD V
TBD TBD 2.1 TBD V
TBD TBD 2.2 TBD V
TBD TBD 2.3 TBD V
TBD TBD 4.0 TBD V
TBD TBD 4.2 TBD V
TBD TBD 4.5 TBD V
Legend: TBD = To Be Determined
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
PIC16F91X
DS41250A-page 240 Advance Information 2004 Microchip Technology Inc.
FIGURE 19-11: SPI™ MASTER MODE TIMING (CKE = 0, SMP = 0)
FIGURE 19-12: SPI™ MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76
78
79
80
79
78
MSb LSb
bit 6 - - - - - -1
MSb In LSb In
bit 6 - - - -1
Note: Refer to Figure 19-2 for load conditions.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
MSb In
bit 6 - - - - - -1
LSb In
bit 6 - - - -1
LSb
Note: Refer to Figure 19-2 for load conditions.
2004 Microchip Technology Inc. Advance Informa tion DS41250A-page 241
PIC16F91X
FIGURE 19-13: SPI™ SLAV E MODE TIMING (CKE = 0)
FIGURE 19-14: SPI™ SLAV E MODE TIMING (CKE = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76 77
78
79
80
79
78
MSb LSb
bit 6 - - - - - -1
MSb In bit 6 - - - -1 LSb In
83
Note: Refer to Figure 19-2 for load conditions.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
82
74
75, 76
MSb bit 6 - - - - - -1 LSb
77
MSb In bit 6 - - - -1 LSb In
80
83
Note: Refer to Figure 19-2 for load conditions.
PIC16F91X
DS41250A-page 242 Advance Information 2004 Microchip Technology Inc.
TA BLE 19-12: SPI™ MODE REQUIREMENTS
FIGURE 19-15 : I2C™ BUS START/STOP BITS TIMING
Param
No. Symbol Characteristic Min Typ† Max Units Conditions
70* TSSL2SCH,
TSSL2SCLSS↓ to SCK↓ or SCK↑ input TCY ——ns
71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns
72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns
73* TDIV2SCH,
TDIV2SCLSetup time of SDI data input to SCK edge 100 — — ns
74* TSCH2DIL,
TSCL2DILHold time of SDI data input to SCK edge 100 — — ns
75* TDOR SDO data outp ut ris e time 3.0-5 .5V — 10 25 ns
2.0-5.5V — 25 50 ns
76* TDOF SDO data outp ut fall time — 10 25 ns
77* TSSH2DOZSS↑ to SDO output high-impedance 10 — 50 ns
78* TSCR SCK output rise time
(Master mo de) 3.0-5.5V — 10 25 ns
2.0-5.5V — 25 50 ns
79* TSCF SCK output fa ll time (Master mode) — 10 25 ns
80* TSCH2DOV,
TSCL2DOVSDO data output valid after
SCK edge 3.0-5.5V — — 50 ns
2.0-5.5V — — 145 ns
81* TDOV2SCH,
TDOV2SCLSDO data output set up to SCK edge Tcy — — ns
82* TSSL2DOV SDO data output valid after SS↓ edge — — 50 ns
83* TSCH2SSH,
TSCL2SSHSS ↑ after SCK edge 1.5TCY + 40 — — ns
* These parameters are charac terized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note: Refer to Figure 19-2 for load conditions.
91
92
93
SCL
SDA
Start
Condition Stop
Condition
90
2004 Microchip Technology Inc. Advance Informa tion DS41250A-page 243
PIC16F91X
TABLE 19-13: I2C™ BUS STAR T/STOP BITS REQUIREMENTS
FIGURE 19-16 : I2C™ BUS DATA TIMING
Param
No. Symbol Characteristic Min Typ Max Units Conditions
90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated
Start condi tio n
Setup time 400 kHz mode 600 — —
91* THD:STA St art condition 100 kHz mode 4000 — — ns After this period, the first clock
pulse is generated
Hold time 400 kHz mode 600 — —
92* TSU:STO S top c on dition 10 0 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
93 THD:STO Stop condi tion 100 kHz mo de 4000 — — ns
Hold time 400 kHz mode 600 — —
* These parameters are charac terized but not tested.
Note: Refer to Figure 19-2 f o r load conditions.
90
91 92
100 101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
PIC16F91X
DS41250A-page 244 Advance Information 2004 Microchip Technology Inc.
TABLE 19-14: I2C™ BUS DATA REQUIREMENTS
Param.
No. Symbol Characteristic Min Max Units Conditions
100* THIGH Clock high time 100 kHz mode 4.0 — µs Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — µs Device mu st ope rate at a
minimum of 10 MHz
SSP Module 1.5TCY —
101* TLOW Clock low time 100 kHz mode 4.7 — µs Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — µs Device mu st ope rate at a
minimum of 10 MHz
SSP Module 1.5TCY —
102* TRSDA and SCL rise
time 100 kHz mode — 1000 ns
400 kHz mode 20 + 0.1CB300 ns CB is specified to be from
10-400 pF
103* TFSDA and SCL fall
time 100 kHz mode — 300 ns
400 kHz mode 20 + 0.1CB300 ns CB is specified to be from
10-400 pF
90* TSU:STA Start condition
setup time 100 kHz mode 4.7 — µs Only releva nt f or
Repeated Start condition
400 kHz mode 0.6 — µs
91* THD:STA Start condition hold
time 100 kHz mode 4.0 — µs After this period the first
clock pulse is generated
400 kHz mode 0.6 — µs
106* THD:DAT Data input hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 µs
107* TSU:DAT Data input setup
time 100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
92* TSU:STO Stop condition
setup time 100 kHz mode 4.7 — µs
400 kHz mode 0.6 — µs
109* TAA Output valid from
clock 100 kHz mode — 3500 ns (Note 1)
400 kHz mode — — ns
110* TBUF Bus free time 100 kHz mode 4.7 — µs Time the bus must be free
before a new transmission
can start
400 kHz mode 1.3 — µs
CBBus capacitive loading — 400 pF
* These parameters are charac terized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 k Hz) I2C bus de vice can be used in a St andard mode (100 kHz ) I 2C bus sys tem, but the
requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not
stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it
must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (ac c ording to the
Standard mode I2C bus speci fication), b efore the S CL line is rele ased.
2004 Microchip Technology Inc. Advance Informa tion DS41250A-page 245
PIC16F91X
TABLE 19-15: PIC16F91X A/D CONVERTER CHARACTERISTICS:
Standard O perating Co ndi tions (unless o th erwise stated)
Operat i ng Temperature -40° C ≤ TA ≤ +125°C
Param
No. Sym Characteristic Min Typ† Max Units Conditions
A01 NRResolution — — 10 bi ts bit
A02 EABS Total Absol ute Error*(1) ——±1LSbVREF = 5.0V
A03 EIL Integral Erro r — — ±1LSbVREF = 5.0V
A04 EDL Differential Error — — ±1 LSb No missing codes to 10 bits
VREF = 5.0V
A05 EFS Full-scale Range 2.2* — 5.5* V
A06 EOFF Offset Error — — ±1LSbVREF = 5.0V
A07 EGN Gain Error — — ±1LSbVREF = 5.0V
A10 — Monotonicity — assured(2) ——VSS ≤ VAIN ≤ VREF+
A20 VREF Reference Voltage (VREF+
– VREF-) 2. 0 — VDD + 0.3 V
A21 VREF+ Refer ence Volt age High AVDD –
2.5V —AVDD +
0.3V V
A22 VREF- Reference Voltage Lo w AVSS –
0.3V —VREF+ –
2.0V V
A25 VAIN Analog Input Voltage VSS —VREF V
A30 ZAIN Recommended Impedance
of Analog Voltage Sour ce ——10kΩ
A50 IREF VREF Input Current (Note 3) —
——
—±5
±150 µA
µADuring VAIN acquisition .
During A/D conversion cycle.
* These para m et er s ar e characterized but not tested.
† Data in ‘Typ’ colu m n i s at 5.0 V, 25°C unless oth er w i se sta te d. These paramet er s ar e f or d esi gn guidanc e onl y
and ar e not teste d.
Note 1: Total Absolut e Er ro r inc lu des integral, different ial , offset and gai n e rr or s.
2: The A/D conver si on r esult neve r de cr eases with an increas e in the in put voltage and has no m i ssing codes.
3: VREF+ current is from RA3/AN3/C1+/VREF+/SEG 15 pin or AVDD, wh ic hever is selected as the VREF+ source.
VREF- cur r ent is from R A 2/AN2/C 2+/VREF-/COM2 pi n or AVSS, whichever is selected as the VREF- source.
PIC16F91X
DS41250A-page 246 Advance Information 2004 Microchip Technology Inc.
FIGURE 19-17: PIC16F91X A/D CONVERSION TIMING (NORMAL MODE)
TABLE 19-16: PIC16F91X A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherw ise stated)
Operating Temperature -40°C ≤ TA ≤ +125°C
Param
No. Sym Characteristic Min Typ† Max Units Conditions
130 TAD A/D Clock Period(2) 1.6 — — µsTOSC-based, VREF ≥ 3.0V
3.0* — — µsTOSC-based, VREF full range
130 TAD A/D Internal RC
Oscillator Perio d 3.0* 6.0 9.0* µsADCS<1:0> = 11 (RC mode)
At VDD = 2.5V
2.0* 4.0 6.0* µsAt VDD = 5.0V
131 TCNV Conversion Time
(not includin g
Acquisiti on Time) (1)
—11—TAD Set GO/DONE bit to new data in A/D
Result regi st er
132 TACQ Acquisition Time
5*
11.5
—
—
—
µs
µs The minimum time is the amplifier
settling time. This may be used if th e
“new” inpu t voltag e has not changed
by more than 1 LSb (i.e., 4.1 mV @
4.096V) from the last sampled
volt a ge (as stored on CHOLD).
134 TGO Q4 to A/D Clock
Start —TOSC/2 — — If the A/D cl ock source is selecte d as
RC, a time of TCY is ad ded before
the A/D clock starts. This allows the
SLEEP instruction to be executed.
* These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested .
Note 1: ADRESH and ADRESL registers ma y be read on the following TCY cycl e.
2: See Table 12-1 for minimum conditions.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D Data
ADRES
ADIF
GO
Sample
OLD_DATA
Sampling Stopped
DONE
NEW_DATA
987 3210
Note 1: If the A /D clock sourc e is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
1 TCY
6
134 (TOSC/2)(1)
1 TCY
2004 Microchip Technology Inc. Preliminary DS41250A-page 247
PIC16F91X
20.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs are not available at this time.
PIC16F91X
DS41250A-page 248 Preliminary 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Preliminary DS41250A-page 249
PIC16F91X
21.0 PACKAGING INFORMATION
21.1 Package Marking Information
Legend: XX...X Customer specific information*
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the even t the full M icroc hip p art num ber cann ot be marked on one lin e, it will
be carried over to the next line thu s li mi tin g the num be r of av ail abl e ch arac te rs
for customer specific information.
*Standard PICmicro® device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
28-Lead PDIP (Skinny DIP)
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC16F913-I/SP
0410017
40-Lead PDIP
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC16F914-I/SP
0410017
Example
28-Lead QFN
XXXXXXXX
XXXXXXXX
YYWWNNN
16F916
-I/ML
0410017
PIC16F91X
DS41250A-page 250 Preliminary 2004 Microchip Technology Inc.
Package Marking Information (Continued)
28-Lead SOIC
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
Example
PIC16F913-I/SO
0410017
28-Lead SSOP
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Example
PIC16F916-I/SS
0410017
XXXXXXXXXX
44-Lead QFN
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Example
PIC16F914
-I/ML
0410017
44-Lead TQFP
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Example
PIC16F917-I/PT
0310017
2004 Microchip Technology Inc. Preliminary DS41250A-page 251
PIC16F91X
21.2 Package Details
The following sections give the technical details of the
packages.
28-Lead Skinny Plasti c Dual In-line (SP) – 300 mil Body (PDIP)
1510515105
β
Mold Draft Angle Bottom 1510515105
α
Mold Draft Angle Top 10.928.898.13.430.350.320eBOverall Row Spacing § 0.560.480.41.022.019.016BLower Lead Width 1.651.331.02.065.053.040B1Upper Lead Width 0.380.290.20.015.012.008
c
Lead Thickness 3.433.303.18.135.130.125LTip to Seating Plane 35.1834.6734.161.3851.3651.345DOverall Len gth 7.497.246.99.295.285.275E1Molded Package Width 8.267.877.62.325.310.300EShoulder to Shoulder Wid th 0.38.015A1Base to Seating Plane 3.433.303.18.135.130.125
A2
Molded Package Thick ness 4.063.813.56.160.150.140ATop to Seating Plane 2.54.100
p
Pitch 2828
n
Number of Pin s MAXNOMMINMAXNOMMINDimen sion Li mits MILLIMETERSINCHES*Units
2
1
D
n
E1
c
eB
β
E
α
p
L
A2
B
B1
A
A1
Notes:
JEDEC Equivalent: MO-095
Drawing No. C04-070
* Controlling Parameter
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0. 254 mm ) per si de.
§ Significant Characteristic
PIC16F91X
DS41250A-page 252 Preliminary 2004 Microchip Technology Inc.
40-Lead Plastic Dual In-line (P) – 600 mil Body (PDIP)
1510515105
β
Mold Draft Angle Bottom 1510515105
α
Mold Draft Angle Top 17.2716.5115.75.680.650.620eBOverall Row Spacing § 0.560.460.36.022.018.014BLower Lea d Width 1.781.270.76.070.050.030B1Upper Lea d Width 0.380.290.20.015.012.008
c
Lead Thic kness 3.433.303.05.135.130.120LTip to Seating Plane 52.4552.2651.942.0652.0582.045DOverall Length 14.2213.8413.46.560.545.530E1Molded Package Width 15.8815.2415.11.625.600.595EShoulder to Shoulder Width 0.38.015
A1
Base to Seating Plane 4.063.813.56.160.150.140A2Molded Package Thickness 4.834.454.06.190.175.160ATop to Seating Plane 2.54.100
p
Pitch 4040
n
Number of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
A2
1
2
D
n
E1
c
βeB
E
α
p
L
B
B1
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
§ Significant Characteristic
2004 Microchip Technology Inc. Preliminary DS41250A-page 253
PIC16F91X
28-Lead Plasti c Quad Flat No Lead Package (ML) 6x6 mm Body (QFN) –
With 0.55 mm Contact Length (Saw Singulated)
Contact Width
*Controlling Parameter
Drawing No. C04-105
Notes:
JEDEC equivalent: MO-220
b .009 .011 .013 0.23 0.28 0.33
Pitch
Number of Pins
Overall Width
Standoff
Overall Length
Overall Height
MAX
Units
Dimension Limits
A1
D
E
n
e
A
.000
INCHES
.026 BSC
MIN
28
NOM MAX
.002 0.00
6.00
MILLIMETERS*
.039
MIN
28
0.65 BSC
NOM
0.05
1.000.90.035
.001 0.02
Contact Length L .020 .024 .028 0.50 0.60 0.70
E2
D2
Exposed Pad Width
Exposed Pad Length
.140 .146 .152 3.55 3.70 3.85
.031 0.80
5.90 6.10.240.236.232
.232 .236 6.00.240 5.90 6.10
.140 .146 3.70.152 3.55 3.85
b
D2
D
PAD OUTLINE
ALTERNATE
SEE DETAIL
A1
A
DETAIL
TOP VIEW
OPTIONAL
INDEX
AREA
1
2
L
BOTTOM VIEW
n
E
METAL
PAD
ALTERNATE
EXPOSED
INDICATORS
INDEX
e
E2
Revised 05-24-04
Contact Thickness A3 .008 REF 0.20 REF
PIC16F91X
DS41250A-page 254 Preliminary 2004 Microchip Technology Inc.
28-Lead Plasti c Quad Flat No Lead Package (ML) 6x6x0.9 mm Body (QFN-S) –
With 0.40 mm Contact Length (Saw Singulated)
Lead Width
*Controlling Parameter
Drawing No. C04-124
Notes:
JEDEC equivalent: MO-220
b .013 .015 .017 0.33 0.38 0.43
Pitch
Number of Pins
Overall Width
Standoff
Overall Length
Overall Height
MAX
Units
Dimension Limits
A1
D
E
n
e
A
.000
INCHES
.026 BSC
MIN
28
NOM MAX
.002 0.00
6.00
MILLIMETERS*
.039
MIN
28
0.65 BSC
NOM
0.05
1.000.90.035
.001 0.02
Lead Length L .012 .016 .020 0.30 0.40 0.50
E2
D2
Exposed Pad Width
Exposed Pad Length
.169 .175 .177 4.30 4.45 4.50
.031 0.80
5.90 6.10.240.236.232
.232 .236 6.00.240 5.90 6.10
.169 .175 4.45.177 4.30 4.50
b
D2D
A1
A
TOP VIEW
OPTIONAL
INDEX
AREA
1
2
L
BOTTOM VIEW
n
E
METAL
PAD
ALTERNATE
EXPOSED
INDICATORS
INDEX
e
E2
Revised 05/24/04
2004 Microchip Technology Inc. Preliminary DS41250A-page 255
PIC16F91X
44-Lead Plasti c Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)
PIC16F91X
DS41250A-page 256 Preliminary 2004 Microchip Technology Inc.
28-Lead Plasti c Small Outline (SO) – Wide, 300 mil Body (SOIC)
Foot Angle Top φ048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.330.280.23.013.011.009
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 18.0817.8717.65.712.704.695DOverall Length 7.597.497.32.299.295.288E1Molded Package Width 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004A1Standoff § 2.392.312.24.094.091.088A2Molded Package Thickness 2.642.502.36.104.099.093AOverall Height 1.27.050
p
Pitch 2828
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
p
n
B
E
E1
L
c
β
45°
h
φ
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
§ Significant Characteristic
2004 Microchip Technology Inc. Preliminary DS41250A-page 257
PIC16F91X
28-Lead Plastic Shrink Small Outline (SS) – 209 mil Body, 5.30 mm (SSOP)
0.38-0.22.015-.009BLead Width
8°4°0°8°4°0°
f
Foot Angle
0.25-0.09.010-.004
c
Lead Thickness
0.950.750.55.037.030.022LFoot Length
10.5010.209.90.413.402.390DOverall Length
5.605.305.00.220.209.009E1Molded Package Width
8.207.807.49.323.307.295EOverall Width
--0.05--.002A1Standoff
1.851.751.65.073.069.065A2Molded Package Thickness
2.0--.079--AOverall Height
0.65.026
p
Pitch
2828
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERS*INCHESUnits
2
1
D
p
n
B
E1
E
L
c
f
A2
A1
A
shall not exceed .010" (0.254mm) per side.
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions
Notes:
JEDEC Equivalent: MO-150
Drawing No. C04-073
*Controlling Parameter
PIC16F91X
DS41250A-page 258 Preliminary 2004 Microchip Technology Inc.
44-Lead Plastic Thin Quad Flatp ack (PT) 10x10x1 mm Body, 1.0/0. 10 mm Lead Form (TQFP)
* Controlling Parameter
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
1.140.890.64.045.035.025CHPin 1 Corner Chamfer
1.00.039
(F)
Footprint (Reference)
(F)
A
A1 A2
α
E
E1
#leads=n1
p
B
D1 D
n
1
2
φ
c
βL
Units INCHES MILLIMETERS*
Dim ension Limits MIN NOM MAX MIN NOM MAX
Numb er of Pin s n44 44
Pitch p.031 0.80
Overall Height A .039 .043 .047 1.00 1.10 1.20
Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05
Standoff § A1 .002 .004 .006 0.05 0.10 0.15
Foot Length L .018 .024 .030 0.45 0.60 0.75
Foot A ngle φ03.5 7 03.5 7
Overall Width E .463 .472 .482 11.75 12.00 12.25
Overall Length D .463 .472 .482 11.75 12.00 12.25
Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10
Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10
Pins per Side n1 11 11
Lead Thickness c.004 .006 .008 0.09 0.15 0.20
Lead Width B .012 .015 .017 0.30 0.38 0.44
Mold Draft Angle Top α51015 51015
Mold Draft Angle Bottom β51015 51015
CH x 45°
§ Significant Characteristic
2004 Microchip Technology Inc. Preliminary DS41250A-page 259
PIC16F91X
APPENDIX A: DATA SHEET
REVISION HISTORY
Revision A
This is a new data sheet.
APPENDIX B: MIGRATING FROM
OTHER PICmicro®
DEVICES
This discusses some of the issues in migrating from
other PICmicro devices to the PIC16F91X family of
devices.
B.1 PIC16F676 to PIC16F91 X
TABLE B-1: FEATURE COMPARISON
Feature PIC16F676 PIC16F91X
Max Operating Speed 20 MHz 20 MHz
Max Program Memory
(Words) 1K 8K
Max SRAM (Bytes) 6 4 352
A/D Resolution 10-bit 10-bit
Data EEPROM (bytes) 128 256
Timers (8/16-bit) 1/1 2/1
Oscillator Modes 8 8
Brown-out Reset Y Y
Internal Pull -up s RB0/1/ 2/ 4/5 RB<7:0>
Interrupt-on-change RB0/1/2/3
/4/5 RB<7:4>
Comparator 1 2
USART N Y
Extended WDT N Y
Software Control
Option of WDT/BOR NY
INTOSC Frequencies 4 MHz 32 kHz -
8MHz
Clock Switch in g N Y
PIC16F91X
DS41250A-page 260 Preliminary 2004 Microchip Technology Inc.
APPENDIX C: CONVERSION
CONSIDERATIONS
Considerations for converting from previous versions
of de vices to the one s listed in this dat a sheet are liste d
in Table C-1.
TABLE C-1: CONVERSION CONSIDERATIONS
Characteristic PIC16F91X PIC16F87X PIC16F87XA
Pins 28/40 28/40 28/40
Timers 3 3 3
Interrupts 11 or 12 13 or 14 14 or 15
Communication USART, SSP
(SPI™, I2C™ Slave) PSP, USART, SSP
(SPI, I2C Master/Sla ve) PSP, USAR T, SSP
(SPI, I2C Master/Slave)
Frequency 20 MHz 20 MHz 20 MHz
Voltage 2.0V-5.5V 2.2V-5.5V 2.0V-5.5V
A/D 10-bit,
7 convers ion clock selects 10-bit,
4 conver si on clo ck selects 10-bit,
7 conve rsi on clock selects
CCP 2 2 2
Comparator 2 — 2
Comparator Voltage
Reference Yes — Yes
Prog ram Memory 4K, 8K E PROM 4K, 8K Flash
(Erase/Write on
single-word)
4K, 8K Flash
(Erase/Write on
four-word blo cks)
RAM 256, 352 bytes 192, 368 bytes 192, 368 bytes
EEPROM Data 256 bytes 128, 256 bytes 128, 256 bytes
Code Protectio n On/Of f Segmented , starting at end
of pr ogram memory On/Off
Program Memory
Write Protection — On/Off Segmented, starting at
beginning of
program memory
LCD Module 16, 24 segment drivers,
4 commons ——
Other In-Circuit Debugger,
Low-Voltage Programming In-Circuit Debugger,
Low-Voltage Programming I n-Circuit Debugger,
Low-Voltage P rogrammi ng
2004 Microchip Technology Inc. Preliminary DS41250A-page 261
PIC16F91X
INDEX
A
A/D Acquisition Requirements.................. .... .... .. ......... ....149
Analog Port Pins.......................................................144
Associ a te d Re g i sters.............. ................... ...............151
Block Diag ram......... ................... ...............................143
Calculating Acquisition Time.....................................149
Channel Selection.......................... .. .... .. .... .. ....... .... ..144
Configuration and Operation.....................................144
Configuring................................................................148
Configur ing Interrupt.................................................148
Conversion (TAD) Cycles ..........................................145
Conversi o n Clo ck...... ................... .......... ...................144
Effects of Reset.........................................................151
Internal Sampling Switch (RSS) Impedance..............149
Operation During Sleep ............................................150
Output Fo rmat................. ................... ................... ....145
Reference Voltage (VREF).........................................144
Source Impedance................ ......... .... .... .... ......... .... ..149
Specifications............................................................246
Starting a Conversion ...............................................145
TAD vs. Operating Frequencies. ................................144
Absolute Maxim um Ratings..............................................221
AC Characteristics
Industrial and Extended......................................... ...231
Load Conditions........................... .. .... .. .. .. .. .. ....... .. .. ..230
ACK pulse.............. ................... ........... ................... ..........169
ADCON0 Register.............................................................146
ADCON1 Register.............................................................147
Addressable Universal Synchronous Asynchronous Rece iver
Transmitter. See USART
Analog Input Connections...................................................94
Analog-to-Digital Converter Module. See A/D
ANSEL Register................................................................146
Assembler
MPASM Ass embler...................................................215
Asynchronous Reception
Associated Registers ........................................135, 137
Asynchronous Transmission
Associ a te d Re g i sters.............. ................... ...............133
B
Baud Rate Generator
Associ a te d Re g i sters.............. ................... ...............129
BF bit........ .................. ................... ....................................160
Block Diagrams
A/D............................................................................143
Analog Input Model.............................................94, 150
Capture Mod e....... ..................................... ...............179
Comparator 1................................. ................... ..........96
Comparator 2................................. ................... ..........96
Comparator Modes .......................... .. .... .. .. ....... .. .... .. ..95
Comparator Voltage Reference (CVREF)....................98
Compare Mode....... .......... ................... ........... ..........180
Fail-S afe Clock Monitor (FSCM).................................41
In-Circuit Serial Programming Connections..............203
Inter rupt Logic................. ................... ................... ....196
LCD Clock Generation..............................................108
LCD Driver Module ...................................................102
LCD Resistor Ladder Connection.............................106
MCLR Circuit............... ................... .......... .................188
On-Chip Rese t Circuit........................ .......................187
PIC16F913/916.............................................................8
PIC16F914/917.............................................................9
PWM Mode..... ................... .................. ..................... 181
RA0 Pin ...................................................................... 45
RA1 Pin ...................................................................... 46
RA2 Pin ...................................................................... 47
RA3 Pin ...................................................................... 48
RA4 Pin ...................................................................... 49
RA5 Pin ...................................................................... 50
RA6 Pin ...................................................................... 51
RA7 Pin ...................................................................... 52
RB Pins....................................................................... 57
RB4 Pin ...................................................................... 58
RB5 Pin ...................................................................... 59
RB6 Pin ...................................................................... 60
RB7 Pin ...................................................................... 61
RC0 Pin...................................................................... 64
RC1 Pin...................................................................... 65
RC2 Pin...................................................................... 65
RC3 Pin...................................................................... 66
RC4 Pin...................................................................... 67
RC5 Pin...................................................................... 68
RC6 Pin...................................................................... 69
RC7 Pin...................................................................... 70
RD Pins ...................................................................... 75
RD0 Pin...................................................................... 74
RD1 Pin...................................................................... 74
RD2 Pin...................................................................... 75
RE Pins....................................................................... 78
Resonator Operation.................................................. 36
SSP (I2C Mode).................................. ...................... 169
SSP (SPI Mode) ............... ..................... ................... 162
System Clock .............................................................. 31
Timer1 ........................................................................ 85
Timer2 ........................................................................ 91
TMR0/WDT Pr escaler ................................................ 81
USART Receive ....................................... .... .. .. 135, 136
USART Transm i t ................. ................... .......... ........ 132
Watchdog Timer (WDT)........................................ .... 199
BRGH bit .......................................................................... 129
Brown-o u t Re set (BOR)............... ................... .......... ........ 189
Associ a te d Re g i sters......................... ................... .... 190
Calibration ................................................................ 189
Specifications ........................................................... 235
Timing and Characteristics................................... .... 234
C
C Compilers
MPLAB C17........ ................... ................... ................ 216
MPLAB C18........ ................... ................... ................ 216
MPLAB C30........ ................... ................... ................ 216
Capture/Compar e /PWM (CCP) .................................. ...... 177
Associated Registers
Capture, Compare and Timer1................. ........ 182
PWM and Timer2.............................................. 183
Capture Mod e............... ...................................... ...... 179
Block Diag ram...... ........... ................... .......... .... 179
CCP1CON Regis te r... .................. ........... .......... 17 8
CCP1IF............................................................. 179
Prescaler .......................................................... 179
CCP Timer Resou rce s.............................................. 177
Compare
Special Trigger Output of CCP1. ...................... 180
Special Trigger Output of CCP2. ...................... 180
Compare Mode.................................. ........... ............ 180
Block Diag ram...... ........... ................... .......... .... 180
PIC16F91X
DS41250A-page 262 Preliminary 2004 Microchip Technology Inc.
Softwa re In terrupt Mode ............................ .......180
Special Event Trigger........................................180
Interaction of Two CCP Modules (table).......... .. .......177
PWM Mode.... .......... ................... ................... ...........181
Block Diag ram......... ................... .......................181
Duty Cycle............. .......... ........... .................. .....181
Example Frequencies/Resolutions (table)........182
PWM Period...................... ................... .............181
Special Event Trigger and A/D Conversions.............180
CCP. See Capture/Compare/ PW M
CCP1CON Registe r..... ...............................................76, 178
CCPR1H Registe r................. .......... ..................................177
CCPR1L Regis ter..............................................................177
CCPxM0 bit.......................................................................178
CCPxM1 bit.......................................................................178
CCPxM2 bit.......................................................................178
CCPxM3 bit.......................................................................178
CCPxX bit..........................................................................178
CCPxY bit..........................................................................178
CKE bit................. ................... ................... .................. .....160
CKP bit................. ................... ................... .................. .....161
CMCON0 Register ..............................................................93
CMCON1 Register ..............................................................97
Code Examples
A/D Conversion............... .......... ................... ........... ..148
Assigni n g Prescaler to Timer0............. ................... ....83
Assigni n g Prescaler to WDT...................... .................83
Call of a Subroutine in Page 1 from Page 0....... .. .......29
Indirect Addressing .....................................................30
Initia lizing PORTA.......................................................43
Initia lizing PORTB.......................................................53
Initia lizing PORTC.......................................................63
Initia lizing PORTD.......................................................72
Initia lizing PORTE.......................................................77
Loading the SSPBUF (SSPSR) R egister..................163
Saving Status and W Registers in RAM ...................198
Code Protection ................................................................203
Comparator Module .................... .. .... .. .. ....... .. .... .. .. .... .. .......93
Comparator Voltage Reference (CVREF)
Associ a te d Re g i sters .................. ........... ...................100
Effects of a Reset........................................................99
Response Time.............................................. .... .........99
Comparator Voltage Reference (CVREF)............................98
Accuracy/Error ............................................................98
Configuring..................................................................98
Specifications............................................................239
Comparators
Associ a te d Re g i sters .................. ........... ...................100
C2OUT as T1 Gate............................ .......... .........86, 97
Configurations.............................................................95
Effects of a Reset........................................................99
Interrupts.....................................................................97
Operation ....................................................................94
Operation During Sleep ..............................................99
Outputs .......................................................................97
Response Time.............................................. .... .........99
Specifications............................................................239
Synchro n i zing C2OUT w/ Timer1 ........ .......... ........... ..97
CONFIG Regi ster....... ................... .......... ................... .......186
Configur ation Bits..............................................................186
Conversi on Co n side rations......... ......................................260
CPU Features ...................................................................185
D
D/A bit...................... ........... ................... ................... ........ 1 6 0
Data EEPRO M Mem ory............................... ................... .. 153
Associ a te d Re g i sters...... ................... .......... ............. 158
Reading .................................................................... 156
Writing ...................................................................... 156
Data Memor y....... ................... ........... .................. ........... .... 14
Data/Address bit (D/A)...................................................... 160
DC Characteristics
Extended and Industrial............................................ 228
Industrial and Extended............................................ 223
Demonstration Boards
PICDEM 1................................................................. 218
PICDEM 17............................................................... 219
PICDEM 18R............................................................ 219
PICDEM 2 Plus ......................................................... 218
PICDEM 3................................................................. 218
PICDEM 4................................................................. 218
PICDEM LIN............................................................. 219
PICDEM USB...........................................................219
PICDEM.net Internet/Ethernet..................................218
Development Support....................................................... 215
Device Overview ................................................................... 7
E
EEADRH Registers................................................... 153, 154
EEADRL Registers . .................................................. 153, 154
EECON1 Register......................... .. ....... .. .... .. .. .... ..... 153, 155
EECON2 Regist e r.... ................... ........... ........................... 1 5 3
EEDATH Register............................................................. 154
EEDATL Register ............................................................. 154
Electrical Specifications.................................................... 221
Enhanced Capture/Compare/PWM (ECCP)
Enhanced PWM Mode
TMR2 to PR2 Match........................................... 90
Errata.................................................................................... 5
Evaluation and Programm i n g To o l s........................ ..........219
F
Fail-S afe Clock Monitor ...................................................... 41
Fail-Safe Condition Clearing....................................... 42
Reset and Wak e -up fr o m Sleep.................................. 42
Firmware Instructions .......................................................205
Flash Pr o g ram Memory....................... ................... .......... 153
Fuses. See Configuration Bits
G
General Purpose Register File ..................................... .... .. 14
I
I/O Ports................. ................... ................... ................... .... 43
I2C Mode
Addressing................................................................ 170
Associ a te d Re g i sters...... ................... ....................... 176
Master M ode............................................................. 175
Mode Sele ction.................................... ........... ..........169
Multi-Master Mode.................................................... 175
Operation.................................................................. 169
Reception ................................................................. 171
Slave Mode
SCL and SDA pins......................................... ... 169
Transmission ............................................................ 173
ID Locations...................................................................... 203
In-Circuit Debugger ........................................................... 204
In-Circuit Serial Programming (ICSP)............................... 203
2004 Microchip Technology Inc. Preliminary DS41250A-page 263
PIC16F91X
Indirect Addressing, INDF and FSR Registers ...................30
Instruction Format.............................................................206
Instruction Set...................................................................205
ADDLW.....................................................................208
ADDWF.....................................................................208
ANDLW.....................................................................208
ANDWF.....................................................................208
BCF...........................................................................208
BSF...........................................................................208
BTFSC......................................................................209
BTFSS ......................................................................208
CALL.........................................................................209
CLRF.........................................................................209
CLRW .......................................................................209
CLRWDT...................................................................209
COMF .......................................................................209
DECF........................................................................209
DECFSZ....................................................................210
GOTO .......................................................................210
INCF..........................................................................210
INCFSZ.....................................................................210
IORLW......................................................................210
IORWF......................................................................210
MOVF........................................................................211
MOVLW ....................................................................211
MOVWF....................................................................211
NOP..........................................................................211
RETFIE.....................................................................212
RETLW .....................................................................212
RETURN...................................................................212
RLF...........................................................................213
RRF...........................................................................213
SLEEP ......................................................................213
SUBLW.....................................................................213
SUBWF.....................................................................213
SWAPF.....................................................................214
XORLW.....................................................................214
XORWF.....................................................................214
Summary Ta b l e..... .................. ........... ................... ....207
INTCON Register................................................................23
Inter-Integrated Circuit (I2C). See I2C Mode
Internal Oscillator Block
INTOSC
Specifications....................................................232
Internal Sampling Switch (Rss) Impedance......................149
Interrupt Sources
USART Receive/Transmit Complete ........................127
Interrupts...........................................................................195
A/D............................................................................148
Associ a te d Re g i sters.............. ................... ...............197
Comparators...............................................................97
Context Saving..........................................................198
Interrupt-on-change ....................................................53
PORTB Interrupt-on-C hange . ...................................196
RB0/INT/SEG0..........................................................196
TMR0........................................................................196
TMR1..........................................................................86
TMR2 to PR2 Match ...................................................91
TMR2 to PR2 Match (PWM).......................................90
INTOSC Specifications .......................... .......... ........... ......232
IOCB Register.......................................... ................... ........54
L
LCD Associ a te d Re g i sters.............. ................... ...............124
Bias Types................................................................106
Clock Source Selection ............................................ 106
Configuring the Module ....................... ..... .. .. .. .... .. .. .. 124
Frame Frequency ..................................................... 107
Interrupts .................................................................. 121
LCDCON Register.................................................... 101
LCDDATA Register ........... .......... ........... .................. 101
LCDPS Register....................................................... 101
LCDSE Register....................................................... 101
Multiplex Types..... ...................................... .......... .... 107
Operation During Sleep............................................ 122
Pixel Control............................................................. 107
Prescaler .................................................................. 106
Segment Enables ............................ .. ....... .. .... .. .. .... .. 107
Waveform Generation . ............................................. 110
LCDCON Register............................................................ 101
LCDDATA Register... ............................... ........... .............. 101
LCDPS Register ............................................................... 101
LP Bits...................................................................... 106
LCDSE Register ............................................................... 101
Liquid Crystal Display (LCD) Driver.................................. 101
Load Conditions................................................................ 230
M
MCLR ............................................................................... 188
Internal...................................................................... 188
Memory Organization ......................................................... 13
Data............................................................................ 14
Program...................................................................... 13
Migratin g fr o m oth e r PICm ic ro Devices................ .......... .. 259
MPLAB ASM30 Assembler, Linker, Librarian................... 216
MPLAB ICD 2 In-Circuit Debugger................................... 217
MPLAB ICE 2000 High-Performance Universal In-Circuit Em-
ulator......................................................................... 217
MPLAB ICE 4000 High-Performance Universal In-Circuit Em-
ulator......................................................................... 217
MPLAB Integrated Development Environment Software.. 215
MPLAB PM3 Device Programmer.................................... 217
MPL IN K Obje ct Link e r / M PLIB Ob j e ct Libra ri a n... ...... .. ..... 21 6
O
OPCODE Field Desc r i p tions................ ........... .................. 205
OPTION_R EG Re gister........ ...................................... .. 22, 82
OSCCON Register.............................................................. 32
Oscillator
Associ a te d Re g i sters......................... ................... ...... 42
Oscillator Configurations. .. ......... ......................................... 31
Oscillato r Delay Examples......... ................................. 34
Special Cases............................................................. 33
Oscillato r S pecifications...... ..................... ........... .............. 231
Oscillator Start-up Timer (OST)
Specifications ........................................................... 235
Oscillator Switching
Fail-S afe Clock Monitor .............................................. 41
Two-Spe ed Clock Star t- u p ................................... ...... 40
OSCTUNE Regis te r................................... ........... .............. 38
P
P (Stop) bit........................................................................ 160
Packaging......................................................................... 249
Marking............................................................. 249, 250
PDIP Details............................................................. 251
SOIC Details................. .............................. .............. 256
TSSOP Details ............... ........... ................... .......... .. 256
Pagin g , Pr o gram Memory................ ................... ................ 29
PCL and PCLATH............................................................... 29
Computed GOTO ....................................................... 29
PIC16F91X
DS41250A-page 264 Preliminary 2004 Microchip Technology Inc.
Stack...........................................................................29
PCON Register .................................................................190
PICkit 1 Flash Starter Kit...................................................219
PICSTART Plus Developm ent Programm er . ....................218
PIE1 Register......................................................................24
PIE2 Register......................................................................25
Pin Diagram
PIC16F913/916, 28-pin.................................................3
PIC16F914/917, 40-pin.................................................2
PIC16F914/917, 44-pin.................................................4
Pinout Description.......................................... .. .... .. .... .. .......10
PIR1 Regi ster................. ........... ................... ................... ....26
PIR2 Regi ster................. ........... ................... ................... ....27
PORTA
Associ a te d Re g i sters .................. ........... ................... ..52
Pin Descriptions and Diagrams...................................45
RA0.............................................................................45
RA1.............................................................................46
RA2.............................................................................47
RA3.............................................................................48
RA4.............................................................................49
RA5.............................................................................50
RA6.............................................................................51
RA7.............................................................................52
Registers.....................................................................43
Specifications............................................................233
PORTA Register .................................................................44
PORTB
Additional Pin Functions .............................................53
Weak Pull-up.......................................................53
Associ a te d Re g i st e rs . ...................................... ...........62
Interrupt-on-change ....................................................53
Pin Descriptions and Diagrams...................................56
RB0.............................................................................56
RB1.............................................................................56
RB2.............................................................................56
RB3.............................................................................56
RB4.............................................................................58
RB5.............................................................................59
RB6.............................................................................60
RB7.............................................................................61
Registers.....................................................................53
PORTB Register .................................................................54
PORTC
Associ a te d Re g i sters .................. ........... ................... ..71
Pin Descriptions and Diagrams...................................64
RC0.............................................................................64
RC1.............................................................................64
RC2.............................................................................64
RC3.............................................................................66
RC4.............................................................................67
RC5.............................................................................68
RC6.............................................................................69
RC6/TX/ CK/SCK/SCL/SEG9 Pin............... ...............128
RC7.............................................................................70
RC7/RX/DT Pin.........................................................129
RC7/RX/DT/SDI/SDA/ SE G8 Pin...................... .........128
Registers.....................................................................63
Specifications............................................................233
TRISC Register............... ................... .......... .............127
PORTC Register.................................................................63
PORTD
Associ a te d Re g i sters .................. ........... ................... ..76
Pin Descriptions and Diagrams...................................73
RD0.............................................................................73
RD1 ............................................................................ 73
RD2 ............................................................................ 73
RD3 ............................................................................ 73
RD4 ............................................................................ 73
RD5 ............................................................................ 73
RD6 ............................................................................ 73
RD7 ............................................................................ 73
Registers .................................................................... 72
PORTD Register................................................................. 72
PORTE
Associ a te d Re g i sters...... ................... .......... ............... 79
Pin Descriptions and Diagrams .................................. 78
RE0............................................................................. 78
RE1............................................................................. 78
RE2............................................................................. 78
RE3............................................................................. 78
Registers .................................................................... 77
PORTE Register................................................................. 77
Power-Down Mode (Sleep)............................................... 201
Power-on Reset................................................................ 188
Power-up Timer (PWRT).................................................. 188
Specifications ........................................................... 235
Precision In ternal Os cillator Parameters .......................... 23 2
Prescaler
Shared WDT/Timer0.............................. ........... .......... 83
Swit ch i n g Pr escal e r As si g n ment .... .. ...... ...... . ...... .. ..... 83
PRO MATE II Univer sal Device Programmer................... 217
Product Identification System........................................... 271
Program Memory................................................................ 13
Map and Stack (PIC16F913/914)............................... 13
Map and Stack (PIC16F916/917)............................... 13
Paging ........................................................................ 29
Programmable Low-Voltage Detect (PLVD) Module ........ 125
Programm ing, Device Instructions.................................... 205
Pulse Width Modulation.SeeCapture/Compare/PWM, PWM
Mode.
R
R/W bit.............................................................................. 160
RCSTA Register
ADDEN Bit................................................................ 128
CREN Bit..... ................... ................... .......... ............. 128
FERR Bit................................................................... 128
OERR Bit.................................................................. 128
RX9 Bit ..................................................................... 128
RX9D Bit....................... ................... ................... ...... 128
SPEN Bit. .......................................................... 127, 128
SREN Bit ... ................... ................... .......... ............... 128
Read-Modify-Write Operations ......................................... 205
Receive Overflow Indicator bi t (SSPOV).......................... 161
Registers
ADCON0 (A/D Contr o l 0 )........ ........... ....................... 146
ADCON1 (A/D Contr o l 1 )........ ........... ....................... 147
ANSEL (Analog Select)............................................ 146
CCP1CON (CCP Control 2)...................................... 178
CCP2CON (CCP Control 1)...................................... 178
CMCON 0 (Co mpa ra tor C o n tr ol 0) ........ ...... ......... ....... 93
CMCON 1 (Co mpa ra tor C o n tr ol 1) ........ ...... ......... ....... 97
CON FIG (C o n fi g u rati o n Wo rd) ..... .. ...... ...... ..... ...... ... 186
EEADRH (EEPROM Addr e ss)........... .......... ........... ..154
EEADRL (EEPROM Address)..................................154
EECON1 (EEPROM Control 1) ................................ 155
EEDATH (EEPROM Data)........................................ 154
EEDATL (EEPROM Data)........................................ 154
INTCON (Interru pt Control) ......................................... 23
IOCB (PORTB Interrupt-on-change)........................... 54
2004 Microchip Technology Inc. Preliminary DS41250A-page 265
PIC16F91X
LCDCON (LCD Control)............................................103
LCDDATAx (LCD Datax) ..........................................105
LCDPS (LCD Prescaler Select) ............... .................104
LCDSEn (LCD Segment). .........................................105
LVDCON (Low-Voltage Detect Control) ....................125
OPTION_REG ......................................................22, 82
OSCCON (Oscillator Control).....................................32
OSCTUNE ..................................................................38
PCON (Power Control) .............................................190
PIE1 (Peripheral Interrupt Enable 1)...........................24
PIE2 (Peripheral Interrupt Enable 2)...........................25
PIR1 (Peripheral Interrupt Register 1) ........................26
PIR2 (Peripheral Interrupt Register 2) ........................27
PORTA........................................................................44
PORTB........................................................................54
PORTC .......................................................................63
PORTD .......................................................................72
PORTE........................................................................77
RCSTA (Receive Status and Control). ......................128
Reset Value s........... ................... .......... ................... ..192
Reset Values (Special Registers).............................194
Special Function Register Map
PIC16F913/916...................................................15
PIC16F914/917...................................................16
Special Register Summary
Bank 0........ ................... ................... ...................17
Bank 1........ ................... ................... ...................18
Bank 2........ ................... ................... ...................19
Bank 3........ ................... ................... ...................20
SSPCON (Sy nc Serial Port Control) Register...........161
SSPSTAT (S ync Serial Port Status) Register...........160
Status..........................................................................21
T1CON (Timer1 Con trol)..... ........... .......... ........... ........87
T2CON (Timer2 Con trol)..... ........... .......... ........... ........90
TRISA (PORTA Tri-state) ...........................................44
TRISB (PORTB Tri-state) ...........................................54
TRISC (PORTC Tri- state).................. .......... ........... ....63
TRISD (PORTD Tri- state).................. .......... ........... ....72
TRISE (PORTE Tri-state) ...........................................77
TXSTA (Transmit Status and Control)......................127
VRCON (Voltage Reference Control).......................100
WDTCON (Watchdog Tim er Contro l) .......................200
WPUB (Wea k Pull-up PORTB)............................... ....55
Reset.................................................................................187
Revision History................................................................259
S
S (Start) bit........................................................................160
SCI. See USART
Serial Communication Interface. See USART.
Slave Select Synchronization ...........................................166
SMP bit .............................................................................160
Softwa re Simulator (MPLAB SIM )................ ........... ..........216
Softwa re Simulator (MPLAB SIM 3 0 )................ ........... ......216
Special Function Registers.................................................14
SPI Mode .. ................................................................159, 166
Associ a te d Re g i sters.............. ................... ...............168
Bus Mode Compatibility............................................168
Effects of a Reset......................................................168
Enabling SPI I/O .......................................................164
Master Mode.............................................................165
Master/Slave Connection........................... ....... .... .. ..164
Serial Clock (SCK pin)..............................................159
Serial Data In (SDI pin).............................................159
Serial Data Out (SDO pin)........................................159
Slave Select..............................................................159
Slave Select Synchroniz a tion................. .................. 166
Sleep Operation. ....................................................... 168
SPI Clock.................................................................. 165
Typical Connection........................ .. .... ..... .... .. .... .. .. .. 164
SSP Overview
SPI Master/Slave Connection . .................................. 164
SSP I2C Operation ............. ................... ........... ................ 169
Slave Mode........................ .................. ................... .. 1 6 9
SSP Module
Clock Synchronization and the CKP Bit ................... 175
SPI Mas ter Mode...................................................... 165
SPI Slave Mode........................................................ 166
SSPBUF................................................................... 165
SSPSR ..................................................................... 165
SSPEN bit........ ................... ........... ................... ................ 161
SSPM bits.... ................... ................... ................... .......... .. 161
SSPOV bit ........................................................................ 161
Statu s Reg i ster..... .................. ........... ................... .............. 21
Synchronous Master Reception
Associ a te d Re g i sters......................... ................... .... 140
Synchronous Master Transmission
Associ a te d Re g i sters......................... ................... .... 139
Synchronous Serial Port Enable bit (SSPEN) .................. 161
Synchronous Serial Port Mode Select bits (SSPM).......... 161
Synchronous Serial Port. See SSP
Synchronous Slave Reception
Associ a te d Re g i sters......................... ................... .... 142
Synchronous Slave Transmission
Associ a te d Re g i sters......................... ................... .... 142
T
T1CON Registe r......... .......... ................... ........... ................ 87
Time-out Sequence .............. .. ......... .. .... .... .. ......... .... .. .... .. 190
Timer0
Associ a te d Re g i sters......................... ................... ...... 83
External Clock ............................................................ 82
External Clock Requirements................................... 236
Interrupt...................................................................... 81
Operation.................................................................... 81
T0CKI ......................................................................... 82
Timer0 Module..... ............................................................... 81
Timer1
Associ a te d Re g i sters......................... ................... ...... 89
Asynchronous Counter Mode..................................... 88
Reading and Writing........................................... 88
External Clock Requirements................................... 236
Interrupt...................................................................... 86
Modes of Ope rations....................... ................... ........ 86
Operation During Sleep.............................................. 89
Prescaler .................................................................... 86
Resetting of Timer1 Registers.................................... 89
Resetting Timer1 Using a CCP Trigger Output. ......... 88
Timer1 Gate
Inverting Gate..................................................... 86
Selectin g So u rce ................. ........... .............. 86, 97
Synchro n i zing C2OUT w/ Timer1....................... 97
TMR1H Register......................................................... 85
TMR1L Register ......................................................... 85
Timer1 Module with Gate Control....................................... 85
Timer2 ................................................................................ 90
Associ a te d regist e rs .................. ................... .............. 91
Operation.................................................................... 90
Postscaler................................................................... 90
PR2 Register.............................................................. 90
Prescaler .................................................................... 90
PIC16F91X
DS41250A-page 266 Preliminary 2004 Microchip Technology Inc.
TMR2 Output ..............................................................91
TMR2 Register............................................................90
TMR2 to PR2 Match Interrupt...............................90, 91
Timing Diagrams
A/D Conversion............... .......... ................... ........... ..246
Asynchronous Master Transmission.........................132
Asynchronous Master Transmission (Back to Back).132
Asynchronous Reception..........................................135
Asynchronous R eception with Address By te First ....137
Asynchronous Re ception with Address Dete ct.........137
Brown-out Reset (BOR)............................................234
Brown-out Reset Situations ......................................189
Capture/Compare/PWM............................................238
CLKO and I/O ...........................................................233
Clock Synchronization ..............................................176
Comparator Output ......... ..................................... .......94
External Clock...........................................................231
Fail-S afe Clock Monitor (FSCM).................................42
I2C Bus Data.............................................................243
I2C Bus Start/Stop Bits..............................................242
I2C Recepti o n (7-bit Address)...................................171
I2C Slave Mode (Transmission, 10-bit Address).... ...174
I2C Slave Mode with SEN = 0 (Reception, 10-bit Ad-
dress)................................................................172
I2C Transmission (7-bit Addres s)..............................173
INT Pin Interrupt........................................................197
LCD Interrupt Timing in Quarter-Duty Cycle Drive....121
LCD Sleep Entry/Exit when SLPEN = 1 or CS = 00 .123
Reset, WDT, OST and Power-up Timer ...................234
Slave Synchronization ..............................................166
SPI Mast e r Mode (CKE = 1, SMP = 1) .. ...................240
SPI Mode (Master Mode)..........................................165
SPI Mode (Slave Mode with CKE = 0)......................167
SPI Mode (Slave Mode with CKE = 1)......................167
SPI Slave Mode (CKE = 0) .......................................241
SPI Slave Mode (CKE = 1) .......................................241
Synchronous Reception (Master Mode, SREN) .......141
Synchronous Transmission............. ............... ...... .....139
Synchronous Transmission (T hrough TXEN) ...........139
Time-out Sequence
Case 1...............................................................191
Case 2...............................................................191
Case 3...............................................................191
Timer0 and Timer1 External Clock ...........................236
Timer1 Incrementing Edge..........................................86
Two Speed Start-up............................... .. .. .. .... .. .. ..... ..41
Type-A in 1/2 Mux, 1/2 Bias Driv e ..... .......................111
Type-A in 1/2 Mux, 1/3 Bias Driv e ..... .......................113
Type-A in 1/3 Mux, 1/2 Bias Driv e ..... .......................115
Type-A in 1/3 Mux, 1/3 Bias Driv e ..... .......................117
Type-A in 1/4 Mux, 1/3 Bias Driv e ..... .......................119
Type-A/Type-B in Static Drive ...................................110
Type-B in 1/2 Mux, 1/2 Bias Driv e ..... .......................112
Type-B in 1/2 Mux, 1/3 Bias Driv e ..... .......................114
Type-B in 1/3 Mux, 1/2 Bias Driv e ..... .......................116
Type-B in 1/3 Mux, 1/3 Bias Driv e ..... .......................118
Type-B in 1/4 Mux, 1/3 Bias Driv e ..... .......................120
USART Synchronous Receive (Master/Slave) .........237
USART Synchronous Transmission (Master/Slave).237
Wake-up from Interrupt.............................................202
Timing Pa rameter Symbolo g y................................ ...........230
Timing Requirements
I2C Bus Data.............................................................244
I2C Bus St a rt/Stop Bits...................... .......................243
SPI Mode ..................................................................242
TMR1H Register................................................................. 85
TMR1L Register.................................................................. 85
TRISA
Registers .................................................................... 43
TRISA Register................................................................... 44
TRISB
Registers .................................................................... 53
TRISB Register................................................................... 54
TRISC
Registers .................................................................... 63
TRISC Regist e r.... ................... ........... ................................. 63
TRISD
Registers .................................................................... 72
TRISD Regist e r.... ................... ........... ................................. 72
TRISE
Registers .................................................................... 77
TRISE Register................................................................... 77
Two-Spe ed Clock Star t-up Mode................. ................... .... 40
TXSTA Register
BRGH Bit.................................................................. 127
CSRC Bit.............. .................. ................... ............... 127
SYNC Bit .............. .......... ................... .......... ............. 127
TRMT Bit.......... ........... ................... ................... ........ 12 7
TX9 Bit...................................................................... 127
TX9D Bit ................................................................... 127
TXEN Bit............ ................... ................... ................. 12 7
U
UA..................................................................................... 160
Update Address bit, UA.............. .... ..... .... .. .. .... .. .. ....... .. .... 160
USART.............................................................................. 127
Address Detect Enable (ADD EN Bit)........................ 128
Asynchronous Mode................................................. 131
Asynchronous Receive (9-bit Mode). ........................ 136
Asynchronous Receive with Address Detect. See Asyn-
chronous Receive (9-bit Mode).
Asynchronous Receiver............................................ 134
Asynchronous Receptio n.......................................... 134
Asynchronous Tran smitter........................................ 131
Baud Rate Generator (BRG) .................................... 129
Baud Rate Formula .......................................... 129
Baud Rates, Asynchronous Mode (B RGH = 0) 130
Baud Rates, Asynchronous Mode (B RGH = 1) 130
High Baud Rate Select (BRGH Bit).................. 127
Sampling........................................................... 129
Clock Source Select (CSRC Bit)............................... 127
Continuous Receive Enable (CREN Bit)................... 128
Framing Er ror (FERR Bit)............ ................... .......... 128
Mode Select (SYNC Bit)........................................... 127
Overrun Error (OERR Bit) ......................................... 128
Recei v e Data , 9 th Bi t (RX9D Bi t).. ...... .. ...... .. ..... .. .. ... 128
Receive Enable, 9-bit (RX9 Bit)................................ 128
Serial Port Enable (SPEN Bit) .......................... 127, 128
Single Receive Enable (SREN Bit)........................... 128
Synchronous Master Mode....................................... 138
Requirements, Synchronous Receive .............. 237
Requirements, Synchronous Transmission...... 237
Timing Diagram, Synchronous Receive ....... .... 237
Timing Diagram, Synchronous Transmission... 237
Synchronous Master Reception................................ 140
Synchronous Master Transmission . .......... ............... 138
Synchronous Slave Mode.................. .... .... ......... .... .. 141
Synchronous Slave Reception..................................142
Synchronous Slave Transmit.................................... 141
Transmit Data, 9th Bit (TX9D)....... .......... ................. 127
Transmit Enable (TXEN Bit) ..................................... 127
2004 Microchip Technology Inc. Preliminary DS41250A-page 267
PIC16F91X
Transmit Enable, Nine-bit (TX9 Bit)..........................127
Transmit Shift Register Status (TRMT Bit)................127
V
Voltage Reference. See Comparator Voltage Reference
(CVREF)
VRCON Register...............................................................100
W
Wake-up Using Interrupts.................................................201
Watchdog Timer (WDT)....................................... ......... ....199
Associ a te d Re g i sters.............. ................... ...............200
Clock Source.............................................................199
Modes.......................................................................199
Period........................................................................199
Specifications............................................................235
WCOL bit ... ................... .......... ................... .......................161
WDTCON Registe r ............. ................... .......... .................200
WPUB Regist e r........................... ................... ................... ..55
Write Collision Detect bit (WCOL).....................................161
WWW, On-Line Support .......................................................5
PIC16F91X
DS41250A-page 268 Preliminary 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. Preliminary DS41250A-page 269
PIC16F91X
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web site.
The web site is used b y Micr ochip as a me ans to mak e
files and information easily available to customers. To
view t he site, the user must have acce ss to the In ternet
and a web browser, such as Netscape® or Microsoft®
Internet Explorer. Files are also available for FTP
download from our FTP site.
Connecting to the Microchip Internet
Web S ite
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP
service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
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Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A vari-
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distributors and factory representatives. Other data
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042003
PIC16F91X
DS41250A-page 270 Preliminary 2004 Microchip Technology Inc.
READER RESPONSE
It is ou r intention to pro vi de you with the b est do cu me nt ation possib le to e ns ure successful u se of y ou r Mic r oc hip pro d-
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DS41250APIC16F91X
1. What are the best features of thi s document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
2004 Microchip Technology Inc. Preliminary DS41250A-page 271
PIC16F91X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
* JW Devices are UV er asable and can be programm ed to any device configuration . JW Devices meet the electrical requirem ent of
each oscillator type.
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device PIC16F91X: Standard VDD range
PIC16F91XT: (Tape and Reel)
Temperatu re Rang e I = -40°C to +85°C
E= -40°C to +125°C
Package P = PDIP
SL = SOIC (Gull wing, 150 mil body)
ST = TSSOP(4.4 mm)
Pattern 3-Digit Pattern Code for QTP (blank otherwise)
Examples:
a) PIC16F913-E/P 301 = Extended Temp., PDIP
package, 20 MHz, QTP patter n #301
b) PIC16F913-I/SO = Industrial Temp., SOIC
package, 20 MHz
DS41250A-page 272 Preliminary 2004 Microchip Technology Inc.
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08/24/04
