1White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
EDI816256CA
August 2004
Rev. 8
256Kx16 MONOLITHIC SRAM, SMD 5962-96795
FEATURES
256Kx16 bit CMOS Static
Random Access Memory
• Access Times of 17, 20, 25, 35ns
• Data Retention Function (LPA version)
• TTL Compatible Inputs and Outputs
• Fully Static, No Clocks
44 lead JEDEC Approved Revolutionary Pinout
• Ceramic SOJ (Package 322)
• Ceramic Flatpack (Package 323)
Single +5V (±10%) Supply Operation
PIN CONFIGURATION
TOP VIEW PIN DESCRIPTION
A0-17 Address Inputs
LB# (I/O1-8) Lower-Byte Control (I/O1-8)
UB# (I/O9-16) Upper-Byte Control (I/O9-16)
I/O1-16 Data Input/Output
CS# Chip Select
OE# Output Enable
WE# Write Enable
VCC +5.0V Power
VSS Ground
NC No Connection
The EDI816256CA is a 4 megabit Monolithic CMOS Static
RAM.
The EDI816256CA uses 16 common input and output
lines and has an output enable pin which operates faster
than address access time at read cycle. The device allows
upper and lower byte access by use of the data byte control
pins (LB#, UB#).
The devices are available in a fully hermetic 44 lead
ceramic SOJ and a 44 lead Ceramic Flatpack. The Ceramic
SOJ is pin for pin compatible with the commercially
available plastic SOJ. This allows the user the luxury of
designing a board that can be used for both the commercial
and military market.
A Low Power version with Data Retention (EDI816256LPA)
is also available for battery backed applications. Military
product is available compliant to Appendix A of MIL-PRF-
38535.
A0
A1
A2
A3
A4
CS#
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE#
A5
A6
A7
A8
A9
A17
A16
A15
OE#
UB#
LB#
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
2White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
EDI816256CA
August 2004
Rev. 8
ABSOLUTE MAXIMUM RATINGS
Parameter Unit
Voltage on any pin relative to VSS -0.5 to 7.0 V
Operating Temperature TA (Ambient)
Commercial 0 to +70 °C
Industrial -40 to +85 °C
Military -55 to +125 °C
Storage Temperature, Plastic -65 to +125 °C
Power Dissipation 1.5 W
Output Current 20 mA
Junction Temperature, TJ175 °C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specifi cation is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter Sym Min Typ Max Units
Supply Voltage VCC 4.5 5.0 5.5 V
Supply Voltage VSS 0 0 0 V
Input High Voltage VIH 2.2 — Vcc +0.5 V
Input Low Voltage VIL -0.3 — 0.8 V
CAPACITANCE
TA = +25°C
Parameter
Symbol
Condition Max Unit
Address Lines CI
VIN = Vcc or Vss, f = 1.0MHz
12 pF
Data Lines CD/Q
VIN = Vcc or Vss, f = 1.0MHz
14 pF
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS
VCC = 5V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter Symbol Conditions Min Max Units
Input Leakage Current ILI VIN = 0V to VCC 10 μA
Output Leakage Current ILO VI/O = 0V to VCC 10 μA
Operating Power Supply Current ICC1 WE#, CS# = VIL, II/O = OmA, Min Cycle 300 mA
Standby (TTL) Power Supply Current ICC2 CS# ≥ VIH, VIN ≤ VIL, VIN ≥ VIH 60 mA
Full Standby Power Supply Current ICC3 CS# ≥ VCC -0.2V CA — 25 mA
VIN ≥ VCC -0.2V or VIN ≤ 0.2V LPA — 16 mA
Output Low Voltage VOL IOL = 6.0mA 0.4 V
Output High Voltage VOH IOH = -4.0mA 2.4 V
NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V
Input Pulse Levels VSS to 3.0V
Input Rise and Fall Times 5ns
Input and Output Timing Levels 1.5V
Output Load Figure 1
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF (Figure 2)
30pF
480Ω
Vcc
Q
Figure 1 Figure 2
255Ω 5pF
480Ω
Vcc
Q
255Ω
AC TEST CONDITIONS
TRUTH TABLE
CS# WE# OE# LB# UB# Mode Data I/O Supply
Current
I/O1-8 I/O9-16
HXXXXNot Select High Z High Z ICC2, ICC3
LHHXX Output
Disable
LXXHH
LHL
LH
Read
Data Out High Z
ICC1
H L High Z Data Out
L L Data Out Data Out
LLX
LH
Write
Data In High Z
ICC1
H L High Z Data In
L L Data In Data In
3White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
EDI816256CA
August 2004
Rev. 8
AC CHARACTERISTICS – WRITE CYCLE
VCC = 5V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter Symbol 17ns 20ns 25ns 35ns UnitsJEDEC Alt. Min Max Min Max Min Max Min Max
Write Cycle Time tAVAV tWC 17 20 25 35 ns
Chip Enable to End of Write tELWH
tELEH
tCW
tCW
14
14
15
15
17
17
20
20
ns
ns
Address Setup Time tAVWL
tAVEL
tAVUBL
tAS
tAS
tAS
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
Address Valid to End of Write tAVWH
tAVEH
tAVUBH
tAW
tAW
tAW
14
14
14
15
15
15
17
17
17
20
20
20
ns
ns
ns
Write Pulse Width tWLWH
tWLEH
tWP
tWP
14
14
14
14
15
15
17
17
ns
ns
Write Recovery Time tWHAX
tEHAX
tWR
tWR
0
0
0
0
0
0
0
0
ns
ns
Data Hold Time tWHDX
tEHDX
tDH
tDH
0
0
0
0
0
0
0
0
ns
ns
Write to Output in High Z (1) tWLQZ tWHZ 080808010ns
Data to Write Time tDVWH
tDVEH
tDW
tDW
10
10
10
10
12
12
15
15
ns
ns
Output Active from End of Write (1) tWHQX tWLZ 0000ns
LB, UB Valid to End of Write tLBLLBH
tUBLUBH
tBW 14 16 18 20 ns
NOTE:
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS – READ CYCLE
VCC = 5V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter Symbol 17ns 20ns 25ns 35ns UnitsJEDEC Alt. Min Max Min Max Min Max Min Max
Read Cycle Time tAVAV tRC 17 20 25 35 ns
Address Access Time tAVQV tAA 17 20 25 35 ns
Chip Enable Access Time tELQV tACS 17 20 25 35 ns
Chip Enable to Output in Low Z (1) tELQX tCLZ 2555ns
Chip Disable to Output in High Z (1) tEHQZ tCHZ 070708010ns
Output Hold from Address Change tAVQX tOH 0000ns
Output Enable to Output Valid tGLQV tOE 10 10 12 15 ns
Output Enable to Output in Low Z (1) tGLQX tOLZ 0000ns
Output Disable to Output in High Z(1) tGHQZ tOHZ 070708010ns
LB#, UB# Access Time tUBLQV
tLBLQV
tBA 10 10 12 15 ns
LB#, UB# Enable to Low Z Output tUBLQX
tLBLQX
tBLZ 00000ns
LB#, UB# Disable to High Z Output tUBHQZ
tLBHQZ
tBHZ 070708010ns
NOTE:
1. This parameter is guaranteed by design but not tested.
4White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
EDI816256CA
August 2004
Rev. 8
WRITE CYCLE - CS# CONTROLLED WRITE CYCLE - LB#, UB# CONTROLLED
TIMING WAVEFORM – READ CYCLE
WRITE CYCLE – WE# CONTROLLED
ADDRESS
READ CYCLE 2 (WE# HIGH)
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
AVAV
t
EHQZ
t
GHQZ
OE#
t
LBLQX
t
UBLQX
t
LBHQZ
t
UBHQZ
LB#, UB#
CS#
t
LBLQV
t
UBLQV
DATA I/O
ADDRESS
DATA I/O
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
t
AVQX
t
AVQV
t
AVAV
DATA 2
ADDRESS 1 ADDRESS 2
DATA 1
ADDRESS
DATA IN
WRITE CYCLE 1, WE# CONTROLLED
t
AVWH
t
ELWH
t
WHAX
t
WLWH
t
DVWH
t
WLQZ
t
WHQX
t
AVWL
t
WHDX
t
AVAV
DATA VALID
HIGH
WE#
t
LBLLBH
t
UBLUBH
CS#
DATA OUT
LB#, UB#
WRITE CYCLE 2, CS# CONTROLLED
t
AVEH
t
ELEH
t
EHAX
t
WLEH
t
DVEH
t
EHDX
t
AVAV
DATA VALID
HIGH
t
LBLLBH
t
UBLUBH
t
AVEL
ADDRESS
DATA IN
WE#
LB#, UB#
CS#
DATA OUT
ADDRESS
DATA IN
DATA OUT
WRITE CYCLE 3, LB#, UB# CONTROLLED
t
AVWH
t
AVUBL
t
WHAV
t
AVUBH
t
WLWH
t
WLQX
t
AVAV
CS#
WE#
DATA UNDEFINED
DATA VALID
t
UBHAV
t
WHDX
t
DVWH
t
UBLUBH
LB#, UB#
HIGH ZHIGH Z
5White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
EDI816256CA
August 2004
Rev. 8
DATA RETENTION CHARACTERISTICS (EDI816256LPA ONLY)
-55°C ≤ TA ≤ +125°C
Characteristic Low Power Version only Sym Conditions Min Typ Max Units
Data Retention Voltage
Data Retention Quiescent Current
VCC
ICCDR
VCC = 2.0V
CS# ≥ VCC -0.2V
2
–
–
–
–
2.2
V
mA
Chip Disable to Data Retention Time (1)
Operation Recovery Time (1)
TCDR
TR
VIN ≥ VCC -0.2V
or VIN ≤ 0.2V
0
TAVAV
–
–
–
–
ns
ns
NOTE:
1. This parameter is guaranteed by design but not tested.
* Read Cycle Time
WS32K32-XHX
DATA RETENTION – CS# CONTROLLED
DATA RETENTION MODE
CS# = V
CC
-0.2V
V
CC
CS#
t
CDR
V
CC
4.5V 4.5V
t
R
DATA RETENTION, CS# CONTROLLED
6White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
EDI816256CA
August 2004
Rev. 8
PACKAGE 322: 44 LEAD, CERAMIC SOJ
0.445
0.435
1.130
1.110
0.155
0.120
0.050 Typ
DIMENSIONS ARE IN INCHES
PACKAGE 323: 44 PIN, CERAMIC FLATPACK
Pin 1
0.019
0.015
0.038
0.032
0.395
0.385
0.115 Max.
0.050 Typ
0.515
0.505
1.00 Ref
0.045
0.015
0.007
0.003 0.370
0.250
1.130
1.110
DIMENSIONS ARE IN INCHES
7White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
EDI816256CA
August 2004
Rev. 8
ORDERING INFORMATION
EDI 8 16256 CA X X X
WHITE ELECTRONIC DESIGNS
SRAM
ORGANIZATION, 256Kx16
TECHNOLOGY:
CA = CMOS Standard Power
LPA = Low Power
ACCESS TIME (ns)
PACKAGE TYPE:
F44 = 44 pin Ceramic Flatpack (Package 323)
N44 = 44 lead Ceramic SOJ (Package 322)
DEVICE GRADE:
B = MIL-STD-883 Compliant
M = Military Screened -55°C to +125°C
I = Industrial -40°C to +85°C
C = Commercial 0°C to +70°C
