General Description
The MAX1421 is a 3.3V, 12-bit analog-to-digital con-
verter (ADC), featuring a fully-differential input,
pipelined, 12-stage ADC architecture with wideband
track-and-hold (T/H) and digital error correction incor-
porating a fully-differential signal path. The MAX1421 is
optimized for low-power, high-dynamic performance
applications in imaging and digital communications.
The converter operates from a single 3.3V supply, con-
suming only 188mW while delivering a typical signal-to-
noise ratio (SNR) of 66dB at an input frequency of
15MHz and a sampling frequency of 40Msps. The fully-
differential input stage has a small signal -3dB band-
width of 400MHz and may be operated with
single-ended inputs.
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure accommodates an internal or externally
applied buffered or unbuffered reference for applica-
tions requiring increased accuracy or a different input
voltage range.
In addition to low operating power, the MAX1421 fea-
tures two power-down modes, a reference power-down
and a shutdown mode. In reference power-down, the
internal bandgap reference is deactivated, resulting in
a typical 2mA supply current reduction. For idle peri-
ods, a full shutdown mode is available to maximize
power savings.
The MAX1421 provides parallel, offset binary, CMOS-
compatible three-state outputs.
The MAX1421 is available in a 7mm x 7mm, 48-pin
TQFP package, and is specified over the commercial
(0°C to +70°C) and the extended industrial (-40°C to
+85°C) temperature ranges.
Pin-compatible higher- and lower-speed versions of the
MAX1421 are also available. Please refer to the
MAX1420 data sheet for a frequency of 60Msps and
the MAX1422 data sheet for a frequency of 20Msps.
________________________Applications
Medical Ultrasound Imaging
CCD Pixel Processing
Data Acquisition
Radar
IF and Baseband Digitization
Features
♦Single 3.3V Power Supply
♦67dB SNR at fIN = 5MHz
♦66dB SNR at fIN = 15MHz
♦Internal, 2.048V Precision Bandgap Reference
♦Differential, Wideband Input T/H Amplifier
♦Power-Down Modes
180mW (Reference Shutdown Mode)
10µW (Shutdown Mode)
♦Space-Saving 48-Pin TQFP Package
MAX1421
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
________________________________________________________________ Maxim Integrated Products 1
D9
D8
D7
D6
DVDD
DVDD
DGND
DGND
D5
D4
D3
D2
AGND
AVDD
AVDD
AGND
AGND
INP
INN
AGND
AGND
AVDD
AVDD
AGND
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
48-TQFP
MAX1421
AGND
AVDD
AVDD
AGND
CLK
CLK
AGND
AVDD
DVDD
DGND
D0
D1
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
AGND
AVDD
CML
REFN
REFP
REFIN
AVDD
AGND
PD
OE
D11
D10
Pin Configuration
19-1900; Rev 1; 5/06
Ordering Information
Functional Diagram appears at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+Denotes lead-free package.
PART* TEMP RANGE PIN-
PACKAGE
PKG
CODE
M AX1421CCM
0°C to +70°C 48 TQFP
C48-2
M AX1421ECM
-40°C to +85°C 48 TQFP
C48-2
M AX1421ECM+
-40°C to +85°C 48 TQFP
C48-2
MAX1421
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dB FS, internal reference,
fCLK = 40MHz (50% duty cycle), digital output load CL≈10pF, TA≥+25°C guaranteed by production test, TA< +25°C guarnateed
by design and characterization. Typical values are at TA = +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD, DVDD to AGND..............................................-0.3V to +4V
DVDD, AVDD to DGND..............................................-0.3V to +4V
DGND to AGND.....................................................-0.3V to +0.3V
INP, INN, REFP, REFN, REFIN,
CML, CLK, CLK,....................(AGND - 0.3V) to (AVDD + 0.3V)
D0–D11, OE, PD .......................(DGND - 0.3V) to (DVDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
48-Pin TQFP (derate 12.5mW/°C above +70°C)........1000mW
Maximum Junction Temperature .....................................+150°C
Operating Temperature Ranges
MAX1421CCM ...................................................0°C to +70°C
MAX1421ECM ................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
DC ACCURACY
Resolution RES 12
Bits
TA = +25°C, no missing codes -1 +1
Differential Nonlinearity DNL TA = TMIN to TMAX
±0.5
LSB
Integral Nonlinearity INL TA = TMIN to TMAX ±2
LSB
Midscale Offset MSO -3
±.75
+3
%FSR
Midscale Offset Temperature
Coefficient
MSOTC 3 ✕ 10-4
%/°C
Internal reference (Note 1) -5
+0.1
+5
External reference applied to REFIN (Note 2)
-5 ±3 +5
Gain Error GE
External reference applied to REFP, CML,
and REFN (Note 3)
-1.5 ±0.5 +1.5
%FSR
Gain-Error Temperature
Coefficient GETC External reference applied to REFP, CML,
and REFN (Note 3) 15 ✕ 10-6
%/°C
DYNAMIC PERFORMANCE (fCLK = 40MHz, 4096-point FFT)
fIN = 5MHz 67
Signal-to-Noise Ratio SNR fIN = 15MHz, TA = +25°C6266
dB
fIN = 5MHz 73
Spurious-Free Dynamic Range SFDR fIN = 15MHz, TA = +25°C6470
dBc
fIN = 5MHz -74
Total Harmonic Distortion THD fIN = 15MHz, TA = +25°C -69 -62
dBc
fIN = 5MHz 66
Signal-To-Noise Plus Distortion
SINAD
fIN = 15MHz, TA = +25°C60
63.5
dB
fIN = 5MHz
10.7
Effective Number of Bits
ENOB
fIN = 15MHz, TA = +25°C60
10.3
Bits
Two-Tone Intermodulation
Distortion
IMDTT
fIN1 = 11.569MHz, fIN2 = 13.445MHz
(Note 4) -80
dBc
MAX1421
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dB FS, internal reference,
fCLK = 40MHz (50% duty cycle), digital output load CL≈10pF, TA≥+25°C guaranteed by production test, TA< +25°C guarnateed
by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Differential Gain DG ±1%
Differential Phase DP
±0.25
degrees
ANALOG INPUTS (INP, INN, CML)
Input Resistance RIN Either input to ground
32.5
kΩ
Input Capacitance CIN Either input to ground 4 pF
Common-Mode Input Level
(Note 5) VCML
VAVDD
× 0.5
V
Common-Mode Input Voltage
Range (Note 5)
VCMVR VCML
±5%
V
Differential Input Range VIN VINP - VINN (Note 6)
±VDIFF
V
Small-Signal Bandwidth
BW-3dB
(Note 7) 400
MHz
Large-Signal Bandwidth
FPBW-3dB
(Note 7) 150
MHz
Overvoltage Recovery OVR 1.5 ✕ FS input 1
Clock
Cycle
INTERNAL REFERENCE (REFIN bypassed with 0.22µF in parallel with 1nF)
Common-Mode Reference Input
Voltage VCML At CML
VAVDD
✕ 0.5
V
Positive Reference Voltage
Range VREFP At REFP
VCML
+ 0.512
V
Negative Reference Voltage
Range
VREFN
At REFN
VCML
- 0.512
V
Differential Reference Voltage
Range VDIFF (Note 6)
1.024
±5%
V
Differential Reference
Temperature Coefficient
REFTC ±100
ppm/°C
EXTER N AL R EF ER EN C E (VREFIN = 2.048V)
REFIN Input Resistance RIN (Note 8) 5 kΩ
REFIN Input Capacitance CIN 10 pF
REFIN Reference Input Voltage
VREFIN 2.048
±10%
V
Differential Reference Voltage VDIFF (Note 6)
0.92 ✕
VREFIN /
2
VREFIN /
2
1.08 ✕
VREFIN /
2
V
EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and CML)
REFP, REFN, CML Input Current
IIN
-200 +200
µA
REFP, REFN, CML Input
Capacitance CIN 15 pF
MAX1421
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
4_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dB FS, internal reference,
fCLK = 40MHz (50% duty cycle), digital output load CL≈10pF, TA≥+25°C guaranteed by production test, TA< +25°C guarnateed
by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS
Differential Reference Voltage
Range VDIFF (Note 6)
1.024
±10%
V
CML Input Voltage Range VCML
1.65
±10%
V
REFP Input Voltage Range VREFP VCML +
VDIFF / 2
V
REFN Input Voltage Range
VREFN
VCML -
VDIFF / 2
V
DIGITAL INPUTS (CLK, CLK, OE, PD)
Input Logic-High VIH 0.7 ✕
VDVDD
V
Input Logic-Low VIL 0.3 ✕
VDVDD
V
CLK, CLK
±330
PD -20
+20
Input Current
OE -20
+20
µA
Input Capacitance 10 pF
DIGITAL OUTPUTS (D0–D11)
Output Logic-High VOH IOH = 200µA
VDVDD
- 0.5 VDVDD
V
Output Logic-Low VOL IOL = -200µA 0 0.5 V
Three-State Leakage -10
+10
µA
Three-State Capacitance 2pF
POWER REQUIREMENTS
Analog Supply Voltage
VAVDD 3.135
3.3
3.465
V
Digital Supply Voltage
VDVDD
2.7 3.3 3.6 V
Analog Supply Current IAVDD 52 65
mA
Analog Supply Current with
Internal Reference in Shutdown REFIN = AGND 50 63
mA
Analog Shutdown Current PD = DVDD 20 µA
Digital Supply Current IDVDD 5.5
mA
Digital Shutdown Current PD = DVDD 20 µA
Power Dissipation PDISS Analog power 188 214
mW
Power-Supply Rejection Ratio PSRR (Note 9) ±1
mV/V
TIMING CHARACTERISTICS
Clock Frequency fCLK Figure 5 0.1
40.0
MHz
Clock High tCH Figure 5, clock period 25ns
12.5
ns
Clock Low tCL Figure 5, clock period 25ns
12.5
ns
MAX1421
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
_______________________________________________________________________________________ 5
Note 1: Internal reference, REFIN bypassed to AGND with a combination of 0.22µF in parallel with 1nF capacitor.
Note 2: External 2.048V reference applied to REFIN.
Note 3: Internal reference disabled. VREFIN = 0, VREFP = 2.162V, VCML = 1.65V, and VREFN = 1.138V.
Note 4: IMD is measured with respect to either of the fundamental tones.
Note 5: Specifies the common-mode range of the differential input signal supplied to the MAX1421.
Note 6: VDIFF = VREFP - VREFN.
Note 7: Input bandwidth is measured at a 3dB level.
Note 8: VREFIN is internally biased to 2.048V through a 10kΩresistor.
Note 9: Measured as the ratio of the change in mid-scale offset voltage for a ± 5% change in VAVDD using the internal reference.
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dB FS, internal reference,
fCLK = 40MHz (50% duty cycle), digital output load CL≈10pF, TA≥+25°C guaranteed by production test, TA< +25°C guarnateed
by design and characterization. Typical values are at TA = +25°C.)
SYMBOL
MIN TYP MAX UNITS
cycles
Typical Operating Characteristics
(VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage, fCLK = 40MHz (50% duty cycle), digital output
load CL= 10pF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
-120
-80
-100
-40
-60
-20
0
01051520
FFT PLOT, 4096-POINT RECORD,
DIFFERENTIAL INPUT
MAX1421 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
fIN = 7.54MHz
AIN = -0.45dB FS
HD3
HD2
-120
-80
-100
-40
-60
-20
0
01051520
FFT PLOT, 4096-POINT RECORD,
DIFFERENTIAL INPUT
MAX1421 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
fIN = 19.90MHz
AIN = -0.50dB FS
HD2 HD3
fIN
-120
-80
-100
-40
-60
-20
0
01051520
FFT PLOT, 4096-POINT RECORD,
DIFFERENTIAL INPUT
MAX1421 toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
fIN = 38.54MHz
AIN = -0.49dB FS
HD3
HD2
MAX1421
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
6_______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage, fCLK = 40MHz (50% duty cycle), digital output
load CL= 10pF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
-120
-80
-100
-40
-60
-20
0
024 1012141668 1820
TWO-TONE IMD, 8192-POINT RECORD,
DIFFERENTIAL INPUT
MAX1421 toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dB)
fIN1 = 11.51MHz
fIN2 = 13.51MHz
AIN1 = AIN2 = -6.5dB FS
IM2
IM3
fIN1 fIN2
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT FREQUENCY
ANALOG INPUT FREQUENCY (MHz)
SINAD (dB)
MAX1421 toc08
05101520 25 30 35 40 45 50 55
50
54
58
62
66
70
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER (fIN = 15MHz)
ANALOG INPUT POWER (dBFS)
SFDR (dBc)
MAX1421 toc09
-60 -50 -40 -30 -20 -10 0
20
30
40
50
60
70
80
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER (fIN = 15MHz)
ANALOG INPUT POWER (dBFS)
THD (dBc)
MAX1421 toc11
-60 -50 -40 -30 -20 -10 0
-80
-70
-60
-50
-40
-30
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT POWER (fIN = 15MHz)
ANALOG INPUT POWER (dBFS)
SINAD (dB)
MAX1421 toc12
-60 -50 -40 -30 -20 -10 0
0
10
20
30
40
50
60
70
80
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
ANALOG INPUT FREQUENCY (MHz)
THD (dBc)
MAX1421 toc07
051015 20 25 30 35 40 45 50 55
-80
-74
-68
-62
-56
-50
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT POWER (fIN = 15MHz)
ANALOG INPUT POWER (dBFS)
SNR (dB)
MAX1421 toc10
-60 -50 -40 -30 -20 -10 0
0
10
20
30
40
50
60
70
80
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
ANALOG INPUT FREQUENCY (MHz)
SFDR (dBc)
MAX1421 toc05
05101520 25 30 35 40 45 50 55
45
53
61
69
77
85
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
ANALOG INPUT FREQUENCY (MHz)
SNR (dB)
MAX1421 toc06
05101520 25 30 35 40 45 50 55
50
54
58
62
66
70
MAX1421
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage, fCLK = 40MHz (50% duty cycle), digital output
load CL= 10pF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
64
68
76
72
80
84
-40 10-15 35 60 85
SPURIOUS-FREE DYNAMIC RANGE
vs. TEMPERATURE
MAX1421 toc13
TEMPERATURE (°C)
SFDR (dBc)
fIN = 5.52MHz
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
020481024 3072 4096
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1421 toc17
DIGITAL OUTPUT CODE
INL (LSB)
0.500
0.375
0.250
0.125
0
-0.125
-0.250
-0.375
-0.500
020481024 3072 4096
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1421 toc18
DIGITAL OUTPUT CODE
DNL (LSB)
70
60
50
40
30
-40 10-15 35 6085
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
MAX1421 toc20
TEMPERATURE (°C)
IAVDD (mA)
12
10
8
6
4
-40 10-15 35 6085
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
MAX1421 toc21
TEMPERATURE (°C)
IAVDD (mA)
CL ≈ 10pF
60
62
66
64
68
70
-40 10-15 35 60 85
SIGNAL-TO-NOISE PLUS DISTORTION
vs. TEMPERATURE
MAX1421 toc16
TEMPERATURE (°C)
SINAD (dB)
fIN = 5.52MHz
0.50
0.25
0
-0.25
-0.50
-40 10-15 35 60 85
GAIN ERROR vs. TEMPERATURE, EXTERNAL
REFERENCE (VREFIN = 2.048V)
MAX1421 toc19
TEMPERATURE (°C)
GAIN ERROR (%FSR)
60
62
66
64
68
70
-40 10-15 35 60 85
SIGNAL-TO-NOISE RATIO
vs. TEMPERATURE
TEMPERATURE (°C)
SNR (dB)
fIN = 5.52MHz
MAX1421 toc14
-80
-78
-74
-76
-72
-70
-40 10-15 35 60 85
TOTAL HARMONIC DISTORTION
vs. TEMPERATURE
MAX1421 toc15
TEMPERATURE (°C)
THD (dBc)
fIN = 5.52MHz
________________________________________________________________________________________ 7
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
020481024 3072 4096
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1421 toc17
DIGITAL OUTPUT CODE
INL (LSB)
MAX1421
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
8_______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage, fCLK = 40MHz (50% duty cycle), digital output
load CL= 10pF, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
80
75
70
65
60
55
50
45
40
10 302015 25 35 40
SNR/SINAD, -THD/SFDR
vs. CLOCK FREQUENCY
MAX1421 toc22
CLOCK FREQUENCY (MHz)
SNR/SINAD, -THD/SFDR (dB, dBc)
SFDR
-THD
SNR SINAD
fIN = 5MHz
0
10,000
5000
20,000
15,000
25,000
30,000
N-1 N+2
OUTPUT NOISE HISTOGRAM (DC-INPUT)
MAX1421 toc25
DIGITAL OUTPUT NOISE
COUNTS
N-3 NN+1 N+3
43707
10709
116
10
10824
179
N-2
40,000
35,000
45,000
50,000
2.00
2.02
2.06
2.04
2.08
2.10
-40 10-15 35 60 85
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1421 toc24
TEMPERATURE (°C)
VREFIN (V)
2.0750
2.0625
2.0500
2.0375
2.0250
3.1 3.33.2 3.4
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
MAX1421 toc23
VDD (V)
VREFIN (V)
3.5
MAX1421
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
_______________________________________________________________________________________ 9
PIN NAME FUNCTION
1, 4, 5, 8,
9, 12, 13,
16, 19, 41,
48
AGND Analog Ground. Connect all return paths for analog signals to AGND.
2, 3, 10,
11, 14, 15,
20, 42, 47
AVDD
Analog Supply Voltage. For optimum performance bypass each pin to the closest AGND with a
parallel combination of a 0.1µF and a 1nF capacitor. Connect a single 10µF and 1µF capacitor
combination between AVDD and AGND.
6 INP Positive Analog Signal Input
7 INN Negative Analog Signal Input
17 CLK Clock Frequency Input. Clock frequency input ranges from 100kHz to 40MHz.
18 CLK Complementary Clock Frequency Input. This input is used for differential clock inputs. If the ADC is
driven with a single-ended clock, bypass CLK with a 0.1µF capacitor to AGND.
21, 31, 32,
DVDD
Digital Supply Voltage. For optimum performance bypass each pin to the closest DGND with a
parallel combination of a 0.1µF and a 1nF capacitor. Connect a single 10µF and 1µF capacitor
combination between DVDD and DGND.
22, 29, 30
DGND Digital Ground
23–28 D0–D5 Digital Data Outputs. Data bits D0 through D5, where D0 represents the LSB.
33–38 D6–D11 Digital Data Outputs. D6 through D11, where D11 represents the MSB.
39 OE Output Enable Input. A logic “1” on OE places the outputs D0–D11 into a high-impedance state. A
logic “0” allows for the data bits to be read from the outputs.
40 PD Shutdown Input. A logic “1” on PD places the ADC into shutdown mode.
43 REFIN
External Reference Input. Bypass to AGND with a capacitor combination of 0.22µF in parallel with
1nF. REFIN can be biased externally to adjust reference levels and calibrate full-scale errors. To
disable the internal reference, connect REFIN to AGND.
44 REFP P osi ti ve Refer ence I/O . Byp ass to AG N D w i th a cap aci tor com b i nati on of 0.22µF i n p ar al l el w i th 1nF.
W i th the i nter nal r efer ence d i sab l ed ( RE FIN = AG N D ) , RE FP shoul d b e b i ased to V
C M L
+ V
D IF F / 2.
45 REFN N eg ati ve Refer ence I/O . Byp ass to AG N D w i th a cap aci tor com b i nati on of 0.22µF i n p ar al l el w i th 1nF.
W i th the i nter nal r efer ence d i sab l ed ( RE FIN = AG N D ) , RE FN shoul d b e b i ased to V
C M L
- V
D IF F / 2.
46 CML Common-Mode Level Input. Bypass to AGND with a capacitor combination of 0.22µF in parallel
with 1nF. With the internal reference disabled (REFIN = AGND).
Pin Description
MAX1421
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
10 ______________________________________________________________________________________
Detailed Description
The MAX1421 uses a 12-stage, fully-differential, pipe-
lined architecture (Figure 1) that allows for high-speed
conversion while minimizing power consumption. Each
sample moves through a pipeline stage every half-
clock-cycle. Including the delay through the output latch,
the latency is seven clock cycles.
A 2-bit (2-comparator) flash ADC converts the held-
input voltage into a digital code. The following digital-to-
analog converter (DAC) converts the digitized result
back into an analog voltage, which is then subtracted
from the original held-input signal. The resulting error
signal is then multiplied by two, and the product is
passed along to the next pipeline stage. This process is
repeated until the signal has been processed by all 12
stages. Each stage provides a 1-bit resolution. Digital
error correction compensates for ADC comparator off-
sets in each pipeline stage and ensures no missing
codes.
Input Track-and-Hold Circuit
Figure 2 displays a simplified functional diagram of the
input T/H circuit in both track-and-hold modes. In track
mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b
are closed. The fully differential circuit passes the input
signal to the two capacitors (C2a and C2b) through-
switches (S4a and S4b). Switches S2a and S2b set the
common mode for the transconductance amplifier
(OTA) input, and open simultaneously with S1, sam-
pling the input waveform. The resulting differential volt-
age is held on capacitors C2a and C2b. Switches S4a
and S4b are then opened before switches S3a and S3b,
connecting capacitors C1a and C1b to the output of the
amplifier, and switch S4c is closed. The OTA is used to
charge capacitors C1a and C1b to the same values
originally held on C2a and C2b. This value is then pre-
sented to the first-stage quantizer and isolates the
pipeline from the fast-changing input. The wide-input
bandwidth, T/H amplifier allows the MAX1421 to track
and sample/hold analog inputs of high frequencies
beyond Nyquist. The analog inputs INP and INN can be
driven either differentially or single-ended. Match the
impedance of INP and INN and set the common-mode
voltage to midsupply (AVDD / 2) for optimum perfor-
mance.
Analog Input and Reference Configuration
The full-scale range of the MAX1421 is determined by
the internally generated voltage difference between
REFP (AVDD / 2 + VREFIN / 4) and REFN (AVDD / 2 -
VREFIN / 4). The MAX1421’s full-scale range is
adjustable through REFIN, which provides a high input
impedance for this purpose. REFP, CML (AVDD / 2), and
REFN are internally buffered low impedance outputs.
T/H VOUT
x2
Σ
FLASH
ADC DAC
2 BITS
MDAC
12
VIN
VIN
STAGE 1 STAGE 2
D11–D0
DIGITAL CORRECTION LOGIC
STAGE 12
TO NEXT
STAGE
Figure 1. Pipelined Architecture
S3b
S3a
CML
S5bS2b
S5a
S1
OUT
OUT
C2a
C2b
S4c
S4a
S4b
C1b
C1a
INTERNAL
BIAS
OTA
INTERNAL
BIAS
CML
S2a
Figure 2. Internal Track-and-Hold Circuit
MAX1421
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
______________________________________________________________________________________ 11
The MAX1421 provides three modes of reference oper-
ation:
•Internal reference mode
•Buffered external reference mode
•Unbuffered external reference mode
In internal reference mode, the on-chip +2.048V
bandgap reference is active and REFIN, REFP, CML,
and REFN are left floating. For stability purposes,
bypass REFIN, REFP, REFN, and CML with a capacitor
network of 0.22µF, in parallel with a 1nF capacitor to
AGND.
In buffered external reference mode, the reference volt-
age levels can be adjusted externally by applying a
stable and accurate voltage at REFIN.
In unbuffered external reference mode, REFIN is con-
nected to AGND, which deactivates the on-chip buffers
of REFP, CML, and REFN. With their buffers shut down,
these nodes become high impedance and can be dri-
ven by external reference sources, as shown in Figure 3.
Clock Inputs (CLK,
CCLLKK
)
The MAX1421’s CLK and CLK inputs accept both sin-
gle-ended and differential input operation, and accept
CMOS-compatible clock signals. If CLK is driven with a
single-ended clock signal, bypass CLK with a 0.1µF
capacitor to AGND. Since the interstage conversion of
the device depends on the repeatability of the rising
and falling edges of the external clock, use a clock with
low jitter and fast rise and fall times (< 2ns). In particu-
lar, sampling occurs on the rising edge of the clock sig-
nal, requiring this edge to have the lowest possible
jitter. Any significant aperture jitter limits the SNR per-
formance of the ADC according to the following rela-
tionship:
where fIN represents the analog input frequency and
tAJ is the aperture jitter.
Clock jitter is especially critical for high input frequency
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log or digital signal lines.
The MAX1421 clock input operates with a voltage
threshold set to AVDD / 2. Clock inputs must meet the
specifications for high and low periods, as stated in the
Electrical Characteristics.
S1
2t
dB IN AJ
NR =× ××
20 10
log πƒ
MAX1421
REFIN
REFN
R
50Ω
R
R
R
R
+1V
R
50Ω
50Ω
R
R
AVDD
CML
1nF
0.22µF
1nF0.22µF
1nF0.22µF
AGND
AVDD
2
AVDD
4
MAX4284
MAX4284
( )
REFP + 1V
( )
AVDD
2
+ 1V
( )
AVDD
2
AVDD
2
AVDD
4
AVDD
2
Figure 3. Unbuffered External Reference Drive—Internal Reference Disabled
MAX1421
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
12 ______________________________________________________________________________________
Figure 4 shows a simplified model of the clock input cir-
cuit. This circuit consists of two 10kΩresistors to bias
the common-mode level of each input. This circuit may
be used to AC-couple the system clock signal to the
MAX1421 clock input.
Output Enable (
OOEE
), Power-Down (PD), and
Output Data (D0–D11)
With OE high, the digital outputs enter a high-imped-
ance state. If OE is held low with PD high, the outputs
are latched at the last value prior to the power-down. All
data outputs, D0 (LSB) through D11 (MSB), are
TTL/CMOS-logic compatible. There is a seven clock-
cycle latency between any particular sample and its
valid output data. The output coding is in offset binary
format (Table 1).
The capacitive load on the digital outputs D0 through
D11 should be kept as low as possible (≤10pF), to avoid
large digital currents that could feed back into the analog
portion of the MAX1421, thereby degrading its dynamic
performance. The use of digital buffers (e.g.,
74LVCH16244) on the digital outputs of the ADC can fur-
ther isolate the digital outputs from heavy capacitive
loads. To further improve the dynamic performance of
the MAX1421, add small-series resistors of 100Ωto the
digital output paths, close to the ADC. Figure 5 displays
the timing relationship between output enable and data
output.
System Timing Requirements
Figure 6 depicts the relationship between the clock
input, analog input, and data output. The MAX1421
samples at the rising edge of CLK (falling edge of CLK)
and output data is valid seven clock cycles (latency)
later. Figure 6 also displays the relationship between
the input clock parameters and the valid output data.
Applications Information
Figure 7 depicts a typical application circuit containing
a single-ended to differential converter. The internal ref-
erence provides an AVDD / 2 output voltage for level-
shifting purposes. The input is buffered and then split to
a voltage follower and inverter. A lowpass filter at the
input suppresses some of the wideband noise associat-
ed with high-speed op amps. Select the RISO and CIN
values to optimize the filter performance and to suit a
particular application. For the application in Figure 7, a
RISO of 50Ωis placed before the capacitive load to pre-
vent ringing and oscillation. The 22pF CIN capacitor
acts as a small bypassing capacitor.
Connecting CIN from INN to INP may further improve
dynamic performance.
D11–D0
10kΩ
10kΩ
10kΩ
10kΩ
AVDD
ADC
CLK
CLK
INN
INP
AGND MAX1421
Figure 4. Simplified Clock Input Circuit
OUTPUT
DATA D11–D0
OE
tBD
tBE
HIGH-ZHIGH-Z VALID DATA
Figure 5. Output Enable Timing
Table 1. MAX1421 Output Code for
Differential Inputs
DIFFERENTIAL
INPUT VOLTAGE*
DIFFERENTIAL
INPUT
OFFSET
BINARY
VREF × 2047/2048
+FULL SCALE -
1LSB
1111 1111 1111
VREF × 2046/2048
+FULL SCALE -
2LSB
1111 1111 1110
VREF × 1/2048 + 1 LSB
1000 0000 0001
0Bipolar Zero
1000 0000 0000
-VREF × 1/2048 - 1 LSB
0111 1111 1111
-VREF × 2046/2048
-FULL SCALE +
1 LSB
0000 0000 0001
-VREF × 2047/2048
-FULL SCALE
0000 0000 0000
*VREF = VREFP - VREFN
MAX1421
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
______________________________________________________________________________________ 13
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent solu-
tion to convert a single-ended signal to a fully differen-
tial signal, required by the MAX1421 for optimum
performance. Connecting the center tap of the trans-
former to CML provides an AVDD / 2 DC level shift to
the input. Although a 1:1 transformer is shown, a 1:2 or
1:4 step-up transformer may be selected to reduce the
drive requirements.
In general, the MAX1421 provides better SFDR and
THD with fully differential input signals over single-
ended input signals, especially for very high input fre-
quencies. In differential input mode, even-order
harmonics are suppressed and each of the inputs
requires only half the signal swing compared to single-
ended mode.
Single-Ended AC-Coupled Input Signal
Figure 9 shows an AC-coupled, single-ended applica-
tion, using a MAX4108 op amp. This configuration pro-
vides high-speed, high-bandwidth, low noise, and low
distortion to maintain the integrity of the input signal.
Grounding, Bypassing, and
Board Layout
The MAX1421 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side of
the board as the ADC, using surface-mount devices for
minimum inductance. Bypass REFP, REFN, REFIN, and
CML with a parallel network of 0.22µF capacitors and
1nF to AGND. AVDD should be bypassed with a similar
network of a 10µF bipolar capacitor in parallel with two
ceramic capacitors of 1nF and 0.1µF. Follow the same
rules to bypass the digital supply DVDD to DGND.
Multilayer boards with separate ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arrangement
to match the physical location of the analog ground
(AGND) and the digital output driver ground (DGND) on
the ADCs package. The two ground planes should be
joined at a single point so that the noisy digital ground
currents do not interfere with the analog ground plane.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy, digital systems ground plane (e.g.,
downstream output buffer, DSP ground plane). Route
high-speed digital signal traces away from sensitive
analog traces and remove digital ground and power
planes from underneath digital outputs. Keep all signal
lines short and free of 90 degree turns.
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight-
line can be either a best straight-line fit or a line drawn
between the endpoints of the transfer function, once off-
set and gain errors have been nullified. The static lin-
earity parameters for the MAX1421 are measured using
the best straight-line fit method.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step-width and the ideal value of 1LSB. A DNL
N - 7
N
N - 6
N + 1
N - 5
N + 2
N - 4
N + 3
N - 3
N + 4
N - 2
N + 5
N - 1 N
N + 6
7 CLOCK-CYCLE LATENCY
ANALOG INPUT
DATA OUTPUT
tDO tCH tCL
CLK
CLK
Figure 6. System and Output Timing Diagram
MAX1421
error specification of less than 1LSB guarantees no
missing codes.
Dynamic Parameter Definitions
Aperture Jitter
Figure 10 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 10).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADCs reso-
lution (N-bits):
SNR(MAX) = (6.02 ✕N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise e.g., thermal noise, reference noise, clock
jitter, etc. SNR is computed by taking the ratio of the
RMS signal to the RMS noise, which includes all spec-
tral components minus the fundamental, the first four
harmonics, and the DC offset.
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
14 ______________________________________________________________________________________
INPUT
300Ω
-5V
+5V
0.1µF
0.1µF
0.1µF
0.1µF
CIN*
22pF
1nF0.22µF
44pF*
RISO
50Ω
RISO
50Ω
-5V
600Ω
300Ω
300Ω
INP
INN
LOWPASS FILTER
CML
600Ω
+5V
-5V
0.1µF
300Ω
300Ω
600Ω
300Ω
0.1µF
0.1µF
0.1µF
+5V
0.1µF
300Ω
MAX4108
MAX1421
MAX4108
MAX4108
LOWPASS FILTER
*TWO CIN (22pF) CAPS MAY BE REPLACED BY
ONE 44pF CAP, TO IMPROVE PERFORMANCE.
CIN*
22pF
Figure 7. Typical Application Circuit for Single-Ended to Differential Conversion
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components minus the fundamental
and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB
is computed from:
ENOB SINAD
-
=176
602
.
.
MAX1421
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
______________________________________________________________________________________ 15
MAX1421
T1
N.C.
VIN 6
1
5
2
43
22pF
22pF
1nF
0.1µF
0.22µF
25Ω
25Ω
MINICIRCUITS
T1–1T–KK81
INN
INP
CML
44pF
*
*
*
*REPLACE BOTH 22pF CAPS WITH 44pF BETWEEN
INP AND INN TO IMPROVE DYNAMIC PERFORMANCE.
Figure 8. Using a Transformer for AC-Coupling
MAX1421
1nF
1kΩ100Ω
100Ω
CIN
22pF
CML
CIN
22pF
INP
INN
0.1µFRISO
50Ω
RISO
50Ω
0.22µF
VIN
MAX4108
Figure 9. Single-Ended AC-Coupled Input Signal
HOLD
ANALOG
INPUT
SAMPLED
DATA (T/H)
T/H
tAD
tAJ
TRACK TRACK
CLK
CLK
Figure 10. Track-and-Hold Aperture Timing
MAX1421
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first four
harmonics of the input signal to the fundamental itself.
This is expressed as:
where V1is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order har-
monics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest spurious
component, excluding DC offset.
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) inter-
modulation products. The individual input tone levels
are at -6.5dB full scale and their envelope is at -0.5dB
full scale.
THD
VVVV
V
1
=× +++
()
20 10
2
2
3
2
4
2
5
2
log
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
16 ______________________________________________________________________________________
CLK
INP
INTERFACE
PIPELINE ADC OUTPUT
DRIVERS
REFIN REFP CML REFN OE
AVDD
AGND
DVDD
DGND
D11–D0
INN
PD
T/H
MAX1421
BANDGAP
REFERENCE
CLK
REF SYSTEM +
BIAS
Functional Diagram
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
17 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
©2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
32L/48L,TQFP.EPS
F
1
2
21-0054
PACKAGE OUTLINE, 32/48L LQFP, 7x7x1.4mm
F
2
2
21-0054
PACKAGE OUTLINE, 32/48L LQFP, 7x7x1.4mm
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
MAX1421
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)