SN74LVC2G125DCTR - Texas Instruments

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FEATURES

See mechanical drawings for dimensions.

DCT PACKAGE

(TOP VIEW)

DCU PACKAGE

(TOP VIEW)

YZP PACKAGE

(BOTTOM VIEW)

1VCC

1OE

1A 2OE

2Y 1Y

GND 2A

1Y2Y

1VCC

1OE

GND 42A

272OE1A

GND 5

42A

3 6 1Y2Y

272OE1A

8VCC

1OE

DESCRIPTION/ORDERING INFORMATION

SN74LVC2G125

DUAL BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SCES204M–APRIL 1999–REVISED JANUARY 2007

•Available in the Texas Instruments •Ioff Supports Partial-Power-Down Mode

NanoFree™ Package Operation

•Supports 5-V VCC Operation •Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

•Inputs Accept Voltages to 5.5 V

•ESD Protection Exceeds JESD 22

•Max tpd of 4.3 ns at 3.3 V

– 2000-V Human-Body Model (A114-A)

•Low Power Consumption, 10-µA Max ICC

– 200-V Machine Model (A115-A)

•±24-mA Output Drive at 3.3 V

– 1000-V Charged-Device Model (C101)

•Typical VOLP (Output Ground Bounce)

<0.8VatV

CC = 3.3 V, TA=25°C

•Typical VOHV (Output VOH Undershoot)

>2VatV

CC = 3.3 V, TA=25°C

The SN74LVC2G125 is a dual bus buffer gate, designed for 1.65-V to 5.5-V VCC operation. This device features

dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is

high.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

TAPACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING(2)

NanoFree™ – WCSP (DSBGA) Reel of 3000 SN74LVC2G125YZPR _ _ _CM_

0.23-mm Large Bump – YZP (Pb-free)

SSOP – DCT Reel of 3000 SN74LVC2G125DCTR C25_ _ _

–40°C to 85°C

Reel of 3000 SN74LVC2G125DCUR

VSSOP – DCU C25_

Reel of 250 SN74LVC2G125DCUT

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.

DCU: The actual top-side marking has one additional character that designates the assembly/test site.

YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, •= Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoFree is a trademark of Texas Instruments.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

www.ti.com

1A 1Y

1OE

2A 2Y

2OE

Absolute Maximum Ratings(1)

SN74LVC2G125

DUAL BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SCES204M–APRIL 1999–REVISED JANUARY 2007

FUNCTION TABLE

(EACH BUFFER)

INPUTS OUTPUT

OE A

LH H

LL L

HX Z

LOGIC DIAGRAM (POSITIVE LOGIC)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

VCC Supply voltage range –0.5 6.5 V

VIInput voltage range(2) –0.5 6.5 V

VOVoltage range applied to any output in the high-impedance or power-off state(2) –0.5 6.5 V

VOVoltage range applied to any output in the high or low state(2)(3) –0.5 VCC + 0.5 V

IIK Input clamp current VI< 0 –50 mA

IOK Output clamp current VO< 0 –50 mA

IOContinuous output current ±50 mA

Continuous current through VCC or GND ±100 mA

DCT package 220

θJA Package thermal impedance(4) DCU package 227 °C/W

YZP package 102

Tstg Storage temperature range –65 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(3) The value of VCC is provided in the recommended operating conditions table.

(4) The package thermal impedance is calculated in accordance with JESD 51-7.

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Recommended Operating Conditions(1)

SN74LVC2G125

DUAL BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SCES204M–APRIL 1999–REVISED JANUARY 2007

MIN MAX UNIT

Operating 1.65 5.5

VCC Supply voltage V

Data retention only 1.5

VCC = 1.65 V to 1.95 V 0.65 × VCC

VCC = 2.3 V to 2.7 V 1.7

VIH High-level input voltage V

VCC =3Vto3.6V 2

VCC =4.5Vto5.5V 0.7×V

VCC = 1.65 V to 1.95 V 0.35 × VCC

VCC = 2.3 V to 2.7 V 0.7

VIL Low-level input voltage V

VCC =3Vto3.6V 0.8

VCC =4.5Vto5.5V 0.3×V

VIInput voltage 0 5.5 V

High or low state 0 VCC

VOOutput voltage V

3-state 0 5.5

VCC = 1.65 V –4

VCC = 2.3 V –8

IOH High-level output current –16 mA

VCC =3V –24

VCC = 4.5 V –32

VCC = 1.65 V 4

VCC = 2.3 V 8

IOL Low-level output current 16 mA

VCC =3V 24

VCC = 4.5 V 32

VCC = 1.8 V ±0.15 V, 2.5 V ±0.2 V 20

∆t/∆v Input transition rise or fall rate VCC = 3.3 V ±0.3 V 10 ns/V

VCC =5V±0.5 V 5

TAOperating free-air temperature –40 85 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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Electrical Characteristics

Switching Characteristics

Operating Characteristics

SN74LVC2G125

DUAL BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SCES204M–APRIL 1999–REVISED JANUARY 2007

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT

IOH = –100 µA 1.65 V to 5.5 V VCC – 0.1

IOH = –4 mA 1.65 V 1.2

IOH = –8 mA 2.3 V 1.9

VOH V

IOH = –16 mA 2.4

IOH = –24 mA 2.3

IOH = –32 mA 4.5 V 3.8

IOL = 100 µA 1.65 V to 5.5 V 0.1

IOL = 4 mA 1.65 V 0.45

IOL = 8 mA 2.3 V 0.3

VOL V

IOL =16mA 0.4

IOL =24mA 0.55

IOL = 32 mA 4.5 V 0.55

IIA or OE inputs VI= 5.5 V or GND 0 to 5.5 V ±5µA

Ioff VIor VO= 5.5 V 0 ±10 µA

IOZ VO= 0 to 5.5 V 3.6 V 10 µA

ICC VI= 5.5 V or GND, IO= 0 1.65 V to 5.5 V 10 µA

∆ICC One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500 µA

Data inputs 3.5

CiVI=V

CC or GND 3.3 V pF

Control inputs 4

CoVO=V

CC or GND 3.3 V 6.5 pF

(1) All typical values are at VCC = 3.3 V, TA= 25°C.

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC =5V

FROM TO ±0.15 V ±0.2 V ±0.3 V ±0.5 V

PARAMETER UNIT

(INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX

tpd A Y 3.3 9.1 1.5 4.8 1.4 4.3 1 3.7 ns

ten OE Y 4 9.9 1.9 5.6 1.2 4.7 1.2 3.8 ns

tdis OE Y 1.5 11.6 1 5.8 1.4 4.6 1 3.4 ns

TA= 25°

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC =5V

TEST

PARAMETER UNIT

CONDITIONS TYP TYP TYP TYP

Outputs enabled 19 19 20 22

Power dissipation

Cpd f = 10 MHz pF

capacitance Outputs disabled 2223

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PARAMETER MEASUREMENT INFORMATION

tsu

From Output

Under Test

(see Note A)

LOAD CIRCUIT

VLOAD

Open

GND

Data Input

Timing Input

Input

Output

Waveform 1

S1 at V

(see Note B)

LOAD

Output

Waveform 2

S1 at GND

(see Note B)

VOL

VOH

»0V

Output

TEST S1

t/t

PLH PHL Open

Output

Control

VMVM

1.8 V 0.15 V±

2.5 V 0.2 V±

3.3 V 0.3 V±

5 V 0.5 V±

1kW

500 W

VCC RL

2×V

VLOAD CL

30 pF

50 pF

0.15 V

0.3 V

VCC/2

1.5 V

VCC/2

£2ns

£2.5 ns

INPUTS

t/t

VCC

VLOAD

t/t

PLZ PZL

GND

t/t

PHZ PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. C includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 .

D. The outputs are measured one at a time, with one transition per measurement.

E. t and t are the same as t .

F. t and t are the same as t .

G. t and t are the same as t .

H. All parameters and waveforms are not applicable to all devices.

PLZ PHZ dis

PZL PZH en

PLH PHL pd

£W

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

V/2

LOAD

tPZL tPLZ

tPHZ

tPZH

V–V

OH D

V+V

OL D

VMVM

VOL

VOH

VOL

tPLH tPHL

tPLH

tPHL

SN74LVC2G125

DUAL BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SCES204M–APRIL 1999–REVISED JANUARY 2007

Figure 1. Load Circuit and Voltage Waveforms

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PACKAGING INFORMATION

Orderable Device Status (1) Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

74LVC2G125DCTRE4 ACTIVE SM8 DCT 8 3000 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

74LVC2G125DCTRE6 ACTIVE SM8 DCT 8 3000 Pb-Free

(RoHS)

CU SNBI Level-1-260C-UNLIM

74LVC2G125DCTRG4 ACTIVE SM8 DCT 8 3000 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

74LVC2G125DCURE4 ACTIVE US8 DCU 8 3000 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

74LVC2G125DCURG4 ACTIVE US8 DCU 8 3000 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

74LVC2G125DCUTE4 ACTIVE US8 DCU 8 250 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

74LVC2G125DCUTG4 ACTIVE US8 DCU 8 250 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC2G125DCTR ACTIVE SM8 DCT 8 3000 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC2G125DCUR ACTIVE US8 DCU 8 3000 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC2G125DCUT ACTIVE US8 DCU 8 250 Green (RoHS &

no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN74LVC2G125YZPR ACTIVE DSBGA YZP 8 3000 Green (RoHS &

no Sb/Br)

SNAGCU Level-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

PACKAGE OPTION ADDENDUM

www.ti.com 18-Sep-2008

Addendum-Page 1

to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC2G125 :

•Automotive: SN74LVC2G125-Q1

NOTE: Qualified Version Definitions:

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

PACKAGE OPTION ADDENDUM

www.ti.com 18-Sep-2008

Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

Package

Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)

Pin1

Quadrant

SN74LVC2G125DCUR US8 DCU 8 3000 180.0 9.2 2.25 3.35 1.05 4.0 8.0 Q3

SN74LVC2G125YZPR DSBGA YZP 8 3000 180.0 8.4 1.1 2.1 0.56 4.0 8.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 22-Jul-2008

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN74LVC2G125DCUR US8 DCU 8 3000 202.0 201.0 28.0

SN74LVC2G125YZPR DSBGA YZP 8 3000 220.0 220.0 34.0

PACKAGE MATERIALS INFORMATION

www.ti.com 22-Jul-2008

Pack Materials-Page 2

MECHANICAL DATA

MPDS049B – MAY 1999 – REVISED OCTOBER 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE

ÇÇÇÇÇ

ÇÇÇ

ÇÇÇÇÇ

0,60

0,20

0,25

0°– 8°

0,15 NOM

Gage Plane

4188781/C 09/02

4,25

0,30

0,15

2,90

3,75

2,70

3,15

2,75

0,10

0,00

1,30 MAX

Seating Plane

0,10

0,13

0,65

PIN 1

INDEX AREA

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion

D. Falls within JEDEC MO-187 variation DA.

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