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74F74
Dual D-type flip-flop
Product specification
Supercedes data of 1990 Oct 23
IC15 Data Handbook
1996 Mar 12
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74F74Dual D-type flip-flop
2
1996 Mar 12 853 0335 16554
FEATURE
•Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F74 is a dual positive edge-triggered D-type flip-flop featuring
individual data, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active low inputs and operate independently of the clock input. When
set and reset are inactive (high), data at the D input is transferred to
the Q and Q outputs on the low-to-high transition of the clock. Data
must be stable just one setup time prior to the low-to-high transition of
the clock for predictable operation. Clock triggering occurs at a
voltage level and is not directly related to the transition time of the
positive-going pulse. Following the hold time interval, data at the D
input may be changed without affecting the levels of the output.
PIN CONFIGURATION
14
13
12
11
10
9
87
6
5
4
3
2
1
GND
VCC
SD1
Q1
Q1
CP1
RD1
D1
RD0
D0
Q0
CP0
SD0
Q0
SF00045
TYPE TYPICAL fmax TYPICAL SUPPLY CURRENT (TOTAL)
74F74 125MHz 11.5mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
INDUSTRIAL RANGE
VCC = 5V ±10%,
Tamb = –40°C to +85°C
PKG. DWG. #
14-pin plastic DIP N74F74N I74F74N SOT27-1
14-pin plastic SO N74F74D I74F74D SOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW
D0, D1 Data inputs 1.0/1.0 20µA/0.6mA
CP0, CP1 Clock inputs (active rising edge) 1.0/1.0 20µA/0.6mA
SD0, SD1 Set inputs (active low) 1.0/3.0 20µA/1.8mA
RD0, RD1 Reset inputs (active low) 1.0/3.0 20µA/1.8mA
Q0, Q1, Q0, Q1Data outputs 50/33 1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
LOGIC SYMBOL
Q0 Q0 Q1 Q1
56 98
VCC = Pin 14
GND = Pin 7
3
4
1
11
10
13
CP0
SD0
RD0
CP1
SD1
RD1
D0 D1
212
SF00046
IEC/IEEE SYMBOL
4
3
2
1
10
11
12
13
5
6
9
8
&
S
S
C1
C2
R
1D
2D
R
SF00047
Philips Semiconductors Product specification
74F74Dual D-type flip-flop
1996 Mar 12 3
LOGIC DIAGRAM
VCC = Pin 14
GND = Pin 7
5, 9
6, 8
Q
Q
4, 10
1, 13
3, 11
2, 12
SD
RD
CP
D
SF00048
FUNCTION TABLE
INPUTS OUTPUTS OPERATING
SD RD CP D Q Q MODE
L H X X H L Asynchronous set
H L X X L H Asynchronous reset
L L X X H H Undetermined*
H H ↑h H L Load ”1”
H H ↑l L H Load ”0”
H H ↑X NC NC Hold
NOTES:
H = High voltage level
h = High voltage level one setup time prior to low-to-high clock
transition
L = Low voltage level
l = Low voltage level one setup time prior to low-to-high clock
transition
NC= No change from the previous setup
X = Don’t care
↑= Low-to-high clock transition
↑= Not low-to-high clock transition
* = This setup is unstable and will change when either set or reset
return to the high level.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL PARAMETER RATING UNIT
VCC Supply voltage –0.5 to +7.0 V
VIN Input voltage –0.5 to +7.0 V
IIN Input current –30 to +5 mA
VOUT Voltage applied to output in high output state –0.5 to VCC V
IOUT Current applied to output in low output state 40 mA
T
O
p
erating free air tem
p
erature range
Commercial range 0 to +70 °C
T
amb
Operating
free
air
temperat
u
re
range
Industrial range –40 to +85 °C
Tstg Storage temperature range –65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5.0 5.5 V
VIH High-level input voltage 2.0 V
VIL Low-level input voltage 0.8 V
IIk Input clamp current –18 mA
IOH High-level output current –1 mA
IOL Low-level output current 20 mA
Tb
O
p
erating free air tem
p
erature range
Commercial range 0 +70 °C
T
amb
O erating
free
air
tem erature
range
Industrial range –40 +85 °C
Philips Semiconductors Product specification
74F74Dual D-type flip-flop
1996 Mar 12 4
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS1
LIMITS
UNIT
SYMBOL
PARAMETER
TEST
CONDITIONS1
MIN TYP2MAX
UNIT
VO
High level out
p
ut voltage
IO= MAX
±10%VCC 2.5 V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
CC =
,
IL =
,
IH =
I
OH =
MAX
±5%VCC 2.7 3.4 V
VO
Low level out
p
ut voltage
IO= MAX
±10%VCC 0.30 0.50 V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
CC =
,
IL =
,
IH =
I
OL =
MAX
±5%VCC 0.30 0.50 V
VIK Input clamp voltage VCC = MIN, II = IIK -0.73 -1.2 V
IIInput current at maximum input
voltage VCC = MAX, VI = 7.0V 100 µA
IIH High-level input current VCC = MAX, VI = 2.7V 20 µA
I
Low-level input Dn, CPn VCC = MAX, VI = 0.5V -0.6 mA
I
IL current SDn, RDn VCC = MAX, VI = 0.5V -1.8 mA
IOS Short-circuit output current3VCC = MAX -60 -150 mA
ICC Supply current (total) 4VCC = MAX 11.5 16 mA
NOTES:
1 For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2 All typical values are at VCC = 5V, Tamb = 25°C.
3 Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
4 Measure ICC with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL PARAMETER TEST
CONDITION
VCC = +5.0V
Tamb = +25°C
CL = 50pF, RL = 500Ω
VCC = +5.0V ± 10%
Tamb = 0°C to +70°C
CL = 50pF, RL = 500Ω
VCC = +5.0V ± 10%
Tamb = –40°C to +85°C
CL = 50pF, RL = 500ΩUNIT
MIN TYP MAX MIN MAX MIN MAX
fmax Maximum clock frequency W aveform 1 100 125 100 90 MHz
tPLH
tPHL Propagation delay
CPn to Qn or Qn Waveform 1 3.8
4.4 5.3
6.2 6.8
8.0 3.8
4.4 7.8
9.2 3.8
4.4 8.5
9.2 ns
tPLH
tPHL Propagation delay
SDn, RDn to Qn or Qn W aveform 2 3.2
3.5 4.6
7.0 6.1
9.0 3.2
3.5 7.1
10.5 3.2
2.5 7.5
10.5 ns
AC SETUP REQUIREMENTS
LIMITS
SYMBOL PARAMETER TEST
CONDITION
VCC = +5.0V
Tamb = +25°C
CL = 50pF, RL = 500Ω
VCC = +5.0V ± 10%
Tamb = 0°C to +70°C
CL = 50pF, RL = 500Ω
VCC = +5.0V ± 10%
Tamb = –40°C to +85°C
CL = 50pF, RL = 500ΩUNIT
MIN TYP MAX MIN MAX MIN MAX
tsu (H)
tsu (L) Setup time, high or low
Dn to CPn W aveform 1 2.0
3.0 2.0
3.0 2.0
3.0 ns
th (H)
th (L) Hold time, high or low
Dn to CPn W aveform 1 1.0
1.0 1.0
1.0 1.0
1.0 ns
tw (H)
tw (L) CPn pulse width,
high or low W aveform 1 4.0
5.0 4.0
5.0 4.0
5.0 ns
tw (L) SDn, RDn pulse width,
low W aveform 2 4.0 4.0 4.0 ns
trec Recovery time
SDn, RDn to CPn W aveform 3 2.0 2.0 2.0 ns
Philips Semiconductors Product specification
74F74Dual D-type flip-flop
1996 Mar 12 5
AC WAVEFORMS
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
VM
VM
CPn
VMVMVMVM
VMVM
tsu(H) th(H)
Dn
Qn
VM
tw(H)
1/fmax
tsu(L) th(L)
VM
VM
tPLH
Qn
tw(L)
tPHL
tPHL
tPLH
SF01276
W aveform 1. Propagation delay for data to output, data setup
time and hold times, and clock width, and maximum clock
frequency
VM
VM
RDn VM
Qn
VM
VM
VM
tPLH
Qn
tw(L)
tPHL
tPHL
tPLH
SDn VM
VMtw(L)
SF00050
W aveform 2. Propagation delay for set and reset to output,
set and reset pulse width
SDn or RDn VM
VM
trec
CPn
SF00051
W aveform 3. Recovery time for set or reset to clock
TEST CIRCUIT AND WAVEFORMS
tw90%
VM
10%
90%
VM10%
90%
VM10%
90%
VM
10%
NEGATIVE
PULSE
POSITIVE
PULSE
tw
AMP (V)
0V
0V
tTHL (tf )
INPUT PULSE REQUIREMENTS
rep. rate twtTLH tTHL
1MHz 500ns 2.5ns 2.5ns
Input Pulse Definition
VCC
family
74F
D.U.T.
PULSE
GENERATOR
RL
CL
RT
VIN VOUT
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
RL= Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
CL= Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
RT= Termination resistance should be equal to ZOUT of
pulse generators.
tTHL (tf )
tTLH (tr )
tTLH (tr )AMP (V)
amplitude
3.0V 1.5V
VM
SF00006
Philips Semiconductors Product specification
74F74Dual D-type flip-flop
1996 Mar 12 6
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
Philips Semiconductors Product specification
74F74Dual D-type flip-flop
1996 Mar 12 7
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
Philips Semiconductors Product specification
74F74Dual D-type flip-flop
yyyy mmm dd 8
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may af fect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques A venue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 10-98
Document order number: 9397-750-05066
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Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition [1]
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
Data sheet status
[1] Please consult the most recently issued datasheet before initiating or completing a design.