ATC AM24LC02 2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM General Description Features * State- of- the- art architecture - Non-volatile data storage - Supply voltage range: 2.7V ~ 5.5V * 2 wire I2C serial interface - Providing bi-directional data transfer protocol * Hard-ware write protection - With WP PIN to disable programming command * 8 bytes page write mode - Minimizing total write time per word * Self-timed write cycle (including auto-erase) * Durability and reliability - 40 years data retention - Minimum of 1KK write/erase cycles per word - Unlimited read cycles - ESD protection * Low standby current * Package: PDIP, SOP and TSSOP The AM24LC02 is a non-volatile, 2048-bit serial EEPROM with enhanced security device and conforms to all specifications in I2C 2-wire protocol. The whole memory can be disabled (Write Protected) by connecting the WP pin to Vcc. This section of memory then becomes unalterable unless WP is switched to Vss. The AM24LC02's communication protocol uses CLOCK(SCL) and DATA I/O(SDA) lines to synchronously clock data between the master (for example a microcomputer)and the slave EEPROM device(s) .In addition, the bus structure allows for a maximum of 16K of EEPROM memory. This is supported by the family in 2K, 4K, 8K, 16K devices, allowing the user to configure the memory as the application requires with any combination of EEPROMs (not to exceed 16K). Anachip EEPROMs are designed and tested for application requiring high endurance, high reliability, and low power consumption. Connection Diagram A0 1 A1 2 A2 VSS Pin Assignments 8 VCC 7 WP 3 6 SCL 4 5 SDA 24LC02 Name A0, A1, A2 VSS SDA SCL WP VCC PDIP/SOP/TSSOP Description Address Inputs Ground Data I/O Clock Input Write Protect Power Input Ordering Information AM 24 LC 02 X XX X Operating Voltage Type LC: 2.7~5.5V, CMOS 02 =2K Temp. grade o Package o Blank : 0 C ~ +70 C I : - 40 o C ~ +85 o C V : - 40 o C ~ +125 o C S : SOP-8L N : PDIP-8L TS : TSSOP-8L Packing Blank : Tube A : Taping This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. Rev.A1 Oct 1/12 20, 2003 ATC 2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM AM24LC02 Block Diagrams WP SCL start cycle CONTROL LOGIC START STOP LOGIC SDA H.V. GENERATION TIMING & CONTROL ck load SLAVE ADDRESS REGISTER & COMPARATOR A0 A1 A2 inc WORD ADDRESS COUNTER EEPROM ARRAY 32x8x8 XDEC R/W ~ VCC VSS YDEC DATA REGISTER Din Dout DOUT ACK Absolute Maximum Ratings Characteristics Symbol Values Unit TS -65 to + 125 -0.3 to + 6.5 C V Storage Temperature Voltage with Respect to Ground NOTE: These are STRESS rating only. Appropriate conditions for operating these devices given elsewhere may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability. Operating Conditions Temperature under bias Values Unit AM24LC02 Commercial 0 to + 70 C AM24LC02I AM24LC02V Industrial Automotive -40 to +85 -40 to +125 C C Anachip Corp. www.anachip.com.tw Rev. A1 Oct 20, 2003 2/12 ATC AM24LC02 2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM Electrical Characteristics DC Electrical Characteristics (Vcc =2.7~5.5V, Ta = 25oC ) Parameter Symbol Operating Current (Program) ** Operating Current (Read) ** Standby Current Standby Current Input Leakage Output Leakage Input Low Voltage** Input High Voltage** Output Low Voltage Output Low Voltage ICC1 ICC2 ISB1 ISB2 IIL IOL VIL VIH VOL1 VOL2 VCC Lockout Voltage VLK Conditions SCL = 100KHz CMOS Input SCL = 100KHz CMOS Input SCL=SDA=0V, Vcc=5V SCL=SDA=0V, Vcc=3V VIN = 0 V to Vcc VOUT = 0 V to Vcc IOL = 2.1mA TTL IOL = 10uA CMOS Programming Command Can Be Executed AM24LC02 Units Min Max -- 3 mA -- 200 A -- 10 A -- 1 -1 +1 A -1 +1 A -0.1 Vcc x 0.3 V Vcc x 0.7 VCC+ 0.2 V -- 0.4 V -- 0.2 V Default -- V Note ** : ICC1, ICC2, VIL min and VIH max are for reference only and are not tested. Switching Characteristics (Under Operating Conditions) AC Electrical Characteristics (Vcc =2.7~5.5V) Parameter Clock frequency Clock high time Clock low time SDA and SCL rise time** SDA and SCL fall time** START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time ** Data out hold time Write cycle time 5V, 25C, Byte Mode AM24LC02 Symbol Min 0 4000 4700 -- -- 4000 4700 0 250 4000 300 4700 300 -- 1M Fscl Thigh Tlow Tr Tf Thd:Sta Tsu:Sta Thd:Dat Tsu:Dat Tsu:Sto Taa Tbuf Tdh Twr Endurance** Units Max 100 -- -- 1000 300 -- -- -- -- -- 3500 -- -- 10 -- kHz ns ns ns ns ns ns ns ns ns ns ns ns ms write cycles Note ** :This parameter is characterized and is not 100% tested. Capacitance TA= 25C , f=250KHz Symbol Parameter COUT Output capacitance CIN Input capacitance A.C. Conditions of Test Input Pulse Levels Input Rise and Fall times Input and Output Timming level Output Load Max 5 5 Units pF pF Vcc x 0.1 to Vcc x 0.9 10 ns Vcc x 0.5 1 TTL Gate and CL = 100pF Anachip Corp. www.anachip.com.tw Rev. A1 Oct 20, 2003 3/12 ATC 2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM AM24LC02 Pin Descriptions TABLE A Device A0 A1 AM24LC02 ADR ADR AM24LC04 XP ADR AM24LC08 XP XP AM24LC16 XP XP ADR indicates the device address pin. XP indicates that device address pin does but refers to an internal PAGE BLOCK segment. Serial Clcok (SCL) The SCL input is used to clock all data into and out of the device. SerialL Data (SDA) SDA is a bidirection pin used to transfer data or security bit into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. Thus, the SDA bus requires a pull-up resistor to Vcc (typical 4.7K for 100KHz, 1K for 400KHz). A2 ADR ADR ADR XP not care memory Write Protection (WP) If WP is connected to Vcc, PROGRAM operation onto the whole memory will not be executed. READ operations are possible. If WP is connected to Vss, normal memory operation is enabled, READ/WRITE over the entire memory is possible. Device Address Inputs (A0, A1, A2) The following table (Table A) shows the active pins across the AM24LCXX device family. Functional Description Applications ATC's electrically erasable programmable read only memories (EEPROMs) offer valuable security features including write protect function, two write modes, three read modes, and a wide variety of memory size. Typical applications for the I2C bus and AM24LCXX memories include SANs(small-area-networks), stereos, televisions, automobiles and other scaled-down systems that do not require tremendous speeds but instead cost efficiency and design simplicity. Clock and Data Conventions Data states on the SDA line can be changed only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. (Shown in Figures 1 and 2) Endurance And Data Retention The AM24LC02 is designed for applications requiring up to 1KK programming cycles (BYTE WRITE and PAGE WRITE). It provides 40 years of secure data retention without power. Stop Condition A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. (Shown in Figure 2) Start Condition A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded with a START condition. (Shown in Figure 2) Device Operation The AM24LC02 device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is the master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the AM24LC02 is considered a slave in all applications. Anachip Corp. www.anachip.com.tw Rev. A1 Oct 20, 2003 4/12 ATC 2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM AM24LC02 Functional Description (Continued) read or write mode. All I2C EEPROMs use and internal protocol that defines a PAGE BLOCK size of 16K bits. The AM24LC02 contains one 2K-bits PAGE BLOCK, and the device address bits A0, A1 and A2 are used for determinating which device will be proceeded in. The eighth bit of slave address determines if the master device wants to read or write to the AM24LC02 (Refer to table B). Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. (Shown in Figure 3) The AM24LC02 monitors the bus for its corresponding slave address all the time. It generates an acknowledge bit if the slave address was true and it is not in a programming mode. Operation Read Write Devices Addressing After generating a START condition, the bus master transmits the slave address consisting of a 4-bit device code (1010) for the AM24LC02, 3-bit device address (A2 A1 A0) and 1-bit value indicating the Control Code 1010 1010 Chip Select A2 A1 A0 A2 A1 A0 R/W 1 0 Table B A0, A1, A2 is used to access the AM24LC02. Write Operations temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. If the master transmits more than 8 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an internal write cycle will begin. (Shown in Figure 5) Byte Write Following the start signal from the master, the slave address is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte transmitted by the master is the word address and will be written into the address pointer of the AM24LC02. After receiving another acknowledge signal from the AM24LC02 the master device will transmit the data word to be written into the addressed memory location. The AM24LC02 acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this period the AM24LC02 will not generate acknowledge signals. (Shown in Figure 4) Acknowledge Polling Since the device will not acknowledge during a write cycle , this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughout). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle , then no ACK will returned. If the cycle is complete then the device will return the ACK and the master can then proceed with the next read or write commands. Page Write The write control byte, word address and the first data byte are transmitted to the AM24LC02 in the same way as in a byte write. But instead of generating a stop condition the master transmit up to 8 data bytes to the AM24LC02 which are Anachip Corp. www.anachip.com.tw Rev. A1 Oct 20, 2003 6/12 ATC 2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM AM24LC02 Write Operations (Continued) any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the AM24LC02 as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with R/W bit set to a one. The AM24LC02 will then issue an acknowledge and transmit the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the AM24LC02 discontinues transmission. (Shown in Figure 7) Write Protection Programming will not take place if the WP pin of the AM24LC02 is connected to Vcc. The AM24LC02 will accept slave and byte addresses; but if the memory accessed is write protected by the WP pin, the AM24LC02 will not generate an acknowledge after the first byte of data has been received, and thus the programming cycle will not be started when the stop condition is asserted. Read Operations Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read. Sequential Read Sequential read is initiated in the same way as a random read except that after the AM24LC02 transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the AM24LC02 to transmit the next sequentially addressed 8 bit word (Shown in Figure 8). To provide sequential read the AM24LC02 contains an internal address pointer which is incremented by one at the completion of each operation. Current Address Read The AM24LC02 contains an address counter that maintains the address of the last accessed word, internally incremented by one. Therefore if the previous access (either a read or write operation ) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the AM24LC02 issues an acknowledge and transmits the eight bit data word . The master will not acknowledge the transfer but does generate a stop condition and the AM24LC02 discontinues transmission. (Shown in Figure 6) Noise Protection The SCL and SDA inputs have filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus and to avert data alteration. Random Read Random read operations allow the master to access Anachip Corp. www.anachip.com.tw Rev. A1 Oct 20, 2003 2/12 ATC 2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM AM24LC02 Timing Diagram Bus Timing Thigh Tf Tr Tlow Tlow SCL Thd:Sta SDA IN Tsu:Sta Tsu:Dat Thd:Dat Tsu:Sta Tbuf Taa Tdh SDA OUT SDA SCL DATA STABLE DATA CHANGE Figure 1. Data Validity SDA SCL START BIT STOP BIT Figure 2. Definition of Start and Stop SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACKNOWLEDGE START Figure 3. Acknowledge Response from Receiver Anachip Corp. www.anachip.com.tw Rev. A1 Oct 20, 2003 7/12 ATC AM24LC02 2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM BUS ACTIVITY MASTER SDA LINE SLAVE ADDRESS START BYTE ADDRESS DATA n STOP S P A C K BUS ACTIVITY SLAVE A C K A C K Figure 4. Byte Write for Data BUS ACTIVITY START MASTER SDA LINE SLAVE ADDRESS BYTE ADDRESS n DATA n DATA n+7 STOP S P A C K A C K BUS ACTIVITY SLAVE A C K A C K Figure 5. Page Write for Data BUS ACTIVITY MASTER START SDA LINE SLAVE ADDRESS STOP s P A C K BUS ACTIVITY SLAVE No A C K DATA Figure 6. Current Address Read for Data BUS ACTIVITY START MASTER SDA LINE SLAVE ADDRESS BYTE ADDRESS n START S SLAVE ADDRESS STOP S A C K BUS ACTIVITY SLAVE P A C K A C K Figure 7. Random Read for Data BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY SLAVE START SLAVE ADDRESS A C K DATA n A C K No A C K STOP S P A C K DATA n+1 DATA n Figure 8. Sequential Read for Data Anachip Corp. www.anachip.com.tw DATA n+x No A C K Rev. A1 Oct 20, 2003 8/12 ATC 2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM AM24LC02 Package Information (1)Package Type: PDIP-8L D E1 E-PIN O0.118 inch E 15 (4X) PIN #1 INDENT O0.025 DEEP 0.006-0.008 inch C 7 (4X) A1 L A A2 eB B S Symbol A A1 A2 B B1 B2 C D E E1 e L eB S e B1 B2 Dimensions in millimeters Min. Nom. Max. 5.33 0.38 3.1 3.30 3.5 0.36 0.46 0.56 1.4 1.52 1.65 0.81 0.99 1.14 0.20 0.25 0.36 9.02 9.27 9.53 7.62 7.94 8.26 6.15 6.35 6.55 2.54 2.92 3.3 3.81 8.38 8.89 9.40 0.71 0.84 0.97 Anachip Corp. www.anachip.com.tw Dimensions in inches Min. Nom. Max. 0.210 0.015 0.122 0.130 0.138 0.014 0.018 0.022 0.055 0.060 0.065 0.032 0.039 0.045 0.008 0.010 0.014 0.355 0.365 0.375 0.300 0.313 0.325 0.242 0.250 0.258 0.100 0.115 0.130 0.150 0.330 0.350 0.370 0.028 0.033 0.038 Rev. A1 Oct 20, 2003 9/12 ATC 2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM AM24LC02 H E (2)Package Type: SOP-8L L VIEW "A" D 0.015x45 C B A1 e 7 (4X) A A2 7 (4X) VIEW "A" y Symbol A A1 A2 B C D E e H L y Dimensions In Millimeters Min. Nom. Max. 1.40 1.60 1.75 0.10 0.25 1.30 1.45 1.50 0.33 0.41 0.51 0.19 0.20 0.25 4.80 5.05 5.30 3.70 3.90 4.10 1.27 5.79 5.99 6.20 0.38 0.71 1.27 0.10 O 8O 0 Anachip Corp. www.anachip.com.tw Dimensions In Inches Min. Nom. Max. 0.055 0.063 0.069 0.040 0.100 0.051 0.057 0.059 0.013 0.016 0.020 0.0075 0.008 0.010 0.189 0.199 0.209 0.146 0.154 0.161 0.050 0.228 0.236 0.244 0.015 0.028 0.050 0.004 O 0 8O Rev. A1 Oct 20, 2003 10/12 ATC AM24LC02 2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM E E1 (3)Package Type: TSSOP-8L PIN 1 INDICATOR 0.70 mm SURFACE POLISHED L L1 DETAIL A D e A A1 A2 b C D E E1 e L L1 y Dimensions In Millimeters Min. Nom. Max. 1.05 1.10 1.20 0.05 0.10 0.15 1.00 1.05 0.20 0.25 0.28 0.13 2.90 3.05 3.10 6.20 6.40 6.60 4.30 4.40 4.50 0.65 0.50 0.60 0.70 0.90 1.00 1.10 0.10 0O 4O 8O Anachip Corp. www.anachip.com.tw DETAIL A C A1 b y Symbol L1 A A2 E1 Dimensions In Inches Min. Nom. Max. 0.041 0.043 0.047 0.002 0.004 0.006 0.039 0.041 0.008 0.01 0.011 0.005 0.114 0.12 0.122 0.244 0.252 0.26 0.169 0.173 0.177 0.026 0.02 0.024 0.028 0.035 0.039 0.043 0.004 0O 4O 8O Rev. A1 Oct 20, 2003 11/12 ATC AM24LC02 2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM Marking Information (1) PDIP-8L & SOP-8L Top view ATC Part Number & grade X = Blank ( 0 ~ + 70 o C) = I = V Logo 24LC02 X XX XX X ( - 40 ~ +85o C) ID code: internal ( - 40 ~ +125o C) Nth week: 01~52 Year: "01" = 2001 "02" = 2002 (2) TSSOP-8L Top view ATC Part Number & Temp.grade X = Blank ( 0 ~ + 70 oC ) = I = V Logo 24LC02 X XX XX X ( - 40 ~ + 85 oC ) ( - 40 ~ + 125 oC ) ID code: internal Nth week: 01~52 Year: Anachip Corp. www.anachip.com.tw "01" = 2001 "02" = 2002 Rev. A1 Oct 20, 2003 12/12