2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM AM24LC02
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev.A1 Oct 20, 2003
1/12
ATC
Features
• State- of- the- art architecture
- Non-volatile data storage
- Supply voltage range: 2.7V ~ 5.5V
• 2 wire I2C serial interface
- Providing bi-directional data transfer protocol
• Hard-ware write protection
- With WP PIN to disable programming command
• 8 bytes page write mode
- Minimizing total write time per word
• Self-timed write cycle (including auto-erase)
• Durability and reliability
- 40 years data retention
- Minimum of 1KK write/erase cycles per word
- Unlimited read cycles
- ESD protection
• Low standby current
• Package: PDIP, SOP and TSSOP
Connection Diagram
VCC
WP
SCL
SDA
A0
A1
A2
VSS
1
2
3
45
6
7
8
24LC02
PDIP/SOP/TSSOP
General Description
The AM24LC02 is a non-volatile, 2048-bit serial
EEPROM with enhanced security device and
conforms to all specifications in I2C 2-wire protocol.
The whole memory can be disabled (Write Protected)
by connecting the WP pin to Vcc. This section of
memory then becomes unalterable unless WP is
switched to Vss. The AM24LC02's communication
protocol uses CLOCK(SCL) and DATA I/O(SDA)
lines to synchronously clock data between the
master (for example a microcomputer)and the slave
EEPROM device(s) .In addition, the bus structure
allows for a maximum of 16K of EEPROM memory.
This is supported by the family in 2K, 4K, 8K, 16K
devices, allowing the user to configure the memory
as the application requires with any combination of
EEPROMs (not to exceed 16K).
Anachip EEPROMs are designed and tested for
application requiring high endurance, high reliability,
and low power consumption.
Pin Assignments
Name Description
A0, A1, A2 Address Inputs
VSS Ground
SDA Data I/O
SCL Clock Input
WP Write Protect
VCC Power Input
Ordering Information
Type Package
02 =2K S : SOP-8L
N : PDIP-8L
TS : TSSOP-8L
Temp. grade
AM 24 LC 02 XXX X
Packing
Blank : C70~C0 oo +
I : C85~C40 oo +−
V : C125~C40 oo +−
Blank : Tube
A : Taping
Operating Voltage
LC: 2.7~5.5V, CMOS
2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM AM24LC02
Anachip Corp.
www.anachip.com.tw Rev. A1 Oct 20, 2003
2/12
ATC
Block Diagrams
START
STOP
LOGIC
CONTROL
LOGIC
SLAVE
ADDRESS
REGISTER
&
COMPARATOR
WORD
ADDRESS
COUNTER
H.V.
GENERATION
TIMING
&
CONTROL
XDEC
EEPROM
ARRAY
32x8x8
YDEC
DATA
REGISTER
DOUT
ACK
SDA
SCL
A0
A1
A2
VCC
VSS
Din
R/W ~
Dout
incload
ck
start cycle
WP
Absolute Maximum Ratings
Characteristics Symbol Values Unit
Storage Temperature TS -65 to + 125 °C
Voltage with Respect to Ground -0.3 to + 6.5 V
NOTE: These are STRESS rating only. Appropriate conditions for operating these devices given elsewhere may permanently damage
the part. Prolonged exposure to maximum ratings may affect device reliability.
Operating Conditions
Temperature under bias Values Unit
AM24LC02 Commercial 0 to + 70 °C
AM24LC02I Industrial -40 to +85 °C
AM24LC02V Automotive -40 to +125 °C
2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM AM24LC02
Anachip Corp.
www.anachip.com.tw Rev. A1 Oct 20, 2003
3/12
ATC
Electrical Characteristics
DC Electrical Characteristics (Vcc =2.7~5.5V, Ta = 25oC )
AM24LC02
Parameter Symbol Conditions Min Max Units
Operating Current (Program) ** ICC1 SCL = 100KHz CMOS Input — 3 mA
Operating Current (Read) ** ICC2 SCL = 100KHz CMOS Input — 200 µA
Standby Current ISB1 SCL=SDA=0V, Vcc=5V — 10 µA
Standby Current ISB2 SCL=SDA=0V, Vcc=3V — 1
Input Leakage IIL V
IN = 0 V to Vcc -1 +1 µA
Output Leakage IOL V
OUT = 0 V to Vcc -1 +1 µA
Input Low Voltage** VIL -0.1 Vcc x 0.3 V
Input High Voltage** VIH Vcc x 0.7 VCC+ 0.2 V
Output Low Voltage VOL1 I
OL = 2.1mA TTL — 0.4 V
Output Low Voltage VOL2 I
OL = 10uA CMOS — 0.2 V
VCC Lockout Voltage VLK Programming Command Can Be
Executed Default — V
Note ** : ICC1, ICC2, VIL min and VIH max are for reference only and are not tested.
Switching Characteristics (Under Operating Conditions)
AC Electrical Characteristics (Vcc =2.7~5.5V)
AM24LC02
Parameter Symbol Min Max Units
Clock fre
q
uenc
y
Fscl 0 100 kHz
Clock hi
g
h time Thi
g
h 4000 — ns
Clock low time Tlow 4700 — ns
SDA and SCL rise time** Tr — 1000 ns
SDA and SCL fall time** Tf — 300 ns
START condition hold time Thd:Sta 4000 — ns
START condition setu
p
time Tsu:Sta 4700 — ns
Data in
p
ut hold time Thd:Dat 0 — ns
Data in
p
ut setu
p
time Tsu:Dat 250 — ns
STOP condition setu
p
time Tsu:Sto 4000 — ns
Out
p
ut valid from clock Taa 300 3500 ns
Bus free time ** Tbuf 4700 — ns
Data out hold time Tdh 300 — ns
Write c
y
cle time Twr — 10 ms
5V
,
25ºC
,
B
y
te Mode Endurance** 1M — write c
y
cles
Note ** :This parameter is characterized and is not 100% tested.
Capacitance TA= 25°C , f=250KHz
Symbol Parameter Max Units
COUT Output capacitance 5 pF
CIN Input capacitance 5 pF
A.C. Conditions of Test
Input Pulse Levels Vcc x 0.1 to Vcc x 0.9
Input Rise and Fall times 10 ns
Input and Output Timming level Vcc x 0.5
Output Load 1 TTL Gate and CL = 100pF
2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM AM24LC02
Anachip Corp.
www.anachip.com.tw Rev. A1 Oct 20, 2003
4/12
ATC
Pin Descriptions
Serial Clcok (SCL)
The SCL input is used to clock all data into and out
of the device.
SerialL Data (SDA)
SDA is a bidirection pin used to transfer data or
security bit into and out of the device. It is an open
drain output and may be wire-ORed with any
number of open drain or open collector outputs.
Thus, the SDA bus requires a pull-up resistor to Vcc
(typical 4.7KΩ for 100KHz, 1KΩ for 400KHz).
Device Address Inputs (A0, A1, A2)
The following table (Table A) shows the active pins
across the AM24LCXX device family.
TABLE A
Device A0 A1 A2
AM24LC02 ADR ADR ADR
AM24LC04 XP ADR ADR
AM24LC08 XP XP ADR
AM24LC16 XP XP XP
ADR indicates the device address pin.
XP indicates that device address pin does not care
but refers to an internal PAGE BLOCK memory
segment.
Write Protection (WP)
If WP is connected to Vcc, PROGRAM operation
onto the whole memory will not be executed. READ
operations are possible. If WP is connected to Vss,
normal memory operation is enabled, READ/WRITE
over the entire memory is possible.
Functional Description
Applications
ATC’s electrically erasable programmable read only
memories (EEPROMs) offer valuable security
features including write protect function, two write
modes, three read modes, and a wide variety of
memory size. Typical applications for the I2C bus
and AM24LCXX memories include
SANs(small-area-networks), stereos, televisions,
automobiles and other scaled-down systems that do
not require tremendous speeds but instead cost
efficiency and design simplicity.
Endurance And Data Retention
The AM24LC02 is designed for applications
requiring up to 1KK programming cycles (BYTE
WRITE and PAGE WRITE). It provides 40 years of
secure data retention without power.
Device Operation
The AM24LC02 device supports a bidirectional bus
oriented protocol. The protocol defines any device
that sends data onto the bus as a transmitter and
the receiving device as the receiver. The device
controlling the transfer is the master and the device
being controlled is the slave. The master will always
initiate data transfers and provide the clock for both
transmit and receive operations. Therefore, the
AM24LC02 is considered a slave in all applications.
Clock and Data Conventions
Data states on the SDA line can be changed only
during SCL LOW. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. (Shown in Figures 1 and 2)
Start Condition
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded with a START
condition. (Shown in Figure 2)
Stop Condition
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition.
All operations must be ended with a STOP condition.
(Shown in Figure 2)
2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM AM24LC02
Anachip Corp.
www.anachip.com.tw Rev. A1 Oct 20, 2003
6/12
ATC
Functional Description (Continued)
Acknowledge
Each receiving device, when addressed, is obliged
to generate an acknowledge after the reception of
each byte. The master device must generate an
extra clock pulse which is associated with this
acknowledge bit. The device that acknowledges,
has to pull down the SDA line during the
acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by
not generating an acknowledge bit on the last byte
that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable
the master to generate the STOP condition. (Shown
in Figure 3)
Devices Addressing
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit
device code (1010) for the AM24LC02, 3-bit device
address (A2 A1 A0) and 1-bit value indicating the
read or write mode. All I2C EEPROMs use and
internal protocol that defines a PAGE BLOCK size of
16K bits. The AM24LC02 contains one 2K-bits
PAGE BLOCK, and the device address bits A0, A1
and A2 are used for determinating which device will
be proceeded in. The eighth bit of slave address
determines if the master device wants to read or
write to the AM24LC02 (Refer to table B).
The AM24LC02 monitors the bus for its
corresponding slave address all the time. It
generates an acknowledge bit if the slave address
was true and it is not in a programming mode.
Operation Control Code Chip Select R/W
Read
Write
1010
1010
A2 A1
A0
A2 A1
A0
1
0
Table B
A0, A1, A2 is used to access the AM24LC02.
Write Operations
Byte Write
Following the start signal from the master, the slave
address is placed onto the bus by the master
transmitter. This indicates to the addressed slave
receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte
transmitted by the master is the word address and
will be written into the address pointer of the
AM24LC02. After receiving another acknowledge
signal from the AM24LC02 the master device will
transmit the data word to be written into the
addressed memory location. The AM24LC02
acknowledges again and the master generates a
stop condition. This initiates the internal write cycle,
and during this period the AM24LC02 will not
generate acknowledge signals. (Shown in Figure 4)
Page Write
The write control byte, word address and the first
data byte are transmitted to the AM24LC02 in the
same way as in a byte write. But instead of
generating a stop condition the master transmit up
to 8 data bytes to the AM24LC02 which are
temporarily stored in the on-chip page buffer and will
be written into the memory after the master has
transmitted a stop condition. If the master transmits
more than 8 bytes prior to generating the stop
condition, the address counter will roll over and the
previously received data will be overwritten. As with
the byte write operation, once the stop condition is
received an internal write cycle will begin. (Shown in
Figure 5)
Acknowledge Polling
Since the device will not acknowledge during a write
cycle , this can be used to determine when the cycle
is complete (this feature can be used to maximize
bus throughout). Once the stop condition for a write
command has been issued from the master, the
device initiates the internally timed write cycle. ACK
polling can be initiated immediately. This involves
the master sending a start condition followed by the
control byte for a write command (R/W = 0). If the
device is still busy with the write cycle , then no ACK
will returned. If the cycle is complete then the device
will return the ACK and the master can then proceed
with the next read or write commands.
2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM AM24LC02
Anachip Corp.
www.anachip.com.tw Rev. A1 Oct 20, 2003
2/12
ATC
Write Operations (Continued)
Write Protection
Programming will not take place if the WP pin of the
AM24LC02 is connected to Vcc. The AM24LC02 will
accept slave and byte addresses; but if the memory
accessed is write protected by the WP pin, the
AM24LC02 will not generate an acknowledge after
the first byte of data has been received, and thus the
programming cycle will not be started when the stop
condition is asserted.
Read Operations
Read operations are initiated in the same way as
write operations with the exception that the R/W bit
of the slave address is set to one. There are three
basic types of read operations: current address read,
random read, and sequential read.
Current Address Read
The AM24LC02 contains an address counter that
maintains the address of the last accessed word,
internally incremented by one. Therefore if the
previous access (either a read or write operation )
was to address n, the next current address read
operation would access data from address n + 1.
Upon receipt of the slave address with R/W bit set to
one, the AM24LC02 issues an acknowledge and
transmits the eight bit data word . The master will
not acknowledge the transfer but does generate a
stop condition and the AM24LC02 discontinues
transmission. (Shown in Figure 6)
Random Read
Random read operations allow the master to access
any memory location in a random manner. To
perform this type of read operation, first the word
address must be set. This is done by sending the
word address to the AM24LC02 as part of a write
operation. After the word address is sent, the master
generates a start condition following the
acknowledge. This terminates the write operation,
but not before the internal address pointer is set.
Then the master issues the control byte again but
with R/W bit set to a one. The AM24LC02 will then
issue an acknowledge and transmit the eight bit data
word. The master will not acknowledge the transfer
but does generate a stop condition and the
AM24LC02 discontinues transmission. (Shown in
Figure 7)
Sequential Read
Sequential read is initiated in the same way as a
random read except that after the AM24LC02
transmits the first data byte, the master issues an
acknowledge as opposed to a stop condition in a
random read. This directs the AM24LC02 to transmit
the next sequentially addressed 8 bit word (Shown
in Figure 8). To provide sequential read the
AM24LC02 contains an internal address pointer
which is incremented by one at the completion of
each operation.
Noise Protection
The SCL and SDA inputs have filter circuits which
suppress noise spikes to assure proper device
operation even on a noisy bus and to avert data
alteration.
2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM AM24LC02
Anachip Corp.
www.anachip.com.tw Rev. A1 Oct 20, 2003
7/12
ATC
Timing Diagram
Bus Timing
Figure 3. Acknowledge Response from Receiver
81 9
ACKNOWLEDGE
START
SCL FROM MASTER
DATA OUTPUT FROM
TRANSMITTER
DATA OUTPUT FROM
RECEIVER
SCL
Figure 1. Data Validity
SDA
IN
Tf
Thd:Sta
Thd:Dat
Tsu:Dat
Tbuf
Tlow
Thigh
Tlow
Tr
Tsu:StaTsu:Sta
SDA
OUT
Tdh
Taa
DATA STABLE DATA
CHANGE
SDA
SCL
Figure 2. Definition of Start and Stop
BITSTOPSTART BIT
SDA
SCL
2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM AM24LC02
Anachip Corp.
www.anachip.com.tw Rev. A1 Oct 20, 2003
8/12
ATC
DATA
P
A
C
K
Figure 6. Current Address Read for Data
s
BUS ACTIVITY
SLAVE
SDA
LINE
BUS ACTIVITY
MASTER
SLAVE
ADDRESS STOP
START
S
A
C
KDATA n
A
C
K
DATA n+1
A
C
K
DATA n+x
P
Figure 8. Sequential Read for Data
BUS ACTIVITY
SLAVE
SDA
LINE
BUS ACTIVITY
MASTER
SLAVE
ADDRESS
START
STOP
PSS
A
C
K
A
C
K
A
C
KDATA n
Figure 7. Random Read for Data
BYTE
ADDRESS n
SLAVE
ADDRESS STOP
START SLAVE
ADDRESS
START
BUS ACTIVITY
SLAVE
SDA
LINE
BUS ACTIVITY
MASTER
Figure 5. Page Write for Data
BUS ACTIVITY
SLAVE
SDA
LINE
BUS ACTIVITY
MASTER
DATA n
BYTE
ADDRESS n
SLAVE
ADDRESS STOP
START DATA n+7
A
C
K
A
C
K
A
C
K
A
C
K
S P
DATA n
BYTE
ADDRESS
SLAVE
ADDRESS
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
SLAVE
SDA
LINE
BUS ACTIVITY
MASTER
Figure 4. Byte Write for Data
S P
STOP
START
No
A
C
K
A
C
K
No
A
C
K
No
2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM AM24LC02
Anachip Corp.
www.anachip.com.tw Rev. A1 Oct 20, 2003
9/12
ATC
Package Information
(1)Package Type: PDIP-8L
E1
D
7(4X)
AL
A2A1
B2
B1
B
e
S
15 (4X)
E
C
eB
E-PIN O0.118 inch
PIN #1 INDENT O0.025 DEEP 0.006-0.008 inch
Dimensions in millimeters Dimensions in inches
Symbol Min. Nom. Max. Min. Nom. Max.
A - -
5.33 - - 0.210
A1 0.38 - - 0.015 - -
A2 3.1 3.30 3.5 0.122 0.130 0.138
B 0.36 0.46 0.56 0.014 0.018 0.022
B1 1.4 1.52 1.65 0.055 0.060 0.065
B2 0.81 0.99 1.14 0.032 0.039 0.045
C 0.20 0.25 0.36 0.008 0.010 0.014
D 9.02 9.27 9.53 0.355 0.365 0.375
E 7.62 7.94 8.26 0.300 0.313 0.325
E1 6.15 6.35 6.55 0.242 0.250 0.258
e - 2.54 - - 0.100 -
L 2.92 3.3 3.81 0.115 0.130 0.150
eB 8.38 8.89 9.40 0.330 0.350 0.370
S 0.71 0.84 0.97 0.028 0.033 0.038
2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM AM24LC02
Anachip Corp.
www.anachip.com.tw Rev. A1 Oct 20, 2003
10/12
ATC
(2)Package Type: SOP-8L
VIEW "A"
L
C
VIEW "A"
H
E
A
A2
A1
B
e
D
7(4X) 0.015x45 7(4X)
y
Dimensions In Millimeters Dimensions In Inches
Symbol Min. Nom. Max. Min. Nom. Max.
A 1.40 1.60 1.75 0.055 0.063 0.069
A1 0.10 - 0.25 0.040 - 0.100
A2 1.30 1.45 1.50 0.051 0.057 0.059
B 0.33 0.41 0.51 0.013 0.016 0.020
C 0.19 0.20 0.25 0.0075 0.008 0.010
D 4.80 5.05 5.30 0.189 0.199 0.209
E 3.70 3.90 4.10 0.146 0.154 0.161
e - 1.27 - - 0.050 -
H 5.79 5.99 6.20 0.228 0.236 0.244
L 0.38 0.71 1.27 0.015 0.028 0.050
y - - 0.10 - - 0.004
θ 0O - 8O 0
O - 8O
2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM AM24LC02
Anachip Corp.
www.anachip.com.tw Rev. A1 Oct 20, 2003
11/12
ATC
(3)Package Type: TSSOP-8L
A
E
E1
b
y
e
C
DETAIL A
DETAIL A
L 1
L
E1 L1
A2
A1
D
PIN 1 INDICATOR
ψ
0.70 mm
SURFACE POLISHED
Dimensions In Millimeters Dimensions In Inches
Symbol Min. Nom. Max. Min. Nom. Max.
A 1.05 1.10 1.20 0.041 0.043 0.047
A1 0.05 0.10 0.15 0.002 0.004 0.006
A2 - 1.00 1.05 - 0.039 0.041
b 0.20 0.25 0.28 0.008 0.01 0.011
C - 0.13 - - 0.005 -
D 2.90 3.05 3.10 0.114 0.12 0.122
E 6.20 6.40 6.60 0.244 0.252 0.26
E1 4.30 4.40 4.50 0.169 0.173 0.177
e - 0.65 - - 0.026 -
L 0.50 0.60 0.70 0.02 0.024 0.028
L1 0.90 1.00 1.10 0.035 0.039 0.043
y - - 0.10 - - 0.004
θ 0O 4
O 8
O 0
O 4
O 8
O
2-Wire Serial 2K-bits (256 x 8) CMOS Electrically Erasable PROM AM24LC02
Anachip Corp.
www.anachip.com.tw Rev. A1 Oct 20, 2003
12/12
ATC
Marking Information
(1) PDIP-8L & SOP-8L
ATC
24LC02 X
Part Number & grade
Logo
ID code: internal
Year:
Top view
"02" = 2002
"01" = 2001
XX XX X
Nth week: 01~52
)C125~40(V
)C85~40(I
)C70~0(BlankX
o
o
o
+-=
+-=
+=
(2) TSSOP-8L
ATC
24LC02 X
Part Number & Temp.grade
Logo
ID code: internal
Year:
Top view
"02" = 2002
"01" = 2001
XX XX X
Nth week: 01~52
)C125~40(V
)C85~40(I
)C70~0(BlankX
o
o
o
+-=
+-=
+=
