74LV595D,118 - NXP Semiconductors / Philips Semiconductors

1. General description

The 74LV595 is an 8 stage serial shift register with a storage register and 3-state outputs.

Both the shift and storage register have separate clocks. It is a low-voltage Si-gate CMOS

device and is pin and functionally compatible with the 74HC595 and 74HCT595.

Data is shifted on the positive-going transitions of the SHCP input. The data in the shift

input. If both clocks are connected together, the shift register will always be one clock

pulse ahead of the storage register.

The shift register has a serial input (DS) and a serial output (Q7S) for cascading the

device. It is also provided with an asynchronous reset input MR (active LOW) for all 8 shift

storage register appears at the output whenever the output enable input (OE) is LOW.

2. Features

nOptimized for low voltage applications: 1.0 V to 3.6 V

nAccepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

nTypical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C

nTypical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and

Tamb =25°C

nSpeciﬁed from −40 °Cto+85°C and from −40 °C to +125 °C

nHas a shift register with direct clear

nMultiple package options

nOutput capability:

uParallel outputs; bus driver

userial output; standard

nESD protection:

uHBM JESD22-A114E exceeds 2000 V

uMM JESD22-A115-A exceeds 200 V

3. Applications

nSerial-to-parallel data conversion

nRemote control holding register

74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

Rev. 03 — 21 April 2009 Product data sheet

Product data sheet Rev. 03 — 21 April 2009 2 of 20

NXP Semiconductors 74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

4. Ordering information

5. Functional diagram

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74LV595N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4

74LV595D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body

width 3.9 mm SOT109-1

74LV595DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads;

body width 5.3 mm SOT338-1

74LV595PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm SOT403-1

Fig 1. Logic symbol Fig 2. Logic symbol (IEEE/IEC)

OEMR

1310

11 12

mna552

Q7S

STCP

SHCP

mna553

1D 2D

C1/

13 EN3

SRG8

Fig 3. Functional diagram

mna554

3-STATE OUTPUTS

8-BIT STORAGE REGISTER

8-STAGE SHIFT REGISTER

Q0Q1Q2Q3Q4Q5Q6Q7

Q7S

151234567

SHCP

STCP

Product data sheet Rev. 03 — 21 April 2009 3 of 20

NXP Semiconductors 74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

Fig 4. Logic diagram

STAGE 0 STAGES 1 TO 6 STAGE 7

FF0

LATCH

FF7

LATCH

mna555

Q1Q2Q3Q4Q5Q6Q7

Q7S

STCP

SHCP

Fig 5. Timing diagram

SHCP

STCP

Q7S

Z-state

mna556

Product data sheet Rev. 03 — 21 April 2009 4 of 20

NXP Semiconductors 74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 6. Pin conﬁguration DIP16, SO16 Fig 7. Pin conﬁguration SSOP16, TSSOP16

74LV595

Q1 VCC

Q2 Q0

Q3 DS

Q4 OE

Q5 STCP

Q6 SHCP

Q7 MR

GND Q7S

001aaj970

15 74LV595

Q1 VCC

Q2 Q0

Q3 DS

Q4 OE

Q5 STCP

Q6 SHCP

Q7 MR

GND Q7S

mla001

Table 2. Pin description

Symbol Pin Description

Q0 to Q7 15, 1, 2, 3, 4, 5, 6, 7 parallel data output

GND 8 ground (0 V)

Q7S 9 serial data output

MR 10 master reset (active LOW)

SHCP 11 shift register clock input

STCP 12 storage register clock input

OE 13 output enable input (active LOW)

DS 14 serial data input

VCC 16 supply voltage

Product data sheet Rev. 03 — 21 April 2009 5 of 20

NXP Semiconductors 74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

7. Functional description

[1] H = HIGH voltage state; L = LOW voltage state; ↑= LOW-to-HIGH transition; X = don’t care; NC = no change;

Z = high-impedance OFF-state.

8. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For DIP16 packages: above 70 °C the value of Ptot derates linearly with 12 mW/K.

For SO16 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.

For (T)SSOP16 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.

Table 3. Function table[1]

Input Output Function

SHCP STCP OE MR DS Q7S Qn

X X L L X L NC a LOW-state on MR only affects the shift register

X↑L L X L L empty shift register loaded into storage register

X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state

↑X L H H Q6S NC logic HIGH-state shifted into shift register stage 0. Contents of all

shift register stages shifted through, e.g. previous state of stage 6

(internal Q6S) appears on the serial output (Q7S).

X↑L H X NC QnS contents of shift register stages (internal QnS) are transferred to

the storage register and parallel output stages

↑↑L H X Q6S QnS contents of shift register shifted through; previous contents of the

shift register is transferred to the storage register and the parallel

output stages

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage −0.5 +4.6 V

IIK input clamping current VI<−0.5 V or VI > +0.5 V - ±20 mA

IOK output clamping current VI<−0.5 V or VI > +0.5 V - ±50 mA

IOoutput current −0.5 V < VO<V

CC + 0.5 V -

standard driver outputs 25 mA

bus driver outputs 35 mA

ICC supply current standard driver outputs 50 mA

bus driver outputs 70 mA

IGND ground current standard driver outputs −50 mA

bus driver outputs −70 mA

Tstg storage temperature −65 +150 °C

Ptot total power dissipation Tamb =−40 °C to +125 °C[2]

DIP16 - 750 mW

SO16, SSOP16, TSSOP16 - 500 mW

Product data sheet Rev. 03 — 21 April 2009 6 of 20

NXP Semiconductors 74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

9. Recommended operating conditions

10. Static characteristics

Table 5. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ Max Unit

VCC supply voltage 1.0 3.3 3.6 V

VIinput voltage 0 - VCC V

VOoutput voltage 0 - VCC V

Tamb ambient temperature −40 - +125 °C

∆t/∆V input transition rise and fall rate VCC = 1.0 V to 2.0 V - - 500 ns/V

VCC = 2.0 V to 2.7 V - - 200 ns/V

VCC = 2.7 V to 3.6 V - - 100 ns/V

Table 6. Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ[1] Max Min Max

VIH HIGH-level

input voltage VCC = 1.2 V 0.9 - - 0.9 - V

VCC = 2.0 V 1.4 - - 1.4 - V

VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V

VIL LOW-level

input voltage VCC = 1.2 V - - 0.3 - 0.3 V

VCC = 2.0 V - - 0.6 - 0.6 V

VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V

VOH HIGH-level

output voltage all outputs; VI=V

IH or VIL;

IO=−100 µA;

VCC = 1.2 V - 1.2 - - - V

VCC = 2.0 V 1.8 2.0 - 1.8 - V

VCC = 2.7 V 2.5 2.7 - 2.5 - V

VCC = 3.0 V 2.8 3.0 - 2.8 - V

standard outputs;

VI=V

IH or VIL; IO=−6 mA;

VCC = 3.0 V 2.4 2.82 - 2.2 - V

bus outputs; VI=V

IH or VIL;

IO=−8 mA;

VCC = 3.0 V 2.4 2.82 - 2.2 - V

Product data sheet Rev. 03 — 21 April 2009 7 of 20

NXP Semiconductors 74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb =25°C.

VOL LOW-level

output voltage all outputs; VI=V

IH or VIL;

IO= 100 µA;

VCC = 1.2 V - 0 - - - V

VCC = 2.0 V - 0 0.2 - 0.2 V

VCC = 2.7 V - 0 0.2 - 0.2 V

VCC = 3.0 V - 0 0.2 - 0.2 V

standard driver outputs

VCC = 3.0 V; IO=6mA - 0.25 0.4 - 0.5 V

bus driver outputs

VCC = 3.0 V; IO=8mA - 0.20 0.4 - 0.5 V

IIinput leakage

current VCC = 3.6 V;

VI= 5.5 Vor GND - - 1.0 - 1.0 µA

IOZ OFF-state

output current VI=V

IH or VIL;

VO=VCC or GND;

VCC = 3.6 V

--5-10µA

ICC supply current VCC = 3.6 V;

VI=V

CC or GND; IO=0A - - 20 - 160 µA

∆ICC additional supply

current per input pin;

VCC = 2.7 V to 3.6 V;

VI=V

CC −0.6 V

- - 500 - 850 µA

CIinput capacitance - 3.5 - - - pF

Table 6. Static characteristics

…continued

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ[1] Max Min Max

Product data sheet Rev. 03 — 21 April 2009 8 of 20

NXP Semiconductors 74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

11. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.

Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ[1] Max Min Max

tpd propagation delay SHCP to Q7S; see Figure 8 [2]

VCC = 1.2 V - 95 - - - ns

VCC = 2.0 V - 32 61 - 75 ns

VCC = 2.7 V - 24 45 - 55 ns

VCC = 3.3 V; CL = 15 pF - 15 - - - ns

VCC = 3.0 V to 3.6 V [3] - 18 36 - 44 ns

STCP to Qn; see Figure 9 [2]

VCC = 1.2 V - 100 - - - ns

VCC = 2.0 V - 34 65 - 77 ns

VCC = 2.7 V - 25 48 - 56 ns

VCC = 3.3 V; CL = 15 pF - 16 - - - ns

VCC = 3.0 V to 3.6 V [3] - 19 38 - 45 ns

MR to Q7S; see Figure 11

VCC = 1.2 V - 85 - - - ns

VCC = 2.0 V - 29 56 - 66 ns

VCC = 2.7 V - 21 41 - 49 ns

VCC = 3.3 V; CL = 15 pF - 14 - - - ns

VCC = 3.0 V to 3.6 V [3] - 16 33 - 33 ns

ten enable time OE to Qn; see Figure 12 [4]

VCC = 1.2 V - 85 - - - ns

VCC = 2.0 V - 29 56 - 66 ns

VCC = 2.7 V - 21 41 - 49 ns

VCC = 3.0 V to 3.6 V - 16 33 - 39 ns

tdis disable time OE to Qn; see Figure 12 [5]

VCC = 1.2 V - 65 - - - ns

VCC = 2.0 V - 24 40 - 49 ns

VCC = 2.7 V - 18 32 - 37 ns

VCC = 3.0 V to 3.6 V [3] - 14 26 - 30 ns

Product data sheet Rev. 03 — 21 April 2009 9 of 20

NXP Semiconductors 74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

tWpulse width SHCP, HIGH or LOW;

see Figure 8

VCC = 2.0 V 34 10 - 41 - ns

VCC = 2.7 V 25 8 - 30 - ns

VCC = 3.0 V to 3.6 V [3] 20 6 - 24 - ns

STCP, HIGH or LOW;

see Figure 9

VCC = 2.0 V 34 7 - 41 - ns

VCC = 2.7 V 25 5 - 30 - ns

VCC = 3.0 V to 3.6 V [3] 20 4 - 24 - ns

MR LOW; see Figure 11

VCC = 2.0 V 34 10 - 41 - ns

VCC = 2.7 V 25 8 - 30 - ns

VCC = 3.0 V to 3.6 V [3] 20 6 - 24 - ns

tsu set-up time DS to SHCP; see Figure 10

VCC = 1.2 V - 40 - - - ns

VCC = 2.0 V 26 14 - 31 - ns

VCC = 2.7 V 19 10 - 23 - ns

VCC = 3.0 V to 3.6 V [3] 15 8 - 18 - ns

SHCP to STCP; see Figure 9

VCC = 1.2 V - 40 - - - ns

VCC = 2.0 V 26 14 - 31 - ns

VCC = 2.7 V 19 10 - 23 - ns

VCC = 3.0 V to 3.6 V [3] 15 8 - 18 - ns

thhold time DS to SHCP; see Figure 10

VCC = 1.2 V - −10.0 - - - ns

VCC = 2.0 V 5.0 −4.0 - 5.0 - ns

VCC = 2.7 V 5.0 −3.0 - 5.0 - ns

VCC = 3.0 V to 3.6 V 5.0 −2.0 - 5.0 - ns

trec recovery time MR to SHCP; see Figure 11

VCC = 1.2 V - −35 - - - ns

VCC = 2.0 V 5.0 −12.0 - 5.0 - ns

VCC = 2.7 V 5.0 −9.0 - 5.0 - ns

VCC = 3.0 V to 3.6 V [3] 5.0 −7.0 - 5.0 - ns

Table 7. Dynamic characteristics

…continued

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.

Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ[1] Max Min Max

Product data sheet Rev. 03 — 21 April 2009 10 of 20

NXP Semiconductors 74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

[1] Typical values are measured at Tamb =25°C.

[2] tpd is the same as tPLH and tPHL.

[3] Typical value measured at VCC = 3.3 V.

[4] ten is the same as tPZH and tPZL.

[5] tdis is the same as tPHZ and tPLZ.

[6] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

[7] CPD is used to determine the dynamic power dissipation (PDin µW).

PD=C

PD ×VCC2×fi×N+∑(CL×VCC2×fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

CL= output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

∑(CL×VCC2×fo) = sum of outputs.

12. Waveforms

fmax maximum

frequency SHCP or STCP; see Figure 8

and Figure 9

VCC = 2.0 V 14.0 40.0 - 12 - MHz

VCC = 2.7 V 19.0 58.0 - 16 - MHz

VCC = 3.3 V; CL = 15 pF - 77 - - - MHz

VCC = 3.0 V to 3.6 V [3] 24.0 70.0 - 20 - MHz

CPD power dissipation

capacitance VI = GND to VCC; VCC = 3.0 V [7] - 115 - - - pF

Table 7. Dynamic characteristics

…continued

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.

Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ[1] Max Min Max

Measurement points are given in Table 8.

VOL and VOH are typical output voltage drops that occur with the output load.

Fig 8. The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and

maximum shift clock frequency

mna557

SHCP input

Q7S output

tPLH tPHL

1/fmax

VOH

GND

VOL

Product data sheet Rev. 03 — 21 April 2009 11 of 20

NXP Semiconductors 74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

Measurement points are given in Table 8.

VOL and VOH are typical output voltage drops that occur with the output load.

Fig 9. The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width

and the shift clock to storage clock set-up time

mna558

STCP input

Qn output

tPLH tPHL

tsu 1/fmax

VOH

GND

VOL

SHCP input

GND

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

VOL and VOH are typical output voltage drops that occur with the output load.

Fig 10. The data set-up and hold times for the serial data input (DS)

mna560

GND

tsu th

tsu

VOH

VOL

Q7S output

SHCP input

DS input

Product data sheet Rev. 03 — 21 April 2009 12 of 20

NXP Semiconductors 74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

Measurement points are given in Table 8.

VOL and VOH are typical output voltage drops that occur with the output load.

Fig 11. The master reset (MR) pulse width, the master reset to serial data output (Q7S) propagation delays and

the master reset to shift clock (SHCP) recovery time

mna561

MR input

SHCP input

Q7S output

tPHL

tWtrec

VOH

VOL

GND

Measurement points are given in Table 8.

VOL and VOH are typical output voltage drops that occur with the output load.

Fig 12. Enable and disable times

001aae821

tPLZ

tPHZ

outputs

disabled outputs

enabled

outputs

enabled

output

LOW-to-OFF

OFF-to-LOW

output

HIGH-to-OFF

OFF-to-HIGH

OE input

VCC

VOL

VOH

GND

tPZL

tPZH

Table 8. Measurement points

Supply voltage Input Output

VCC VMVMVXVY

VCC < 2.7 V 0.5VCC 0.5VCC VOL +0.1VCC VOH −0.1VCC

VCC ≥2.7 V 1.5 V 1.5 V VOL +0.3 V VOH −0.3 V

Product data sheet Rev. 03 — 21 April 2009 13 of 20

NXP Semiconductors 74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

Test data is given in Table 9.

Deﬁnitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Fig 13. Load circuit for measuring switching times

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

001aae331

VEXT

VCC

VIVO

DUT

Table 9. Test data

Supply voltage VCC Input Load VEXT

VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH

< 2.7 V VCC ≤ 2.5 ns 50 pF 1 kΩopen 2VCC GND

2.7 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 1 kΩopen 2VCC GND

Product data sheet Rev. 03 — 21 April 2009 14 of 20

NXP Semiconductors 74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

13. Package outline

Fig 14. Package outline SOT38-4; (DIP16)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT38-4 95-01-14

03-02-13

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

UNIT A

max. 12 b1(1) (1) (1)

b2cD E e M Z

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min. A

max. bmax.

1.73

1.30 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 0.764.2 0.51 3.2

inches 0.068

0.051 0.021

0.015 0.014

0.009

1.25

0.85

0.049

0.033 0.77

0.73 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.030.17 0.02 0.13

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

Product data sheet Rev. 03 — 21 April 2009 15 of 20

NXP Semiconductors 74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

Fig 15. Package outline SOT109-1 (SO16)

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 10.0

9.8 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.39

0.38 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.020 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 03 — 21 April 2009 16 of 20

NXP Semiconductors 74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

Fig 16. package outline (SOT338-1); (SSOP16)

UNIT A1A2A3bpcD

(1) E(1) eH

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.25 0.38

0.25 0.20

0.09 6.4

6.0 5.4

5.2 0.65 1.25

7.9

7.6 1.03

0.63 0.9

0.7 1.00

0.55 8

0.130.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT338-1 99-12-27

03-02-19

(1)

vMA

16 9

detail X

(A )

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1

max.

Product data sheet Rev. 03 — 21 April 2009 17 of 20

NXP Semiconductors 74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

Fig 17. Package outline SOT403-1 (TSSOP16)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.40

0.06 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT403-1 MO-153 99-12-27

03-02-18

0.25

16 9

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

max.

1.1

pin 1 index

Product data sheet Rev. 03 — 21 April 2009 18 of 20

NXP Semiconductors 74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

14. Abbreviations

15. Revision history

Table 10. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74LV595_3 20090421 Product data sheet - 74LV595_2

Modiﬁcations: •The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP

Semiconductors.

•Legal texts have been adapted to the new company name where appropriate.

74LV595_2 980402 Product data sheet - 74LV595_1

74LV595_1 970606 Product data sheet - -

Product data sheet Rev. 03 — 21 April 2009 19 of 20

NXP Semiconductors 74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 21 April 2009

Document identifier: 74LV595_3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Functional description . . . . . . . . . . . . . . . . . . . 5

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

9 Recommended operating conditions. . . . . . . . 6

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8

12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19

16.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 19

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19

17 Contact information. . . . . . . . . . . . . . . . . . . . . 19

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20