Serial RapidIO Physical Layer Interface February 2004 IP Data Sheet Features Error Detection Supports High Speed 1x Mode (up to 2.5 Gbps) Packet/Control Symbol Assembly and De-assembly 8B/10B Encoding and Decoding Simple User Interface for Easy Integration into User Logic Clock and Data Recovery (CDR) Targets ORT82G5/ORT42G5 FPSC Lane Synchronization CRC Generation and Checking Block Diagram Figure 1. Serial RapidIO Physical Layer Block Diagram RX Transmit Ack Ctrl RX USER Interface TX Ctrl Symb RX Symbol Decoder RX Packet/ Control DisAssy RX USR I/F 8 64 RX SERDES Interface Block 4 RD 32 RD_N RX Serial RapidIO I/F RX CRC Checker RX Receive Pkt Ack Ctrl PMI Interface Phy Layer Management I/F Control TX Pkt Data Embedded SERDES on ORT82G5/ ORT42G5 RECEIVE TRANSMIT TX Symbol Generator TX USER Interface TX USR I/F TX Packet/ Control Assy 8 64 TX SERDES Interface Block 4 TD 32 TD_N TX Serial RapidIO I/F TX CRC Generator Soft IP Core FPSC Device Unshaded portions indicate blocks running in User System Clock domain Shaded portion indicates blocks running in Management I/F Clock domain (c) 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. The product described herein is subject to continuing development, and applicable specifications and information are subject to change without notice. Such specifications and information are provided in good faith; actual performance is not guaranteed, as it is dependent on many factors, including the user's system design. www.latticesemi.com 1 ip1028_01 Serial RapidIO Physical Layer Interface Lattice Semiconductor General Description The Serial RapidIO core supports the physical layer specification as defined in the RapidIO Specification Rev 1.2. The Serial RapidIO Physical Layer defines a protocol for packet delivery between Serial RapidIO devices and other devices, including packet transmission, flow control, error management and link maintenance protocols. The core supports one-lane high speed (1x mode) running at 1.0, 2.0 Gbps or a maximum of 2.5 Gbps. This Serial RapidIO core is optimized to support ORT82G5/ORT42G5 FPSCs. For more information on Lattice products, refer to the Lattice web site at www.latticesemi.com. Functional Description Figure 1 shows the block diagram of the Serial RapidIO Physical Layer core. Transmit data presented at the TX User Interface is first passed through a CRC (Cyclic Redundancy Code) generation block and then to the TX Packet/Control assembly block that assembles the packets and control symbols. The control symbols for this block are received from the TX Symbol Generator. The assembled data which contains both packet and control symbols are sent to the TX SERDES Interface block. The incoming data from the RX Serial RapidIO Interface are processed by the RX SERDES Interface block. The data is then passed to the RX Packet and Control Disassembly block. This block separates the data packets from the control symbols. The data packets are sent to the RX CRC Checker and the control symbols are sent to RX Symbol Decoder. The decoded control symbols are passed to the RX Transmit Ack Ctrl and RX Receive Packet Ack Ctrl blocks, which takes the appropriate actions. Finally the data from the RX CRC Checker is sent out to the user logic through the RX User Interface. Embedded SERDES on Lattice ORT82G5/ORT42G5 FPSC device: Several RapidIO processes are performed in the device's embedded SERDES such as clock and data recovery, 8b/10b encoding and decoding, and serial-toparallel conversion or vice versa. PHY Layer Management Interface (PMI) Block This block contains the Command and Status Registers (CSR) that allow the user to configure and read the capabilities, configuration and status of the input and output ports. Transmit Physical Layer Block TX User Interface The TX User Interface generates all the signals necessary to interface to user logic or the Logical and Transport layers of the RapidIO stack. The main function of this block is to indicate that the TX PHY is ready to receive data. It also controls the discard signal tx_rios_discard, which is used to discard a packet being sent to the core. The TX User Interface consists of two types of interface: TX User Control Interface and TX Generic FIFO Bridge Interface. The TX Generic FIFO Bridge Interface is a standard FIFO interface used to manage the data flow coming from the user side (signals beginning with "sine_tx_"). TX CRC Generator This block generates the 16-bit CRC using the polynomial X16+X12+X5+1. The CRC is generated over all of a packet header and the entire data payload, except the first six bits of the added physical layer fields (which are treated as logical 0s) as shown below. The initial value of the CRC is 0xFFFF, or all logic 1s. For the CRC calculation, the first six bits (ACK ID field and first reserved field) are assumed to be logic zero. This structure allows the ACK ID to be changed on a link-by-link basis as the packet is transported, without requiring the CRC to be recomputed for each link. TX Symbol Generator This block generates the appropriate control symbols based on the control symbol generation request and writes them into the Symbol Queue FIFO. 2 Serial RapidIO Physical Layer Interface Lattice Semiconductor TX Packet/Control Assembly The TX Packet/Control Assembly block gets packet data from the user logic and then appends physical layer header information within the relevant physical fields before sending the data to the TX SERDES Interface Block. It also adds control symbols received from the TX Symbol Generator block in between packets. This block also generates and adds the 5-bit control symbol CRC using the polynomial X5+X4+X2+1. TX SERDES Interface Block The TX SERDES Interface Block connects this soft IP core to the embedded TX SERDES section of a Lattice ORT82G5/ORT42G5 FPSC device. This Interface Block generates the code-group sequences for transmission when neither data nor control symbols are being transmitted. Receive Physical Layer Block RX SERDES Interface Block The RX SERDES Interface Block connects this soft IP core to the embedded RX SERDES section of a Lattice ORT82G5/ORT42G5 FPSC device. This Interface Block contains a retimer, data converter, and initialization state machine. Further details can be found in the User's Guide for this IP core. RX Packet/Control Disassembly The RX Packet and Control Disassembly block separates the data packets and control symbols from the received data. This block also has the Control Symbol CRC Checker which checks the 5-bit CRC present in the control symbols received. If any errors are found on the control symbols, this information is passed to the RX Transmit Ack Ctrl block. RX Symbol Decoder This block stores the ACK control symbols that are to be received into a synchronous FIFO. Since the data width is 64 bits, and each control symbol 32 bits wide (24 bits data + 8 bits /SC/ special character), it can receive up to two control symbols on every clock. Hence the FIFO stores up to two control symbols received in one location. Subsequently, this block decodes the control symbol data. The decoded signals contain information on the type of control symbol that was decoded. RX Transmit ACK Control The RX Transmit ACK control block keeps track of the acknowledgement control symbols for packets transmitted. This is implemented by maintaining an ACK received queue. This block also contains the Retry Recovery process and Error Recovery process. RX Receive Packet ACK Control The RX Receive Packet ACK Control block generates the ACK control symbols for the packets received. When this block detects an error on a packet (CRC error/unexpected ACK ID value/over running the maximum data payload) it immediately transitions into an input error-stopped state and silently discards all new packets until it receives a restart-from-error control symbol from the sender. RX CRC Checker The RX CRC Checker generates a separate CRC for each data packet and compares it to the appended CRC transmitted with each packet, to determine any errors. RX User Interface The RX User Interface generates all the control signals necessary to interface to the RX user logic or the Logical and Transport layers of the RapidIO stack. This block generates the signals indicating that the RX PHY is ready to send data. This block also controls the discard signal, which is used to discard a packet being sent to the user logic if packet errors are detected. The RX User Interface consists of two types of interface: RX User Control Interface and RX Generic FIFO Bridge Interface. The RX Generic FIFO Bridge Interface is a standard FIFO interface used to manage the data flow going to the user side (signals beginning with "sine_rx_"). 3 Serial RapidIO Physical Layer Interface Lattice Semiconductor Register Descriptions This section describes the registers available in this core. * PHY CSR Registers: These implement the PHY Command and Status Registers as defined in the Serial RapidIO Specification. * USER Registers: These implement the registers required by the core, and gives status information about the core. * SERDES Registers: For SERDES Registers please refer to the ORT42G5/ORT82G5 FPSC data sheet available at www.latticesemi.com. Signal Descriptions Table 1. Serial RapidIO Physical Layer Interface Definitions Port Name I/O Type Active State Signal Description TD Output -- Transmit Data. This is a unidirectional point-to-point bus carrying packet information. This bus is connected to the RD bus of the receiving device. TD_N Output -- Transmit Data complements. These are the differential pairs of the TD signal. RD Input -- Receive Data. This is a unidirectional point-to-point bus carrying packet information. This bus is connected to the TD bus of the receiving device. RD_N Input -- Receive Data complements. These are the differential pairs of the RD signal. TX Interface RX Interface Table 2. Serial RapidIO User Interface Signal Definitions I/O Type Active State reset_n Port Name Input Low Signal Description sys_clk Input -- System Clock rx_buf_status [4:0] Input -- This signal specifies the number of available packet buffers in the receiving device. Encoding value specifies the number of packet buffers the receiving device has currently available. rx_rios_ready Output High Ready signal indicating RX RapidIO-PHY is ready and that receiver initialization is complete. rx_rios_discard Output High Indicates that RX RapidIO-PHY wants to terminate the current packet being sent to the user interface. rx_usr_discard Input High Indicates that the user interface wants to terminate the current packet being received from the RX RapidIO-PHY interface. sine_rx_data [63:0] Output -- Indicates that data was sent from the RX RapidIO- PHY interface to the user. sine_rx_hwen [3:0] Output -- This signal indicates the valid half word of the data bus sine_rx_data of the current packet transfer. sine_rx_sof Output -- SOF signal indicating the start of sine_rx_data. sine_rx_eof Output -- EOF signal indicating the end of sine_rx_data. Output -- This signal is asserted when RX RapidIO-PHY writes the data received to the user interface FIFO. Output High Ready signal indicating TX RapidIO-PHY is ready to receive data from the user. When tx_rios_ready is de-asserted, all user interface signals are regarded as invalid input or output. Active low system reset signal. RX User Interface sine_rx_write TX User Interface tx_rios_ready 4 Serial RapidIO Physical Layer Interface Lattice Semiconductor Table 2. Serial RapidIO User Interface Signal Definitions (Continued) Port Name Active State Signal Description Output -- Indicates that the buffer data associated with this ACKID should be sent by the user through the Generic FIFO Bridge interface. tx_release_ackid [4:0] Output -- Indicates that the buffer data associated with this ACKID can be released and reused by the user interface. tx_rios_discard Output High Indicates that TX RapidIO-PHY wants to terminate the current packet being received from the user interface. tx_usr_discard Input High Indicates the user interface wants to terminate the current packet being sent to the RapidIO-PHY interface. tx_prio[1:0] Input -- Indicates the priority of the packet being received. tx_next_ackid [4:0] I/O Type Output -- Indicates that tx_release_ackid is valid. sine_tx_data [63:0] Input -- Indicates that data was received from the user interface. sine_tx_alm_empty Input High This signal is asserted when the user transmit FIFO is almost empty. The threshold is set to one 64 bit. sine_tx_read Output High This signal is asserted when the TX RapidIO PHY requests data from the user transmit FIFO. sine_tx_sof Input High This signal is asserted with the first data transferred to indicate the start of a new packet. It should be asserted for a maximum of one clock cycle. sine_tx_eof Input High This signal is asserted with the last data transferred to indicate the end of the packet. sine_tx_data_en [3:0] Input -- This signal indicates the valid half word of the data bus on the last data transfer of the current packet. sine_tx_data_avail Input High pmi_usr_clk Input -- pmi_sel Input High Management Device Select. This signal is asserted to access Management registers. Output High Indicates when Management is ready. This signal is asserted to indicate that Management has taken/kept the data from/to the data bus. pmi_wr Input High Management register write. Valid when pmi_sel is asserted. When this signal is low, it indicates a read. pmi_addr [31:0] Input -- Management address bus for register access. pmi_datain[31:0] Input -- Register Data In tx_release_val This signal is asserted as long as there is one full packet or predetermined amount of data in the user transmit FIFO. PMI Interface pmi_ready pmi_dataout [31:0] Output -- pmi_int Output High Management interface clock Register Data Out Management Interrupt Serial RapidIO Core Design Flow Lattice has created a detailed software IP tutorial available on the Lattice web site at www.latticesemi.com. Both a simple IP module evaluation and tutorial and a more detailed ispLeverCORETM tutorial are available for download. Type "tutorial" in the Lattice website search engine. For further information about this Serial RapidIO Physical Interface core, please refer to the Serial RapidIO Physical Layer Interface User's Guide. Custom Core Configurations For Serial RapidIO core configurations that are not available in the Evaluation Package, please contact your Lattice sales office to request a custom configuration. 5 Serial RapidIO Physical Layer Interface Lattice Semiconductor Appendix A. ORCA(R) Series 4 FPSCs - ORT42G5 Table 3. Performance and Resource Utilization1 Name of Parameter File rio_seri_t42g5_1_001.lpc ORCA 42 PFUs LUTs2 Registers2 EBR PIO2 fMAX sys_clk and pmi_usr_clk (MHz) 996 4386 4232 23 178 39.0625 1. Performance and utilization characteristics are generated using an ORT42G5-2BM484 in Lattice's ispLEVER(R) v.3.1 software. When using this IP core in a different density, package, speed, or grade within ORCA 4 family, performance and utilization may vary. 2. Performance and utilization characteristics are counted based on the utilization of the top level module which includes rios_smi module. Supplied Netlist Configurations The Ordering Part Number (OPN) for all configurations of this core is RIO-SERI-T42G5-N1. Table 3 lists the netlists available as Evaluation Packages for the ORCA Series 4 FPSC devices, which can be downloaded from the Lattice website at www.latticesemi.com. To load the preset parameters for this core, click on the "Load Parameters" button inside the IP Manager tool. Make sure that you are looking for a file inside of this core's directory location. The Lattice Parameter Configuration files (.lpc) are located inside this directory. 6