40313HKIM 20120403-S00001 No.A2175-1/23
Semiconductor Components Industries, LLC, 2013
April, 2013
http://onsemi.com
LC87F2608A
Overview
The LC87F2608A is an 8-bit microcontroller that, centered around a CPU running at a mini mum bus cycle time of
100ns, integrates on a sing le chip a number of hardware features such as 8K-byte flash ROM, 512-by t e R AM , a n
on-chip debugger, two sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a synchronous SIO
interface, a high-s peed 12-bit PWM, two hi g h-s peed pulse width/ period counters, a 3-ch annel AD conv ert e r wi t h
12-/8-bit resolution selector , an analog comparator, a watchdog timer , an internal reset circuit, a system clock fre quency
divider, and a 16-source 10-vector interrupt feature.
Features
Flash ROM
8192 × 8 bits (LC87F2608A)
Capable of on- b oard-program m i ng wit h wi de ran ge of
voltage source (3.0 to 5.5V).
Block-erasable in 128-b yte units
RAM
512 × 9 bits (LC87F2608A)
Package Form
MFP10SK: Lead-/Halogen-free type
MFP14S (for debugging only): Lead-free type
MFP10S: Lead-/Halogen-free type (discontinued)
Package Dimensions Package Dimensions
unit : mm (typ) unit : mm (typ)
3111A (for debuggi ng only) 3086B (disconti n ued)
Orderin
g
numbe
r
: ENA2175
CMOS IC
8K-byte FROM and 512-byte RAM integrated
8-bit 1-chip microcontroller
MFP10S(225mil)
1
10
5
6
(0.5)
1.7max
1.00.35
5.0
0.15
6.4
(1.5)
0.1
4.4
0.63
MFP14S(225mil)
1
14
7
8
8.0
0.15
(1.0) 1.0 0.35
1.7MAX
(1.5)
0.1 4.4
0.63
6.4
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Package Dimensions
unit : mm (typ)
3420
MFP10SK(225mil)
1
10
2
0.8 MAX
1.55
1.0 0.35
5.0
0.15
6.2
(1.5)
0.05 4.4
0.5
LC87F2608A
No.A2175-2/23
Minimum Bus Cycle Time (Not e1)
100ns (10MHz) VDD=2.7 to 5.5V (Note2)
Minimum Instruction Cycle Time
300ns (10MHz) VDD=2.7 to 5.5V (Note2)
Note1: The bus cycle time here refers to the ROM read speed.
Note2: Use this product in a voltage range of 3.0 to 5.5V because the minimum release voltage (PORRL) of the
power-on reset (POR) circuit is 2.87V±0.12V.
Ports
I/O ports
Ports whose I/O direct i o n can be desi g nat ed in 1 bit units: 7 (P10 to P12, P30 to P33 )
Reset pins: 1 (RES)
Power pins: 2 (VSS1, VDD1)
Timers
Timer 0: 16-bit timer/counter with a capture register
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
+ 8-bit counter (with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
Timer 1: 16-bit timer/counter
Mode 0: 8-bit timer with an 8-bit prescaler + 8-bit timer/counter with an 8-bit prescaler
Mode 2: 16-bit timer/counter with an 8-bit prescaler
Serial Interface
SIO7: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
High-spee d 12 - bi t PWM
System clock/high-speed RC oscillation clock (20MHz or 40MHz) operation selectable
Duty/period programmable
Continuo us P WM output/specific count P WM output (automatic stop) selectable
High-speed Pulse Width/Period Counter
HCT1: Hig h- speed pulse width/period counte r 1
1) System clock/high-speed RC oscillation clock (20MHz or 40MHz) operation selectable
2) H-level width/L-level width/period measurement modes selectable
3) Input triggering noise filter
HCT2: Hig h- speed pulse width/period counte r 2
1) System clock/high-speed RC oscillation clock (20MHz or 40MHz) operation selectable
2) Can measure both L-level width and period simultaneously.
3) Input triggering noise filter
4) Input trigger selectable (from 3 signals, i.e., P11/HCT2IN, P31/HCT2IN, and analog comparator output)
LC87F2608A
No.A2175-3/23
AD Converter: 12 bits × 3 channels
12-/8-bit AD converter resolution selectable
Analog Comparator
Sends output to the P32/CMPO port (polarity selectable).
Edge detection functio n (shared with INTC and also allows the selection of the noise filter function)
Watchdog Timer
Can generate the internal reset signal on a timer overflow monitored by the WDT-dedicated low-speed RC
oscillation clock (30kHz).
Allows selection of continue, stop, or hold mode operation of the counter on entry into the HALT/ HOLD mode.
Interrupt Source Flags
16 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control.
Any interrupt requests of the level equal to or lower than the current interrup t are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time,
the interrupt of the highest level takes preceden ce over the other interrupts.
For interrupts of the same level, the interrupt into the smallest vector address takes precedence.
No. Vector Address Level Interrupt Source
1 00003H X or L INTA
2 0000BH X or L INTB
3 00013H H or L INTC/T0L/INTE
4 0001BH H or L INTD/INTF
5 00023H H or L T0H/SIO7
6 0002BH H or L T1L/T1H
7 00033H H or L HCT1
8 0003BH H or L HCT2
9 00043H H or L ADC/HPWM automatic stop/HPWM cycle
10 0004BH H or L None
Priority levels X > H > L
Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels: 256 levels maximum (The stack is allocated in RAM.)
High-speed Multiplication/Division Instructions
16 bits × 8 bits (5 tCYC execution time)
24 bits × 16 bits (12 tCYC execution time)
16 bits ÷ 8 bits (8 tCYC ex ecution time)
24 bits ÷ 16 bits (12 tCYC execu tion time)
Oscillation Circuits
Medium speed RC oscillation circuit (internal): For system clock (1MHz)
Low speed RC oscillation circuit (internal): For watchdog timer (30kHz)
High speed RC oscillation circuit (internal): For system clock (20MHz or 40MHz)
1) 2 source oscillation frequencies (20MHz or 40MHz) selectable for the high-speed RC oscillation circuit
by optional configuration.
System Clock Divider Function
Can run on low current.
The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and
76.8μs (when high speed RC oscillation is selected for system clock.).
LC87F2608A
No.A2175-4/23
Internal Reset Circuit
Power-on res e t (POR) fu nction
1) POR reset is generated only at power-on time.
2) The POR release level can be selected from 3 levels (2.87V, 3.86V, and 4.35V) by optional configuration.
Low-voltage detection reset (LVD) function
1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls
below a certain level.
2) The use or disuse of the LVD function and the low voltage threshold level (3 levels: 2.81V, 3.79V, and 4.28V)
can be selected by optional configuration.
Standby Function
HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) There are the following three ways of resetting the HALT mode.
(1) Setting the Reset pin to the low level
(2) Generating a reset signal via the watchdog timer or brown-out detector
(3) Having an interrupt generated
HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The medium- and high-speed RC oscillation circuits automatically stop operation.
2) There are the following four ways of resetting the HOLD mode.
(1) Setting the Reset pin to the low level
(2) Generating a reset signal via the watchdog timer or brown-out detector
(3) Setting at least one of the INTA, INTB, INTC, INTD, INTE, and INTF pins to the specified level
(INTA and INTB HOLD mode reset is available only when level detection is set.)
(4) Applyi ng i nput si gnals to t he IN+ a nd IN- pins so t hat t he anal og com parator out put is set to t he speci fied level
(when the analog comparator output is assigned to the INTC input)
On-chip Debu g ger F unct i o n
Supports software debugging with the IC mounted on the target board (selectable from 3 series).
1) LC87D2708A : All terminal function of LC87F2608A can be used.
2) LC87F2708A : All terminal function of LC87F2608A can be used. The debug feature is limited.
3) LC87F2608 A : The debugger terminal function when a n O n- chi p debugger is used cann ot be used.
The debug feature is limited.
Two channels of on-chip debugger pins are available (LC87F2608A).
Data Security Function (Note3)
Protects the program data stored in flash memory from unauthorized read or copy.
Note3: This data security function does not necessarily provide absolute data security.
LC87F2608A
No.A2175-5/23
Development Tools
On-chip debugger: 1) TCB87-Type B + LC87D2708A or LC87F2708A
2) TCB87-Type B + LC87F2608A
3) TCB87-Type C (3 wire version) + LC87D2708A or LC87F2708A
4) TCB87-Type C (3 wire version) + LC87F2608A
Programming Board
Package Programming Board
MFP10S
W87F27M-DBG
MFP10SK
MFP14S
Flash ROM Programming Board
Maker Model Version Device
Flash Support Group, Inc.
(FSG)
+
Our company
(Note 4)
In-circuit
Programmer
AF9101/AF9103 (Main body)
(FSG models)
Rev.01.01 or later LC87F2608A
SIB87 (Inter Face Driver)
(Our company model)
Our company
Single/Gang
Programmer
SKK-DBG Type B
(Sanyo FWS)
Application Version
1.04 or later
Chip Data Version
2.10 or later
LC87F2608A
In-circuit/
Gang
Programmer
For information about AF-series:
Flash Support Group, Inc.
TEL: +81-53-459-1050
E-mail: sales@j-fsg.co.jp
Note4: On-board-programmer from FSG (AF9101/AF9103) and serial interface driver from Our company (SIB87)
together can give a PC-less, standalone on-board-programming capab ilities.
LC87F2608A
No.A2175-6/23
Pin Assignment
MFP10S “Lead-/Halogen-free type”
MFP10SK “Lead-/Halogen-free type”
MFP10S
MFP10SK NAME
1 P31/INTB/HCT2IN/DBGP01
2 P30/INTA/HCT1IN/DBGPX0
3 RES
4 P10/SO7/INTE/AN0/DBGP02
5 VSS1
6 P12/SCK7/INTF/IN-/AN2
7 P11/SI7/SB7/INTE/IN+/HCT2IN/AN1
8 P33/INTD/HPWM/DBGP12
9 P32/INTC/CMPO/DBGP11
10 VDD1
P31/INTB/HCT2IN/DBGP01
P30/INTA/HCT1IN/DBGPX0
RES
P10/SO7/INTE/AN0/DBGP02
VSS1
VDD1
P32/INTC/CMPO/DBGP11
P33/INTD/HPWM/DBGP12
P11/SI7/SB7/INTE/IN+/HCT2IN/AN1
P12/SCK7/INTF/IN-/AN2
1
2
3
4
5
10
9
8
7
6
LC87F2608A
No.A2175-7/23
MFP14S (for debugging only) “Lead-free type”
MFP14S NAME
1 P31/INTB/HCT2IN/DBGP01
2 P30/INTA/HCT1IN/DBGPX0
3 RES
4 P10/SO7/INTE/AN0/DBGP02
5 VSS1
6 NC
7 DBGP22
8 DBGP21
9 DBGP20
10 P12/SCK7/INTF/IN-/AN2
11 P11/SI7/SB7/INTE/IN+/HCT2IN/AN1
12 P33/INTD/HPWM/DBGP12
13 P32/INTC/CMPO/DBGP11
14 VDD1
P31/INTB/HCT2IN/DBGP01
P30/INTA/HCT1IN/DBGPX0
RES
P10/SO7/INTE/AN0/DBGP02
VSS1
NC
DBGP22
VDD1
P32/INTC/CMPO/DBGP11
P33/INTD/HPWM/DBGP12
P11/SI7/SB7/INTE/IN+/HCT2IN/AN1
P12/SCK7/INTF/IN-/AN2
DBGP20
DBGP21
1
2
3
4
5
6
7
14
13
12
11
10
9
8
LC87F2608A
No.A2175-8/23
System Block Diagram
Interrupt control
Standby control
IR PLA
Flash ROM
PC
Bus interface
Port 1
(INTE-INTF)
Port 3
(INTA-INTD)
SIO7
Timer 0
Timer 1
High-speed PWM
High-speed pulse
width/period counter1
ADC
High-speed pulse
width/period counter2
ACC
B register
C register
PSW
RAR
RAM
Stack pointer
ALU
On-chip debugger
Medium-
speed RC
Freq. divider
Clock
generator
Reset circuit
(LVD/POR)
WDT
(Low-speed RC)
Reset
control
RES
DATA BUS
DATA BUS
Analog
comparator
High-speed
RC
LC87F2608A
No.A2175-9/23
Pin Description
Pin Name I/O Description Option
VSS1 - - power supply pin No
VDD1 - + power supply pin No
PORT1
P10 to P12
I/O 3-bit I/O port
I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1-bit units
Multiplexed pins
P10: SIO7 data output/
INTE input/HOLD release input/timer 1 event input/
timer 0L capture input/timer 0H capture input
P11: SIO7 data input/bus I/O/
high-speed pulse width/period counter 2 inpu/t
INTE input/HOLD release input/timer 1 event input/
timer 0L capture input/timer 0H capture input
P12: SIO7 clock I/O/
INTF input/HOLD release input/timer 1 event input/
timer 0L capture input/timer 0H capture input
AD converter input ports: AN0 to AN2 (P10 to P12)
Analog comparator input ports: IN+, IN- (P11, P12)
On-chip debugger pin 1: DBGP02 (P10)
Interrupt acknowledge type
Rising Falling
Rising &
Falling H level L level
INTE
INTF
enable
enable
enable
enable
enable
enable
disable
disable
disable
disable
Yes
PORT3
P30 to P33
I/O 4-bit I/O port
I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1-bit units
Multiplexed pins
P30: INTA input/HOLD release input/timer 0L capture input/
high-speed pulse width/period counter 1 input
P31: INTB input/HOLD release input/timer 0H capture input/
high-speed pulse width/period counter 2 input
P32: INTC input/HOLD release input/timer 0 event input/
timer 0L capture input/analog comparator output
P33: INTD input/HOLD release input/timer 0 event input/
timer 0H capture input/high-speed PWM output
On-chip debugger pin 1: DBGPX0 to DBGP01 (P30 to P31)
On-chip debugger pin 2: DBGPX0 to DBGP12 (P30, P32 to P33)
Interrupt acknowledge type
Rising Falling
Rising &
Falling H level L level
INTA
INTB
INTC
INTD
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Yes
RES I/O
External reset input/internal reset output No
LC87F2608A
No.A2175-10/23
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name Option Selected
in Units of Option Type Output Type Pull-up Resistor
P10 to P12 1 bit
1 CMOS Programmable
2 N-channel open drain Programmable
P30 to P33 1 bit
1 CMOS Programmable
2 N-channel open drain Programmable
On-chip Debugger Pin Processing
For the processing of the on-chip debugger pins, refer to the separately available documents entitled "RD87 On-chip
Debugger Installation" and "LC872000 Series On-chip Debugger Pin Processing."
Recommended Unused Pin Connections
Pin Name
Recommended Unused Pin Connections
Board Software
P10 to P12 OPEN Set output low
P30 to P33 OPEN Set output low
User Options
Option Name Option Type Flash Version
Option
Switched in
Unit of
Description
Port output type
P10 to P12 enable 1bit
CMOS
N-channel open drain
P30 to P33 enable 1bit
CMOS
N-channel open drain
Program start address - enable -
00000H
01E00H
Brown-out detector reset
function
Brown-out detector
function enable -
Enable: Used
Disable: Not used
Brown-out trip level enable - 3 levels
Power-on-reset function Power-on-reset level enable - 3 levels
High-speed RC oscillator
circuit Oscillation frequency enable -
20 MHz
40 MHz
Package type - enable -
MFP10S: LC87F2608A
MFP14S: Debugged by using
LC87D2708A or LC87F2708A
LC87F2608A
No.A2175-11/23
Absolute Maximum Ratings at Ta=25°C, VSS1=0V
Parameter Symbol Pin/Remarks Conditions
Specification
VDD[V] min typ max unit
Maximum supply
voltage
VDD max VDD1 -0.3 to +6.5 V
Input voltage VI RES -0.3
to VDD+0.3
Input/output
voltage
VIO Port 1
Port 3
-0.3 to VDD+0.3
High level output current
Peak output
current
IOPH(1) Port 1 CMOS output selected
Per applicable pin
-7.5 mA
IOPH(2) Port 3 CMOS output selected
Per applicable pin
-10
Mean output
current
(Note 1-1)
IOMH(1) Port 1 CMOS output selected
Per applicable pin
-5
IOMH(2) Port 3 CMOS output selected
Per applicable pin
-7.5
Total output
current
ΣIOAH(1) Port 10
Ports 30, 31
Total of currents at all
applicable pins
-20
ΣIOAH(2) Ports 11, 12
Ports 32, 33
Total of currents at all
applicable pins
-20
ΣIOAH(3) Port 1
Port 3
Total of currents at all
applicable pins
-35
Low level output current
Peak output
current
IOPL(1) Port 1 Per applicable pin 15
IOPL(2) Port 3 Per applicable pin 10
Mean output
current
(Note 1-1)
IOML(1) Port 1 Per applicable pin 10
IOML(2) Port 3 Per applicable pin 7.5
Total output
current
ΣIOAL(1) Port 10
Ports 30, 31
Total of currents at all
applicable pins
25
ΣIOAL(2) Ports 11, 12
Ports 32, 33
Total of currents at all
applicable pins
35
ΣIOAL(3) Port 1
Port 3
Total of currents at all
applicable pins
55
Power dissipation
Pd max(1) MFP10S Ta=-40 to +85°C
Independent package
100 mW
Pd max(2) Ta=-40 to +85°C
Mounted on thermal test
board
(Note 1-2)
237
Pd max(3) MFP10SK Ta=-40 to +85°C
Independent package
100
Pd max(4) Ta=-40 to +85°C
Mounted on thermal test
board
(Note 1-2)
237
Operating ambient
temperature
Topr -40 to +85 °C
Storage ambient
temperature
Tstg -55 to +125
Note 1-1: Mean output current refers to the average of output currents measured for a period of 100ms.
Note 1-2: Thermal test board used conforms to SEMI (size: 76.1×114.3×1.6tmm, glass epoxy board).
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
LC87F2608A
No.A2175-12/23
Allowable Operating Conditions at Ta= -40 to +85°C, VSS1=0V
Parameter Symbol Pin/Remarks Conditions
Specification
VDD[V] min typ max unit
Operating
supply voltage
(Note 2-1)
VDD V
DD1 0.272μs tCYC 100μs 2.7 5.5 V
Memory
sustaining
supply voltage
VHD V
DD1 RAM and register contents sustained
in HOLD mode
2.0 5.5
High level
input voltage
VIH(1) Port 1
Port 3
Output disabled 2.7 to 5.5 0.3VDD
+0.7
V
DD
VIH(2) RES 2.7 to 5.5
0.75VDD
V
DD
Low level
input voltage
VIL(1) Port 1
Port 3
Output disabled 4.0 to 5.5 VSS
0.1VDD+0.4
2.7 to 4.0 VSS 0.2VDD
VIL(2) RES 2.7 to 5.5 VSS 0.
25VDD
Instruction
cycle time
(Note 2-2)
tCYC 2.7 to 5.5 0.272 100 μs
Oscillation
frequency
range
FmHRC(1) High-speed RC oscillation
40MHz selected as option
Ta=-20 to +85°C
4.5 to 5.5 38 40 42 MH
z
FmHRC(2) High-speed RC oscillation
40MHz selected as option
Ta=-40 to +85°C
4.5 to 5.5 37.6 40 42.4
FmHRC(3) 3.5 to 5.5 36.8 40 43.2
FmHRC(4) 2.7 to 5.5 32 40 43.2
FmHRC(5) High-speed RC oscillation
20MHz selected as option
Ta=-20 to +85°C
3.0 to 5.5 19 20 21
FmHRC(6) High-speed RC oscillation
20MHz selected as option
Ta=-40 to +85°C
2.7 to 5.5 18.7 20 21.3
FmRC Medium-speed RC oscillation 2.7 to 5.5 0.5 1.0 2.0
FmSLRC Low-speed RC oscillation 2.7 to 5.5 15 30 60 kHz
Oscillation
stabilization
time
tmsHRC When high-speed RC oscillation
state is switched from stopped to
enabled.
See Fig. 2.
2.7 to 5.5 100 μs
Note 2-1: Use this product in a voltage range of 3.0 to 5.5V because the minimum release voltage (PORRL) of
the power-on reset (POR) circuit is 2.87V±0 .12V.
Note 2-2: Relationship between tCYC and oscillation frequency is as follows:
When system clock sou rce is set to medium-speed RC oscillation
3/FmRC at a division ratio of 1/1, 6/FmRC at a division ratio of 1/2, 12/FmRC a division ratio of 1/4,
and so forth
When system clock source is set to high-speed RC oscillation (40MHz selected by optional configuration)
12/FmHRC at a division rat io of 1/ 1, 24/Fm HRC at a divi sion ratio of 1/ 2, 48/Fm HRC a divisio n ratio o f 1/4,
and so forth
When system clock source is set to high-speed RC oscillation (20MHz selected by optional configuration)
6/FmHRC at a division ratio of 1/1, 12/FmHRC at a division ratio of 1/2, 24/FmHRC a division ratio of 1/4,
and so forth
LC87F2608A
No.A2175-13/23
Electrical Characteristics at Ta= -40 to +85°C, VSS1=0V
Parameter Symbol Pin/Remarks Conditions
Specification
VDD[V] min typ max unit
High level input
current
IIH(1) Port 1
Port 3
Output disabled
Pull-up resistor off
VIN=VDD
(including output Tr. off leakage
current)
2.7 to 5.5 1 μA
IIH(2) RES V
IN=VDD 2.7 to 5.5 1
Low level input
current
IIL Port 1
Port 3
Output disabled
Pull-up resistor off
VIN=VSS
(including output Tr. off leakage
current)
2.7 to 5.5 -1
High level output
voltage
VOH(1) CMOS output
type port 1
IOH=-1mA 4.5 to 5.5 VDD-1 V
VOH(2) IOH=-0.35mA 2.7 to 5.5 VDD-0.4
VOH(3) CMOS output
type port 3
IOH=-5mA 4.5 to 5.5 VDD-1.5
VOH(4) IOH=-0.7mA 2.7 to 5.5 VDD-0.4
Low level output
voltage
VOL(1) Port 1 IOL=10mA 4.5 to 5.5 1.5
VOL(2) IOL=1.4mA 2.7 to 5.5 0.4
VOL(3) Port 3 IOL=5mA 4.5 to 5.5 1.5
VOL(4) IOL=0.7mA 2.7 to 5.5 0.4
Pull-up resistance Rpu(1) Port 1
Port 3
VOH=0.9VDD 4.5 to 5.5 15 35 80 k
Rpu(2) 2.7 to 4.5 18 50 150
Rpu(3) RES 2.7 to 5.5 216 360 504
Hysteresis voltage VHYS Port 1
Port 3
RES
2.7 to 5.5 0.1VDD V
Pin capacitance CP All pins VIN=VSS for pins other than that
under test
f=1 MHz
Ta=25°C
2.7 to 5.5 10 pF
LC87F2608A
No.A2175-14/23
Serial I/O Characteristics at Ta= -40 to +85°C, VSS1=0V
SIO7 Serial I/O Characteristics (Note 4-1-1)
Parameter Symbol Pin/Remarks Conditions
Specification
VDD [V] min typ max unit
Serial clock
Input clock
Frequency tSCK(1) SCK7(P12) See Fig. 4.
(Note 4-1-2)
2.7 to 5.5 2 tCYC
Low level
pulse width
tSCKL(1) 1
High level
pulse width
tSCKH(1) 1
Output clock
Frequency tSCK(2) SCK7(P12) CMOS output selected
See Fig. 4.
2.7 to 5.5 4/3
Low level
pulse width
tSCKL(2) 1/2 tSCK
High level
pulse width
tSCKH(2) 1/2
Serial input
Data setup time
tsDI(1) SB7(P11),
SI7(P11)
Must be specified with respect to
Rising edge of SIOCLK.
See Fig. 4.
2.7 to 5.5 0.03 μs
Data hold time
thDI(1) 0.03
Serial output
Input clock
Output delay
time
tdDO(1) SO7(P10),
SB7(P11)
Must be specified with respect to
rising edge of SIOCLK.
Must be specified as the time to
the beginning of output state
change in open drain output
mode.
See Fig. 4.
2.7 to 5.5 1tCYC
+0.05
Output clock
tdDO(2)
(1/3)tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in transmission/reception mode, the time from SI7RUN being set
when serial clock is "H" to the first falling edge of the serial clock must be longer than 1tCYC.
LC87F2608A
No.A2175-15/23
Pulse Input Conditions at Ta= -40 to +85°C, VSS1=0V
Parameter Symbol Pin/Remarks Conditions
Specification
VDD[V] min typ max unit
High/low level
pulse width
tPIH(1)
tPIL(1)
INTA(P30),
INTB(P31),
INTD(P33),
INTE(P10, P11),
INTF(P12)
Interrupt source flag can be
set.
Event inputs for timers 0
and 1 are enabled.
2.7 to 5.5 1 tCYC
tPIH(2)
tPIL(2)
INTC(P32) when noise
filter time constant is
"none"
Interrupt source flag can be
set.
Event inputs for timer 0 are
enabled.
2.7 to 5.5 1
tPIH(3)
tPIL(3)
INTC(P32) when noise
filter time constant is
"1/16"
Interrupt source flag can be
set.
Event inputs for timer 0 are
enabled.
2.7 to 5.5 64
tPIH(4)
tPIL(4)
INTC(P32) when noise
filter time constant is
"1/32"
Interrupt source flag can be
set.
Event inputs for timer 0 are
enabled.
2.7 to 5.5 128
tPIH(5)
tPIL(5)
INTC(P32) when noise
filter time constant is
"1/64"
Interrupt source flag can be
set.
Event inputs for timer 0 are
enabled.
2.7 to 5.5 256
tPIH(6)
tPIL(6)
HCT1IN(P30) Pulses can be recognized as signals
by the high-speed pulse
width/period counter 1.
2.7 to 5.5 3 H1CK
(Note
5-1)
tPIH(7)
tPIL(7)
HCT2IN(P11, P31) Pulses can be recognized as signals
by the high-speed pulse
width/period counter 2.
2.7 to 5.5 6 H2CK
(Note
5-2)
tPIL(8) RES Resetting is enabled. 2.7 to 5.5 200 μs
Note 5-1: H1CK denotes the period of the base clock (1 to 8 × high-speed RC oscillation clock or system clock)
for the high-speed pulse width/period counter 1.
Note 5-2: H2CK denotes the period of the base clock (2 to 16 × high-speed RC oscillation clock or system clock)
for the high-speed pulse width/period counter 2.
Comparator Characteristics at Ta= -40 to +85°C, VSS1=0V
Parameter Symbol Pin/Remarks Conditions
Specification
VDD [V] min typ max unit
Common mode
input voltage
range
VCMIN IN+(P11),
IN-(P12)
2.7 to 5.5 VSS
VDD-1.5
V
Offset voltage VOFF Within common mode input voltage
range
2.7 to 5.5 ±10 ±30 mV
Response time tRT Within common mode input
voltage range
Input amplitude=100mV
Overdrive=50mV
2.7 to 5.5 200 600 ns
Operation
stabilization time
(Note 6-1)
tCMW 2.7 to 5.5 1.0 μs
Note 6-1: The interval after CMPON is set till the operation gets stabilized.
LC87F2608A
No.A2175-16/23
AD Converter Characteristics at VSS1=0V
<12-bit AD conversion mode at Ta=-40 to +85°C >
Parameter Symbol Pin/Remarks Conditions
Specification
VDD [V] min typ max unit
Resolution N AN0(P10)
to AN2(P12)
3.0 to 5.5 12 bit
Absolute
accuracy
ET (Note 7-1) 3.0 to 5.5 ±16 LSB
Conversion time tCAD See "Conversion time calculation
method."
(Note 7-2)
4.0 to 5.5 38 104.3 μs
3.0 to 5.5 75.8 104.3
Analog input
voltage range
VAIN 3.0 to 5.5 VSS V
DD V
Analog port input
current
IAINH VAIN= VDD 3.0 to 5.5 1 μA
IAINL VAIN= VSS 3.0 to 5.5 -1
<8-bit AD Converter Mode at Ta=-40 to +85°C >
Parameter Symbol Pin/Remarks Conditions
Specification
VDD [V] min typ max unit
Resolution N AN0(P10)
to AN2(P12)
3.0 to 5.5 8 bit
Absolute
accuracy
ET (Note 7-1) 3.0 to 5.5 ±1.5 LSB
Conversion time tCAD See "Conversion time calculation
method."
(Note 7-2)
4.0 to 5.5 23.4 64.3 μs
3.0 to 5.5 46.7 64.3
Analog input
voltage range
VAIN 3.0 to 5.5 VSS V
DD V
Analog port
input current
IAINH VAIN= VDD 3.0 to 5.5 1 μA
IAINL VAIN= VSS 3.0 to 5.5 -1
<Conversion time calculation method>
12-bit AD conversion mode: tCAD (conversion time) = ((52/(division ratio)) + 2) × (1/3) × tCYC
8-bit AD conversion mode: tCAD (conversion time) = ((32/(division ratio)) + 2) × (1/3) × tCYC
<Recommended Operating Conditions>
High-speed RC
Oscillation
(FmHRC)
Supply Voltage
Range
(VDD)
System Clock
Division Ratio
(SYSDIV)
Cycle Time
(tCYC)
AD Division Ratio
(ADDIV)
Conversion Time (tCAD)
12-bit AD 8-bit AD
40MHz/20MHz
4.0V to 5.5V 1/1 300ns 1/8 41.8μs 25.8μs
3.0V to 5.5V 1/1 300ns 1/16 83.4μs 51.4μs
Note 7-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy. The absolute accuracy is measured
when no change occurs in the I / O state of the pins tha t are adja cent to the analog input channel
during AD conversion processing.
Note 7-2: The conversion time refers to the interval from the time a conversion starting instruction is issued till the time
the complete digital conversion value against the analog input value is loaded in the result register.
*The conversion time is twice the normal value when one of the following conditions occurs:
The first AD conversion executed in the 12-bit AD conversion mode after a system reset.
The first AD conversion ex ecuted af ter the AD conversion mode is switched from 8-bit to
12-bit AD conversion mode.
LC87F2608A
No.A2175-17/23
Power-on Reset (POR) Characteristic s at Ta= -40 to +85°C, VSS 1=0V
Parameter Symbol Pin/Remarks Conditions
Specification
Option Selecting
Voltage min typ max unit
POR release
voltage
PORRL Option selected
See Fig. 6.
(Note 8-1)
2.87V 2.75 2.87 2.99 V
3.86V 3.73 3.86 3.99
4.35V 4.21 4.35 4.49
Unknown voltage
area
POUKS See Fig. 6.
(Note 8-2)
0.7 0.95
Power startup time PORIS Power startup time
from VDD=0V to 2.8V
100 ms
Note 8-1: The POR release voltage can be selected from three levels when the low-voltage detection feature is deselected.
Note 8-2: There is an unpredictable period before the power-on reset transistor starts to turn on.
Low-voltage Detection (LVD) Characteristics at Ta=-40 to +85°C, VSS 1=0V
Parameter Symbol Pin/Remarks Conditions
Specification
Option Selecting
Voltage min typ max unit
LVD reset voltage
(Note 9-2)
LVDET Option selected
See Fig. 7.
(Note 9-1)
(Note 9-3)
2.81V 2.71 2.81 2.91 V
3.79V 3.69 3.79 3.89
4.28V 4.18 4.28 4.38
LVD voltage
hysteresis
LVHYS 2.81V 60 mV
3.79V 65
4.28V 65
Unknown voltage
area
LVUKS See Fig. 7.
(Note 9-4)
0.7 0.95 V
Minimum low
voltage detection
width (response
sensitivity)
tLVDW LVDET-0.5V
See Fig. 8.
0.2 ms
Note 9-1: The LVD reset voltage can be selected from three levels when the low-voltage detection feature is selected.
Note 9-2: The hysteresis voltage is not included in the LVD reset voltage value.
Note 9-3: There are cases when the LVD reset voltage value is exceeded when a greater change in the output level
or large current is applied to the port.
Note 9-4: There is an unpredictable period before the low-voltage detection resetting transistor starts to run.
LC87F2608A
No.A2175-18/23
Consumption Current Charac teristics at Ta=-40 to +85°C, VSS 1=0V
Parameter
Symbol Pin/Remarks Conditions
Specification
VDD [V] min typ max unit
Normal mode
consumption
current
(Note 10-1)
IDDOP(1)
VDD1 FmHRC=40MHz oscillation mode
System clock set to high-speed RC,
10MHz (1/4 of 40MHz)
Medium-speed RC oscillation stopped
System clock frequency division ratio
set to 1/1
4.5 to 5.5 7.8 14 mA
IDDOP(2) 2.7 to 3.6 4.9 9.4
IDDOP(3)
FmHRC=20MHz oscillation mode
System clock set to high-speed RC,
10MHz (1/2 of 20MHz)
Medium-speed RC oscillation stopped
System clock frequency division ratio
set to 1/1
4.5 to 5.5 7.1 12.8
IDDOP(4) 2.7 to 3.6 4.5 8.6
IDDOP(5)
High-speed RC oscillation stopped
System clock set to medium-speed RC
oscillation mode
System clock frequency division ratio
set to 1/2
4.5 to 5.5 0.60 1.9
IDDOP(6) 2.7 to 3.6 0.38 1.3
HALT mode
consumption
current
(Note 10-1)
IDDHALT(1)
HALT mode
FmHRC=40MHz oscillation mode
System clock set to high-speed RC,
10MHz(1/4 of 40MHz)
Medium-speed RC oscillation stopped
System clock frequency division ratio
set to 1/1
4.5 to 5.5 3.2 5.0
IDDHALT(2) 2.7 to 3.6 2.0 3.1
IDDHALT(3)
HALT mode
FmHRC=20MHz oscillation mode
System clock set to high-speed RC,
10MHz (1/2 of 20MHz)
Medium-speed RC oscillation stopped
System clock frequency division ratio
set to 1/1
4.5 to 5.5 2.5 3.9
IDDHALT(4) 2.7 to 3.6 1.6 2.5
IDDHALT(5)
HALT mode
High-speed RC oscillation stopped
System clock set to medium-speed RC
oscillation mode
System clock frequency division ratio
set to 1/2
4.5 to 5.5 0.32 1.0
IDDHALT(6) 2.7 to 3.6 0.16 0.55
HOLD mode
consumption
current
(Note 10-1)
IDDHOLD(1) HOLD mode
Ta=-10 to +50°C
4.5 to 5.5 0.04 3.0 μA
IDDHOLD(2) 2.7 to 3.6 0.02 1.8
IDDHOLD(3) HOLD mode
Ta=-40 to +85°C
4.5 to 5.5 0.04 34
IDDHOLD(4) 2.7 to 3.6 0.02 22
IDDHOLD(5) HOLD mode
LVD option selected
Ta=-10 to +50°C
4.5 to 5.5 3.1 6.8
IDDHOLD(6) 2.7 to 3.6 2.4 4.2
IDDHOLD(7) HOLD mode
LVD option selected
Ta=-40 to +85°C
4.5 to 5.5 3.1 39
IDDHOLD(8) 2.7 to 3.6 2.4 25
IDDHOLD(9) HOLD mode
Watchdog timer active
Ta=-10 to +50°C
4.5 to 5.5 3.4 10
IDDHOLD(10) 2.7 to 3.6 1.7 6.0
IDDHOLD(11) HOLD mode
Watchdog timer active
Ta=-40 to +85°C
4.5 to 5.5 3.4 42
IDDHOLD(12) 2.7 to 3.6 1.7 27
IDDHOLD(13) HOLD mode
Comparator active
(IN+= VDD, IN-= VSS)
4.5 to 5.5 110 160
IDDHOLD(14) 2.7 to 3.6 65 100
Note 10-1: The consumption current valu e includes none of the currents that flow into the output Tr and internal pull-up
resistors.
LC87F2608A
No.A2175-19/23
F-ROM Programming Characteristics at Ta=+10 to +55°C, VSS1=0V
Parameter Symbol Pin/Remarks Conditions
Specification
VDD [V] min typ max unit
Onboard
programming
current
IDDFW VDD 1 Microcontroller consumption
current is excluded.
3.0 to 5.5 5 10 mA
Programming
time
tFW(1) Erase operation 3.0 to 5.5 20 30 ms
tFW(2) Programming operation 40 60 μs
Power Pin Treatment Recommendations (VDD1, VSS1)
Connect bypass capacitors that meet the following conditio ns between the VDD1 and VSS1 pins:
Connect among the VDD1 and VSS1pins and bypass capacitors C1 and C2 with the shortest possible heavy lead
wires, making sure that the impedances between the both pins and the bypass capacitors are as equal as possible
(L1=L1', L2=L2').
Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel.
The capacitance of C2 should be approximately 0.1μF.
VSS1
VDD1
L1’
L2’
L1
L2
C1 C2
LC87F2608A
No.A2175-20/23
Figure 1 AC Tim i ng Measurement Point
Figure 2 Oscillation Stabilization Times
0.5VDD
Operating VDD
lower limit
Medium-speed
RC oscillation
Power
RES
Medium-speed
RC scillation
High-speed
RC oscillation
Operating mode
Reset time
tmsHRC
Unpredictable Reset Instruction execution
Reset Time and Oscillation Stabilization Time
VDD
0V
High-speed
RC oscillation
State
HOLD/HALT
release signal No HOLD release signal HOLD release
Signal valid
HOLD Release Signal and Oscillation Stabilization Time
HOLD HALT Instruction execution
tmsHRC
HALT release signal valid
LC87F2608A
No.A2175-21/23
Figure 3 Sample Reset Circuit
Figure 4 Serial I/O Waveforms
Figure 5 Pulse Input Timing Signal Wavefo rm
DI0 DI7
DI2 DI3 DI4 DI5 DI6
DO0 DO7
DO2 DO3 DO4 DO5 DO6
DI1
DO1
SIOCLK:
DATAIN:
DATAOUT:
DATAOUT:
DATAIN:
SIOCLK:
tSCK
tSCKL tSCKH
thDItsDI
tdDO
tPIL tPIH
Note:
The external peripheral circuit differs depending
on the way in which the power-on reset and
low-voltage detection reset functions are used.
Refer to the Chapter, entitled "Reset Function,"
of the user's manual.
CRES
VDD
RRES
RES
LC87F2608A
No.A2175-22/23
Figure 6 Example of POR Only (LVD Deselected) Mode Waveforms (at Reset Pin with RRES Pull-up Resistor On ly)
The POR circuit generates a reset signal only when the power voltage is raised from the VSS level.
No stable reset signal is generated if power is turned on again when the power voltage does not go down to the VSS level
as shown in (a). If this case is anticipated, use the LVD function as explained below or configure an external reset
circuit.
A reset is effected only when power is turned on again after the power voltage goes down to and remains
at the VSS level for 100μs or longer as shown in (b).
Figure 7 Example of POR + LVD Mode Waveforms (at Reset Pin with RRES Pull-up Resistor Only)
A reset is effected both when power is turned on and when it goes down.
The hysteresis width (LVHYS) is introduced in the LVD circuit to prevent the iterations of the IC entering an d
exiting the reset state near the detection threshold level.
LVD voltage
(LVDET)
VDD
RES
LVD hysteresis width
(LVHYS)
Reset unknown area
(LVUKS)
Reset period Reset period Reset period
LVD release voltage
(LVDET+LVHYS)
POR release voltage
(PORRL)
VDD
RES
Reset unknown area
(POUKS)
(a) (b)
Reset period
Reset period
100μs or longer
LC87F2608A
PS No.A2175-23/23
Figure 8 Minimum Low Volt age Det e ction Width
(Example of Short Interruption of Power/ Power Fluctuation Waveform)
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VDD
LVD voltage
tLVDW
VSS
LVD release voltage
LVDET-0.5V