19-5511; Rev 1; 11/10 Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA The MAX2062 high-linearity, dual analog/digital variablegain amplifier (VGA) operates in the 50MHz to 1000MHz frequency range with two independent attenuators in each signal path. Each digital attenuator is controlled as a slave peripheral using either the SPIK-compatible interface, or a 5-bit parallel bus with 31dB total adjustment range in 1dB steps. An added feature allows rapid-fire gain selection among each of the four steps, preprogrammed by the user through the SPI-compatible interface. A separate 2-pin control lets the user quickly access any one of four customized attenuation states without reprogramming the SPI bus. Each analog attenuator is controlled using an external voltage or through the SPI-compatible interface using an on-chip 8-bit DAC. Since each of the stages has its own external RF input and RF output, this component can be configured to either optimize noise figure (NF) (amplifier configured first), OIP3 (amplifier last), or a compromise of NF and OIP3. The device's performance features include 24dB amplifier gain (amplifier only), 7.3dB NF at maximum gain (includes attenuator insertion losses), and a high OIP3 level of +41dBm. Each of these features makes the device an ideal VGA for multipath receiver and transmitter applications. In addition, the device operates from a single +5V supply with full performance or a +3.3V supply for an enhanced power-savings mode with lower performance. The device is available in a compact 48-pin TQFN package (7mm x 7mm) with an exposed pad. Electrical performance is guaranteed over the extended temperature range, from TC = -40NC to +85NC. Applications Features S Independently Controlled Dual Paths S 50MHz to 1000MHz RF Frequency Range S Pin-Compatible Family Includes MAX2063 (Digital-Only VGA) MAX2064 (Analog-Only VGA) S 19.4dB (typ) Maximum Gain S 0.34dB Gain Flatness Over 100MHz Bandwidth S 64dB Gain Range (33dB Analog Plus 31dB Digital) S 56dB Path Isolation (at 200MHz) S Built-In 8-Bit DACs for Analog Attenuation Control S Supports Four Rapid-Fire Preprogrammed Attenuator States Quickly Access Any One of Four Customized Attenuator States Ideal for Fast-Attack, High-Level Blocker Protection Protects ADC Overdrive Condition S Excellent Linearity (Configured with Amp Last at 200MHz) +41dBm OIP3 +56dBm OIP2 +19dBm Output 1dB Compression Point S 7.3dB Typical Noise Figure (at 200MHz) S Fast, 25ns Digital Switching S Very Low Digital VGA Amplitude Overshoot/ Undershoot S Single +5V Supply (or +3.3V Operation) S Amplifier Power-Down Mode for TDD Applications Ordering Information IF and RF Gain Stages Temperature-Compensation Circuits TEMP RANGE PIN-PACKAGE GSM/EDGE Base Stations MAX2062ETM+ -40NC to +85NC 48 TQFN-EP* WCDMA, TD-SCDMA, and cdma2000M Base Stations MAX2062ETM+T -40NC to +85NC 48 TQFN-EP* WiMAXK, LTE, and TD-LTE Base Stations and Customer-Premise Equipment PART +Denotes lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. T = Tape and reel. Fixed Broadband Wireless Access Wireless Local Loop Military Systems SPI is a trademark of Motorola, Inc. cdma2000 is a registered trademark of Telecommunications Industry Association. WiMAX is a trademark of WiMAX Forum. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. MAX2062 General Description MAX2062 Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA ABSOLUTE MAXIMUM RATINGS VCC_AMP_1, VCC_AMP_2, VCC_RG to GND...........-0.3V STA_A_1, STA_A_2, STA_B_1, STA_B_2, PD_1, PD_2, AMPSET to GND..........................-0.3V A_VCTL_1, A_VCTL_2 to GND..............................-0.3V DAT, CS, CLK, AA_SP, DA_SP to GND................-0.3V D0_1, D1_1, D2_1, D3_1, D4_1, D0_2, D1_2, D2_2, D3_2, D4_2 to GND................................-0.3V AMP_IN_1, AMP_IN_2 to GND...........................+0.95V AMP_OUT_1, AMP_OUT_2 to GND......................-0.3V D_ATT_IN_1, D_ATT_IN_2, D_ATT_OUT_1, D_ATT_OUT_2 to GND.......................................... 0V A_ATT_IN_1, A_ATT_IN_2, A_ATT_OUT_1, A_ATT_OUT_2 to GND.......................................... 0V to +5.5V to +3.6V to +3.6V to +3.6V to +3.6V to +1.2V to +5.5V to +3.6V to +3.6V REG_OUT to GND.................................................-0.3V to +3.6V RF Input Power (D_ATT_IN_1, D_ATT_IN_2)................ +20dBm RF Input Power (A_ATT_IN_1, A_ATT_IN_2) ............... +20dBm RF Input Power (AMP_IN_1, AMP_IN_2)....................... +18dBm qJC (Notes 1, 2).......................................................... +12.3NC/W qJA (Notes 2, 3)............................................................. +38NC/W Continuous Power Dissipation (Note 1)...............................5.3W Operating Case Temperature Range (Note 4)... -40NC to +85NC Junction Temperature......................................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Note 1: Based on junction temperature TJ = TC + (qJC x VCC x ICC). This formula can be used when the temperature of the exposed pad is known while the device is soldered down to a PCB. See the Applications Information section for details. The junction temperature must not exceed +150NC. Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Note 3: Junction temperature TJ = TA + (qJA x VCC x ICC). This formula can be used when the ambient temperature of the PCB is known. The junction temperature must not exceed +150NC. Note 4: TC is the temperature on the exposed pad of the package. TA is the ambient temperature of the device and PCB. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 5.0V SUPPLY DC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 4.75V to 5.25V, AMPSET = 0, PD_1 = PD_2 = 0, TC = -40NC to +85NC. Typical values are at VCC_ = 5.0V and TC = +25NC, unless otherwise noted.) PARAMETER SYMBOL Supply Voltage VCC Supply Current IDC Power-Down Current Logic-Low Input Voltage Logic-High Input Voltage Input Logic Current IDCPD CONDITIONS MIN 4.75 PD_1 = PD_2 = 1, VIH = 3.3V TYP MAX 5 5.25 V 148 210 mA 8 mA 0.5 V 5.3 VIL UNITS VIH 1.7 3.465 V IIH, IIL -1 +1 FA 3.3V SUPPLY DC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 3.135V to 3.465V, AMPSET = 1, PD_1 = PD_2 = 0, TC = -40NC to +85NC. Typical values are at VCC_ = 3.3V and TC = +25NC, unless otherwise noted.) PARAMETER SYMBOL Supply Voltage VCC Supply Current IDC Power-Down Current IDCPD CONDITIONS PD_1 = PD_2 = 1, VIH = 3.3V MIN TYP MAX UNITS 3.135 3.3 3.465 V 87 145 mA 4.5 8 mA Logic-Low Input Voltage VIL 0.5 V Logic-High Input Voltage VIH 1.7 V 2 _______________________________________________________________________________________ Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA PARAMETER RF Frequency SYMBOL fRF CONDITIONS (Note 5) MIN TYP 50 MAX UNITS 1000 MHz 5.0V SUPPLY AC ELECTRICAL CHARACTERISTICS (Each Path, Unless Otherwise Noted) (Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 4.75V to 5.25V, attenuators are set for maximum gain, RF ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, 100MHz P fRF P 500MHz, TC = -40NC to +85NC. Typical values are at maximum gain setting, VCC_ = 5.0V, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) (Note 6) PARAMETER Small-Signal Gain SYMBOL G CONDITIONS MIN 20.3 fRF = 100MHz 19.9 fRF = 200MHz 19.4 fRF = 350MHz, TC = +25NC 17.0 18.6 fRF = 750MHz 17.8 fRF = 900MHz 16.5 -0.01 Gain Flatness vs. Frequency NF Total Attenuation Range Output Second-Order Intercept Point OIP2 Path Isolation Output Third-Order Intercept Point OIP3 From 100MHz to 200MHz 0.5 Any 100MHz frequency band from 200MHz to 500MHz 0.34 fRF = 50MHz 6.4 fRF = 100MHz 6.8 fRF = 200MHz 7.3 fRF = 350MHz 7.6 fRF = 450MHz 7.8 fRF = 750MHz 8.7 P1dB MAX UNITS 21.0 dB dB/NC dB dB fRF = 900MHz 9.0 Analog and digital combined 64.1 dB POUT = 0dBm/tone, Df = 1MHz, f1 + f2 52.1 dBm RF input 1 amplified power measured at RF output 2 relative to RF output 1, all unused ports terminated to 50I 48.6 RF input 2 amplified signal measured at RF output 1 relative to RF output 2, all unused ports terminated to 50I 47.7 POUT = 0dBm/tone, Df = 1MHz, fRF = 50MHz 47.5 POUT = 0dBm/tone, Df = 1MHz, fRF = 100MHz 43.4 POUT = 0dBm/tone, Df = 1MHz, fRF = 200MHz 41.3 POUT = 0dBm/tone, Df = 1MHz, fRF = 350MHz 37.4 POUT = 0dBm/tone, Df = 1MHz, fRF = 450MHz 35.1 POUT = 0dBm/tone, Df = 1MHz, fRF = 750MHz 28.8 dB fRF = 350MHz, TC = +25NC (Note 7) dBm 25.8 POUT = 0dBm/tone, Df = 1MHz, fRF = 900MHz Output -1dB Compression Point 18.9 fRF = 450MHz Gain vs. Temperature Noise Figure TYP fRF = 50MHz 17 18.8 dBm _______________________________________________________________________________________ 3 MAX2062 RECOMMENDED AC OPERATING CONDITIONS MAX2062 Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA 5.0V SUPPLY AC ELECTRICAL CHARACTERISTICS (Each Path, Unless Otherwise Noted) (continued) (Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 4.75V to 5.25V, attenuators are set for maximum gain, RF ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, 100MHz P fRF P 500MHz, TC = -40NC to +85NC. Typical values are at maximum gain setting, VCC_ = 5.0V, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) (Note 6) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Second Harmonic POUT = +3dBm -55.0 dBc Third Harmonic POUT = +3dBm -72.7 dBc Group Delay Includes EV kit PCB delays 1.03 ns Amplifier Power-Down Time PD_1 or PD_2 from 0 to 1, amplifier DC supply current settles to within 0.1mA 0.5 Fs Amplifier Power-Up Time PD_1 or PD_2 from 1 to 0, amplifier DC supply current settles to within 1% 0.5 Fs 50I source 16.1 dB 50I load 30.8 dB 3.0 dB Input Return Loss Output Return Loss RLIN RLOUT DIGITAL ATTENUATOR (Each Path, Unless Otherwise Noted) Insertion Loss Input Second-Order Intercept Point PIN1 = 0dBm, PIN2 = 0dBm (minimum attenuation), Df = 1MHz, f1 + f2 53.6 dBm Input Third-Order Intercept Point PIN1 = 0dBm, PIN2 = 0dBm (minimum attenuation), Df = 1MHz 41.5 dBm Attenuation Range fRF = 350MHz, TC = +25NC, VCC = 5.0V 30.9 dB Step Size 29.5 1 dB Relative Attenuation Accuracy 0.13 dB Absolute Attenuation Accuracy 0.14 dB Insertion Phase Step fRF = 170MHz 0dB to 16dB 0 0dB to 24dB 1.1 0dB to 31dB 1.2 1.0 Degrees Amplitude Overshoot/Undershoot Between any two Elapsed time = 15ns states Elapsed time = 40ns Switching Speed RF settled to within Q0.1dB Input Return Loss 50I source 22.0 dB Output Return Loss 50I load 21.9 dB 0.05 31dB to 0dB 25 0dB to 31dB 21 dB ns ANALOG ATTENUATOR (Each Path, Unless Otherwise Noted) Insertion Loss 2.2 dB Input Second-Order Intercept Point PIN1 = 0dBm, PIN2 = 0dBm (minimum attenuation), Df = 1MHz, f1 + f2 61.9 dBm Input Third-Order Intercept Point PIN1 = 0dBm, PIN2 = 0dBm (minimum attenuation), Df = 1MHz 37.0 dBm 4 _______________________________________________________________________________________ Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA (Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 4.75V to 5.25V, attenuators are set for maximum gain, RF ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, 100MHz P fRF P 500MHz, TC = -40NC to +85NC. Typical values are at maximum gain setting, VCC_ = 5.0V, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) (Note 6) PARAMETER SYMBOL CONDITIONS MIN TYP 29.5 33.2 dB Analog control input -13.3 dB/V Maximum Gain Control Slope Over analog control input range -35.2 dB/V Insertion Phase Change Over analog control input range 17.6 Deg Attenuation Range fRF = 350MHz, TC = +25NC, VCC = 5.0V Gain Control Slope RF settled to within Q0.5dB Attenuator Response Time AA_SP = 0, VA_VCTL__ from 2.75V to 0.25V 500 AA_SP = 1, DAC code from 11111111 to 00000000, from CS rising edge 500 AA_SP = 0, VA_VCTL__ from 0.25V to 2.75V 500 AA_SP = 1, DAC code from 00000000 to 11111111, from CS rising edge 500 Analog Control Input Range UNITS ns Over analog control input from 0.25V to 2.75V Group Delay vs. Control Voltage MAX -0.34 0.25 Analog Control Input Impedance ns 2.75 V 19.2 kI Input Return Loss 50I source 16.1 dB Output Return Loss 50I load 16.8 dB D/A CONVERTER Number of Bits 8 DAC code = 00000000 Output Voltage DAC code = 11111111 Bits 0.35 2.7 V SERIAL PERIPHERAL INTERFACE (SPI) Maximum Clock Speed 20 MHz Data-to-Clock Setup Time tCS 2 ns Data-to-Clock Hold Time tCH 2.5 ns Clock-to-CS Setup Time tES 3 ns CS Positive Pulse Width tEW 7 ns CS Setup Time Clock Pulse Width tEWS 3.5 ns tCW 5 ns _______________________________________________________________________________________ 5 MAX2062 5.0V SUPPLY AC ELECTRICAL CHARACTERISTICS (Each Path, Unless Otherwise Noted) (continued) 3.3V SUPPLY AC ELECTRICAL CHARACTERISTICS (Each Path, Unless Otherwise Noted) (Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 3.135V to 3.465V, attenuators are set for maximum gain, RF ports are driven from 50I sources, AMPSET = 1, PD_1 = PD_2 = 0, 100MHz P fRF P 500MHz, TC = -40NC to +85NC. Typical values are at maximum gain setting, VCC_ = 3.3V, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) (Note 6) PARAMETER SYMBOL CONDITIONS MIN TYP Small-Signal Gain MAX UNITS 18.8 dB 29.4 dBm Noise Figure 7.8 dB Total Attenuation Range 64.1 dB Output Third-Order Intercept Point OIP3 POUT = 0dBm/tone Path Isolation Output -1dB Compression Point P1dB RF input 1 amplified power measured at RF output 2 relative to RF output 1, all unused ports terminated to 50I 49.1 RF input 2 amplified signal measured at RF output 1 relative to RF output 2, all unused ports terminated to 50I 48.0 (Note 7) 13.4 dB dBm Note 5: Operation outside this range is possible, but with degraded performance of some parameters. See the Typical Operating Characteristics section. Note 6: All limits include external component losses. Output measurements are performed at the RF output port of the Typical Application Circuit. Note 7: It is advisable not to continuously operate the RF input 1 or RF input 2 above +15dBm. Typical Operating Characteristics (Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 5.0V, attenuators are set for maximum gain, RF ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) SUPPLY CURRENT vs. VCC TC = +85C 20 19 18 TC = +25C 17 140 16 4.875 5.00 VCC (V) 5.125 5.250 VCC = 4.75V, 5.00V, 5.25V 19 18 17 TC = +85C 16 15 130 4.750 21 GAIN (dB) TC = +25C MAX2062 toc03 TC = -40C 20 GAIN (dB) 150 NOTCH DUE TO SELF-RESONANCE OF BIAS COIL. SEE TABLE 7. 21 22 MAX2062 toc02 TC = -40C 160 GAIN vs. RF FREQUENCY GAIN vs. RF FREQUENCY 22 MAX2062 toc01 170 SUPPLY CURRENT (mA) MAX2062 Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA 15 14 14 50 250 450 650 RF FREQUENCY (MHz) 850 1050 50 250 450 650 RF FREQUENCY (MHz) 6 _______________________________________________________________________________________ 850 1050 Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA DIGITAL ATTENUATOR RELATIVE ERROR vs. RF FREQUENCY -8 0.25 0 -0.25 450 650 850 1050 0.25 0 -0.25 -0.75 -1.00 250 0.50 -0.50 ERROR FROM 23dB TO 24dB -0.75 -18 MAX2062 toc06 MAX2062 toc05 0.50 0.75 -0.50 -1.00 50 250 450 650 850 1050 50 250 450 650 1050 850 RF FREQUENCY (MHz) RF FREQUENCY (MHz) INPUT MATCH OVER DIGITAL ATTENUATOR SETTING vs. RF FREQUENCY OUTPUT MATCH OVER DIGITAL ATTENUATOR SETTING vs. RF FREQUENCY CHANNEL-TO-CHANNEL ISOLATION vs. RF FREQUENCY 8dB, 16dB -20 -30 31dB -40 4dB 2dB -50 0 200 400 600 800 1000 -10 -20 2dB 0dB, 1dB, 4dB, 8dB -30 -40 BOTH DIGITAL ATTENUATORS = 31dB 30 40 50 BOTH DIGITAL ATTENUATORS = 0dB 60 70 BOTH ANALOG ATTENUATORS = 0dB 16dB, 31dB -50 80 0 200 400 600 800 1000 50 250 450 650 850 RF FREQUENCY (MHz) REVERSE ISOLATION OVER DIGITAL ATTENUATOR SETTING vs. RF FREQUENCY DIGITAL ATTENUATOR PHASE CHANGE BETWEEN STATES vs. RF FREQUENCY GAIN OVER ANALOG ATTENUATOR SETTING vs. RF FREQUENCY DIGITAL ATTENUATOR 0dB 50 DIGITAL ATTENUATOR 31dB 60 70 80 REFERENCED TO HIGH GAIN STATE 40 30 20 10 0 -10 -20 POSITIVE PHASE = ELECTRICALLY SHORTER -30 50 250 450 650 RF FREQUENCY (MHz) 850 1050 MAX2062 toc11 MAX2062 toc10 40 50 50 250 450 650 RF FREQUENCY (MHz) 850 1050 22 1050 MAX2062 toc12 RF FREQUENCY (MHz) GAIN OVER ANALOG ATTENUATOR SETTING (dB) RF FREQUENCY (MHz) 30 MAX2062 toc09 1dB 20 CHANNEL-TO-CHANNEL ISOLATION (dB) 0dB -10 0 MAX2062 toc08 0 OUTPUT MATCH OVER DIGITAL ATTENUATOR SETTING (dB) RF FREQUENCY (MHz) MAX2062 toc07 INPUT MATCH OVER DIGITAL ATTENUATOR SETTING (dB) 1.00 ABSOLUTE ERROR (dB) 2 50 REVERSE ISOLATION OVER DIGITAL ATTENUATOR SETTING (dB) 0.75 RELATIVE ERROR (dB) 12 DIGITAL ATTENUATOR ABSOLUTE ERROR vs. RF FREQUENCY 1.00 MAX2062 toc04 22 DIGITAL ATTENUATOR PHASE CHANGE BETWEEN STATES (DEGREES) GAIN OVER DIGITAL ATTENUATOR SETTING (dB) GAIN OVER DIGITAL ATTENUATOR SETTING vs. RF FREQUENCY DAC CODE 64 17 12 DAC CODE 32 7 DAC CODE 0 2 -3 -8 DAC CODE 128 DAC CODE 255 250 650 -13 -18 50 450 850 1050 RF FREQUENCY (MHz) _______________________________________________________________________________________ 7 MAX2062 Typical Operating Characteristics (continued) (Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 5.0V, attenuators are set for maximum gain, RF ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) Typical Operating Characteristics (continued) (Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 5.0V, attenuators are set for maximum gain, RF ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) GAIN vs. ANALOG ATTENUATOR SETTING 12 200MHz GAIN (dB) 7 350MHz 1000MHz 7 2 -8 -8 -8 -13 -13 -13 -18 64 96 128 160 192 224 256 -18 0 32 64 96 128 160 192 224 256 0 96 128 160 192 224 256 OUTPUT MATCH vs. ANALOG ATTENUATOR SETTING CHANNEL-TO-CHANNEL ISOLATION vs. RF FREQUENCY -20 -10 OUTPUT MATCH (dB) -15 350MHz -20 50MHz, 200MHz, 350MHz -30 -40 1000MHz -25 1000MHz 64 96 128 160 192 224 256 0 32 64 96 REVERSE ISOLATION OVER ANALOG ATTENUATOR SETTING vs. RF FREQUENCY S21 PHASE CHANGE vs. ANALOG ATTENUATOR SETTING 50 DAC CODE 255 60 70 80 80 S21 PHASE CHANGE (DEGREES) MAX2062 toc19 DAC CODE 0 REFERENCED TO HIGH GAIN STATE 60 40 250 450 650 RF FREQUENCY (MHz) 850 1050 50 60 BOTH ANALOG ATTENUATORS = CODE 0 70 BOTH DIGITAL ATTENUATORS = 0dB 1000MHz 350MHz POSITIVE PHASE = ELECTRICALLY SHORTER 32 64 96 128 160 192 224 256 ANALOG ATTENUATOR SETTING (DAC CODE) 850 TC = +85C 10 TC = +25C 9 1050 8 7 6 TC = -40C 5 50MHz 0 650 NOISE FIGURE vs. RF FREQUENCY 200MHz -60 450 11 0 -20 250 RF FREQUENCY (MHz) 20 -40 90 40 50 MAX2062 toc20 ANALOG ATTENUATOR SETTING (DAC CODE) 40 30 128 160 192 224 256 ANALOG ATTENUATOR SETTING (DAC CODE) 30 BOTH ANALOG ATTENUATORS = CODE 255 20 80 -50 32 NOISE FIGURE (dB) -30 10 CHANNEL-TO-CHANNEL ISOLATION (dB) MAX2062 toc16 200MHz -10 0 MAX2062 toc18 INPUT MATCH vs. ANALOG ATTENUATOR SETTING MAX2062 toc17 ANALOG ATTENUATOR SETTING (DAC CODE) 50MHz 50 64 ANALOG ATTENUATOR SETTING (DAC CODE) -5 0 32 ANALOG ATTENUATOR SETTING (DAC CODE) 0 MAX2062 toc15 2 -3 32 VCC = 4.75V, 5.00V, 5.25V 7 -3 0 INPUT MATCH (dB) 12 TC = -40C, +25C, +85C -3 -18 fRF = 350MHz 17 MAX2062 toc21 2 fRF = 350MHz 17 GAIN vs. ANALOG ATTENUATOR SETTING 22 GAIN (dB) 12 GAIN (dB) MAX2062 toc13 50MHz 17 22 MAX2062 toc14 GAIN vs. ANALOG ATTENUATOR SETTING 22 REVERSE ISOLATION OVER ANALOG ATTENUATOR SETTING (dB) MAX2062 Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA 4 50 250 450 650 RF FREQUENCY (MHz) 8 _______________________________________________________________________________________ 850 1050 Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA OUTPUT P1dB vs. RF FREQUENCY 6 TC = +85C 15 TC = +25C 13 5 11 250 450 650 850 1050 250 RF FREQUENCY (MHz) OUTPUT IP3 vs. RF FREQUENCY POUT = 0dBm/TONE 40 TC = -40C 35 TC = +85C 30 650 850 40 35 VCC = 4.75V 44 250 fRF = 350MHz 850 TC = +25C LSB, USB TC = +85C LSB, USB 84 126 168 ANALOG ATTENUATOR STATE (DAC CODE) POUT = -3dBm/TONE 0 210 4 8 12 16 20 24 28 POUT = 3dBm 2ND HARMONIC vs. RF FREQUENCY 60 TC = +25C 50 TC = -40C 70 POUT = 3dBm 60 VCC = 5.25V VCC = 5.00V 50 VCC = 4.75V 40 30 25 42 TC = +85C LSB TC = +85C USB 30 1050 40 30 0 36 DIGITAL ATTENUATOR STATE (dB) TC = +85C 2ND HARMONIC (dBc) 40 35 38 2ND HARMONIC vs. RF FREQUENCY POUT = -3dBm/TONE TC = -40C LSB, USB TC = +25C LSB, USB 34 650 70 MAX2062 toc28 45 450 1050 TC = -40C LSB TC = -40C USB 40 RF FREQUENCY (MHz) RF FREQUENCY (MHz) OUTPUT IP3 vs. ANALOG ATTENUATOR STATE fRF = 350MHz 42 32 50 1050 850 OUTPUT IP3 vs. DIGITAL ATTENUATOR STATE 2ND HARMONIC (dBc) 450 650 OUTPUT IP3 vs. RF FREQUENCY MAX2062 toc29 250 450 RF FREQUENCY (MHz) VCC = 5.25V 30 250 50 RF FREQUENCY (MHz) 20 50 VCC = 5.00V 1050 25 20 OUTPUT IP3 (dBm) 850 VCC = 5.00V TC = +25C 25 650 POUT = 0dBm/TONE 45 OUTPUT IP3 (dBm) OUTPUT IP3 (dBm) 45 450 50 MAX2062 toc25 50 15 11 50 OUTPUT IP3 (dBm) 50 VCC = 4.75V 13 MAX2062 toc26 4 17 MAX2062 toc27 7 17 MAX2062 toc30 8 VCC = 5.25V 19 OUTPUT P1dB (dBm) 9 TC = -40C 19 OUTPUT P1dB (dBm) NOISE FIGURE (dB) VCC = 4.75V, 5.00V, 5.25V 21 MAX2062 toc23 MAX2062 toc22 10 OUTPUT P1dB vs. RF FREQUENCY 21 MAX2062 toc24 NOISE FIGURE vs. RF FREQUENCY 11 30 50 250 450 650 RF FREQUENCY (MHz) 850 1050 50 250 450 650 850 1050 RF FREQUENCY (MHz) _______________________________________________________________________________________ 9 MAX2062 Typical Operating Characteristics (continued) (Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 5.0V, attenuators are set for maximum gain, RF ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) Typical Operating Characteristics (continued) (Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 5.0V, attenuators are set for maximum gain, RF ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) TC = -40C TC = +25C 50 TC = +85C 55 90 TC = -40C 50 45 8 12 16 20 24 28 126 168 3RD HARMONIC vs. DIGITAL ATTENUATOR STATE MAX2062 toc34 3RD HARMONIC vs. RF FREQUENCY 85 VCC = 5.00V 70 VCC = 4.75V TC = +85C 80 75 250 450 650 850 1050 RF FREQUENCY (MHz) 3RD HARMONIC vs. ANALOG ATTENUATOR STATE POUT = 0dBm TC = -40C 50 90 TC = +25C TC = +85C POUT = 0dBm TC = -40C 85 3RD HARMONIC (dBc) VCC = 5.25V 70 210 fRF = 350MHz 3RD HARMONIC (dBc) 90 60 84 ANALOG ATTENUATOR STATE (DAC CODE) POUT = 3dBm 80 42 DIGITAL ATTENUATOR STATE (dB) 100 TC = +25C 50 0 MAX2062 toc35 4 TC = -40C 80 60 45 0 3RD HARMONIC (dBc) TC = +25C 60 POUT = 3dBm TC = +25C fRF = 350MHz MAX2062 toc36 55 fRF = 350MHz 3RD HARMONIC (dBc) 60 POUT = 0dBm 65 2ND HARMONIC (dBc) 2ND HARMONIC (dBc) fRF = 350MHz 3RD HARMONIC vs. RF FREQUENCY 100 MAX2062 toc32 POUT = 0dBm TC = +85C 70 MAX2062 toc31 65 2ND HARMONIC vs. ANALOG ATTENUATOR STATE MAX2062 toc33 2ND HARMONIC vs. DIGITAL ATTENUATOR STATE 80 75 TC = +85C 70 65 450 650 850 60 70 1050 0 RF FREQUENCY (MHz) 8 12 16 20 24 MAX2062 toc37 70 60 VCC = 5.25V OIP2 (dBm) TC = +25C 50 50 VCC = 5.00V TC = -40C 40 30 65 168 210 POUT = -3dBm/TONE fRF = 350MHz 60 TC = +85C 55 TC = +25C 50 650 RF FREQUENCY (MHz) 850 1050 TC = -40C 45 40 30 450 126 VCC = 4.75V 40 250 84 OIP2 vs. DIGITAL ATTENUATOR STATE POUT = 0dBm/TONE 60 42 ANALOG ATTENUATOR STATE (DAC CODE) OIP2 vs. RF FREQUENCY POUT = 0dBm/TONE TC = +85C 50 0 28 DIGITAL ATTENUATOR STATE (dB) OIP2 vs. RF FREQUENCY 70 4 OIP2 (dBm) 250 MAX2062 toc38 50 MAX2062 toc39 50 OIP2 (dBm) MAX2062 Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA 50 250 450 650 RF FREQUENCY (MHz) 850 1050 0 4 8 12 16 20 24 DIGITAL ATTENUATOR STATE (dB) 10 28 Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA OIP2 vs. ANALOG ATTENUATOR STATE 50 TC = -40C 45 40 2.0 1.5 1.0 TC = -40C, +25C, +85C 0.5 42 0 84 126 168 32 64 DAC VOLTAGE DRIFT vs. DAC CODE 0 -0.01 TC CHANGED FROM +25C TO +85C -0.03 0 -0.04 -0.0075 -0.05 0.0100 0 32 64 96 128 160 192 224 256 VCC CHANGED FROM 5.00V TO 4.75V 0 32 64 96 GAIN vs. RF FREQUENCY (DIGITAL ATTENUATOR ONLY) GAIN vs. RF FREQUENCY (ANALOG ATTENUATOR ONLY) GAIN (dB) -1 VCC = 4.75V, 5.00V, 5.25V -3 -4 -2 -3 250 450 650 RF FREQUENCY (MHz) 850 1050 MAX2062 toc42 250 450 650 850 0 -1 1050 -2 -3 VCC = 4.75V, 5.00V, 5.25V TC = +25C -4 -5 50 TC = +25C GAIN vs. RF FREQUENCY (ANALOG ATTENUATOR ONLY) -4 -5 50 TC = -40C TC = +85C TC = +85C RF FREQUENCY (MHz) 0 MAX2062 toc46 -2 -3 -5 128 160 192 224 256 DAC CODE -1 TC = -40C -2 -4 DAC CODE 0 -1 0.0025 -0.0050 128 160 192 224 256 0 VCC CHANGED FROM 5.00V TO 5.25V -0.0025 96 GAIN vs. RF FREQUENCY (DIGITAL ATTENUATOR ONLY) GAIN (dB) -0.02 64 DAC VOLTAGE DRIFT vs. DAC CODE 0.0075 0.0050 32 DAC CODE GAIN (dB) 0.01 VCC = 4.75V, 5.00V, 5.25V 0 MAX2062 toc44 MAX2062 toc43 TC CHANGED FROM +25C TO -40C 0.02 128 160 192 224 256 MAX2062 toc47 DAC VOLTAGE DRIFT (V) 0.03 96 0.0100 DAC VOLTAGE DRIFT (V) 0.04 1.0 DAC CODE ANALOG ATTENUATOR STATE (DAC CODE) 0.05 1.5 0 0 210 2.0 0.5 0 35 GAIN (dB) 2.5 MAX2062 toc45 DAC VOLTAGE (V) OIP2 (dBm) TC = +25C 2.5 MAX2062 toc48 fRF = 350MHz 55 DAC VOLTAGE (V) POUT = -3dBm/TONE DAC VOLTAGE vs. DAC CODE 3.0 MAX2062 toc41 TC = +85C DAC VOLTAGE vs. DAC CODE 3.0 MAX2062 toc40 60 -5 50 250 450 650 RF FREQUENCY (MHz) 850 1050 50 250 450 650 850 1050 RF FREQUENCY (MHz) ______________________________________________________________________________________ 11 MAX2062 Typical Operating Characteristics (continued) (Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 5.0V, attenuators are set for maximum gain, RF ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) Typical Operating Characteristics (continued) (Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 3.3V, attenuators are set for maximum gain, RF ports are driven from 50I sources, AMPSET = 1, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) SUPPLY CURRENT vs. VCC GAIN vs. RF FREQUENCY 19 18 TC = +85C 17 3.2 3.1 3.3 3.4 MAX2062 toc51 VCC = 3.135V 17 16 16 15 15 14 3.5 18 VCC = 3.30V 14 50 250 450 650 850 1050 250 50 450 650 850 RF FREQUENCY (MHz) INPUT MATCH OVER DIGITAL ATTENUATOR SETTING vs. RF FREQUENCY OUTPUT MATCH OVER DIGITAL ATTENUATOR SETTING vs. RF FREQUENCY INPUT MATCH vs. ANALOG ATTENUATOR SETTING 1dB 8dB, 16dB -20 -30 4dB 31dB -40 2dB -50 200 0 400 600 800 1000 -10 2dB -20 -30 0dB, 1dB, 4dB, 8dB 1000MHz 50MHz, 200MHz, 350MHz -40 200 400 600 800 1000 32 64 96 0 VCC = 3.3V TC = +85C 10 128 160 192 224 256 ANALOG ATTENUATOR SETTING (DAC CODE) 64 96 128 160 192 224 256 NOISE FIGURE vs. RF FREQUENCY 9 8 7 TC = -40C 6 32 ANALOG ATTENUATOR SETTING (DAC CODE) 11 VCC = 3.30V 10 VCC = 3.135V 9 8 7 VCC = 3.465V 6 TC = +25C 5 4 -50 350MHz 1000MHz -30 0 5 0 -20 NOISE FIGURE vs. RF FREQUENCY NOISE FIGURE (dB) -10 200MHz -15 -25 11 MAX2062 toc55 VCC = 3.3V -30 50MHz -10 RF FREQUENCY (MHz) OUTPUT MATCH vs. ANALOG ATTENUATOR SETTING -20 -5 -50 RF FREQUENCY (MHz) 0 VCC = 3.3V 16dB, 31dB -40 1050 0 INPUT MATCH (dB) -10 VCC = 3.3V NOISE FIGURE (dB) 0dB 0 MAX2062 toc53 VCC = 3.3V MAX2062 toc56 0 OUTPUT MATCH OVER DIGITAL ATTENUATOR SETTING (dB) RF FREQUENCY (MHz) MAX2062 toc52 VCC (V) MAX2062 toc54 TC = +85C VCC = 3.465V 19 MAX2062 toc57 80 60 INPUT MATCH OVER DIGITAL ATTENUATOR SETTING (dB) 20 TC = +25C GAIN (dB) 90 70 21 20 TC = +25C 100 TC = -40C 22 MAX2062 toc50 TC = -40C GAIN vs. RF FREQUENCY VCC = 3.3V 21 GAIN (dB) SUPPLY CURRENT (mA) 110 22 MAX2062 toc49 120 OUTPUT MATCH (dB) MAX2062 Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA 4 50 250 450 650 RF FREQUENCY (MHz) 850 1050 50 250 450 650 RF FREQUENCY (MHz) 12 850 1050 Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA 12 10 TC = +85C 8 VCC = 3.465V 10 8 6 VCC = 3.135V 250 450 650 850 1050 TC = +25C 25 TC = +85C 20 10 250 50 450 650 850 1050 250 50 450 650 850 RF FREQUENCY (MHz) OUTPUT IP3 vs. RF FREQUENCY OUTPUT IP3 vs. DIGITAL ATTENUATOR STATE OUTPUT IP3 vs. ANALOG ATTENUATOR STATE 32 30 OUTPUT IP3 (dBm) VCC = 3.30V 25 20 VCC = 3.135V POUT = -3dBm/TONE fRF = 350MHz VCC = 3.3V TC = -40C LSB, USB 30 TC = +25C LSB, USB 28 35 fRF = 350MHz TC = -40C LSB, USB OUTPUT IP3 (dBm) VCC = 3.465V 34 MAX2062 toc62 POUT = 0dBm/TONE MAX2062 toc61 RF FREQUENCY (MHz) 15 1050 POUT = -3dBm/TONE VCC = 3.3V 30 TC = +25C LSB, USB 25 TC = +85C LSB, USB 26 TC = +85C LSB, USB 450 650 850 20 24 1050 0 RF FREQUENCY (MHz) 2ND HARMONIC vs. RF FREQUENCY TC = +85C POUT = 3dBm VCC = 3.3V TC = +25C 45 35 25 16 20 24 250 450 650 RF FREQUENCY (MHz) 850 1050 84 126 ANALOG ATTENUATOR STATE (DAC CODE) 2ND HARMONIC vs. RF FREQUENCY 2ND HARMONIC vs. DIGITAL ATTENUATOR STATE 70 POUT = 0dBm fRF = 350MHz VCC = 3.3V 55 VCC = 3.135V 45 VCC = 3.30V 50 168 DIGITAL ATTENUATOR STATE (dB) 25 50 42 0 28 POUT = 3dBm 35 TC = -40C 12 VCC = 3.465V 2ND HARMONIC (dBc) 55 8 65 MAX2062 toc64 65 4 2ND HARMONIC (dBc) 250 MAX2062 toc65 50 250 450 650 RF FREQUENCY (MHz) 850 1050 60 210 MAX2062 toc66 10 2ND HARMONIC (dBc) 30 RF FREQUENCY (MHz) 40 35 VCC = 3.3V 15 6 50 OUTPUT IP3 (dBm) 12 POUT = 0dBm/TONE TC = -40C 35 MAX2062 toc63 TC = +25C 14 OUTPUT P1dB (dBm) OUTPUT P1dB (dBm) 14 VCC = 3.30V OUTPUT IP3 (dBm) VCC = 3.3V OUTPUT IP3 vs. RF FREQUENCY 40 MAX2062 toc59 MAX2062 toc58 TC = -40C OUTPUT P1dB vs. RF FREQUENCY 16 MAX2062 toc60 OUTPUT P1dB vs. RF FREQUENCY 16 TC = +85C TC = +25C TC = -40C 50 40 0 4 8 12 16 20 24 28 DIGITAL ATTENUATOR STATE (dB) ______________________________________________________________________________________ 13 MAX2062 Typical Operating Characteristics (continued) (Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 3.3V, attenuators are set for maximum gain, RF ports are driven from 50I sources, AMPSET = 1, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) Typical Operating Characteristics (continued) (Typical Application Circuit, VCC = VCC_AMP_1 = VCC_AMP_2 = VCC_RG = 3.3V, attenuators are set for maximum gain, RF ports are driven from 50I sources, AMPSET = 1, PD_1 = PD_2 = 0, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) 3RD HARMONIC vs. RF FREQUENCY TC = -40C 50 TC = +25C 60 50 70 VCC = 3.30V 60 VCC = 3.135V 50 TC = +85C 40 84 126 210 250 50 450 650 850 ANALOG ATTENUATOR STATE (DAC CODE) RF FREQUENCY (MHz) 3RD HARMONIC vs. DIGITAL ATTENUATOR STATE 3RD HARMONIC vs. ANALOG ATTENUATOR STATE VCC = 3.3V 65 TC = +25C 60 55 TC = -40C 70 VCC = 3.3V 8 12 16 20 24 DIGITAL ATTENUATOR STATE (dB) 126 168 OIP2 (dBm) 40 250 VCC = 3.3V TC = +85C 50 450 650 850 1050 RF FREQUENCY (MHz) OIP2 vs. ANALOG ATTENUATOR STATE 70 POUT = -3dBm/TONE fRF = 350MHz VCC = 3.3V TC = +85C 60 TC = +25C 40 30 TC = -40C 50 210 POUT = -3dBm/TONE fRF = 350MHz 60 VCC = 3.30V 50 84 70 MAX2062 toc73 VCC = 3.465V 40 OIP2 vs. DIGITAL ATTENUATOR STATE POUT = 0dBm/TONE 60 TC = +25C 50 ANALOG ATTENUATOR STATE (DAC CODE) OIP2 vs. RF FREQUENCY 70 1050 20 42 0 28 OIP2 (dBm) 4 850 VCC = 3.3V TC = +85C 30 TC = +85C MAX2062 toc74 0 650 POUT = 0dBm/TONE 60 50 50 450 OIP2 vs. RF FREQUENCY TC = +25C 55 TC = +85C 250 70 65 60 50 RF FREQUENCY (MHz) POUT = 0dBm fRF = 350MHz 3RD HARMONIC (dBc) TC = -40C 70 1050 OIP2 (dBm) POUT = 0dBm fRF = 350MHz 75 MAX2062 toc70 75 3RD HARMONIC (dBc) 168 40 MAX2062 toc71 42 0 VCC = 3.465V 40 MAX2062 toc72 TC = +25C TC = -40C POUT = 3dBm MAX2062 toc75 TC = +85C 70 3RD HARMONIC (dBc) 60 POUT = 3dBm VCC = 3.3V 3RD HARMONIC (dBc) 2ND HARMONIC (dBc) VCC = 3.3V 3RD HARMONIC vs. RF FREQUENCY 80 MAX2062 toc68 POUT = 0dBm fRF = 350MHz 80 MAX2062 toc67 70 MAX2062 toc69 2ND HARMONIC vs. ANALOG ATTENUATOR STATE OIP2 (dBm) MAX2062 Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA TC = +25C 50 40 VCC = 3.135V TC = -40C 20 30 50 250 450 650 RF FREQUENCY (MHz) 850 1050 TC = -40C 30 0 4 8 12 16 20 24 DIGITAL ATTENUATOR STATE (dB) 28 0 42 84 126 168 ANALOG ATTENUATOR STATE (DAC CODE) 14 210 Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA GND AMP_IN_2 PD_2 GND AMP_OUT_2 REG_OUT AMPSET AMP_OUT_1 GND PD_1 AMP_IN_1 GND TOP VIEW 36 35 34 33 32 31 30 29 28 27 26 25 VCC_AMP_2 VCC_AMP_1 37 24 A_ATT_OUT_1 38 23 A_ATT_OUT_2 A_VCTL_1 39 22 A_VCTL_2 AA_SP 40 21 DA_SP A_ATT_IN_1 41 20 A_ATT_IN_2 D4_1 42 19 D4_2 MAX2062 D_ATT_OUT_1 43 18 D_ATT_OUT_2 D3_1 44 17 D3_2 D2_1 45 16 D2_2 D1_1 46 15 D1_2 D0_1 47 14 D0_2 13 GND 8 9 10 11 12 GND DAT 7 D_ATT_IN_2 STA_B_1 6 STA_A_2 5 VCC_RG 4 STA_B_2 3 CS 2 CLK 1 STA_A_1 + D_ATT_IN_1 48 GND GND EP TQFN Pin Description PIN NAME 1, 12, 13, 25, 28, 33, 36, 48 FUNCTION GND 2 D_ATT_IN_1 3 STA_A_1 4 STA_B_1 5 DAT SPI Data Digital Input 6 CLK SPI Clock Digital Input 7 CS 8 VCC_RG Ground 5-Bit Digital Attenuator Input (50I), Path 1. Requires a DC-blocking capacitor. Digital Attenuator Preprogrammed Attenuation-State Logic Input, Path 1 State A State B Digital Attenuator Logic = 0 Logic = 0 Preprogrammed State 1 Logic = 1 Logic = 0 Preprogrammed State 2 Logic = 0 Logic = 1 Preprogrammed State 3 Logic = 1 Logic = 1 Preprogrammed State 4 SPI Chip-Select Digital Input Regulator Supply Input. Connect to a 3.3V or 5V external power supply. VCC_RG powers all circuits except for the driver amplifiers. Bypass with a 10nF capacitor as close as possible to the pin. ______________________________________________________________________________________ 15 MAX2062 Pin Configuration MAX2062 Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA Pin Description (continued) PIN NAME FUNCTION Digital Attenuator Preprogrammed Attenuation-State Logic Input, Path 2 State A State B Digital Attenuator Logic = 0 Logic = 0 Preprogrammed State 1 Logic = 1 Logic = 0 Preprogrammed State 2 Logic = 0 Logic = 1 Preprogrammed State 3 Logic = 1 Logic = 1 Preprogrammed State 4 9 STA_B_2 10 STA_A_2 11 D_ATT_IN_2 14 D0_2 1dB Attenuator Logic Input, Path 2. Logic 0 = disable, logic 1 = enable. 15 D1_2 2dB Attenuator Logic Input, Path 2. Logic 0 = disable, logic 1 = enable. 16 D2_2 4dB Attenuator Logic Input, Path 2. Logic 0 = disable, logic 1 = enable. 17 D3_2 8dB Attenuator Logic Input, Path 2. Logic 0 = disable, logic 1 = enable. 18 D_ATT_OUT_2 19 D4_2 20 A_ATT_IN_2 21 DA_SP Digital Attenuator Serial/Parallel Control Select. Set DA_SP to logic 1 to select serial control. Set DA_SP to logic 0 to select parallel control. 22 A_VCTL_2 Analog Attenuator Voltage Control Input, Path 2. Bypass to ground with a 150pF capacitor if on-chip DAC is used (AA_SP = 1). 23 A_ATT_OUT_2 Analog Attenuator Output (50I), Path 2. Requires a DC-blocking capacitor. Connect to AMP_IN_2 through a 1000pF capacitor. 24 VCC_AMP_2 Driver Amplifier Supply Voltage Input, Path 2. Bypass with a 10nF capacitor as close as possible to the pin. 26 AMP_IN_2 Driver Amplifier Input (50I), Path 2. Requires a DC-blocking capacitor. Connect to A_ATT_OUT_2 through a 1000pF capacitor. 27 29 PD_2 5-Bit Digital Attenuator Output (50I), Path 2. Requires a DC-blocking capacitor. Connect to A_ATT_IN_2 through a 1000pF capacitor. 16dB Attenuator Logic Input, Path 2. Logic 0 = disable, logic 1 = enable. Analog Attenuator Input (50I), Path 2. Requires a DC-blocking capacitor. Connect to D_ATT_OUT_2 through a 1000pF capacitor. Power-Down, Path 2. See Table 2 for operation details. AMP_OUT_2 Driver Amplifier Output (50I), Path 2. Connect a pullup inductor from AMP_OUT_2 to VCC_. 30 REG_OUT 31 AMPSET 32 5-Bit Digital Attenuator Input (50I), Path 2. Requires a DC-blocking capacitor. Regulator Output. Bypass with 1FF capacitor. Driver Amplifier Bias Setting for 3.3V Operation. Set to logic 1 for 3.3V operation on pins VCC_AMP_1 and VCC_AMP_2. Set to logic 0 for 5V operation. AMP_OUT_1 Driver Amplifier Output (50I), Path 1. Connect a pullup inductor from AMP_OUT_1 to VCC_. 34 PD_1 Power-Down, Path 1. See Table 2 for operation details. 35 AMP_IN_1 Driver Amplifier Input (50I), Path 1. Requires a DC-blocking capacitor. Connect to A_ATT_OUT_1 through a 1000pF capacitor. 37 VCC_AMP_1 Driver Amplifier Supply Voltage Input, Path 1. Bypass with a 10nF capacitor as close as possible to the pin. 38 A_ATT_OUT_1 Analog Attenuator Output (50I), Path 1. Requires a DC-blocking capacitor. Connect to AMP_IN_1 through a 1000pF capacitor. 39 A_VCTL_1 Analog Attenuator Voltage Control Input, Path 1. Bypass to ground with a 150pF capacitor if on-chip DAC is used (AA_SP = 1). 16 Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA PIN NAME FUNCTION DAC Enable/Disable Logic Input for Analog Attenuators. Set AA_SP to logic 1 to enable on-chip DAC circuit and digital SPI control. Set AA_SP to logic 0 to disable DAC circuit and digital SPI control. When AA_SP = 0, use analog control lines (A_VCTL_1 and A_VCTL_2). 40 AA_SP 41 A_ATT_IN_1 42 D4_1 43 D_ATT_OUT_1 44 D3_1 8dB Attenuator Logic Input, Path 1. Logic 0 = disable, logic 1 = enable. 45 D2_1 4dB Attenuator Logic Input, Path 1. Logic 0 = disable, logic 1 = enable. 46 D1_1 2dB Attenuator Logic Input, Path 1. Logic 0 = disable, logic 1 = enable. 47 D0_1 1dB Attenuator Logic Input, Path 1. Logic 0 = disable, logic 1 = enable. -- EP Analog Attenuator Input (50I), Path 1. Requires a DC-blocking capacitor. Connect to D_ATT_OUT_1 through a 1000pF capacitor. 16dB Attenuator Logic Input, Path 1. Logic 0 = disable, logic 1 = enable. 5-Bit Digital Attenuator Output (50I), Path 1. Requires a DC-blocking capacitor. Connect to A_ATT_IN_1 through a 1000pF capacitor. Exposed Pad. Internally connected to GND. Connect to GND for proper RF performance and enhanced thermal dissipation. Detailed Description The MAX2062 high-linearity analog/digital VGA is a general-purpose, high-performance amplifier designed to interface with 50I systems operating in the 50MHz to 1000MHz frequency range. Each channel of the device integrates one digital attenuator and one analog attenuator to provide 64dB of total gain control, as well as a driver amplifier optimized to provide high gain, high IP3, low NF, and low power consumption. Each digital attenuator is controlled as a slave peripheral using either the SPI-compatible interface, or a 5-bit parallel bus with 31dB total adjustment range in 1dB steps. An added feature allows rapid-fire gain selection among each of the four steps, preprogrammed by the user through the SPI-compatible interface. A separate 2-pin control lets the user quickly access any one of four customized attenuation states without reprogramming the SPI bus. Each analog attenuator is controlled using an external voltage or through the SPI-compatible interface using an on-chip 8-bit DAC. See the Applications Information section for attenuator programming details. Because each of the three stages in the separate signal paths has its own RF input and RF output, this component can be configured to either optimize NF (amplifier configured first), OIP3 (amplifier last), or a compromise of NF and OIP3. The device's performance features include 24dB amplifier gain (amplifier only), 7.3dB NF at maximum gain (includes attenuator insertion losses), and a high OIP3 level of +41dBm. Each of these features makes the device an ideal VGA for multipath receiver and transmitter applications. In addition, the device operates from a single +5V supply with full performance, or a +3.3V supply for an enhanced power-savings mode with lower performance. The device is available in a compact 48-pin TQFN package (7mm x 7mm) with an exposed pad. Electrical performance is guaranteed over the extended temperature range (TC = -40NC to +85NC). Analog and 5-Bit Digital Attenuator Control The device integrates two analog attenuators and two 5-bit digital attenuators to achieve a high level of dynamic range. Each analog attenuator has a 33dB range and is controlled using an external voltage or through the 3-wire SPI interface using an on-chip 8-bit DAC. Each digital attenuator has a 31dB control range, a 1dB step size, and is programmed either through the 3-wire SPI or through a separate 5-bit parallel bus. See the Applications Information section and Table 1 for attenuator programming details. The attenuators can be used for both static and dynamic power control. Note that when the analog attenuators are controlled by the DACs through the SPI bus, the DAC output voltage shows on pins A_VCTL_1 and A_VCTL_2 (pins 39 and 22, respectively). Therefore, in SPI mode, the A_VCTL_1 and A_VCTL_2 pins must only connect to the resistor and capacitor to ground, as shown in the Typical Application Circuit. ______________________________________________________________________________________ 17 MAX2062 Pin Description (continued) MAX2062 Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA Table 1. Control Logic AA_SP ANALOG ATTENUATOR D/A CONVERTER 0 Controlled by external control voltage Disabled 1 Controlled by on-chip DAC Enabled (DAC output voltage shows on A_VCTL__ pins); DAC uses on-chip voltage reference DA_SP DIGITAL ATTENUATOR 0 Parallel controlled 1 SPI controlled (control voltages show up on the parallel control pins) Driver Amplifier Each path of the device includes a high-performance driver with a fixed gain of 24dB. The driver amplifier circuits are optimized for high linearity for the 50MHz to 1000MHz frequency range. Applications Information Operating Modes The device features an optional +3.3V supply voltage operation with reduced linearity performance. The AMPSET pin needs to be biased accordingly in each mode, as listed in Table 2. In addition, the driver amplifiers can be shut down independently to conserve DC power. See the biasing scheme outlined in Table 2 for details. Path 1 DAC and Digital Attenuator Programming D0:D7 Sent to DAC register D0 = LSB, D7 = MSB D8:D12 Preprogrammed Attenuation State 1 D8 = 1dB bit, D9 = 2dB Bit, D10 = 4dB bit, D11 = 8dB bit, D12 = 16dB bit D13:D17 Preprogrammed Attenuation State 2 D13 = 1dB bit, D14 = 2dB bit, D15 = 4dB bit, D16 = 8dB bit, D17 = 16dB bit D18:D22 Preprogrammed Attenuation State 3 D18 = 1dB bit, D19 = 2dB bit, D20 = 4dB bit, D21 = 8dB bit, D22 = 16dB bit D23:D27 Preprogrammed Attenuation State 4 D23 = 1dB bit, D24 = 2dB bit, D25 = 4dB bit, D26 = 8dB bit, D27 = 16dB bit SPI Interface and Attenuator Settings The digital attenuators can be programmed through the 3-wire SPI/MICROWIRE(R)-compatible serial interface using 5-bit words. Fifty-six bits of data are shifted in MSB first and are framed by CS. The first 28 bits set the first attenuator and the following 28 bits set the second attenuator. When CS is low, the clock is active and data is shifted on the rising edge of the clock. When CS transitions high, the data is latched and the attenuator setting changes (Figure 1). See Table 3 for details on the SPI data format. Table 2. Operating Modes RESULT All on AMP1 off AMP2 on AMP1 on AMP2 off All off VCC (V) AMPSET PD_1 PD_2 5 0 0 0 3.3 1 0 0 5 0 1 0 3.3 1 1 0 5 0 0 1 3.3 1 0 1 5 0 1 1 3.3 1 1 1 Path 2 DAC and Digital Attenuator Programming D28:D35 Sent to DAC register D28 = LSB, D35 = MSB D36:D40 Preprogrammed Attenuation State 1 D36 = 1dB bit, D37 = 2dB bit, D38 = 4dB bit, D39 = 8dB bit, D40 = 16dB bit D41:D45 Preprogrammed Attenuation State 2 D41 = 1dB bit, D42 = 2dB bit, D43 = 4dB bit, D44 = 8dB bit, D45 = 16dB bit D46:D50 Preprogrammed Attenuation State 3 D46 = 1dB bit, D47 = 2dB bit, D48 = 4dB bit, D49 = 8dB bit, D50 = 16dB bit D51:D55 Preprogrammed Attenuation State 4 D51 = 1dB bit, D52 = 2dB bit, D53 = 4dB bit, D54 = 8dB bit, D55 = 16dB bit MICROWIRE is a registered trademark of National Semiconductor Corp. 18 Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA FUNCTION BIT D55 (MSB) Digital Attenuator State 4 (Path 2) Digital Attenuator State 3 (Path 2) Digital Attenuator State 2 (Path 2) Digital Attenuator State 1 (Path 2) On-Chip DAC (Path 2) Digital Attenuator State 4 (Path 1) Digital Attenuator State 3 (Path 1) DESCRIPTION 16dB step (MSB of the 5-bit word used to program the Path 2 digital attenuator state 4) D54 8dB step D53 4dB step D52 2dB step D51 1dB step D50 16dB step (MSB of the 5-bit word used to program the Path 2 digital attenuator state 3) D49 8dB step D48 4dB step D47 2dB step D46 1dB step D45 16dB step (MSB of the 5-bit word used to program the Path 2 digital attenuator state 2) D44 8dB step D43 4dB step D42 2dB step D41 1dB step D40 16dB step (MSB of the 5-bit word used to program the Path 2 digital attenuator state 1) D39 8dB step D38 4dB step D37 2dB step D36 1dB step D35 Bit 7 (MSB) of on-chip DAC used to program the Path 2 analog attenuator D34 Bit 6 of DAC D33 Bit 5 of DAC D32 Bit 4 of DAC D31 Bit 3 of DAC D30 Bit 2 of DAC D29 Bit 1 of DAC D28 Bit 0 (LSB) of DAC D27 16dB step (MSB of the 5-bit word used to program the Path 1 digital attenuator state 4) D26 8dB step D25 4dB step D24 2dB step D23 1dB step D22 16dB step (MSB of the 5-bit word used to program the Path 1 digital attenuator state 3) D21 8dB step D20 4dB step D19 2dB step D18 1dB step ______________________________________________________________________________________ 19 MAX2062 Table 3. SPI Data Format MAX2062 Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA Table 3. SPI Data Format (continued) FUNCTION BIT Digital Attenuator State 2 (Path 1) Digital Attenuator State 1 (Path 1) On-Chip DAC (Path 1) DESCRIPTION D17 16dB step (MSB of the 5-bit word used to program the Path 1 digital attenuator state 2) D16 8dB step D15 4dB step D14 2dB step D13 1dB step D12 16dB step (MSB of the 5-bit word used to program the Path 1 digital attenuator state 1) D11 8dB step D10 4dB step D9 2dB step D8 1dB step D7 Bit 7 (MSB) of on-chip DAC used to program the Path 1 analog attenuator D6 Bit 6 of DAC D5 Bit 5 of DAC D4 Bit 4 of DAC D3 Bit 3 of DAC D2 Bit 2 of DAC D1 Bit 1 of DAC D0 (LSB) Bit 0 (LSB) of DAC MSB DAT LSB DN D(N-1) D1 D0 CLK tCW tCS CS tCH tES tEWS tEW NOTES: DATA ENTERED ON CLOCK RISING EDGE. ATTENUATOR REGISTER STATE CHANGE ON CS RISING EDGE. N = NUMBER OF DATA BITS. Figure 1. SPI Timing Diagram 20 Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA Digital Attenuator Settings Using the Parallel Control Bus To capitalize on its fast 25ns switching capability, the device offers a supplemental 5-bit parallel control interface. The digital logic attenuator control pins (D0_-D4_) enable the attenuator stages (see Tables 3 and 4). Direct access to these 5-bit buses enables the user to avoid any programming delays associated with the SPI interface. One of the limitations of any SPI bus is the speed at which commands can be clocked into each peripheral device. By offering direct access to the 5-bit parallel interface, the user can quickly shift between digital attenuator states needed for critical fast-attack automatic gain control (AGC) applications. Note that when the digital attenuators are controlled by the SPI bus, the control voltages of each digital attenuator appears on the five parallel control pins (pins 14-17 and 19 for digital attenuator 2, pins 42 and 44-47 for digital attenuator 1). When the digital attenuators are in SPI mode, the parallel control pins must be left unconnected. Rapid-Fire Preprogrammed Attenuation States The device has an added feature that provides rapidfire gain selection among four preprogrammed attenuation steps. As with the supplemental 5-bit buses previously mentioned, this rapid-fire gain selection allows the user to quickly access any one of four customized digital attenuation states without incurring the delays associated with reprogramming the device through the SPI bus. The switching speed is comparable to that achieved using the supplemental 5-bit parallel buses. However, by employing this specific feature, the digital attenuator I/O is further reduced by a factor of either 5 or 2.5 (5 control bits vs. 1 or 2, respectively), depending on the number of states desired. The user can employ the STA_A_1 and STA_B_1 (STA_A_2 and STA_B_2 for digital attenuator 2) logicinput pins to apply each step as required (see Tables 5 and 6). Toggling just the STA_A_1 pin (1 control bit) yields two preprogrammed attenuation states; toggling both the STA_A_1 and STA_B_1 pins together (2 control bits) yields four preprogrammed attenuation states. Table 4. Digital Attenuator Settings (Parallel Control, DA_SP = 0) INPUT LOGIC = 0 (OR GROUND) LOGIC = 1 D0 Disable 1dB attenuator Enable 1dB attenuator D1 Disable 2dB attenuator Enable 2dB attenuator D2 Disable 4dB attenuator Enable 4dB attenuator D3 Disable 8dB attenuator Enable 8dB attenuator D4 Disable 16dB attenuator Enable 16dB attenuator Table 5. Programmed Attenuation State Settings for Attenuator 1 (DA_SP = 1) STA_A_1 STA_B_1 0 0 1 0 0 1 SETTING FOR DIGITAL ATTENUATOR 1* Table 6. Programmed Attenuation State Settings for Attenuator 2 (DA_SP = 1) SETTING FOR DIGITAL ATTENUATOR 2** STA_A_2 STA_B_2 Preprogrammed attenuation state 1 0 0 Preprogrammed attenuation state 1 Preprogrammed attenuation state 2 1 0 Preprogrammed attenuation state 2 1 Preprogrammed attenuation state 3 0 1 Preprogrammed attenuation state 3 1 Preprogrammed attenuation state 4 1 1 Preprogrammed attenuation state 4 *Defined by SPI programming bits D8:D27 (see Table 3 for details). **Defined by SPI programming bits D36:D55 (see Table 3 for details). ______________________________________________________________________________________ 21 MAX2062 Attenuator and DAC Operation The two analog attenuators are controlled by an external control voltage applied at A_VCTL_1 and A_VCTL_2 (pins 39 and 22) or by the on-chip 8-bit DACs, while the digital attenuators are controlled through the SPIcompatible interface or through two independent, parallel 5-bit buses. The DAC enable/disable logic-input pin (AA_SP) and digital attenuator SPI/parallel control selection logic-input pin (DA_SP) determine how the attenuators are controlled. MAX2062 Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA As an example, assume that the AGC application requires a static attenuation adjustment to trim out gain inconsistencies within a receiver lineup. The same AGC circuit can also be called upon to dynamically attenuate an unwanted blocker signal that could desensitize the receiver and lead to an ADC overdrive condition. In this example, the device would be preprogrammed (through the SPI bus) with two customized attenuation states--one to address the static gain-trim adjustment, the second to counter the unwanted blocker condition. Toggling just the STA_A_1 control bit enables the user to switch quickly between the static and dynamic attenuation settings with only one I/O pin. If desired, the user can also program two additional attenuation states by using the STA_B_1 control bit as a second I/O pin. These two additional attenuation settings are useful for software-defined radio applications where multiple static gain settings are needed to account for different frequencies of operation, or where multiple dynamic attenuation settings are needed to account for different blocker levels (as defined by multiple wireless standards). Power-Supply Sequencing The sequence to be used is: 1) Power supply 2) Control lines Layout Considerations The pin configuration of the device is optimized to facilitate a very compact physical layout of the device and its associated discrete components. The exposed pad (EP) of the device's 48-pin TQFN-EP package provides a low thermal-resistance path to the die. It is important that the PCB on which the device is mounted be designed to conduct heat from the EP. In addition, provide the EP with a low inductance path to electrical ground. The EP MUST be soldered to a ground plane on the PCB, either directly or through an array of plated via holes. The layout of the PCB should include proper top-layer ground shielding to isolate the amplifier's inputs and outputs from each other. Shielding between the paths (inputs and outputs) is important for channel-to-channel isolation. Table 7. Typical Application Circuit Component Values DESIGNATION C1, C2, C5, C6, C8, C9, C12, C13 QTY DESCRIPTION COMPONENT SUPPLIER 8 1000pF ceramic capacitors (0402) GRM1555C1H102J Murata Electronics North America, Inc. C3, C10 2 150pF ceramic capacitors (0402) GRM1555C1H151J Murata Electronics North America, Inc. C4, C7, C11, C14, C16 5 10nF ceramic capacitors (0402) GRM155R71E103K Murata Electronics North America, Inc. C15 1 1FF ceramic capacitor (0603) GRM188R71C105K Murata Electronics North America, Inc. L1, L2* 2 820nH inductors (1008) Coilcraft 1008CS-821XJLC Coilcraft, Inc. R1, R2 2 47.5kI resistors (0402) -- U1 1 48 TQFN-EP (7mm x 7mm) Maxim MAX2062ETM Maxim Integrated Products, Inc. *Select the inductors to ensure that self-resonance of the inductors is outside the band of operation. 22 Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA RF OUTPUT 1 C7 C6 RF OUTPUT 2 C14 VCC C13 L1 L2 D2_1 D1_1 D0_1 GND 38 39 AMP 23 22 21 ANALOG ATTENUATOR 1 41 42 43 DAC 1 DAC 2 44 45 47 20 19 MAX2062 DIGITAL ATTENUATOR 1 46 ANALOG ATTENUATOR 2 18 EXPOSED PAD 17 16 DIGITAL ATTENUATOR 2 SPI 15 14 13 48 2 GND 1 3 4 5 6 C1 RF INPUT 1 7 8 9 10 11 C12 VCC_AMP_2 ANALOG ATTENUATOR CONTROL 2 A_ATT_OUT_2 A_VCTL_2 DA_SP R2 A_ATT_IN_2 D4_2 C10 C9 D_ATT_OUT_2 D3_2 D2_2 D1_2 D0_2 GND 12 C8 VCC C16 Chip Information PROCESS: SiGe BiCMOS GND AMP_IN_2 PD_2 GND AMP_OUT_2 REG_OUT AMPSET AMP_OUT_1 AMP ACTIVE BIAS 40 + C11 25 GND D3_1 26 D_ATT_IN_2 D_ATT_OUT_1 27 STA_A_2 C2 ACTIVE BIAS STA_B_2 D4_1 28 24 CS A_ATT_IN_1 R1 29 VCC_RG C3 30 VCC 37 CLK AA_SP_1 31 32 DAT A_VCTL_1 33 STA_B_1 A_ATT_OUT_1 34 STA_A_1 VCC_AMP_1 ANALOG ATTENUATOR CONTROL 1 35 36 GND C4 D_ATT_IN_1 C5 GND VCC PD_1 AMP_IN_1 C15 RF INPUT 2 Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 48 TQFN-EP T4877+7 21-0144 90-0133 ______________________________________________________________________________________ 23 MAX2062 Typical Application Circuit Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Analog/Digital VGA MAX2062 Revision History REVISION NUMBER REVISION DATE 0 9/10 Initial release -- 1 11/10 Updated Output Voltage specification 5 DESCRIPTION PAGES CHANGED Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 (c) Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.