MOTOROLA SEMICONDUCTOR TECHNICAL Order this document by MC1450731D DATA - - MC145073 Product Preview DuaI 16-Bit Stereo Audio Sigma-DeIta ADC CMOS The MC1 45073 is a dual<hannel, 16-bit ND converter intended for use in digital audio systems such as multimedia, DCC, DAT, and professional audio applications, It uses a sigma-delta architecture consisting of a second-order analog modulator and two stages of digital filtering for each channel. The analog modulator samples the input signal at 128 times the output data rate, performs a single-bit quantization, and shapes the quantization noise towards higher frequencies. Subsequent on+hip digital filters reject most of the shaped quantization noise and lower the data rate. Sixteen unique user-selectable intetiacing modes make the MC1 45073 compatible with a multitude of application interfacing requirements. A single 5 V supply and a power-down mode reduce power supply requirements, mating@Fjj the part attractive for portable applications. ,,.&w$}y*{:: $8:."*N. ;$, :. Single Supply, Operating Voltage Range: 4.5 to 5.5 V .! ~t~zi> ~k~$ ,, ....*. ,,..~'~ . 128x OSR Sigma-Delta Modulator ...>,#~ , ,.*, %Ii. (,$, 82 dB Typical S/(N+D) Analog Inputs Can Be Driven as Either Differential or SingleT~~#&~, Clock Input May Be 128x, 256x, or 384x the Output Data R~$e "k :h:,,,.,.:,<y~$!-' Out-of-Range Input Signals Internally Limited .T.:k:,k,::,.], .,. . . ~.> $,,1! OnShip Digital Filters: "~~ * ~'1 5th Order Decimate-by-32 Comb Filter ~~\ ~.+l ,..>$I,!,* ~ 121 Tap Decimate-by+ FIR Filter t` &J.\, User-Selectable Digital Filter Transition Band~,t,, ** Versatile Serial Digital Output Intetiace: ,$ "$.~~q? ,>:t+l ,,$~,:. \~ .,s Configurable as Master or Slave Data Can Be Either Left- or Right#&d Interfaces to DSP56000/1 and,:@~OT" DSPS i2S or Japanese lnte~ace ~~~fiili~ a . . 23 > AIN(-R) AIN(-L) [ 2 22 ] VAG REF [ 3 VDD(A)[ 4 21 ] CSELO VSS(A)[ 5 20 ] CSEL1 lg ] FSEL SUB [ 6 1 ISYNC VSS(D) [ 7 18 VDD(D)[ 8 17 ] ls~v 16 ] IJUST nP [ 9 FTP[ 10 15 ] IDOE SYNC[ 11 14 ] CLK SCLK [ 12 13 ] SDO CS5326 Compatible lnte~tek~e Multiplexing of Two M~.~~5Q@s Accommodated Power-Down Mode Co~u@;on: 2.0 mW Operating Temper<~~~$%~ge: - 40 to 85C `. "'+J?~J' ,> AIN(tL) AIN(_L) SERIAL INTERFACE ~i:, MODES $ ?A IN v AIN(tR) MODULATOR COMBFILTER FIRFILTER -- - TMs dwument containsinformationon a productunderdevelopment.Motorolareservesthe rightto chengeor discontinuet~s productwithoutnotice. TMS320 is a trademark of Texas Instruments. REV 1 5/97 @ Motorola,Inc. 1997 MOTOROLA @ MAXIMUM RATINGS* (Voltages referenced to VSS, ----unless otherwise stated) Symbol VDD(A) Parameter Value Unit Analog Supply Voltage 6.0 v Digital Supply Voltage 6.0 v *20 mA VDD(D) DC Input Current, per Pin Iin ~n(A) Analog input Voltage V"(D) Digital Inputs Tstg TI VSS(A) -0.3 tO VDD(A) + 0.3 v - 0.3 to VDD(D) + 0.3 v Storage Temperature Lead Temperature 10 Seconds -65to 1 mm From Case for This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. *,\ *'X,l, $J,$<,. ,,.,'~ ,'$:. `!,., .,.,,. ,* ~1+ts., .$"" `,,>*+?., ~?} f, `c 150 `~e~. `.@" ,.,ii$...}:* ~,!,. `J.:. ,. , ~,-.,,,! r ~.s. *,..,.l. ,.,.;% +, . ` ,X,a,.>?, :$~*#b$'"'"'" .t$, ` .,.:a> }~t.~ ~t:!.,, ~.t':' `" t. ~?$>:,% "" &.\,,/!$ +'~?~,-<$:,* `c 260 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted tothe Operation Ranges, Analog Specifications, AC Electrical Characteristics, and DC Electrical Characteristics tables. OPERATION RANGES I Symbol I Parameter I VDD(A) I Analog Supply Voltage VDD(D) Digital Supply Voltage ~n(A) Analog Input Voltage (AIN(+L), AIN(-L), fCLK CLK Frequency 5.5 v 1,9 v p-p AIN(+R), AI N(-R)) 1 18.432 MHz 2 `.:,, ,,,3. CLOAD Capacitive Load on Any Output 0 50 pF ~i;:'~"::?i. ,>. *<X? ,.~s., ., s },s Ambient Operating Temperature Ta - 40 85 `c )'... ~~ .t + ~, ",~:2>* NOTES: ~ .,,.,,../,.$ ,~~ \+!* 1. Differential inputs greater than 3.8 V p-p will overload the modu~q~Y&."These voltages are subject to the gain error tolerance specifications in the Analog Specifications table. ~,.:,, 2, The internal clock frequency or input sampling frequen~~ governed by the divide mode and output data rate. The divide mode can be either 1,2, or 3. The output data rate ranges from 24 kHz tQ{8~,z. The minimum clock frequency of 3.072 MHz is for a 24 kHz output rate in the clock divide by 1 mode. The maximum clock fre+,.of 18.432 MHz is for a 48 kHz output rate in the clock divide by 3 mode. ,,:,: ~ .,.,.$:;)* .t$,,${f' .$j>s;i. .<:~h..%.:.. \\*\.. .& ~$, DC ELECTRICAL SPECIFICATIONS (Voltages referenced to VSS(D); Full Temp~*%$%d Voltage Ranges per Operation Ranges Table, unless otherwise indicated.) ... `~~:i}, ` ~.i>,,,<~$ Parameter \,/+,.> Symbol VIH Minimum High-Level*~j~i#l ,,*,k\.h, ,,,>,,~~ Input Voltage VIL Maximum Low-&vel{@igital ,>.,* .!., >.+.,* Min Max Unit 0.7 x VDD(D) v Input Voltage 0.3 x VDD(D) v 10 pA *"- 11N Maximum I&t `@akage Current VOH Mini~~&$Ni$h-Level Digital Output Voltage (IOH = -20 VOL ~~i$~%$~ow-Level Digital output Voltage (IOL = 20 ~) IDDu(D) , $~~~rnum lDD@! 4.4 v Digital Power Supply Current, Operating `:': ,,M'aximum Digital Power Supply Current, Power-Down lD&:~w$# "I Maximum Analog Power Supply Current, Operating ,., .,,.. , l~~:(i) :~:t /:,,.. w -f?: `*PO pA) I I 0.1 v 45 mA 250 KA 10 I mA Maximum Analog Power Supply Current, Power-Down 150 LA Power Consumption, Operating 250 mW ppd Power Consumption, Power-Down 2.0 mW Cin Maximum Input Capacitance 20 pF MC145073 2 MOTOROU ANALOG SPECIFICATIONS (Full Temperature, CLK = 6.144 MHz in divl, VDD(A) = VDD(D) = 5.OV, 1007.8 Hz Full-Scale Input Sinewave, 1.4 V EP @ AIN(L) and AIN(R), Common Mode Input Voltage = 2.5 V. Measured bandwidth is 23 Hz to 24 kHz, inputs driven differentially per Figure 1.) Parameter Min Resolution Bits 16 S/(N+D) 76 Typ Unit Bits 62 Dynamic Range dB 85 Total Harmonic Distortion (Vin = ~ F.S.) .003 Gain Error *5 Gain Drifi 50 Channel to Channel Isolation 90 PSRR (VDD(A)) 60 PSRR (VDD(D)) 100 Time (for Reference and Bias Circuits) ."'>?, dB kQ ms ->:,,., ~~ .+$'" -.~,. \:,i;$+\,$,. DIGITAL FILTER CHARACTERIZATION (Over full operating ranges per Operating FIR filter.) .",,4$:,? ~~j.< j .q:$~" -<>Y.t, ~,.>;,.4.."'J'2ppm/"C ..:.S...,,,,..*, ,,.. .$"~ :$+ dB ,,,{,\ ,,> .:$8<P ,*. ... "`i.;~i},,i,, . dB i:."'~.>+~ .. ;/., :... ;...,, "~~%~" .'1,', ........:>.:) Weq>$ "u ,,{&~,,,~ "s> , *$,f. ,,..{. .. ,,,, \*f~,``.,*J*S ..3:;:;My,$, Input Impedance Warm-Up Max Ranges table, Stated values are for inpuV@ka~onships .. ,,:<*\:/ "'~ ,,..,, - . -~').:,.., ...~J. ,. \, ,$ d~ut Parameter from input of comb filter to output of Data Rate 48 kHz Unit 0 to 18.3 0 to 20 kHz *0.1 * 0.1 dB 18.3 to 23.5 20 to 25.8 kHz -84 - 84 -84 dB -86 - 86 -66 333@,z:3 44.1 kHz Notes *:4 FSEL = IOW *t:$&'1 FIR Filter Passband Maximum Passband Ripple FIR Filter Transition Band FIR Filter Rejection (Min) Maximum Alias Level (Figure 3) Group Delay Setting Time FIR Filter Passband ., Maximum Passband Ri&' FIR Filter Transiti:$$d FIR Filter Rej,~o$(~) ,7,, ,,,, `s,$,,,' J:*~iti,..>ir .,~ ..:.~~l:~, $$\ i..f,. ,.. ~)&, ~,.,.,,.,:l.,~. , \ .,>~.,...,>,.:. ~,,., .:,.. ~.S,tt ,,,,:, . .f,.J" ./, .?:~i~.$\\..,l>~ :$#'..?,/, .:ltf!.:t:, ,\::~\,~}+> ~~.,. > ..~::).,. ..:., ~.i;+:i, ,, :+,: .,,,,/ ~',- .:.$ .]~ik `~} ~} " ,,.. `" ,$t 3.3 +0.1 13.3to 17 dB 1,2 33 33 33 Out CLKS 3 49 49 49 Out CLKS 3 o to 14.5 0 to 20 0 to 21.7 kHz *0.1 & 0.1 dB 20 to 25.0 21.7 to 27.3 kHz -84 -84 -84 dB -86 -86 -86 dB 1,2 33 33 33 Out CLKS 3 49 49 49 Out CLKS 3 io.1 14.5 to 18.2 *ypy5s: ~::$'"~. There is no rejection of input signals that are multiples of the sampling frequency (nxCLKl + Filter Bandwidth, where n = O, 1,2, ...). `~$ 2. The maximum alias level spec does not apply to input signals in the range of 24 to 25.8 kHz in the 48 kHz output mode, 22.05 to 23.675 kHz in the 44.1 kHz output mode, or 16 to 17.2 kHz in the 32 kHz output mode. 3. One Out CLK (output clock) is equal in length to 128 internal CLKS or one SYNC clock period. -- MOTOROLA MC145073 3 VDD(A) T AIN(L) I I o AOUT(+L) AouT(_L) AIN(R) -- MC145073 4 MOTOROM VDD(A) T VDD(D) T C74HCU04 * 820 % kQ J * 22 (and -- MOTOROM ? MC1 45073 5 M~lMUMALIAS 0 24 48 72 96 = -86.713 120 144 dbAT 24.0 kHz 168 192 216 MWIMUM AUAS = -67.5884 . 240 264 dbAT 169.125 kHz 288 DIGITAL FILTER RESPONSE (20 -25.6 kHz TRANSITION BAND) 0 12 24 36 48 60 72 84 96 lNPUTFREQUENCY(kHz) OUTPUT DATA RATE = 44.1 kHz, FSEL = HIGH SIMUMTED o 25 50 75 100 125 150 175 TIME (OUTPUT CLOCKS) 200 225 250 o 5 DEMYS to 30 TlfE (OUT:iT 35 CLOC::) Figure 5. Group Delay and Setiing Wme MC145073 6 MOTOROM 40 AC ELECTRICAL SPECIFICATIONS (Full temperature and voltage ranges per Operation unless othemise noted.) Figure 6 Master Clock (CLK) Frequency (Note 1) I Min tw~h Master Clock High, CLK Master Clock Low, CLK 6 tsync Sync Period (Master and Slave Modes) 7 t~sh Sync High (Slave Mode) Cin 1 2,3 38 20 1 38 20 8 SCLK Duty Cycle 20 8 8 tcsc tcDv Delay (Note 2~Y~,,. Edge to SeriaBQat~Vaiid, SDO Edge to @w~a Valid, SDO Edge,,#~~rl~FOata Valid, SDO -' ." ts" th Setup Ti~$ `&t&3) SCLK@$#&~:Edge ~*~*~Note .~~~!o ls~v ,pi<$;::ga;*Ycf& ns ,\ "":t},,;#26* tcl~ ns 20 pF 2 ` tcl~ ns 1.50 ns ns ns tclk + 40 2 * tclk + 40 40 ns ns ns tclk + 40 2 * tclk + 40 40 1 2 3 ns ns ns ~lk + 40 2 * tclk + 40 =1 15 ns of CLK } 3) o ns Rising Edge of CLK $LK High 20 ns $CLK LOW 20 ns 15 ns Setup Time (Note 3) SYNC to Rising Edge of CLK o Hold Tme (Note 3) SYNC to Rising Edge of CLK tcDv MHz 40 ,.:/,>> -a; ~.~:.'?,. ~ .:.-.., ..'K$,. ,, *' $ .~`$'.~. ~, >$i$: ?* 1 .,:t.i*?* ,:,j}::.. .<?,,:$,,. .1.>tiv 2 ,.:, ..... 3 ,>,?$ Propagation CLK Falling CLK Rising CLK Falling sl~;wa: w.' `~g;;~ " ~:$~e 0.667 ,.,'$:+:$l't, .~~. Delay (Note 2) Edge to SCLK Edge to SCLK Edge to SCLK MHz ++. "\f;$Y!,P .;*c' `?;>, ..>. .~..., >,,.,. ~h, i$i, `$ ,$l& ~'t'-" Propagation CLK Falhng CLK Rising CLK Falting I `"t?' ` $*:$*: t?+ .,, ns ,.>t:j,-,.:? .,+.~,,. ... ~:1:... .... .,\ \\., ~.~ ..!.,,,. ,\\\:f.)::i ns **,? ?) ` ji]{i? \ `:.i+l-' ,,,,~" ,.*.,.*;P' .:'~,s.,. `\, >'., ~. `i~R\ *;:.,,, ~";~?tj,., 1,$, \.# -~$,.,,i ,,.:{.',' ..3' . \\.pr Propagation Delay (Note 2) CLK Falling Edge to SYNC CLK Rising Edge to SYNC CLK Falling Edge to SYNC 8 18.432 6.144 128 * tcl~ Master Mode: ISLAV = O SCLK Period Unit ~!:$l, Input Capacitance (Except for LeWRight Channel Inputs) 8 I 3.072 2,3 7 Max 3.072 I Internal Clock Frequency, CLKI (Note 1) tcl~ = l/(fclk~ivide Ratio) 6 6 measured with respect to 307. and 70% of VDD(D) Divide Ratio Parameter Symbol iit~lk Ranges table. All timing parameters Propagation Delay Clk Rising Edge to Serial Data Valid, SDO 1 2 3 twch tclk tclk + twch ns twch +40 2 * tclk + 40 3 * tclk + twch + 40 NOTES: 1. The internal clock frequency, or input sampling frequency (CLKI) is governed by the divide mode and output data rate. The divide mode can be either 1,2, or 3. The output data rate ranges frOm 24 kHz to 48 kHz. The minimum clock frequency of 3.072 MHz corresponds to an ou;put data rate of 24 kHz with the device in the clock divide by one mode. The maximum clock frequency of 18.432 MHz corresponds to an output data rate of 48 kHz with the device in the clock divide by three mode. 2. Propagation delay is measured with a capacitive load of 50 pF. 3. In the slave mode, SYNC or SCLK transitions can occur an~here except O to -5 ns relative to the CLK rising edge. MOTOROLA MC145073 7 + twch+ L CLK, CLKI 1 `YNCW 1~ $Ik, tclti ~1 Figure 6. Cwl CW2 CLW3 MC145073 8 MOTOROLA ANALOG PINS when the SYNC signal is active high, and right channel data is transmitted when the SYNC signal is low. See the Serial Interface Description section for more information. AIN(+L), AIN(-L) Left Channel Analog Inputs (Pins 1,2) SCLK Serial Interface Clock lnputiOutput PIN DESCRIPTIONS These two pins comprise the left channel analog differential inputs. The voltage range of signals applied to these pins is from VSS(A) to VDD(A). A positive full-scale input to the ND is defined as a difference of 3.8 V p-p between AIN(+L) and AI N(-L). AIN(+R), AIN(-R) Right Channel Analog Inputs (Pins 24, 23) These two pins comprise the right channel analog differential inputs. The voltage range of signals applied to these pins is from VSS(A) to VDD(A). A positive full-scale input to the ND is defined as a difference of 3.8 V Wp between AIN(+R) and AIN(_R). REF Output of the Internal Voltage Reference (Pin 3) The nominal value of this internal voltage reference is 2 V. The output of the reference is brought out to this pinto facilitate filtering. For proper device operation, this pin should be decoupled to VSS(A) with a 1.0 pF electrolytic capacitor in parallel with a 0.1 LF ceramic capacitor. In order to economize on filtering capacitors, the REF pin can, be The SCLK pin is an input or output depending on the state of the ISLAV pin. Serial output data is clocked out of the MCI 45073 on the rising edge of SCLK. When SC% is an input, it is reclocked by the internal sample rate,:wWLKl, before being used by the MCI 45073 to cloc~~ow$~~ serial data. This reclocking ensures that rapid ~$ed changes through the SDO pin do not affect the an~~~$'~tiormance of the device. See the Serial lnterface,pc~on section for %,,$ti{:' ,,2,< `! ,,}$w~i,. \*,> more information. .,:: ~,p,e ,., $ .~...,, . . `\& ,13. $ .:%:+. .$,* SDO Serial Interface Data Ou,~~~&Jn 13) , ;: ~ The ND conversion~&<$ulf&Hor the Iefi and right channels are output on this pifit,<~~'+is shitied out of the MCI 45073 MSB first, with the ~~wnel data preceding the tight channel data. The,,@~ial ohtput data is clocked out on the rising edge of SCNi6&&lhe Serial Interface Description section `i " .$i:.`**, for more i~for~at]on. *!,.$*~?+,i,{. ,<,<: "..,., ,,>.. FT~ `r$~.. R~,ory Test Mode Inputs (Pins 9, 10) ,,?, ,"~+'fl~hese pins should be connected to VSS(A) ., for normal ~(~$+~~vice operation. connected to VAG. However, this could result in a posslbl~~&k$ degradation of petiormance of the device at high signal `~!~ ,) .<.:+,,, Analog ground is used to bias the ,#WPanalog circuits and is nominally 2 V. VAG is brougM,9u?~%is pin to facilitate filtering. This pin should be deco~&~%+VSS(A) with a 1.0 ~F electrolytic capacitor in paral~a~t,&Q,~;0.1 yF ceramic capacitor for normal device opera$n.:, ,,,.., ~~~ ~`~il,.h .*V .,,y..,, ,y. `~:~ .>,>>,. ,$,, DIGITAL PINS J$$\,t!. *j . .:*$.. ,'+>i.$ This p~}$~~,~e master clock input for the device, Analog input $~ha~to the MC145073 are sampled at a rate equal to thi~$&~&./frequency divided by 1, 2, or 3, depending on the ~~~ @ clock mode pins CSELI ,0. The serial data output ?$~$ws equal to the input sample rate divided by 128. `:~or example, if CLK is running at a 12.288 MHz rate, and divide by 2 is selected, then the output data rate is (12.288 MHd2)/128 = 48 kHz. For more detail, see the Summary of Operating Modes section. SYNC Serial Interface Frame Sync lnpuVOutput (Pin 11) The SYNC pin is an input or output depending on the state of the ISLAV pin. The SYNC signal resets and synchronizes the serial interface transmitter and receivers, as well as most internal clocks. Left channel serial output data is transmitted MOTOROM (Pin 12) CSELO, CSEL1 Clock Divide Mode Select Inputs (Pins 21, 20) The device master clock input is divided by 1, 2, or 3, or the device is placed in a power-down mode depending on the state of these pins. See the Summary of Operating Modes section for more information. FSEL FIR Filter Response Select Input (Pin 19) A low level on the FSEL input selects a FIR filter transition band from 20 to 25.8 kHz at the 48 kHz output data rate. A high level on the FSEL pin selects a filter transition band from 20 to 24 kHz at the 44.1 kHz output data rate. See the Summary of Operating Modes section for more information. [SYNC Serial Interface Sync Format Select Input (Pin 18) A low level input on the lSyNC pin selects a SYNC rising edge one SCLK cycle before the initiation of a serial data transfer. A high level on the lSyNC pin will select a SYNC rising edge that is coincident with the initiation of a serial data transfer. See the Summary of Operating Modes and the Serial Intetiace Description sections for more information. ISLAV Serial Intetiace Slave Mode Select Input (Pin 17) This pin controls the direction of the serial intetiace SYNC and SCLK signals. A low level on the ISLAV pin will configure the SYNC and SCLK pins as outputs, while a high level on the ISLAV pin will configure the SYNC and SCLK pins as inputs, See the Summary of Operating Modes and the Serial Intetiace Description sections for more information. MC1 45073 9 IJUST Serial Interface Data Justification FUNCTIONAL A low level on the IJUST pin will cause the serial output data to be left justified relative to the SYNC signal. A high level on the IJUST pin will select right justification of the serial output data, See the Summary of Operating Modes and the Serial Interface Description sections for more information. IDOE Serial Intetiace DESCRIPTION Select Input (Pin 16) Data Output Enable (Pin 15) This pin controls the state of the SDO pin between 16-bit data word transfers. A high level on this pin will force the SDO pinto a low level between serial data words, while a low level on the IDOE pin will force the SDO pin to a high-impedance state between data words, See the Summary of Operating Modes and the Serial Interface Description sections for more information. POWER SUPPLY PINS VDD(A) (pin 4) Positive analog power supply input. The voltage range for this pin is 4.5 to 5.5 V with respect to VSS(A). The absolute value of the difference between VDD(A) and VDD(D) must not exceed 0.5 V. For proper device operation, this pin should be decoupled to VSS(A) with a 1.0 ~F or larger capacitor. The MCI 45073 is a 1-bit stereo audio ND convener intended for use in digital audio systems. The MC1 45073 uses a sigma+elta architecture consisting of a second order analog modulator followed by two stages of digital filtering for each channel. The analog modulator samples the input signal at a very high rate (128x the output data rate), petiorms a single bit quantization, and shapes the quantization noise towards out-of-band frequencies. The digital filter#$Qf the ."$.>.. "t}. MCI 45073 reject most of the shaped quantizatio~,pqwsand lower the serial data output rate. The digital filt~~n$'&~mplemented with a 5th order, decimate-by-32 com.~a$$ollowed by a 121 tap, decimate-by-4, FIR filter o~~~~~~$channel. In addition to rejecting quantization nois~:~~d R&Rfilter cancels the curvature in the response of tQ&~:~:@'ding comb filter. The comb and FIR filters also pr&Jd$anti-alias filtering of out-of-band signals present~~+he Thbut to the device. The analog inputs to the MC14,%,~@n be fully differential (both inputs dynamic and 180.<~~~r<&&out of phase), or single+ nded (positive inputs dy~~~@~khile negative inputs are static at a level in the mid@~$%e supply range). Analog input signals that excee,~~,e difibrential analog input voltage range of 3.8 V p-p ar~. order to prevent overflow of the digi*,*itc]$~~%din ,:}, $* tal filters.,$~~e ~~1 45073 operates from a single 5 V power supply. .~:~,'xtiable or other low power applications, a power-d~wn'~,ode is available, 9$,oPeration of the MC1 45073 can be tailored to specific .:~~llc~ions by proper selection of the states of seven mode .{.<"~q!~t pins. These mode pins control the divide ratio of the ~~~$~aster clock, the FIR filter response, and the serial interface VSS(A) (pin 5) `%?format. The master clock input can be divided by either 1, 2, Negative analog power supply input. This pin sho~!d be or 3 to yield the input sampling rate. This means that the in,>,$,%. * connected to ground for normal device operation. ..,., .`:~'..$ put clock frequency is either 128x, 256x, or 512x the serial -4. :s,,., ,,.. output data rate. NOTE VDD(D) (pin 8) Positive digital power supply input. Th{~~~~&; range for this pin is 4,5 to 5.5 V with respect to V~#~#~ The absolute value of the difference between VD~:~~@~VDD(D) must not exceed 0.5 V. For proper device o$er~~on, this pin should be decoupled to VSS(D) with a ~&~J5?larger capacitor. ,-\. P ,ii-*}.! ..,." VSS(D) (pin 7) ,, `$" ,' ,,.. Negative digital f@iw~~supply input. This pin should be connected to g{~~'&foY .,~$:l)?normal device operation. -**,, . MC145073 10 The oversampling ratio (OSR), which is the ratio of input sampling frequency to output data rate, is 128x in all three cases. Two sets of FIR filter coeticients are stored in the on- board ROM of the MC1 45073. One set provides a transition band from 20 kHz to 25.8 kHz for operation at the 48 kHz output data rate, The other set of FIR filter coefficients provides a transition band from 20 kHz to 25 kHz for use with the 44.1 kHz output data rate, Four mode select pins configure the serial intetiace. This yields sixteen possible serial interface operating modes. Included are modes that provide for intetiacing directly to Motorola and TI general purpose DSPS, multiplexing of two MC145073s, as well as formats similar to the CS5326 interface, MOTOROLA SUMMARY The seven OF DEVICE OPERATING pins summarized the MC1 45073 to operate modes can be chosen in the tables below configure in one of the modes specified. The in any combination. CSEL1 CSELO o 0 Power-Down o 1 Divide CLK by 1 1 0 Divide CLK by 2 1 1 Divide CLK by 3 FSEL Master CLK Divider FIR Filter Transition o MODES Select Band Select 20 kHz - 25.8 kHz Transition Band 8.144 MHz Input Rate, 48 kHz Output Data Rate. 1 20 kHz -25 kHz Transition The TMS320 interfa~~~us~be initialized with frame sync enable~+~'~~n switched to the no frame sync mod@~~#rhltialization. Band 5.6448 MHz Input Rate, 44.1 kHz Output Data Rate Serial Interface SYNC Signal Format SYNC rising edge is one SCLK cycle before the stati of the serial output data transfer. (This IS compatible with the DSP5800/58001 and TMS320 ~ serial interface is provided in the AC Electrical Specifications section . Compatibility with the DSP56000/1 and TMS320 general- purpose DSPS is accomplished by applying the appropriate logic level to the lSyNC pin. The phase of the rising edge of the SYNC signal is different for the DSP56000 and TMS320 applications, while the falling edge of SYNC is not critical in such applications. To interface to one or two MC145073~, the DSP56000/56001 should be configured as follo~~vdwork mode, four time slots per frame, 16 bits per sl,$?~~~$inuous clock, and control signals configured as eit@$~:P~iWaster or slave. If intetiacing to a TMS320 is desi~'~t,+& serial interface should be configured in continuo@<mQ@&without frame `,~>;?,..i>~... ~.,,., sync. ~~iy ..,/. ,S.,:f .*,?.*,,, (Y$ NOT~'~$,,,;} The IJ UST and j,~~~$ti;al intetiace mode control inputs are provided toafa~~@~e multiplexing of two MC145073s. The IJUST i~~~$~lects between left and right justification of the serial ,,m~$ata relative to the SYNC signal, while the lDOE,i@$&,p@vides a way to force the SDO pinto the high impe%~eifate between the output data words. To multip~,~~ th~eerial data outputs of two MCI 45073s onto the ,,b~ak$ SDO line, IDOE must be forced low on both ,$%145073s, I SYNC rising edge is coincident with the start of the while the I JUST pin is forced high on one `~~~MCI 45073 and low on the other. TheMC145073s must be in serial output data transfer. (This is compatible with , the CS5328 interface definition.) ` .~s,?t :~'""++ the slave mode (I.--SLAV= I ) when multiplexing. It is not Pos. .. , ,- 1 sible to operate with one MC1 45073 as a master tied to a second MC1 45073 operating as a slave due to the reclocking of the SYNC and SCLK inputs in the slave mode (see Operation with the MC1 45073 as a Slave (I SLAV = 1) section). NOTE When multiplexing two MC1 45073 devices, all four analog channels are sampled at exactly the same phase. <c.% :, .,,. IDOE .$), ?+?$,'" Serial Interface Data Output Enable $: ` *, `SDO goes to a high-impedance `.:,*'* 16-bit output words. SDO is forced low between 1&bit state between output words. ?. SERIAL INTERFACE ~ ~ DESCRIPTION As summarized in the previous section, the format of the serial intetiace is controlled by four mode pins: ISYNC, ISLAV, IJUST, and IDOE. These control inputs can be configured in any combination, yielding 24 = 16 unique modes. The following two subsections describe the format of the serial interface for these various modes, Timing information for the MOTOROLA In Figures 10 and 11, the internal clock signal CLKI is plotted instead of CLK. This is due to the fact that all internal clocks, as well as the serial interface, are slaved to this divided version of the master clock. Input signals to the serial interface are reclocked by CLKI to reduce the amount of noise injected into the analog section of the MCI 45073. Serial output data and high-impedance states of the SDO pin are clocked out relative to CLKI. This reclocking can cause a shift in phase of SDO relative to SCLK when operating in the slave mode. In cases where the MC1 45073 output is multiplexed with another device, the clock divide by 1 mode is recommended. NOTE If the clock divide by 2 or 3 mode is selected, it is impossible to know the exact phase of CLKI, On initial power-up or recove~ from a power+ own condition, the first 68 serial output words of the MC1 45073 are indeterminate. This is because the digital filters and internal logic of the MC1 45073 must settle. This time is also used to charge the external REF filter capacitor. MC1 45073 11 Operation with the MC145073 as a Master (ISLAV = O) When ISMV = O, the SYNC and SCLK signals are defined as outputs, and the MC1 45073 is configured as master device. In this mode there are eight possible serial formats as illustrated in Rgure 10. The phase of the SYNC output can precede the serial output data by one SCLK cycle (compatible with DSP56000/56001, TMS320, and 12S interface format), or the SYNC signal can be coincident with the serial output data (similar to the CS5326 serial intetiace format). As shown in Hgure 10, with each of these two SYNC formats there are four possible formats for the serial output data. Serial output data is shifted out MSB first, with left channel data preceding the tight channel data, All of the serial interface outputs, SYNC, SCLK, and SDO are initiated by a CLKI rising edge. There are 128 CLKI cycles, and 64 SCLK cycles per output data cycle. Multiplexing of two MC145073s is not feasible in the master mode since the exact phase of the output cannot be controlled. NOTE The serial data in one output cycle represents data that was simultaneously sampled on the two analog input channels. It is possible to initiate the device in the slave mode described in the Operation with the MC1 45073 as a Slave (ISLAV = 1) section, and then switch to master mode. Once set, the phase of SYNC should not change. Operation with the MC145073 as a Slave (ISLAV = 1) S When ISLAV = 1 the SYNC and SCLK signals are defined as inputs, and the MCI 45073 is configured as a slave device, However, the slave mode of the MC1 45073 is not a true slave mode since the SYNC and SCLK inputs are rg~~ked by the internal sample clock, CLKI. These intern@r~~&ked versions of SYNC and SCLK are shown in Figu&.,f~lfin addition to the external SYNC and SCLK signa~.~$.~~i+i)" Similar to the master mode of the prW'ti&%ection, there t,J<... are two formats for the SYNC signal, ~~~~dr SDO formats, yielding eight possible slave mode@?W*$~*# Multiplexing of two MC1450~~s:}k,.@e slave mode is performed by forcing IDOE low ~;~~thM"C145073s, and forcing IJUST high on one MC14@b%;3:~?d low on the other. ,$;$$;TE When multi@~$;wo MC145073s, the master clockpd~vid~.by 1 mode should be used (CSELl,&+*I*) so that the exact phase of CLKI is de~$rfi~~. - MC145073 12 MOTOROLA .,,,. MOTOROLA ---- 0 Figure 10. Serial Interface Operation with MC145073 ? isnri Configured "1 c I =lsnrl -- 11 .-- as Master (ISLAV = O) MCI 45073 13 MC145073 14 -- ----- ----- -- .--_-- ---_-- -- .------ ------ w 0 "m w "m 0 -- -- -- ---4--------- as Slave (ISLAV = 1) ----4--------- Configured ----4----- ------ .------ ------- .------ ------- Figure 11. Serial Intetiace Operation with MC145073 w 0 0 n = n m -- --. MOTOROW PACKAGE DIMENSIONS DW SUFFIX SOG PACKAGE CASE 751 E+4 i 12 PL 1+1 0.010(0.25)@ I B@l MATERIALi m ,"1". r R I 1 "., . , ".. 10< . . .. . , . . .. . 0.25 I 0.75 , . .. . . I 0.010 [ , . .. !. 0.029 LG22PL MOTOROU MC145073 15 ....-.,,,, *.l, .~*~:J,, ,,.< . >a,y,, \,.$.. .,,,, .1:., ..;> ;~,. %~'ad,b,ny Motorola rese~@~e fight to make changea without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding theauitati ,?~l%roducts for any Perficular purpose, nor does Motorola aasume any liabiHfy arising out of the application or use of any product or circuit, and apecifia %d" ,,,aima any and all liability, including without limitation consequential or incidental damages. TYPical" Pammaters w~ch maY be Provided in Motorola datas&,eta@d/or apecificationacan and do vary in different applicafionsand actual performance mayvaryovartima. All operating parameters, including `Typicels" ~y~$~wated for each customer application by customer'a technical exPefls. Motorola does not convey any license under its Patent rights nor the ri9hfs of ow~otorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other ~Np@tionsintended to suPPofl 0rau5Wn life, or for any other application in which the failure of the Motorola Product could create a situation where personal injury ,:.@?&ath may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized apphcation, Buyer shall indamnifyand hold Motorola ~~pnd ite officers, employees, subsidiaries, affiliates, and distributors harrnleas against all claima, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indrectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and@ are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA/EUROPE/Locationa Not Listed: Motorola Literature Distribution; PO. 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