MOTOROLA
SEMICONDUCTOR TECHNICAL DATA Order this document
by MC1450731D
-Product Preview
-DuaI 16-Bit Stereo Audio
Sigma-DeIta ADC
CMOS
The MC1 45073 is adual<hannel, 16–bit ND converter intended for use in
digital audio systems such as multimedia, DCC, DAT, and professional audio
applications, It uses asigma–delta architecture consisting of asecond–order
analog modulator and two stages of digital filtering for each channel. The
analog modulator samples the input signal at 128 times the output data rate,
performs asingle-bit quantization, and shapes the quantization noise towards
higher frequencies. Subsequent on+hip digital filters reject most of the shaped
quantization noise and lower the data rate.
Sixteen unique user–selectable intetiacing modes make the MC1 45073
compatible with amultitude of application interfacing requirements. Asingle 5V
supply and a power–down mode reduce power supply requirements, mating@Fjj
the part attractive for portable applications. ,,.&w$}y*{::
●Single Supply, Operating Voltage Range: 4.5 to 5.5 V*N.:.
$8:.” ;$,
.! ~t~zi>~k~$
.128x OSR Sigma–Delta Modulator ,, ....*.
,,..~’~
...>,#~
●82 dB Typical S/(N+D) %Ii.,
,.*, (,$,
●Analog Inputs Can Be Driven as Either Differential or SingleT~~#&~,
●Clock Input May Be 128x, 256x, or 384x the Output Data R~$e “k
●Out–of–Range Input Signals Internally Limited :h:,,,.,.:,<y~$!-’
.T.:k:,k,::,.],
●OnShip Digital Filters: .,....~.>$,,1!
“~~*
a5th Order Decimate–by–32 Comb Filter ~’1
~.+l
121 Tap Decimate–by+ FIR Filter ~~\
,..>$I,!,*~
t‘&J.\,
.User–Selectable Digital Filter Transition Band~,t,, **
.Versatile Serial Digital Output Intetiace: ,$ “$.~~q?
Configurable as Master or Slave ,>:t+l
,,$~,:.\~.,s
Data Can Be Either Left– or Right#&d
Interfaces to DSP56000/1 and,:@~OT” DSPS
i2S or Japanese lnte~ace ~~~fiili~
—
-
MC145073
AIN(-L) [223 >AIN(-R)
REF [322 ]VAG
VDD(A)[421 ]CSELO
VSS(A)[520 ]CSEL1
SUB [6lg ]FSEL
VSS(D) [718 1ISYNC
VDD(D)[817 ]ls~v
nP [916 ]IJUST
FTP[10 15 ]IDOE
SYNC[11 14 ]CLK
SCLK[12 13 ]SDO
CS5326 Compatible lnte~tek~e -
Multiplexing of Two M~.~~5Q@s Accommodated
●Power–Down Mode Co~u@;on: 2.0 mW
●Operating Temper<~~~$%~ge: – 40 to 85°C
‘.
,> “’+J?~J’
AIN(tL)
AIN(_L)
SERIAL
-INTERFACE
~i:,
MODES $?A
IN
AIN(tR) v
MODULATOR ●COMBFILTER FIRFILTER
TMs dwumentcontainsinformationonaproductunderdevelopment.Motorolareservestherighttochengeor discontinuet~s productwithoutnotice.
TMS320 is atrademark of Texas Instruments.
REV 1
5/97
@MOTOROLA
@Motorola,Inc.1997
MAXIMUM RATINGS* (Voltages referenced to VSS, unless otherwise stated)
——
Symbol Parameter Value Unit This device contains protection circuitry to
guard against damage due to high static volt-
VDD(A) Analog Supply Voltage 6.0 vages or electric fields. However, precautions
VDD(D) Digital Supply Voltage 6.0 vmust be taken to avoid applications of any volt-
age higher than maximum rated voltages to this
Iin DC Input Current, per Pin *20 mA high-impedance circuit.
~n(A) Analog input Voltage VSS(A) -0.3 tO v
VDD(A) +0.3
V“(D) Digital Inputs –0.3 to VDD(D) +0.3 v*,\
*’X,l,
$J,$<,.,,.,’~,’$:.
Tstg Storage Temperature ‘!,.,~1+ts.,
-65to 150 ‘c .,.,,. ,*
.$““‘,,>*+?.,~?}
f,
TI Lead Temperature 1mm From Case for 260 ‘c ‘~e~. ‘.@”
,.,ii$...}:*
10 Seconds ~,!,.‘J.:. ,.
,~,-.,,,!r~.s.
*,..,.l.,.,.;%
+, .‘,X,a,.>?,
*Maximum Ratings are those values beyond which damage to the device may occur. :$~*#b$’“’”’”
Functional operation should be restricted tothe Operation Ranges, Analog Specifications, .t$, ‘
.,.:a>}~t.~~t:!.,,~.t’:’‘“
t.
AC Electrical Characteristics, and DC Electrical Characteristics tables. ~?$>:,
%““
&.\,,/!$
-<$:,*
+’~?~,
OPERATION RANGES
ISymbol IParameter
IVDD(A) IAnalog Supply Voltage
VDD(D) Digital Supply Voltage 5.5 v
~n(A) Analog Input Voltage (AIN(+L), AIN(-L), AIN(+R), AI N(-R)) 1,9 vp–p 1
fCLK CLK Frequency 18.432 MHz 2
CLOAD Capacitive Load on Any Output ‘.:,, ,,,3. 0 50 pF
~i;:’~”::?i.
,>.
Ta Ambient Operating Temperature *<X?,.~s., .,s
},s –40 85
)’... ~~.t ‘c
NOTES: + ~,“,~:2>*
~.,, ,~~
\+!*.,,../,.$
1. Differential inputs greater than 3.8 Vp-p will overload the modu~q~Y&.”These voltages are subject to the gain error tolerance specifications
in the Analog Specifications table. ~,.:,,
2, The internal clock frequency or input sampling frequen~~ governed by the divide mode and output data rate. The divide mode can be either
1,2, or 3. The output data rate ranges from 24 kHz tQ{8~,z. The minimum clock frequency of 3.072 MHz is for a 24 kHz output rate in the
clock divide by 1mode. The maximum clock fre+,.of 18.432 MHz is for a 48 kHz output rate in the clock divide by 3mode.
,,:,:~.,.,.$:;)*
.t$,,${f’ ~$,
DC ELECTRICAL SPECIFICATIONS .$j>s;i..<:~h..%.:..
\\*\.. .&
(Voltages referenced to VSS(D); Full Temp~*%$%d Voltage Ranges per Operation Ranges Table, unless otherwise indicated.)
Symbol ... ‘~~:i},‘
~.i>,,,<~$ Parameter
\,/+,.> Min Max Unit
VIH Minimum High–Level*~j~i#l Input Voltage 0.7 xVDD(D) v
,,*,k\.h,,,,>,,~~
VIL Maximum Low-&vel{@igital Input Voltage 0.3 xVDD(D) v
,>.,* .!.,>.+.,*
*“-
11N Maximum I&t ‘@akage Current 10 pA
VOH Mini~~&$Ni$h-Level Digital Output Voltage (IOH =-20 pA) 4.4 v
VOL ~~i$~%$~ow-Level Digital output Voltage (IOL =20 ~) 0.1 v
IDDu(D) ,$~~~rnum Digital Power Supply Current, Operating 45 mA
lDD@! ‘:’: ,,M’aximum Digital Power Supply Current, Power–Down 250 KA
“I Maximum Analog Power Supply Current, Operating
lD&:~w$# I I 10 ImA
,., .,,.. ,
l~~:(i) Maximum Analog Power Supply Current, Power-Down
:~:t/:,,.. 150 LA
w
-f?: ‘*PO Power Consumption, Operating 250 mW
ppd Power Consumption, Power-Down 2.0 mW
Cin Maximum Input Capacitance 20 pF
MC145073 MOTOROU
2
ANALOG SPECIFICATIONS
(Full Temperature, CLK =6.144 MHz in divl, VDD(A) =VDD(D) =5.OV, 1007.8 Hz Full-Scale Input Sinewave, 1.4 V EP @AIN(L) and AIN(R),
Common Mode Input Voltage =2.5 V. Measured bandwidth is 23 Hz to 24 kHz, inputs driven differentially per Figure 1.)
Parameter Min Typ Max Unit
Resolution Bits 16 Bits
S/(N+D) 76 62 dB
Dynamic Range 85
Total Harmonic Distortion (Vin = ~ F.S.) .003 .“,,4$:,?
Gain Error *5 ~~j.<
j.q:$~”
Gain Drifi 50 -<>Y.t,
~,.>;,.4..“’J’2ppm/”C
..:.S...,,,,..*,
Channel to Channel Isolation 90 ,,.. .$”~ :$+
,, ,,> .:$8<P
,{,\ dB
PSRR (VDD(A)) 60 ,*.
... “‘i.;~i},,i,,.
i:.“’~.>+~.. dB
;/., :...
PSRR (VDD(D)) 100 ;. “~~%~” dB
..,,
Input Impedance .’1,’,........:>.:)
Weq>$ “u kQ
Warm-Up Time (for Reference and Bias Circuits) ,,{&~,,,~ “s>
,*$,f. ,,..{. ms
..,,,,\*f~,‘‘.,*J*S
..3:;:;My,$,
->:,,.,
.“’>?, ~~
DIGITAL FILTER CHARACTERIZATION .+$’”
-.~,.\:,i;$+\,$,.
(Over full operating ranges per Operating Ranges table, Stated values are for inpuV@ka~onships from input of comb filter to output of
FIR filter.) .. ,,:<*\:/
“’~-~’).:,..,,,..,,\,
~J.-
... . ,.
,$ d~ut Data Rate
Parameter 333@,z:3 44.1 kHz 48kHz Unit Notes
FSEL =IOW *:4 ,7,,
,,,,
‘s,$,,,’J:*~iti,..>ir
FIR Filter Passband *t:$&’1 3.3 0to 18.3 0to 20 kHz
Maximum Passband Ripple ,$t +0.1
.,~ *0.1 *0.1 dB
FIR Filter Transition Band ..:.~~l:~, 13.3to 17 18.3 to 23.5 20 to 25.8 kHz
i..f,.
$$\,..
FIR Filter Rejection (Min) ~)&,~,.,.,,.,:l.,~.,
\ .,>~.,...,>,.:.~,,., -84
.:,.. – 84 -84 dB
~.S,tt
Maximum Alias Level (Figure 3) ,,,,:, .
.f,.J” ./,
.?:~i~.$\\..,l>~ -86 – 86 -66 dB 1,2
:$#’..?,/,
Group Delay .:ltf!.:t:,,\::~\
,-
~}+>~~.,.>33 33 33 Out CLKS 3
Setting Time ..~::).,...:.,
~.i;+:i,,, :+,: 49 49 49 Out CLKS 3
.,,,,/ ~’,- .:.$
FIR Filter Passband ., ~ik ‘~}
.] oto 14.5 0to 20 0to 21.7 kHz
-
Maximum Passband Ri&’ ~} “io.1 *0.1 &0.1 dB
FIR Filter Transiti:$$d ‘“ 14.5 to 18.2 20 to 25.0 21.7 to 27.3 kHz
,,..
FIR Filter Rej,~o$(~) -84 -84 -84 dB
-86 -86 -86 dB 1,2
33 33 33 Out CLKS 3
49 49 49 Out CLKS 3
*ypy5s:
~::$’”~. There is no rejection of input signals that are multiples of the sampling frequency (nxCLKl +Filter Bandwidth, where n=O, 1,2, ...).
‘~$ 2. The maximum alias level spec does not apply to input signals in the range of 24 to 25.8 kHz in the 48 kHz output mode, 22.05 to 23.675 kHz
in the 44.1 kHz output mode, or 16 to 17.2 kHz in the 32 kHz output mode.
3. One Out CLK (output clock) is equal in length to 128 internal CLKS or one SYNC clock period.
—
MOTOROLA MC1450733
AIN(L)
AIN(R)
VDD(A)
TI I oAOUT(+L)
AouT(_L)
—
MC145073 MOTOROM
4
VDD(A) VDD(D)
T T
—
*
*
C74HCU04
%
820 kQ
J
22
(and
MOTOROM MC1 45073
?5
M~lMUMALIAS =-86.713 dbAT 24.0 kHz MWIMUM AUAS =-67.5884 dbAT 169.125 kHz
.
0 24 48 72 96 120 144 168 192 216 240 264 288
DIGITAL FILTER RESPONSE (20 -25.6 kHz TRANSITION BAND)
012 24 36 48 60 72 84 96
lNPUTFREQUENCY(kHz)
OUTPUT DATA RATE =44.1 kHz, FSEL =HIGH
o25 50 75 100 125 150 175 200 225 250
TIME (OUTPUT CLOCKS)
SIMUMTED DEMYS
o5to 30 35 40
TlfE (OUT:iT CLOC::)
Figure 5. Group Delay and Setiing Wme
MC145073 MOTOROM
6
AC ELECTRICAL SPECIFICATIONS
(Full temperature and voltage ranges per Operation Ranges table. All timing parameters measured with respect to 307. and 70% of VDD(D)
unless othemise noted.)
Figure
6
6
6
6
7
7
8
8
8
8
8
Symbol
iit~lk
tw~h
tsync
t~sh
Cin
tcsc
tcDv
ts”
th
tcDv
Divide
Parameter Ratio Min Max Unit
Master Clock (CLK) Frequency (Note 1) I I 3.072 I18.432 IMHz
Internal Clock Frequency, CLKI (Note 1) 3.072 6.144 MHz
tcl~ =l/(fclk~ivide Ratio) ~!:$l,
Master Clock High, CLK 138 ‘“t?’‘$*:$*:
.,, ns
t?+
,.>t:j,-,.:?
2,3 20 .,+.~,,.....
~:1:... ....
.,\ \\., ~.~
Master Clock Low, CLK .)::i..!.,,,.
138 ,\\\:f **,? ns
2,3 ?)‘ji]{i?
20 \‘:.i+l-’
,,,,~”
,.*.,.*;P’
Sync Period (Master and Slave Modes) 128 *tcl~ ,pi<$;::ga;*Ycf& ns
Sync High (Slave Mode) 20 ““:t},,;#26*tcl~ ns
,\
Input Capacitance .:’~,s.,.‘\,
>’.,
;:. 20 pF
~. ‘i~R\*,,,
(Except for LeWRight Channel Inputs) ~“;~?tj,.,1,$,
\.#-~$,.,,i
,,.:{.’,’..3’ .
Master Mode: ISLAV =O++.“f; .;*c’
$Y!,P
‘?;>,\
..>..~...,>,,.,.
SCLKPeriod ‘~g;;~ 2‘tcl~
\\.pr ns
SCLK Duty Cycle “~:$~e 0.667 1.50
,.,’$:+:$l’t,
.- ~~.
Propagation Delay (Note 2) ~h,i$i, ‘$
CLK Falling Edge to SYNC ,$l& ~’t’-” 40 ns
CLK Rising Edge to SYNC ,.:/,>> -a; tclk +40 ns
CLK Falling Edge to SYNC ~.~:.’?,. ~
..’K$,. 2*tclk +40
.:.-.., ns
,,
Propagation Delay (Note 2) *’ $
.~-‘$’..
CLK Falhng Edge to SCLK >$i$:~~,?* 140
.,:t.i*?*,:,j}::.. ns
CLK Rising Edge to SCLK .<?,,:$,,..1.>tiv 2
,.:, tclk +40 ns
CLK Falting Edge to SCLK ..... 32*tclk +40 ns
,>,?$
Propagation Delay (Note 2~Y~,,.
CLK Falling Edge to SeriaBQat~Vaiid, SDO 140
CLK Rising Edge to @w~a Valid, SDO 2~lk +40
CLK Falling Edge,,#~~rl~FOata Valid, SDO 32*tclk +40
-’ .“
sl~;wa: ls~v =1
w.’
Setup Ti~$ ‘&t&3) 15
SCLK@$#&~:Edge of CLK }
ns
ns
ns
ns
~*~*~Note 3)
.~~~!o Rising Edge of CLK ons
$LK High 20 ns
$CLK LOW 20 ns
Setup Time (Note 3) 15 ns
SYNC to Rising Edge of CLK
Hold Tme (Note 3) ons
SYNC to Rising Edge of CLK
Propagation Delay
Clk Rising Edge to Serial Data Valid, SDO 1twch twch +40
2tclk 2*tclk +40
3tclk +twch 3*tclk +twch +40
NOTES:
1. The internal clock frequency, or input sampling frequency (CLKI) is governed by the divide mode and output data rate.
The divide mode can be either 1,2, or 3. The output data rate ranges frOm 24 kHz to 48 kHz.
The minimum clock frequency of 3.072 MHz corresponds to an ou;put data rate of 24 kHz with the device in the clock divide by one mode.
The maximum clock frequency of 18.432 MHz corresponds to an output data rate of 48 kHz with the device in the clock divide by three mode.
2. Propagation delay is measured with acapacitive load of 50 pF.
3. In the slave mode, SYNC or SCLK transitions can occur an~here except Oto -5 ns relative to the CLK rising edge.
MOTOROLA MC1450737
+twch+
1
CLK,CLKI L
‘YNCW
Cwl
CW2
CLW3
1~ $Ik, tclti ~1
Figure 6.
MC145073 MOTOROLA
8
PIN DESCRIPTIONS
ANALOG PINS
AIN(+L), AIN(-L)
Left Channel Analog Inputs (Pins 1,2)
These two pins comprise the left channel analog differ-
ential inputs. The voltage range of signals applied to these
pins is from VSS(A) to VDD(A). Apositive full–scale input
to the ND is defined as adifference of 3.8 Vp–p between
AIN(+L) and AI N(-L).
AIN(+R), AIN(-R)
Right Channel Analog Inputs (Pins 24, 23)
These two pins comprise the right channel analog differ-
ential inputs. The voltage range of signals applied to these
pins is from VSS(A) to VDD(A). Apositive full–scale input
to the ND is defined as adifference of 3.8 VWp between
AIN(+R) and AIN(_R).
REF
Output of the Internal Voltage Reference (Pin 3)
The nominal value of this internal voltage reference is 2V.
The output of the reference is brought out to this pinto facili-
tate filtering. For proper device operation, this pin should be
decoupled to VSS(A) with a1.0 pF electrolytic
capacitor in parallel with a0.1 LF ceramic capacitor. In order
when the SYNC signal is active high, and right channel data
is transmitted when the SYNC signal is low. See the Serial
Interface Description section for more information.
SCLK
Serial Interface Clock lnputiOutput (Pin 12)
The SCLK pin is an input or output depending on the state
of the ISLAV pin. Serial output data is clocked out of the
MCI 45073 on the rising edge of SCLK. When SC% is an
input, it is reclocked by the internal sample rate,:wWLKl,
before being used by the MCI 45073 to cloc~~ow$~~ serial
data. This reclocking ensures that rapid ~$ed changes
through the SDO pin do not affect the an~~~$’~tiormance of
the device. See the Serial lnterface,pc~on section for
more information. %,,$ti{:’,,2,<‘!
,,}$w~i,.\*,>
~,p,e
.,::
,., $
.~...,,... ‘\&
.:%:+.,13.
SDO $
.$,*
Serial Interface Data Ou,~~~&Jn 13)
, ;: ~
The ND conversion~&<$ulf&Hor the Iefi and right channels
are output on this pifit,<~~’+is shitied out of the MCI 45073
MSB first, with the ~~wnel data preceding the tight chan-
nel data. The,,@~ial ohtput data is clocked out on the rising
edge of SCNi6&&lhe Serial Interface Description section
‘i “.$i:.‘**,
for more i~for~at]on.
*!,.$*~?+,i,{.,<,<:
“..,.,,,>..
FT~ ‘r$~..
R~,ory Test Mode Inputs (Pins 9, 10)
,“~+’fl~hese pins should be connected to VSS(A) for normal
,,?,
to economize on filtering capacitors, the REF pin can, be ~(~$+~~vice operation. .,
connected to VAG. However, this could result in aposslbl~~&k$
degradation of petiormance of the device at high signal ‘~!~
,) .<.:+,,,
Analog ground is used to bias the ,#WPanalog circuits
and is nominally 2V. VAG is brougM,9u?~%is pin to facilitate
filtering. This pin should be deco~&~%+VSS(A) with a1.0 ~F
electrolytic capacitor in paral~a~t,&Q,~;0.1 yF ceramic capaci-
tor for normal device opera$n.:,
,,,..,~~
‘~il,.h.*V
.,,y..,,~~
,y.
DIGITAL PINS ‘~:~
.>,>>,.
,$,,
J$$\,t!.
*j .
.:*$.. ,’+>i.$
This p~}$~~,~e master clock input for the device, Analog
input $~ha~to the MC145073 are sampled at arate equal to
thi~$&~&./frequency divided by 1, 2, or 3, depending on the
~~~ @clock mode pins CSELI ,0. The serial data output
?$~$ws equal to the input sample rate divided by 128.
‘:~or example, if CLK is running at a12.288 MHz rate, and
divide by 2is selected, then the output data rate is
(12.288 MHd2)/128 =48 kHz. For more detail, see the Sum-
mary of Operating Modes section.
SYNC
Serial Interface Frame Sync lnpuVOutput (Pin 11)
The SYNC pin is an input or output depending on the state
of the ISLAV pin. The SYNC signal resets and synchronizes
the serial interface transmitter and receivers, as well as most
internal clocks. Left channel serial output data is transmitted
CSELO, CSEL1
Clock Divide Mode Select Inputs (Pins 21, 20)
The device master clock input is divided by 1, 2, or 3, or
the device is placed in apower–down mode depending on
the state of these pins. See the Summary of Operating
Modes section for more information.
FSEL
FIR Filter Response Select Input (Pin 19)
Alow level on the FSEL input selects aFIR filter transition
band from 20 to 25.8 kHz at the 48 kHz output data rate. A
high level on the FSEL pin selects afilter transition band from
20 to 24 kHz at the 44.1 kHz output data rate. See the Sum-
mary of Operating Modes section for more information.
[SYNC
Serial Interface Sync Format Select Input (Pin 18)
Alow level input on the lSyNC pin selects aSYNC rising
edge one SCLK cycle before the initiation of aserial data
transfer. Ahigh level on the lSyNC pin will select aSYNC
rising edge that is coincident with the initiation of aserial data
transfer. See the Summary of Operating Modes and the
Serial Intetiace Description sections for more information.
ISLAV
Serial Intetiace Slave Mode Select Input (Pin 17)
This pin controls the direction of the serial intetiace SYNC
and SCLK signals. Alow level on the ISLAV pin will configure
the SYNC and SCLK pins as outputs, while ahigh level on
the ISLAV pin will configure the SYNC and SCLK pins as in-
puts, See the Summary of Operating Modes and the Serial
Intetiace Description sections for more information.
MOTOROM MC1 450739
IJUST
Serial Interface Data Justification Select Input (Pin 16)
Alow level on the IJUST pin will cause the serial output data
to be left justified relative to the SYNC signal. Ahigh level on
the IJUST pin will select right justification of the serial output
data, See the Summary of Operating Modes and the Serial
Interface Description sections for more information.
IDOE
Serial Intetiace Data Output Enable (Pin 15)
This pin controls the state of the SDO pin between 16–bit
data word transfers. Ahigh level on this pin will force the
SDO pinto alow level between serial data words, while alow
level on the IDOE pin will force the SDO pin to ahigh–imped-
ance state between data words, See the Summary of Oper-
ating Modes and the Serial Interface Description sections
for more information.
POWER SUPPLY PINS
VDD(A) (pin 4)
Positive analog power supply input. The voltage range for
this pin is 4.5 to 5.5 Vwith respect to VSS(A). The absolute
value of the difference between VDD(A) and VDD(D) must not
exceed 0.5 V. For proper device operation, this pin should be
decoupled to VSS(A) with a1.0 ~F or larger capacitor.
FUNCTIONAL DESCRIPTION
The MCI 45073 is a1-bit stereo audio ND convener in-
tended for use in digital audio systems. The MC1 45073 uses
asigma+elta architecture consisting of asecond order ana-
log modulator followed by two stages of digital filtering for
each channel. The analog modulator samples the input sig-
nal at avery high rate (128x the output data rate), petiorms a
single bit quantization, and shapes the quantization noise to-
wards out–of–band frequencies. The digital filter#$Qf the
MCI 45073 reject most of the shaped quantizatio~,pqwsand
.“$.>..“t}.
lower the serial data output rate. The digital filt~~n$’&~mple-
mented with a5th order, decimate–by–32 com.~a$$ollowed
by a 121 tap, decimate–by–4, FIR filter o~~~~~~$channel. In
addition to rejecting quantization nois~:~~d R&Rfilter cancels
the curvature in the response of tQ&~:~:@’ding comb filter.
The comb and FIR filters also pr&Jd$anti–alias filtering of
out–of–band signals present~~+he Thbut to the device. The
analog inputs to the MC14,%,~@n be fully differential (both
inputs dynamic and 180.<~~~r<&&out of phase), or single+ n-
ded (positive inputs dy~~~@~khile negative inputs are static
at alevel in the mid@~$%e supply range). Analog input sig-
nals that excee,~~,e difibrential analog input voltage range of
3.8 Vp–p ar~. c]$~~%din order to prevent overflow of the digi-
*,*it,:},$*
tal filters.,$~~e ~~1 45073 operates from asingle 5Vpower
supply. .~:~,’xtiable or other low power applications, apow-
er–d~wn’~,ode is available,
9$,oPeration of the MC1 45073 can be tailored to specific
.:~~llc~ions by proper selection of the states of seven mode
.{.<“~q!~t pins. These mode pins control the divide ratio of the
Negative analog power supply input. This pin sho~!d be
connected to ground for normal device operation. ,>,$,%.
..,.,.‘:~’..$
-4.
:s,
,., ,,..
VSS(A) (pin 5) ~~~$~aster clock, the FIR filter response, and the serial interface
‘%?format. The master clock input can be divided by either 1, 2,
or 3to yield the input sampling rate. This means that the in- *
put clock frequency is either 128x, 256x, or 512x the serial
VDD(D) (pin 8)
Positive digital power supply input. Th{~~~~&; range for
this pin is 4,5 to 5.5 Vwith respect to V~#~#~ The absolute
value of the difference between VD~:~~@~VDD(D) must not
exceed 0.5 V. For proper device o$er~~on, this pin should be
decoupled to VSS(D) with a~&~J5?larger capacitor.
,-\. P
,ii-*}.! ..,.”
VSS(D) (pin 7) ,, ‘$” ,’
,,..
Negative digital f@iw~~supply input. This pin should be
connected to g{~~’&foY normal device operation.
.,~$:l)?
-**,, .
output data rate.
NOTE
The oversampling ratio (OSR), which is the
ratio of input sampling frequency to output data
rate, is 128x in all three cases.
Two sets of FIR filter coeticients are stored in the on–
board ROM of the MC1 45073. One set provides atransition
band from 20 kHz to 25.8 kHz for operation at the 48 kHz out-
put data rate, The other set of FIR filter coefficients provides
atransition band from 20 kHz to 25 kHz for use with the
44.1 kHz output data rate,
Four mode select pins configure the serial intetiace. This
yields sixteen possible serial interface operating modes.
Included are modes that provide for intetiacing directly to
Motorola and TI general purpose DSPS, multiplexing of two
MC145073s, as well as formats similar to the CS5326 inter-
face,
MC145073 MOTOROLA
10
SUMMARY OF DEVICE OPERATING MODES
The seven pins summarized in the tables below configure
the MC1 45073 to operate in one of the modes specified. The
modes can be chosen in any combination.
CSEL1 CSELO Master CLK Divider Select
o 0 Power-Down
o1Divide CLK by 1
10Divide CLK by 2
11Divide CLK by 3
FSEL FIR Filter Transition Band Select
o20 kHz –25.8 kHz Transition Band
8.144 MHz Input Rate, 48 kHz Output Data Rate.
1 20 kHz -25 kHz Transition Band
5.6448 MHz Input Rate,
44.1 kHz Output Data Rate
~
Serial Interface SYNC Signal Format
SYNC rising edge is one SCLK cycle before the
stati of the serial output data transfer. (This IS
compatible with the DSP5800/58001 and TMS320
serial interface is provided in the AC Electrical Specifica-
tions section .
Compatibility with the DSP56000/1 and TMS320 general–
purpose DSPS is accomplished by applying the appropriate
logic level to the lSyNC pin. The phase of the rising edge of
the SYNC signal is different for the DSP56000 and TMS320
applications, while the falling edge of SYNC is not critical in
such applications.
To interface to one or two MC145073~, the
DSP56000/56001 should be configured as follo~~vdwork
mode, four time slots per frame, 16 bits per sl,$?~~~$inuous
clock, and control signals configured as eit@$~:P~iWaster or
slave. If intetiacing to aTMS320 is desi~’~t,+& serial inter-
face should be configured in continuo@<mQ@&without frame
sync. ‘,~>;?,..i>~...~.,,.,
~~iy.,/.
,S.,:f.*,?.*,,,(Y$.
NOT~’~$,,,;}
The TMS320 interfa~~~us~be initialized with
frame sync enable~+~’~~n switched to the no
frame sync mod@~~#rhltialization.
The IJ UST and j,~~~$ti;al intetiace mode control inputs
are provided toafa~~@~e multiplexing of two MC145073s.
The IJUST i~~~$~lects between left and right justification of
the serial ,,m~$ata relative to the SYNC signal, while the
lDOE,i@$&,p@vides away to force the SDO pinto the high
impe%~eifate between the output data words. To multi-
p~,~~ th~eerial data outputs of two MCI 45073s onto the
,,b~ak$ SDO line, IDOE must be forced low on both
1SYNC rising edge is coincident with the start of the I,$%145073s,
while the IJUST pin is forced high on one
serial output data transfer. (This is compatible with ‘~~~MCI 45073 and low on the other. TheMC145073s must be in
the CS5328 interface definition.) ‘:~’””++the slave mode (ISLAV= I)when multiplexing. It is not Pos-
.~s,?t,
<c.% :, .,,.
IDOE .$), ?+?$,’”Serial Interface Data Output Enable
$: ‘*, ‘SDO goes to ahigh–impedance state between
‘.:,*’* 16–bit output words.
SDO is forced low between 1&bit output words.
?. SERIAL INTERFACE DESCRIPTION
As summarized in the previous section, the format of the
serial intetiace is controlled by four mode pins: ISYNC, ISLAV,
IJUST, and IDOE. These control inputs can be configured in
any combination, yielding 24 =16 unique modes. The follow-
~ing two subsections describe the format of the serial inter-
~face for these various modes, Timing information for the
.-- . .. , ,-
sible to operate with one MC1 45073 as amaster tied to a
second MC1 45073 operating as aslave due to the reclock-
ing of the SYNC and SCLK inputs in the slave mode (see
Operation with the MC1 45073 as a Slave (ISLAV =1) sec-
tion).
NOTE
When multiplexing two MC1 45073 devices, all
four analog channels are sampled at exactly the
same phase.
In Figures 10 and 11, the internal clock signal CLKI is
plotted instead of CLK. This is due to the fact that all internal
clocks, as well as the serial interface, are slaved to this
divided version of the master clock. Input signals to the serial
interface are reclocked by CLKI to reduce the amount of
noise injected into the analog section of the MCI 45073. Seri-
al output data and high–impedance states of the SDO pin are
clocked out relative to CLKI. This reclocking can cause a
shift in phase of SDO relative to SCLK when operating in the
slave mode. In cases where the MC1 45073 output is multi-
plexed with another device, the clock divide by 1mode is
recommended.
NOTE
If the clock divide by 2or 3mode is selected, it
is impossible to know the exact phase of CLKI,
On initial power–up or recove~ from apower+ own condi-
tion, the first 68 serial output words of the MC1 45073 are
indeterminate. This is because the digital filters and internal
logic of the MC1 45073 must settle. This time is also used to
charge the external REF filter capacitor.
MOTOROLA MC1 45073
11
Operation with the MC145073 as a Master (ISLAV =O)
When ISMV =O,the SYNC and SCLK signals are defined
as outputs, and the MC1 45073 is configured as master
device. In this mode there are eight possible serial formats
as illustrated in Rgure 10. The phase of the SYNC output
can precede the serial output data by one SCLK cycle (com-
patible with DSP56000/56001, TMS320, and 12S interface
format), or the SYNC signal can be coincident with the serial
output data (similar to the CS5326 serial intetiace format).
As shown in Hgure 10, with each of these two SYNC formats
there are four possible formats for the serial output data.
Serial output data is shifted out MSB first, with left channel
data preceding the tight channel data, All of the serial inter-
face outputs, SYNC, SCLK, and SDO are initiated by aCLKI
rising edge. There are 128 CLKI cycles, and 64 SCLK cycles
per output data cycle. Multiplexing of two MC145073s is not
feasible in the master mode since the exact phase of the out-
put cannot be controlled.
NOTE
The serial data in one output cycle represents
data that was simultaneously sampled on the two
analog input channels.
It is possible to initiate the device in the slave mode de-
scribed in the Operation with the MC1 45073 as a Slave
(ISLAV =1) section, and then switch to master mode. Once
set, the phase of SYNC should not change.
Operation with the MC145073 as a Slave (ISLAV =1) S
When ISLAV =1the SYNC and SCLK signals are defined
as inputs, and the MCI 45073 is configured as aslave de-
vice, However, the slave mode of the MC1 45073 is not atrue
slave mode since the SYNC and SCLK inputs are rg~~ked
by the internal sample clock, CLKI. These intern@r~~&ked
versions of SYNC and SCLK are shown in Figu&.,f~lfin addi-
tion to the external SYNC and SCLK signa~.~$.~~i+i)”
Similar to the master mode of the prW’ti&%ection, there
t,J<...
are two formats for the SYNC signal, ~~~~dr SDO formats,
yielding eight possible slave mode@?W*$~*#
Multiplexing of two MC1450~~s:}k,.@e slave mode is per-
formed by forcing IDOE low ~;~~thM“C145073s, and forcing
IJUST high on one MC14@b%;3:~?d low on the other.
,$;$$;TE
When multi@~$;wo MC145073s, the mas-
ter clockpd~vid~.by 1mode should be used
(CSELl,&+*I*) so that the exact phase of CLKI
is de~$rfi~~.
-
MC145073
12 MOTOROLA
.,,,.
——
0❑isnri
“1
c
I=lsnrl
—
11
Figure 10. Serial Interface Operation with MC145073 Configured as Master (ISLAV =O)
.—
MOTOROLA MCI 45073
?13
PACKAGE DIMENSIONS
DW SUFFIX
SOG PACKAGE
CASE 751 E+4
i12 PL
1+1 0.010(0.25)@ IB@l
MATERIALi
LG22PL
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,“1”. 10<
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R0.25 I0.75 I0.010 [0.029
MOTOROU MC145073
15
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