CYStech Electronics Corp.
Spec. No. : C510P8
Issued Date : 2003.04.24
Revised Date :
Page No. : 1/15
PL384XBP8 CYStek Product Specification
High Performance Current Mode PWM Controllers
PL384XBP8
Description
The PL384XBP8 family of control ICs provides the necessary features to implement off-line or DC to DC fixed
frequency current mode control schemes with a minimal external parts count. Internally implemented circuits
include a trimmed oscillator for precise duty cycle control, under voltage lockout featuring start-up current less than
0.5mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM
comparator which also provides current limit control, and a totem pole output stage designed to source or sink high
peak current. The output stage, suitable for driving N-channel MOSFETs, is low in the off-state.
Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle
ranges. The PL3842B and PL3844B have UVLO thresholds of 16V (on) and 10V (off), ideally suited off-line
applications. The corresponding thresholds for the PL3843B and PL3845B are 8.5V and 7.9V. The PL3842B and
PL3843B can operate to duty cycles approaching 100%. A range of the zero to <50% is obtained by the PL3844B
and PL3845B by the addition of an internal toggle flip flop which blanks the output off every other clock cycle.
Features
• Trimmed oscillator for precise frequency control
• Oscillator frequency guaranteed at 250 kHz
• Current mode operation to 500kHz
• Automatic feed forward compensation
• Latching PWM for cycle-by-cycle current limiting
• Internally trimmed reference with undervoltage lockout
• High current totem pole output
• Undervoltage lockout with hysteresis
• Low start-up and operating current
Block Diagram( toggle flip flop used only in PL3844B and PL3845B)
S/R
5V
REF
2.50V
VREF GOOD
LOGIC
INTERNAL
BIAS
OSC
ERROR AMP.
2R
R
1V R
S
T
CURRENT
SENSE
COMPARATOR
PWM
LATCH
VREF
5V50mA
OUTPUT
8
6
VI
GROUND
RT/CT
VFB
COMP
CURRENT
SENSE
7
5
34V UVLO
4
2
1
3
PL3842B
CYStech Electronics Corp.
Spec. No. : C510P8
Issued Date : 2003.04.24
Revised Date :
Page No. : 2/15
PL384XBP8 CYStek Product Specification
Absolute Maximum Ratings
Symbol Parameter Value Unit
VI Supply Voltage (low impedance source) 30 V
VI Supply Voltage (Ii<30mA) Self Limiting
IO Output Current ±1 A
EO Output Energy (capacitive load) 5 µJ
Analog Inputs (pins 2, 3) -0.3 to 5.5 V
Error Amplifier Output Sink Current 10 mA
Ptot Power Dissipation at Tamb≤ 25℃ 1.25 W
Tstg Storage Temperature Range -65 to +150 ℃
TJ Junction Operating Temperature -40 to +150 ℃
TL Lead Temperature (soldering 10s) 300 ℃
Note : All voltages are with respect to pin 5, all currents are positive into the specified terminal.
Pin Connection (top view)
Pin Functions
No Function Description
1 COMP This pin is the Error Amplifier output and is made available for loop compensation.
2 VFB This is the inverting input of the Error Amplifier. It is normally connected to the switching
power supply output through a resistor divider.
3 ISENSE A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
4 RT/CT The oscillator frequency and maximum output duty cycle are programmed by connecting
resistor RT to VREF and capacitor CT to ground. Operation to 500kHz is possible.
5 GROUND This pin is the combined control circuitry and power ground.
6 OUTPUT This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced
and sunk by this pin.
7 VCC This pin is the positive supply of the control IC.
8 VREF This is the reference output. It provides charging current for capacitor CT through resistor RT.
Thermal Data
Symbol Description Value Unit
Rth, j-amb Thermal Resistance, junction to ambient 100 ℃/W
COMP
VFB
ISENSE
RT/CT
VREF
VCC
OUTPUT
GROUND
CYStech Electronics Corp.
Spec. No. : C510P8
Issued Date : 2003.04.24
Revised Date :
Page No. : 3/15
PL384XBP8 CYStek Product Specification
Electrical Characteristics (〔note 1〕Unless otherwise stated, these specifications apply for
0≤Tamb≤70℃,Vi=15V(note 5),RT=10k,CT=3.3nF)
Parameter Test Conditions Symbol Min. Typ. Max. Unit
Reference Section
Output Voltage Tj=25℃,IO=1mA VREF 4.9 5.0 5.1 V
Line Regulation 12V ≤ VI≤ 25V ∆VREF - 2 20 mV
Load Regulation 1mA ≤ IO ≤ 20mA ∆VREF - 3 25 mV
Temperature Stability (Note 2) ∆VREF / ∆T - 0.2 -
mV/℃
Total Output Variation Line, Load, Temperature 4.82 - 5.18 V
Output Noise Voltage 10Hz ≤ f ≤10kHz,Tj=25℃ (note 2) eN - 50 - µV
Long Term Stability Tamb=125℃, 1000 Hrs (note 2) - 5 25 mV
Output Short Circuit ISC -30 -100 -180 mA
Oscillator Section
Frequency
Tj=25℃
TA= 0 to 70 ℃
Tj=25℃(RT=6.2k,CT=1nF)
fosc
49
48
225-
52
-
250
55
56
275
kHz
kHz
kHz
Frequency Change with Volt VCC=12V to 25V ∆fosc/∆V - 0.2 1.0 %
Frequency Change with Temp TA= 0 to 70 ℃ ∆fosc/∆T - 0.5 1.0 %
Oscillator Voltage Swing Peak to peak Vosc - 1.6 - V
Discharge Current (Vosc=2V) TJ=25℃
TA= 0 to 70 ℃ Idischg 7.8
7.6
8.3
-
8.8
8.8
mA
mA
Error Amp Section
Input Voltage VPIN 1=2.5V V2 2.42 2.50 2.58 V
Input Bias Current VFB=5V Ib - -0.1 -2 µA
AVOL 2V ≤ Vo ≤ 4V 65 90 - dB
Unity Gain Bandwidth TJ = 25℃ BW 0.7 1 - MHz
Power Supply Rejec. Ratio VI = 12V to 25V PSRR 60 70 - dB
Output Sink Current VPIN 2 = 2.7V, VPIN 1 = 1.1V IO 2 12 - mA
Output Source Current VPIN 2 = 2.3V, VPIN 1 = 5V IO -0.5 -1 - mA
VOUT High VPIN 2 = 2.3V, RL = 15kΩ to ground 5 6.2 - V
VOUT Low VPIN 2 = 2.7V, RL = 15kΩ to Pin 8 - 0.8 1.1 V
Current Sense Section
Gain (note 3 & 4) GV 2.85 3 3.15 V/V
Maximum Input Signal VPIN 1 = 5V (note 3) V3 0.9 1 1.1 V
Supply Voltage Rejection 12V ≤ VI ≤ 25V SVR - 70 - dB
Input Bias Current Ib - -2 -10 µA
Delay to Output - 150 300 ns
Output Section
ISINK = 20mA - 0.1 0.4 V Output Low Level
ISINK = 200mA
VOL
- 1.6 2.2 V
ISOURCE = 20mA 13 13.5 - V Output High Level
ISOURCE = 200mA
VOH
12 13.5 - V
UVLO Saturation VCC = 6V, ISINK = 1mA VOLS - 0.1 1.1 V
Rise Time Tj=25℃, CL=1nF (note 2) tr - 50 150 ns
Fall Time Tj=25℃, CL=1nF (note 2) tf - 50 150 ns
CYStech Electronics Corp.
Spec. No. : C510P8
Issued Date : 2003.04.24
Revised Date :
Page No. : 4/15
PL384XBP8 CYStek Product Specification
Electrical Characteristics (continued)
Parameter Test Conditions Symbol Min. Typ. Max. Unit
Undervoltage Lockout Section
PL3842B/PL3844B 14.5 16 17.5 V
Start Threshold
PL3843B/PL3845B 7.8 8.4 9.0 V
Min Operating Voltage
After Turn-on
PL3842B/PL3844B
PL3843B/PL3845B 8.5
7.0
10
7.6
11.5
8.2 V
PWM Section
PL3842B/PL3843B 94 96 100 %
Maximum Duty Cycle
PL3844B/PL3845B 47 48 50 %
Minimum Duty Cycle - - 0 %
Total Standby Current
VI=6.5V for PL3843B/45B Ist - 0.3 0.5 mA
Start-up Current
VI=14V for PL3842B/44B - 0.3 0.5 mA
Operating Supply Current VPIN 2 = VPIN 3 = 0V II - 12 17 mA
Zener Voltage II = 25 mA VIZ 30 36 - V
Notes: 1. Max. package power dissipation limits must be respected; low duty cycle pulse techniques are used during test
maintain Tj as close to Tamb as possible.
2.These parameters, although guaranteed, are not 100% tested in production.
3.Parameter measured at trip point of latch with VPIN 2= 0 .
4.Gain defined as:
5. Adjust VI above the start threshold before setting at 15V.
A=
∆VPIN 1
∆VPIN 3
, 0 ≤ VPIN 3 ≤ 0.8V
CYStech Electronics Corp.
Spec. No. : C510P8
Issued Date : 2003.04.24
Revised Date :
Page No. : 5/15
PL384XBP8 CYStek Product Specification
Figure 1: Open Loop Test Circuit
8
7
6
5
4
3
2
1
VREF
0.1uF
VI
OUTPUT
GROUND
0.1uF 1W
1k
VI
VREF
OUTPUT
A
RT
2N2222
4.7k
1k
4.7k
100k
5k
COMP
VFB
ISENSE
RT/CT
CT
GROUND
ISENSE
ADJUST
ERROR AMP.
ADJUST
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass
capacitors should be connected close to pin 5 in a single point ground. The transistor and 5kΩ potentiometer are
used to sample the oscillator waveform and apply an adjustable ramp to pin 3.
Figure 2:Timing Resistor vs Oscillator Frequency
1
10
100
10 100 1000
Oscillator Frequency---fosc(kHz)
Timing Resistor---RT(kΩ)
CT=100pF
200pF
500pF
10nF
5nF
2nF
1nF
Vi=15V,TA=25
℃
Figure 3:Output Dead-Time vs Oscillator Frequency
1
10
100
10 100 1000
Oscillator Frequency---fosc(kHz)
Output Dead Time---(%)
CT=200pF
CT=500p
F
CT=1nF
CT=2nF CT=10nF CT=5nF
CT=100pF
Vi=15V
TA=25
CYStech Electronics Corp.
Spec. No. : C510P8
Issued Date : 2003.04.24
Revised Date :
Page No. : 6/15
PL384XBP8 CYStek Product Specification
Figure 4:Oscillator Discharge Current vs Temperature
7
7.5
8
8.5
9
-50-25 0 25 50 75100125
Ambient Temperature---TA(℃)
Discharge Current---Idischg(m
A)
Vi=15V
VOSC=2V
Figure 5:Maximum Output Duty Cycle vs Timing
Resistor
40
50
60
70
80
90
100
0.1 1 10
Timing Resistor---RT(kΩ)
Maximum Duty Cycle---Dmax(%
)
Idischg=7.5mA
Idischg=8.8m
A
Vi=15V
CT=3.3nF
TA=25℃
Figure 6:Error Amp Open-Loop Gain vs Frequency
-20
0
20
40
60
80
100
10 100 1000 10000 100000 100000
0
1E+07
Frequency---f(Hz)
Gain---(d
B)
Vi=15V,Vo=2 to 4V
RL=100l,TA=25℃
Figure 7:Error Amp Phase vs Frequency
0
30
60
90
120
150
180
10 100 1000 10000 100000 100000
0
1E+07
Frequency---f(Hz)
Phase---(deg)
Vi=15V,Vo=2 to
4V
RL=100k,TA=25
Figure 8:Current Sense Input Threshold vs Error Amp
Output Voltage
0
0.2
0.4
0.6
0.8
1
1.2
02468
Error Amp Output Voltage---Vo(V)
Threshold Voltage---Vth(
V)
Vi=15V
TA=-40℃
TA=25℃
TA=125℃
Figure 9:Reference Short Circuit Current vs Temperature
50
60
70
80
90
100
110
-50 -25 0 25 50 75 100 125
Ambient Temperature---TA(℃)
Short Circuit Current---ISC(m
A)
Vi=15V
RL≦0.1Ω
CYStech Electronics Corp.
Spec. No. : C510P8
Issued Date : 2003.04.24
Revised Date :
Page No. : 7/15
PL384XBP8 CYStek Product Specification
Figure 10.Oscillator and Output Waveforms
5V REG
PWM
CLOCK
OUTPUT
Vi
7
6
8
4OSCILLATOR
CT
RT
GND
5
ID
CT
OUTPUT
LARGE RT/SMALL CT
CT
OUTPUT
SMALL RT/LARGE CT
Figure 11:Error Amp Configuration
Zi
Zf COMP
VFB
1mA
2.5V
2
1
CYStech Electronics Corp.
Spec. No. : C510P8
Issued Date : 2003.04.24
Revised Date :
Page No. : 8/15
PL384XBP8 CYStek Product Specification
Figure 12:Under Voltage Lockout
PL3842B
PL3844B
PL3843B
PL3845B
VON
VOFF
16V
10V
8.4V
7.6V
ON/OFF COMMAND
TO REST OF IC
Vi 7
VOFF VON
VC
C
<17mA
<0.5mA
ICC
During UVLO, the Output is low
Figure 13:Current Sense Circuit
2R
R1V
ERROR
AMP
CURRENT
SENSE
COMPARATOR
R
Rs
C
CURRENT
SENSE
GND
COMP
3
1
5
Is
Peak Current (is) is determined by the formula
IS max ≈1.0V/Rs
A small RC filter may be required to suppress switch transients.
CYStech Electronics Corp.
Spec. No. : C510P8
Issued Date : 2003.04.24
Revised Date :
Page No. : 9/15
PL384XBP8 CYStek Product Specification
Figure 14:Slope Compensation Techniques.
VREG 8
4
3
5
GND
ISENSE
RT/CT
RT
Rslope
R1
Rs
CT
Is
VREG 8
4
35
GND
ISENSE
RT/CT
RT
Rslope
R1
Rs
CT
Is
Figure 15:Isolated MOSFET Drive and Current Transformer Sensing
VCC
5.0Vref
7
6
S
RQ
3
COMP/LATCH
Q1
ISOLATION
BOUNDARY
NpNsRs
R
C
Vin
VGS Waveforms
0
50% DC
0
25% DC
Ipk V(pin 1)-1.4
3Rs Np
Ns
CYStech Electronics Corp.
Spec. No. : C510P8
Issued Date : 2003.04.24
Revised Date :
Page No. : 10/15
PL384XBP8 CYStek Product Specification
Figure 16:Latched Shutdown
1mA
R
R
BIAS
OSC
4
8
2
1
2R
R
EA
5
2N
3903
2N
3905
SCR must be selected for a holding current of less than 0.5mA at TA(min).
The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10K.
Figure 17:External Clock Synchronization
R
R
BIAS
OSC
47Ω
0.01μF
EXTERNAL
SYNC INPUT
CT
RT
+
R
2R
5
2
1
4
8
The diode clamp is required if the Sync amplitude is large enough to cause
the bottom side of CT to go more than 300mV below ground.
CYStech Electronics Corp.
Spec. No. : C510P8
Issued Date : 2003.04.24
Revised Date :
Page No. : 11/15
PL384XBP8 CYStek Product Specification
Figure 18: Error Amplifier Compensation
+
2.5V
EA
1mA
2R
2
1
Rf
Cf
Ri
Rd
From Vo
5
R
Error Amp compensation circuit for stabilizing any current -mode topology except
for boost and flyback converters operating with continuous inductor current.
+
2.5V
EA
1mA 2R
2
1
Rf
Cf
Ri
Rd
From Vo
5
R
Rp
Cp
Error Amp compensation circuit for stabilizing current--mode boost and flyback
CYStech Electronics Corp.
Spec. No. : C510P8
Issued Date : 2003.04.24
Revised Date :
Page No. : 12/15
PL384XBP8 CYStek Product Specification
Figure 19:External Duty Cycle Clamp and Multi Unit Synchronization
RA
RB
VREF
6
5
2
5K
5K
5K
1
8
R
S
Q7
3
4BIAS
OSC
R
R
+
EA
1
2
4
8
TO ADDITIONAL
PL384XB
5
2R
R
NE555
f = Dmax =
1.44
(R
R
R
B
A+2R
B
A+2R
B)C
CYStech Electronics Corp.
Spec. No. : C510P8
Issued Date : 2003.04.24
Revised Date :
Page No. : 13/15
PL384XBP8 CYStek Product Specification
Figure 20:Soft-Start Circuit
+
S
R
Q
5Vref
BIAS
OSC
1V
5
R
2R
EA
1
2
8
4
1mA
R
R
C
1MΩ
CYStech Electronics Corp.
Spec. No. : C510P8
Issued Date : 2003.04.24
Revised Date :
Page No. : 14/15
PL384XBP8 CYStek Product Specification
Figure 21:Soft-Start and Error Amplifier Output Duty Cycle Clamp.
+
S
R
Q
5Vref
BIAS
OSC
1V
5
R
2R
EA
1
2
8
4
1mA
R
R
C
R2
R1
BC109
Vclamp
Comp/Latch
Vcc
7
Vin
Q1
Rs
7
6
5
3
VCLAMP =R
R1
1+R2
-where 0< VCLAMP <1V Ipk(max) =
V
Rs
CLAMP
CYStech Electronics Corp.
Spec. No. : C510P8
Issued Date : 2003.04.24
Revised Date :
Page No. : 15/15
PL384XBP8 CYStek Product Specification
DIP-8P Dimension
*:Typical
Inches Millimeters Inches Millimeters
DIM Min. Max. Min. Max.
DIM Min. Max. Min. Max.
A 0.2480 0.2520 6.29 6.40 H 0.0150 0.0210 0.38 0.53
B 0.3630 0.3670 9.22 9.32 I 0.0898 0.1098 2.28 2.79
C - *0.0600 - *1.52 J 0.2950 0.3050 7.49 7.74
D - *0.0500 - *1.27 K - *0.1181 - *3.00
E - *0.0390 - *0.99 L 0.3370 0.7470 8.56 8.81
F 0.1280 0.1320 3.25 3.35 M 0.0090 0.0150 0.229 0.381
G 0.1250 0.1400 3.17 3.55 α1 94° 97° 94° 97°
Notes : 1.Controlling dimension : millimeters.
2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material.
3.If there is any question with packing specification or packing method, please contact your local CYStek sales office.
Material :
• Lead : 42 Alloy ; solder plating
• Mold Compound : Epoxy resin family, flammability solid burning class:UL94V-0
Important Notice:
• All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek.
• CYStek reserves the right to make changes to its products without notice.
• CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems.
• CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance.
DIP-8P Plastic Package
CYStek Packa
e Code : P8
Marking :
A
B
8765
432
1
H
I
F
G
J
K
M
L
α1
E
D
C
384XB