Multi-Channel DMA Controller - Lattice Semiconductor

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ip1011_02

Multi-Channel DMA Controller

April 2003 IP Data Sheet

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

The product described herein is subject to continuing development, and applicable speciﬁcations and information are subject to change without notice. Such speciﬁca-

tions and information are provided in good faith; actual performance is not guaranteed, as it is dependent on many f actors , including the user's system design.

Features

■

Selectable 8237 Mode

■

Conﬁgurable up to 16 Independent DMA

Channels for Non-8237 Mode

■

Conﬁgurable Data Width of 8, 16, 32 or 64

Bits for Non-8237 Mode

■

Conﬁgurable Address Width of 16, 24 or 32

Bits for Non-8237 Mode

■

Conﬁgurable W ord Count Register Width for

Non-8237 Mode

■

Independent Auto-Initialization of All

Channels

■

Memory-to-Memory Transfers on Single,

Block, and Demand Transfer Mode

■

Memory Block Initialization

■

Software DMA Requests

General Description

The Multi-Channel Direct Memory Access (MCDMA)

Controller is designed to improve microprocessor sys-

tem performance by allowing external devices to trans-

fer information directly from the system memory.

Memory-to-memory transfer capability is also sup-

ported.

The MCDMA Controller core supports two modes: 8237

and non-8237. When the 8237 mode is selected, the

core is compatible with the Intel 8237A DMA Controller

with a few variations. These variations are listed in the

Compatibility Differences with the 8237 Intel Device

section of this document. The 8237 mode supports four

independent channels while the non-8237 mode sup-

ports up to 16 independent channels.

Block Diagram

Figure 1. DMA Controller Core Diagram

CPU Interface

AND

DMA State

Machine

hlda

ready

iowin_n

iorin_n

clk

reset

eopin_n

cs_n hreq

aen

iorout_n

iowout_n

memr_n

memw_n

eopout_n

Priority

Request

Encoder

aout[ADDR_BUS_WIDTH-1:0]

dbout[DATA_BUS_WIDTH -1:0]

dack[N-1:0]

ain[AIN_BUS_WIDTH-1:0]

dreq[N-1:0]

N = Number of channels

Block

dbin[DATA_BUS_WIDTH -1:0]

Lattice Semiconductor Multi-Channel DMA Controller

CPU Interface and DMA State Machine

The CPU Interface block consists of two blocks: Control and Data. The CPU Interface Control Block decodes the

ain

bus (address in). It generates the Enable signals to the selected registers during the write cycle. When the reg-

isters are read, it provides the

Select

signal to the multiplexer, which routes the appropriate register’s contents

onto the data bus.

The CPU Interface block implements all of the conﬁguration registers. It includes all the routing logic to transfer

either the selected register contents during the register read cycle or the temporary register contents during the

memory write cycle in a memory-to-memory transfer mode.

The DMA State Machine handles the behavior of the DMA transfer. It controls the transfer mode of memory-to-

memory and I/O-to-memory. While the non-8237 mode does not support the compressed mode, the 8237 mode

does. The 8237 mode can do an I/O-memory transfer in two clock cycles. This enhances greater throughput.

Priority Request Encoder

This Priority Request Encoder prioritizes the DMA requests and asserts the

dack

signal for the winning request. In

the 8237 mode, the arbitr ating scheme is user progr ammab le and a vailable in either ﬁxed priority or rotating priority

mode. The non-8237 mode is restricted to one mode which is ﬁxed priority mode.

In the ﬁxed prior ity mode, the highest priority channel is zero. The lowest priority is three in the 8237 mode and is

user selectable up to channel 15 in the non-8237 mode . With rotating priority, the lowest priority channel is the most

recent ser viced channel. This mode ensures that all channels are served equally. The maximum wait for a channel

to be serviced is the time taken to service all the other channels.

The 8237 and non-8237 modes have different types of registers. Tables 1 and 2 list these registers and show each

width.

Table 1. Internal Registers - 8237 Mode

Name Size in Bits Number of Registers

Base Address Registers 16 4

Base Word Count Registers 16 4

Current Address Registers 16 4

Current Word Count Registers 16 4

Command Register 8 1

Status Register 8 1

Temporary Register 8 1

Mode Register 8 4

Mask Register 8 1

Request Register 4 1

Lattice Semiconductor Multi-Channel DMA Controller

Table 2. Internal Registers - Non-8237 Mode

Compatibility Differences with the 8237 Intel Device

When the MCDMA core is conﬁgured for the 8237 mode, it differs from the 8237A Intel core in the following ways:

• The bidirectional ports are split into separate input and output ports.

• MCDMA does not support the cascade mode of operation.

• The latch that holds the upper byte of the address is internal and the address strobe signal

ADSTB

is not

generated.

• The slave’s write cycle in the MCDMA core is synchronous.

Transfer Mode

Both the 8237 and non-8237 mode of MCDMA supports three kinds of transfer mode:

•

Single T ransfer Mode

- In single transfer mode, MCDMA is programmed to make one transfer only. The

word count decrements. When the word count is about to roll over from zero to FFFFH, the signal End of

Process Output (

eopout_n

) is asserted.

•

Block T ransfer Mode

- In block transfer mode, MCDMA is programmed to continue making transfers until

eopout_n

is encountered.

•

Demand Transfer Mode

- In demand transfer mode, MCDMA is programmed to continue making transfers

until

eopout_n

is asserted or external

eopin_n

is encountered or until

dreq

is deasserted.

Parameter Descriptions

Table 3 lists the parameters used for conﬁguring the MCDMA core. The values of these parameters are to be set

and must be done prior to synthesis or functional veriﬁcation. The parameters in parenthesis are the ones gener-

ated by the IP Manager tool.

Name Size in Bits Number of Registers

Source Address Register 16, 24 or 32

Word Count Register 8, 16, 24 or 32

Destination Address Register 16, 24 or 32

Command Register 4 1

Temporary Register 8, 16, 32 or 64

Mode Register 8 N

Channel Control Register 3 N

1. Based on the width of the address bus selected

2. Based on the width of the word count register selected

3. Based on the width of the data bus selected

4. N = Number of channels selected

Lattice Semiconductor Multi-Channel DMA Controller

Table 3. MCDMA Parameters

Parameter Description Supported Values

DMA Mode

(MODE_8237) Deﬁnes the DMA mode. If it is TRUE, the DMA will be in 8237

mode, otherwise it will be in non-8237 mode. TRUE/FALSE

Number of Channel

(NUM_CHANNELS) Sets the number of channels. In 8237 mode it is ﬁxed to four

channels. In non-8237, it can be set for one to 16 channels 4 (8237)

1 - 16 (non 8237)

Data Width

(DATA_BUS_WIDTH) Sets the size of data buses and the temporary register. 8 (8237)

8 / 16 / 32 / 64 (non 8237)

Address Width

(ADDR_BUS_WIDTH) Sets the size of DMA output address. In the 8237 mode, it sets

the size of the current and base address register. In the non-

8237 mode, it sets the size of the source address register.

16 (8237)

16 / 24 / 32 (non 8237)

Word Count Width

(WORD_COUNT_WIDTH) Sets the size of the Word Count Register. 16 (8237)

8 / 16 / 24 / 32 (non 8237)

Internal Address Width

(AIN_BUS_WIDTH) Value is set automatically based on the Number of Channel

parameter (NUM_CHANNELS or N). 4 (8237)

3 when N = 1 (non 8237)

4 when N = 2 (non 8237)

5 when 3

≤

4 (non 8237)

6 when 5

≤

8 (non 8237)

7 when 9

≤

16 (non 8237)

Table 4. MCDMA I/O Signal List Ports Within User’s Application

Port Name Type Active State Description

clk

Input Rising Edge

Clock

. This signal controls and synchronizes the oper ations

of the MCDMA.

cs_n

Input Low

Chip Select

. This is an active low signal used to select the

MCDMA.

reset

Input High

Reset

. This is an active high signal that clears the internal

registers. After reset, the device is placed in the Idle state

and the DMA requests are masked.

ready

Input High

Ready

. This is an active high signal used to extend the

memory read and write pulses from the MCDMA. This is

most often used to accommodate slow memories.

hlda

Input High

Hold Acknowledge

. This active high signal generated by

the CPU indicates the CPU has relinquished control of the

system buses.

eopin_n

Input Low

End Of Process Input

. This active low input permits the

external termination of the current DMA service.

iorin_n

Input Low

I/O Read Input

. This is an active low signal. When asserted

along with

cs_n

, it permits the CPU to read the internal reg-

isters of the MCDMA.

iowin_n

Input Low

I/O Write Input

. This is an active low signal. When asserted

along with

cs_n

, it permits the CPU to write into the internal

registers of the MCDMA.

ain [AIN_BUS_WIDTH-1:0]

Input N/A

Address

. This signal selects one of the internal registers. In

the 8237 mode,

ain

is four bits wide. In the non-8237 mode,

the bus width depends on the number of channels selected.

dbin [DATA_BUS_WIDTH-1:0]

Input N/A

Data Bus Input

. The CPU writes to the internal registers

through this data bus.

Lattice Semiconductor Multi-Channel DMA Controller

Custom Core Conﬁgurations

For MCDMA conﬁgurations that are not available in the Evaluation Package, please contact your Lattice sales

ofﬁce to request a custom conﬁguration.

Related Information

For more information on core usage, please refer to the

Multi-Channel DMA Controller IP Core User’s Guide,

avail-

able at the Lattice web site at www.latticesemi.com.

dreq[N-1:0]

Input High/Low

(8237)

High

(Non-8237)

DMA Request

. These parity signals are asynchronous sig-

nals generated by peripherals requesting DMA service. A

device reset initializes

dreq

signals to active high. In 8237

mode, these parity signals are programmable to be active

high or low. In non-8237, these signals are always active

high.

hreq

Output High

Hold Request

. This is an activ e high signal sent to the CPU

to request control over the system bus.

eopout_n

Output Low

End of Process Out

. This active low signal indicates normal

termination of a DMA service.

iorout_n

Output Low

I/O Read Output

. This active low signal is used to access

data from a peripheral during a DMA Write transfer.

dbout [DATA_BUS_WIDTH-1:0]

Output N/A

Data Bus Output

. This bus contains the value of the inter-

nal register when read by the CPU. In the write-to-memory

phase of the memory-to-memory DMA operation, the

dbout

data bus transmits the data from the temporary register.

iowout_n

Output Low

I/O Write Output

. This activ e lo w signal is used to load data

to a peripheral during a DMA Read transfer.

memw_n

Output Low

Memory Write

. This active low signal is used to write data to

the selected memory location during a DMA Write or a

memory-to-memory transfer.

memr_n

Output Low

Memory Read

. This activ e lo w signal is used to access data

from the selected memory location during a DMA Read or a

memory-to-memory transfer.

aen

Output High

Address Enable

. This active high signal enables the eight-

bit latch that contains the upper eight address bits onto the

system address bus.

aout [ADDR_BUS_WIDTH-1:0]

Output N/A

Address output

. These lines are enab led only during active

DMA transfer and contain the memory address.

dack[N-1:0]

Output High/Low

DMA Acknowledge

. This signal is used to notify the

requesting peripheral that it has been granted a DMA cycle .

The polarity of this signal is programmable. A device reset

initializes all

dack

signals to active low.

Note: N = Number of channels

Table 4. MCDMA I/O Signal List Ports Within User’s Application (Continued)

Port Name Type Active State Description

Lattice Semiconductor Multi-Channel DMA Controller

Appendix for ORCA

Series 4 FPGAs

Table 5. Performance and Resource Utilization

Supplied Netlist Conﬁgurations

The Ordering Part Number (OPN) for all conﬁgurations of this core in ORCA Series 4 devices is DMA-MC-O4-N2.

Table 6 lists the Lattice-speciﬁc netlists that are available in the Evaluation Package, which can be downloaded

from the Lattice web site at www.latticesemi.com.

Table 6. Core Conﬁguration

To load the preset parameters for this core, click on the “Load Par ameters” button inside the IP Manager tool. Make

sure that you are looking for a ﬁle inside of this core's director y location. The Lattice Parameter Conﬁguration ﬁles

(.lpc) are located within this directory.

Mode Name of Parameter File LUTs ORCA 4

PFUs

Registers SysMem

EBR External

Pins f

MAX

(MHz)

8237 dma_mc_o4_2_001.lpc 1258 200 524 N/A 59 58

Non-8237 dma_mc_o4_2_002.lpc 2661 499 1187 N/A 125 66

1. Performance and utilization characteristics are generated using OR4E02-2PBGAM680-DE in Lattice’s ispLEVER™ v3.0 SP1 software.

Synthesized using Synplicity Synplify v.7.03. When using this IP core in a different density, package, speed, or grade within the ORCA fam-

ily, performance may vary slightly.

2. PFU is a standard logic block of some Lattice devices. For more information, check the data sheet of the device.

Name of

Parameter File Number of Channels Data Bus Width Address Bus Width Word Count Width

8237 Mode

dma_mc_o4_2_001.lpc 4 8 16 16

Non-8237 Mode

dma_mc_o4_2_002.lpc 4 32 32 16

Lattice Semiconductor Multi-Channel DMA Controller

Appendix for ispXPGA

Table 7. Performance and Resource Utilization

Supplied Netlist Conﬁgurations

The Ordering P art Number (OPN) f or all conﬁgurations of this core in ispXPGA devices is DMA-MC-XP-N2. Table 8

lists the Lattice-speciﬁc netlists that are available in the Evaluation Package, which can be downloaded from the

Lattice web site at www.latticesemi.com.

Table 8. Core Conﬁguration

To load the preset parameters for this core, click on the “Load Par ameters” button inside the IP Manager tool. Make

sure that you are looking for a ﬁle inside of this core's director y location. The Lattice Parameter Conﬁguration ﬁles

(.lpc) are located within this directory.

Mode Name of

Parameter File LUT4

ispXPGA

PFUs

Registers sysMEM

EBRs External

Pins f

MAX

(MHz)

8237 dma_mc_xp_2_001.lpc 1450 432 562 N/A 58 58

Non-8237 dma_mc_xp_2_002.lpc 3487 1072 1181 N/A 124 66

1. Performance and utilization characteristics are generated using LFX1200B-05F900C in Lattice’s ispLEVER™ v3.0 software. Synthesized

using Synplicity Synplify v.7.03. When using this IP core in a different density, package, speed, or grade within the ispXPGA family, perfor-

mance may vary slightly.

2. PFU is a standard logic block of some Lattice devices. For more information, check the data sheet of the device.

Name of

Parameter File Number of channels Data Bus Width Address Bus Width Word Count Width

8237 Mode

dma_mc_xp_2_001.lpc 4 8 16 16

Non-8237 Mode

dma_mc_xp_2_002.lpc 4 32 32 16