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Preliminary Datasheet AS3510
Rev. 1v 2, June 2 004 CONF IDENTIA L Page 1 of 19
General Description
The AS3510 combines high flexibility and outstanding
performance for analog audio front-end solutions.
This codec-chip contains a high performance 18 bit digital
to analog converter. The dynamic range exceeds 95dB for
best audio quality, for multi media applications (audio
playback ) within ba ttery or lin e operated equipment.
An additional audio power amplifier can directly drive
external headphones or small 4 speakers with a power of
up to half a watt. The power-up is click- and pop-less due to
a smooth start-up circuitry. The overall distortion level is
always belo w 0.02%.
The microphone input amplifier contains an automatic gain
control (AGC) with a dynamic range of 40dB to generate an
amplified and compressed signal for the ADC, which
provides 14 Bit res olution at 8kHz samplin g-rate.
Furthermore all necessary power management is included
such as bandgap reference and four voltage regulators. The
two 2.9V regulators are used internally (analog and digital
supply), but can also be used for external purposes as well.
The third output is designed to supply the peripheral cells
and an external digital core, and is programmable from 1.5V
to 2.5V in 5 steps (default is 2.5V). They are all powered
through a DCDC-Converter, which can work down to a
voltage of 1V. So the whole chip can work from a single
battery cell.
The fourth regulator is only used for generating the supply
voltage for the analog USB 1.1 interface circuit. It is
supplied via the USB connector. The performance of the
regulators is excellent (noise, line- and load-regulation) and
allows t he direct su pply of se nsitive anal og circui ts.
Because of the internal supply and signal filtering only few
small external capacitors are required for de-coupling and
stabilising and lead to very low output noise.
The current consumption is very low and makes the chip
ideally fo r batte ry powered devices.
Key Feature s
On chip DCDC Converter
- 1.0 to 5.5V input voltage range
4 On-chi p high perf ormance vol tage reg ulators
- Digital Supply, 2.9V
- Analog Su pply, 2.9V
- Core S upply, 1.5 t o 2.5V
- USB Transc eiver Suppl y, 3.2V
18 Bit stereo DAC
- Dynami c range >95 dB
- THD < - 85dB
- De-emphas is for 3 2 kHz, 44.1 kHz and 48 k Hz
Stereo po wer audio amplifie r
- Max. 2x 0.5W @ 4
- Analog vol ume control –39dB to + 3dB, 3dB st eps
including mute)
- Click- a nd pop-less startup a nd power d own
- Auxiliary inputs fo r additional audi o sources
Micropho ne input
- 14 Bit Σ∆−ADC , 8kHz sam pling ra te
- Automatic gain control (AGC)
- Low powe r consumpti on
- Wide batt ery supply range 1.0V – 5.5V
- Standard I2S interface
- Audio sampli ng rates: 8, 11.025, 12, 16, 22.05, 24, 32,
44.1, and 48 kHz
- I2C cont rol interf ace
- USB 1.1 front-e nd
- 49 Pin BGA Packa ge
Applications
- Audio fr ontend for c ellular ph ones
- Stand alo ne MP3 play er
- CD and DVD player
- PDAs
Analog Voice Codec
AS14889 PRELIM INARY DATA SHEET
Analog Audio Front-End
AS3510 DATA SHEET
CONFIDENTIAL
ams AG
Technical content still valid
Product Brief AS 3510
Rev. 1v 2, June 2 004 CONF IDENTIA L Page 2 of 19
Block Diag ram
LDO1
Right
Gain Control
+3...-39dB
Power Amplifier
Serial Audio
Interface (I2S)
&
Clock Generation
Interpolator
*64
Interpolator
*64
Multibit SD Modul a tor
with DWA
Multibit SD Modul a tor
with DWA
DAC +
SC LPF
DAC +
SC LPF
BGND Buffer Pop-less
Startup
-OUTR
-BVSS
-OUTL
-BGND
-QLDO3
-QLDO2
-
QLDO1
-
AVDD
Referenze Voltage &
Current Generation
-
AVSS2
-
AVSS
-
VREF
-
AGND
-
MICN
-
MICP
LDO3
LDO2
Amplifier
Gain Control
+3...-39dB
Left Power
DVSS -
Microphon
Amplifier
2nd Order
SD ADC
14Bit, 8kHz
+ Interpolator
Digital I2S
Synchronisation
Dith er Ge neration Head-
phone
Jack
V_REG1
V_REG3
V_REG2
100n 10u 100n 10u
2,2u / 6,3V
Z5U
2,2u / 6,3V
Z5U
2,2u / 6,3V
Z5U
c2,2u with
RL=150 Ohm,
or 330u with
RL=8 Ohm
2,2u with
R
L
=150 Ohm,
or 330u with
R
L
=8 Ohm
1 to 5.5V
2,9V, 50mA @ BVDD=3V
2,9V, 50mA
@ BVDD=3V
ENLDO12
-
PLDO3
-
ENDCDC
-
Control
Interface
(I2C Slave)
SCL
SDA
DCDC Converter
USB 1.1 + LDO3.2V
AUXR
-
AUXL
-
X
X
X
X
Single Ended to
Differental
Converter
UVDD
-
VTRM
-
D-
-
D+
-
-
-
VBAT1V
-
-
SWVSS
-
BVDD
-
-PVDD
-DVDD
-BVDD
SDO -
MCLK -
LRCK -
SCLK -
SDI -
µP Digital Audio Interface µP Control
Interface
VTRM
BVDD
AVSS
BVDD
AVSS
BVDD
AVSS
BVSS
BVDD
BVDD
BVSS
BVDD
BVSS
VPO
-
VMO
-
VP
-
VM
-
OEN
-
RCV
-
USB ConnectorµP USB Interface
Battery
1,75V to 2.5V, 200mA @ BVDD=3V
Figure 1 Block Diagram of AS3510
ams AG
Technical content still valid
Product Brief AS 3510
Rev. 1v 2, June 2 004 CONF IDENTIA L Page 3 of 19
Modes of Operation
Inputs Outputs
LDO-Modes ENLDO12 ENLDO3 DVDD, AVDD PVDD
OFF LLLDO1, LDO2 are OFF
2.8–3.6V s upply fr. Ex t. LDO3 is OFF
1.75-3.6V supply fr. Ext .
ON_12 HLLDO1, LDO2 are O N
Output is 2 .9Vtyp LDO3 is OFF
1.75-3.6V supply fr. Ext .
or conn ected to DVD D
ON_123 HHLDO1, LDO2 are O N
Output is 2 .9Vtyp LDO3 is ON
Output 2.5Vty p
Tabl e 1 LDO O perat ing Mo des
Nodes:
- 1. BVDD as input to th e LDO regul ators has to be >=3.0V.
- 2. DVDD - AVDD max . differenc e of 100mV.
- 3. PVDD has to be low er or equal to DVDD.
- 4. LDO1 i s to be use d for regulati ng AVDD (connect pin 25 to pin 26)
- 5. LDO2 ou tput is int ernaly connec ted to DVD D (pos. digit al supply)
- 6. LDO3 ou tput is int ernaly connec ted to PV DD (pos. pe ripheral s upply)
Inputs OutputsDAC-Modes DACPD I2S Gain3:0 OUTR, OUTL
OFF H X LLLL TriState
DAC_ON L LRCK up t o 50kHz
MCLK … 12 8*F(LRCK )
SCLK L=> H strobes SDI
SCLK … >=3 8*F(LRCK)
SDI left justified with MSB first
at 2nd SCLK edge
LLLL TriState
AUDIO_ON L LRCK up t o 50kHz
MCLK … 12 8*F(LRCK )
SCLK L=> H strobes SDI
SCLK … >=3 8*F(LRCK)
SDI left justified with MSB first
at 2nd SCLK edge
LLLH
.
.
HHHH
Stereo audio output
with Pow erAmp gai n adjusted
in 3dB ste ps by GAIN(3:0)
Table 2 DA C Operating M odes
Nodes:
- During supply v oltages settling at system start-up GAIN (3:0) should be h eld “L”.
- The MCLK frequency ratio to LRC K is perma nently check ed. If the r atio is diff erent to 128 , the DAC g oes in Reset -Mode (no
audio will betrans ferred).
- MCLK ris ing edge s hould not be within +/ -10ns of LR CK edges.
- Capacito rs at VREF , AGND and BG ND are nee ded for the DAC opera tion.
- The SCLK has to have at l east 34 or 38 cycles within one LRCK cycle
2*(16bit data + the l eading empty bit) or 2* (18bit da ta + the lea ding empty bit)
- There can be more S DI bits prese nted but j ust the first 18 bits are transfe rred.
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Product Brief AS 3510
Rev. 1v 2, June 2 004 CONF IDENTIA L Page 4 of 19
Inputs OutputADC-Modes ENADC I2S-Clocks
LRCK, SCLK,MCLK MICP/MICN SDO
OFF L X X static L
ADC_ON H LRCK up t o 50kHz
MCLK … 12 8*F(LRCK )
SCLK … >=3 4*F(LRCK)
Differential analog
input
to be conve rted to
digital output
SDI serial data out put
Ieft justif ied to LRCK with
MSB first at 2nd SCLK
edge
Table 3 AD C Operating M odes
Nodes:
- There are 16bit presented at SDO at each cycle but just the fi rst 14 do have relevalt data.
- The ADC is a single channel (mono) path. The same SDO bitstrea m is presented for left and right ch annel of one cycle.
- The ADC s ampling rat e is equal to LRCK/4. T his means that th e SDO bitstrea m gets update d at each 4 th cycle of LRCK.
- SCLK has to have at least 34 cycles within one LRCK cycle
2*(16bit data + the l eading empty bit)
ams AG
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Product Brief AS 3510
Rev. 1v 2, June 2 004 CONF IDENTIA L Page 5 of 19
Functional Description
Audio DAC
Block Description
This block is the complete audio DAC delivering 93dB
dynamic range. It is comprised of a multibit sigma-delta
modulator with dither option and a switched-capacitor
analog filter. This architecture provides a high insensitivity
to clock jitter. A digital interpolation filter increases the
sample rate by a facto r of 8 using 3 lin ear phase, h alf-band
filters cascaded, followed by a first order SINC interpolator
with a factor of 8. This filter eliminates the images of
baseband audio remaining only the image at 64* the input
sample rate. Optionally, a dither signal can be added that
may reduce eventual noise tones at the output. However,
the use of a multibit delta-sigma modulator already
provides extremely l ow noise tone energy .
Signal Description
Setting DACPD to ´1´ forces the analog section to power-
down. For Normal-Operation the I2S signals have to be
applied as shown bel ow:
15 0
17 2 01
15 0
17 2 01
MCLK
LRCK
SCLK
SDATA(16)
SDATA(18)
64 MCLK cycles
Left Channel
64 MCLK cycles
Right Channel
Figu re 2 I2S W avefo rms
The LRCK defines if the transferred data is for the left or
right c hannel (L=lef t).
With the rising edge of the serial clock SCLK, the
inputdat a gets stro bed.
The data word at SDATA is max. 18 bit with MSB first and
2nd complement coded. All I2S signals change state with
falling edge of SCLK.
code hex value
Max. positive code 1FFFF (hex)
+1 00001 (hex)
0 00000 (hex)
-1 3F FFF (hex)
Max. negative code: 20000 (hex)
Table 4 I2S Code Values
If the dataword length is less than 18 bit, zeros have to be
added to av oid any offset value.
The frequency of master clock MCLK has to be 128 times
the input sample rate (F(LRCK)*128) with low jitter. The
rising edge of MCLK should be separated by >10ns from
LRCK edges .
There are 2 pins needed for the generation and decoupling
of reference-voltages for the DAC. AGND is AVDD/2 and
VREF is equal to AVDD. Both pins have high output
resistance which provides a suitable lowpass filter for
these reference voltages with external capacitors of 10uF
in parallel with 100nF.
The supply lines are separate for digital DVSS / DVDD and
analog AVSS / AVDD t o minimise co upling infl uences.
The analog output is differential stereo signal at nodes
OUTRN, OUTRP and OUTLN, OUTLP respectively.
ams AG
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Product Brief AS 3510
Rev. 1v 2, June 2 004 CONF IDENTIA L Page 6 of 19
Control Interface
The interface is a standard I2C slave interface (write only).
The system uses address group 8 address 41h for audio-
processors. The following table shows the various control
options.
Byte 0 (default value: 0x80h)
Bit Name Description
7 DITH dither ena ble
1: enabl e (default )
0: disabl e
6..5 DacON 11: Audi o DAC is s witched on
10: Audio DAC is s witched on
01: Audio DAC is s witched off
00: aut omatic mode , DAC is on o nly
when I2S in terface is active
4 LP4/16 audio am plifier l oad switch
1: low p ower mode for speake rs
with more than 16 Ohm.
0: normal mode, 4 Ohm l oads
possible
3..0 Gain gain s ettings for audio amplifi er
from –39d B to +3dB in s teps of 3dB
1111: ful l output swi ng: +3dB
1110: 0dB
.
0010: -36dB
0001: mi nimum output s wing: -39 dB
0000: mute
Table 5 – Softw are I2C By te 0
Byte 1 (default value: 0x10h)
Bit Name Description
7 - not used
6 Fadc2 1: doubl es the sampli ng ADC fr eq.
0: normal A DC sampling frequnecy
5 USBspN 1: normal USB operation
0: suspen d USB
4 PwUphld 0: switc h off
3 AUXen 1: enabl e AUX inputs
0: disabl e AUX inputs
2 ADCen 1: A DC enable fo r micropho ne input
0: ADC disable
1..0 MicGain gain setti ngs for mi crophone
amplifier
11: 40dB
10: 40dB
01: 34dB
00: 28dB
Table 6 – Softw are I2C By te 1
The PowerUp hold (PwUphld; Bit 4) is when an high pulse
on the PowerUp pin occures. To switch of the AS3520 the
PwUphld bit must be cleared.
Byte 2 (default value: 0x01h)
Bit Name Description
7..6 Iaudio audio am plifier sup ply curr ent
11: 50%
10: 66%
01: 83%
00: 100% (default)
5..4 Idac audio DA C supply c urrent
11: 50%
10: 60%
01: 75%
00: 100% (default)
3..1 - not used , must be set t o 000
0 MCLK # 1: DAC us es inve rted MCLK
0: DAC uses norm al MCLK
Table 7 – Softw are I2C By te 2
Byte 3 (default value: 0x11h)
Bit Name Description
7..4 Version not used
3 - not used
1..2 - not used , must be set t o 000
0 I2Sdir 1: only 18 bit data a re accepted
0: also l ess than 18 bit can be se nt
to the I 2S interfac e and are shif ted
internal
Table 8 – Softw are I2C By te 3
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Product Brief AS 3510
Rev. 1v 2, June 2 004 CONF IDENTIA L Page 7 of 19
Power Amplifier
Block Description
The Power Amplifier Block converts the differential output
signals from the AudioDAC into single ended signals with
the drive capability for impedances 4 ohms.
With the conversion from differential to single ended, the
transformation of DC level from AGND (=AVDD/2) to BGND
(=BVDD/2) is done. The gain of this driver stage can be set
by 4 digital input signals in the range from –3 9dB to +3dB in
steps of 3dB. With the maximum gain of +3dB, full scale
gives 4. 95Vpp at the single en ded output.
With I2S data giving full-scale swing, clipping will occur with
the max. gain-step. With min. BVDD of 3.0V the same is
true f or the two highest gai n-steps.
When the control signals Gain(3:0) are all set to “L”, the
block i s set to po wer-down.
There is a BGND generation, which needs an external
capacitor of 100nF for blocking of low frequency
components at BVDD. With this external capacitor, a so
called “Klickless On” is performed so that at power-up, the
output terminals have a smooth startup to avoid any
transient noise in the headpho ne.
Gain
(3:0) Gain
difse FS Swing Gain
(3:0) Gain
difse FS
Swing
H H H H +3dB 4.95Vpp L H H H -21dB 309mVpp
H H H L 0dB 3.50Vpp L H H L -24dB 219mVpp
H H L H -3dB 2.47Vpp L H L H -27dB 155mVpp
H H L L -6dB 1.75Vpp L H L L -30dB 109mVpp
H L H H -9dB 1.24Vpp L L H H -33dB 77mVpp
H L H L -12dB 0.87Vpp L L H L -36dB 55mVpp
H L L H -15dB 0.62Vpp L L L H -39dB 39mVpp
HLLL -18dB 0.44Vpp LLLL OFF -
Table 9 Table of Gain Steps
ams AG
Technical content still valid
Product Brief AS 3510
Rev. 1v 2, June 2 004 CONF IDENTIA L Page 8 of 19
Supply Regulator
Block Description
This block can be used to provide three regulated supply
voltages fo r the
- on_chip di gital sec tion
- on_chip a nalog secti on
- external c ircuit (uP, DSP…)
from the battery supply BVDD which is directly used by the
power_amplifier.
The LDO1 and LDO2 do have the capability to drive 50mA
with a voltage drop of <=50mV (1Ohm). Since the nominal
output voltage for these LDOs is 2.9V (+/-50mV), a
regulation can be done with BVDD as low as 3.0V.
The LDO3 is used to generate a supply voltage PVDD for
the peripheral cells and external digital circuits, which are
controlling the inputs of the AS3510. The drive capability is
200mA wi th a BVDD3V.
The maximum output currents for these LDOs can be
calculate d using t he following equation:
Ohm mVVoutBVDD
I150 )((
max +
=
Vout is 2.9V for LDO1 and LDO2. The output Voltage for
LDO3 can be progra mmed via the PLDO3 pin.
PLD3 pin QLDO3 vol tage
VSS 2.25V
150k to VS S 2.0V
open 2.5
150k to DV DD 1. 5
DVDD 1.75
Table 10 LDO3 Programming
There are two pads at each LDO, o ne is the LDO output pad
and the second is the corresponding chip supply pad, which
are bonded to the same pin (LDO1 only), and have external
blocki ng caps (C block with l ow ESR).
If supply should not be generated from the on_chip LDOs,
these blocks can be disabled with control pin PowerUP.
AVDD, DVDD and PVDD can then be forced from external
regulators.
ams AG
Technical content still valid
Product Brief AS 3510
Rev. 1v 2, June 2 004 CONF IDENTIA L Page 9 of 19
Microphone Path
Block Description
This block converts a differential microphone signal into
digital and does a synchronisation to the DAC I2S input
clocks. The SigmaDelta converter clock gets derived from
MCLK. For LRCK=32kHz MCLK=4.096MHz, the
SD_CLK is 1.024MHz which gives with decimation to 14 bit
a sampli ng rate of 8kHz. Since the I2S sign als for the DAC-
path is 4 times higher, each ADC-output-code will be
present ed 4 times i n both c hannels (left , right) the same.
For LRCK=48kHz MCLK=6.144MHz, the ADC
conversion rate will be 12kHz. Due to this synchronisation
the transfer of the ADC data is possible with just one extra
digital output pin which makes the digital interface very
efficient.
The microphone amplifier can be programmed to three
different gain values 28dB/ 34dB/ 40dB to adjust the circuit
to the used microph one. The mic rophone amplifier i ncludes
a softclip function that reduces the gain when the input
voltag e range of t he ADC is vi olated.
The fullscale ADC input range is 1.157Vp differential with
AVDD=2.9V.
The softclip references are +/-0.434V which gives a
useable ADC-range of 0.868Vp differential. This gives a
nominal mic input voltage range of 34.72 / 17.36 / 8.68mVp
or 24 /12 / 6mVrms for the thr ee micamp g ain settin gs.
SoftCli p is done wit h 15 steps of –1dB.
ams AG
Technical content still valid
Product Brief AS 3510
Rev. 1v 2, June 2 004 CONFIDENTIAL Page 10 of 19
Specifications
Electrical Characteristics
Absolute Maximum Ratings
PARAMETER SYMBOL MIN MAX UNIT Note
DCDC Input Supply Voltage VBAT1.0 -0.5 5.0 V
Battery Inp ut Supply Vol tage BVDD -0.5 7.0 V
USB Input S upply Volta ge UVDD -0.5 7.0 V
AVDD Input Supply Vol tage AVDD -0.5 5.0 V
PVDD Input Supply Vol tage PVDD -0.5 5.0 V
DVDD Inp ut Supply Volta ge DVDD -0.5 5.0 V
Voltage b etween VSS-T erminals
VSS_DCDC, BVSS, AVSS, DVSS xVSS -0.5 0.5 V
Voltage a t pins:
PowerUp, PLDO3, MI CP, MICN,
VREF, AGN D, BGND, QLDO3,
QLDO2, SW
Vin -0.5 AVDD+0.5 V
Voltage a t pins:
CSCL, CSDA Vin -0.5 5.0 V no diode to DVDD
Voltage a t pins:
AUXL, AUXR , OUTL, OUTR Vin -0.5 BVDD+0.5 V
Voltage a t pins:
VTREM, DP , DM Vin -0.5 5.0 V
All oth er digital i nput pins Vi-0.5 DVDD+0.5 V
Input Cu rrent (la tchup immuni ty) Iscr -100 100 mA
Electrostatic Discharge 1 kV HBM, IEC61000-4-2
Storage T emperatur e Tstrg -55 125 OC
Soldering conditions Tlead 240 OC IEC61760-1
Humidi ty non-condens ing 5 85 %
Table 11 Table of Absolute Maximum Ratings
Operating Conditions
PARAMETER SYMBOL MIN TYP MAX UNIT
Analog In put Supply V oltage AVDD 2.8 2.9 3.6 V
Digital Input Supply Voltage DVDD 2.8 2.9 3.6 V
Digital Core Input Supply Voltage PVDD 1.5 2.5 V
Battery Inp ut Supply Volt age BVDD 3.0 3.2 5.5 V
DCDC Input Supply Voltage VBAT1.0 1.0 1.5 3.6 V
USB Input S upply Volta ge UVDD 4.0 5.0 5.5 V
Ambient Temperature -20 25 85 C
Table 12 Table of Operating Conditions
ams AG
Technical content still valid
Product Brief AS 3510
Rev. 1v 2, June 2 004 CONFIDENTIAL Page 11 of 19
Block Characteristics
Overall
SUPPLY MIN TYP MAX UNIT
AVDD (AVD D = 2.9 V) 2.6 9 mA
DVDD analo g (DVDD = 2.9V) 4.5 8.5 mA
IDD in Power Down < 1 10 uA
Tabl e 13 Tabl e of Overall Block Characteri stics
AudioDAC
PARAMETER MIN TYP MAX UNIT
ANALOG PE RFORMANCE
THD+Noise at –1dB_FS -85 -75 dB
Dynamic Range (20Hz-20kHz, -60dBFS) 90 93 dB
Interch annel Mismatc h 0.25 dB
Table 14 Table of AudioDAC Block Characteristics
Power Amplifier
PARAMETER MIN TYP MAX UNIT
ANALOG PE RFORMANCE
R_Load at AOUTR and AOUTL diff erential 8 Ohm
R_Load at AOUTR and AOUTL singl e ended 4 Ohm
Gain Step Precision (RLmin-max,20Hz -20kHz) ±0.5 ±dB
THD @ 1k Hz, BVDD=3 -5V, Gain=8, no Load - - 0.03% %
PSRR (20 0Hz-20kHz ) 60 - - dB
IOUT_powerdown -20 20 uA
Tpower_up (Cbgnd=100 nF) 200 ms
Table 15 Table of Power Amplifier Block Characteristics
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Product Brief AS 3510
Rev. 1v 2, June 2 004 CONFIDENTIAL Page 12 of 19
Supply Regulator
PARAMETER MIN TYP MAX UNIT
POR PERFOR MANCE
DVDD_POR_OFF - 2.15 V
DVDD_POR_ON 2.0 - V
POR_ON/OFF_HYST 100 mV
LRCK WATCHDOG with DVDD=2.9V
F(LRCK)_WD_OFF - 4.1 kHz
F(LRCK)_WD_ON 3.91 - kHz
ON_Delay 50 us
Table 16 Table of Supply Regulator Block Characteristics
Microphone Path
PARAMETER MIN TYP MAX UNIT
ANALOG PE RFORMANCE
Rinp_dif (MICP, MICN) 30 kohm
Gain_MicAmp_0 28 dB
Gain_MicAmp_1 34 dB
Gain_MicAmp_2 40 dB
SoftClip_AGC_Range 15*1.0 dB
Attack_Time 39 us/st
Release_Time 80 ms/st
MIC vin f ull scale_ 0 (AVDD= 2.9V) 24 mVrms
MIC vin f ull scale_ 1 (AVDD= 2.9V) 12 mVrms
MIC vin f ull scale_ 2 (AVDD= 2.9V) 6 mVrms
Decimation Rate 128
ENOB 14 bit
SNR 71 dB
PSRR tbd dB
Table 17 Table of Microphone Path Blo ck Characteristic s
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Product Brief AS 3510
Rev. 1v 2, June 2 004 CONFIDENTIAL Page 13 of 19
Measurements
The following measurement curves are the results from
noise measurements on the AS3510 DAC.
TA.: 25C, Vdd: 2.9 V, Signal: 1kHz, 0dBFS, Clk:128 *48k Hz
Figu re 3 SINA D Meas urem ent at 0dBFS
TA.: 25C, Vdd: 2.9V, Signal: 1kHz, -20dB FS, Clk:128*48kHz
Figur e 4 SINA D Meas uremen t at - 20dBFS
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Product Brief AS 3510
Rev. 1v 2, June 2 004 CONFIDENTIAL Page 14 of 19
Package and Pinning
Pin Configuration for TQFP80
Pin# PinName Type Function
25 DVSS Supply Neg. su pply of digi tal circuit
27 PVDD Supply Supply of peripheral levelshif ter of digi tal inputs
28 DVDD Supply Pos. suppl y of digi tal circui ts
29 MCLK Din with pull down Master cl ock 128*FS / left open - enables P LL
31 LRCK Din wi th pull dow n I2S_Left/ Right Fra meClock = FS
32 SCLK Din with pull down I2S_Seri al data clock >=38*FS
33 SDI Din with pull down I2S_Seri al data 18bi t left orien ted, first bit fix L
36 CSCL Din stt + spike supr I2Ccomp_Serial clock to access control register
37 CSDA Di/od stt + spike supr I2Cc omp_Serial data to ac cess cont rol registe r
38 SDO Dou t_2mA I2S_Serial da ta 14bit lef t orieted, first bit fix L
39 USBon Dout_2mA USB_indicatio n of usb su pply present
40 RCV Dout_2mA USB_diffe rential receiver output
41 VP Dout_2mA USB_sig nle ended pos. receiver output
42 VM Dout_2mA USB_signle ended neg. receiver output
43 VPO Din with pull down USB_ transmitte r pos. input
44 VMO Din with pull down USB_transmi tter neg. input
45 OEN Din with pull up USB_transmitter o utput enable (low active)
46 DVSS Supply Neg. su pply of digi tal circuit
47 DP Di /o with 1uA p d USB_pos. I/O terminal
48 DM Di/o with 1uA pd USB_neg. I /O terminal
49 VTRM Aout/Sup ply USB_3.2 V terminati on voltag e regulat or output
50 UVDD Supply USB_exte rnal supply 4-5.5V
51 AUX_R Ain 40/200k to BGND Analog aux i nput to audi o amp Righ t channel
52 AUX_L Ain 40/200k to BGND Analog a ux input to audio amp Left channel
53 PWRUP Din 360k pull down Enabl e LDO1 and 2 an d DCDC
54 PLDO3 Din_5s tate Sel ects one of 5 LDO3 states (L, 150kpd open, 150k pu, H)
55 MICP Ain 15k to ag nd Mi crophone pos . input (MIC-ADC path )
56 MICN Ain 15k to agnd Micropho ne neg. in put (MIC-ADC path)
57 VREF Ai/o 10uF d ecpl Referenc e voltage of DAC (AVDD )
58 AGND Ai/o 10uF decpl Refer ence volta ge of DAC ( AVDD/2)
59 AVSS Supply Neg. supply ter minal of anal og circuit
60 AVSS2 Supply 2nd Neg. supply terminal o f analog ci rcuit
64 AVDD Aout/Supply P os. supply o f analog circ uits, LDO 1 output – 2. 9V
65 BGND Ai/o 100nF decp Reference voltage of power-amp (BVDD/2)
66 BVDD Supply Battery s upply 3-5.5 V
67 OUTR Aout Speaker/Head phone output (4 ohm min. )
68 BVSS Supply Neg. supply ter minal of Power Amp.
69 OUTL Aout Speaker /Headphone output (4 oh m min.)
70 BVDD Supply Battery s upply 3-5.5 V
71 QLDO2 Aout LDO2 outpu t – 2.9V t o be connected to DVDD
72 QLDO3 Aout LDO3 outpu t – 1.5…2.5V to be con nected to PVD D
73 VSSDCDC Supply Power G round for DCDC Converter
74 VSSDCDC Supply Power G round for DCDC Converter
75 SWDCDC Aout Swi tch Output for DCDC Co nverter
76 SWDCDC Aout Swi tch Output for DCDC Co nverter
77 VB1V Supply Battery Supply Input ( 1V-3V)
Table 1 8 Ta ble of Pin Configur ation for TQ FP80
ams AG
Technical content still valid
Product Brief AS 3510
Rev. 1v 2, June 2 004 CONFIDENTIAL Page 15 of 19
Pin Configuration for CABGA 49
Ball# BallName Type Function
F1 DVSS Supply Neg. su pply of digi tal circ uit
B2 PVDD Supply Supply of pe ripheral l evelshifte r of digital i nputs
A2 DVDD Supply Pos. suppl y of digi tal circuits
G1 MCLK Din with pull down Master cl ock 128*FS / l eft open - enables P LL
D2 LRC K Din with pull dow n I2S_Left /Right Fra meClock = FS
E2 SCLK Din with pull d own I2S_Seri al data cloc k >=38*FS
F2 SDI Din with pull down I2S_Seri al data 18bi t left orien ted, first bit fix L
G2 CSC L Din stt + sp ike supr I2Ccomp_Serial clock to access control register
G3 CSDA Di/od stt + spike supr I2Ccomp _Serial dat a to access c ontrol r egister
F3 SDO Dou t_2mA I2S_S erial data 14bit left o rieted, firs t bit fix L
E3 USBon Dout_2 mA USB_indicatio n of usb su pply present
G4 RCV Dout_2mA USB_differential receiver output
F4 VP Dout_2mA USB_signle ended pos. receiver output
E4 VM Dout_2mA USB_signle ended ne g. receiver output
E5 VPO Din with pull down USB_trans mitter pos . input
F5 VMO Din with pull down USB_ transmitte r neg. inp ut
D5 OEN Din with pull up USB_transmitter output enable (low active)
G5 DVSS Supply Neg. suppl y of digi tal circuit
G6 DP Di /o with 1uA p d USB_pos. I/O terminal
G7 DM Di/o with 1uA pd USB_neg. I /O terminal
F6 VT RM Aout/Sup ply USB_3.2 V terminati on voltag e regulat or output
F7 UVD D Supply USB_exte rnal supply 4-5.5V
D7 AUX_ R Ain 40/200k to BGND Analog aux input to audi o amp Ri ght channel
D6 AUX_ L Ain 40/200k to BGND Analog a ux input to audio amp Left channel
E7 PWRUP Din 3 60k pull dow n Enable L DO1 and 2 an d DCDC
E6 PLDO3 Din_5stat e Selects one of 5 L DO3 states (L, 150kpd o pen, 150kpu, H)
C7 MICP Ain 15k to agnd Mi crophone pos. input (MI C-ADC path )
C6 MICN Ain 15k to agnd Mic rophone neg . input (MIC -ADC path )
C5 VREF Ai/o 1 0uF decpl Ref erence volt age of DA C (AVDD)
B6 AGND Ai/o 10uF dec pl Reference voltage of DAC (AVDD/ 2)
B7 AVSS Supply Neg. supply t erminal of anal og circuit
A7 AVDD Aout/Supply Pos. s upply of a nalog circ uits, LDO1 o utput – 2.9V
A6 BGND Ai/o 100nF decp Reference voltage of power-amp (BVDD/2)
B5 BVDD Supply Battery suppl y 3-5.5V
A5 OUTR Aout Speaker /Headphone output (4 oh m min.)
A4, B4 BVSS Supply Neg. supply t erminal of Pow er Amp.
A3 OUTL Aout Speak er/Headphone output ( 4 ohm min.)
B3 BVDD Supply Battery suppl y 3-5.5V
A1 VSSDCDC Supply Power G round for D CDC Converter
B1 VSSDCDC Supply Power G round for D CDC Converter
C1 SWD CDC Aout Switc h Output fo r DCDC Co nverter
D1 SWD CDC Aout Switc h Output fo r DCDC Co nverter
E1 VB1V Supply Battery Supply Input (1V-3V)
C2 n.c. not conn ected
C3 n.c. not conn ected
C4 n.c. not conn ected
D4 n.c. not conn ected
Table 1 9 Ta ble of Pin Configur ation for C ABGA 49
ams AG
Technical content still valid
Product Brief AS 3510
Rev. 1v 2, June 2 004 CONFIDENTIAL Page 16 of 19
VSSDCDC DVDD OUTL BVSS
VSSDCDC PVDD BVDD BVSS
OUTR BGND
BVDD AGND
1234567
A
B
C
D
E
F
G
AVDD
AVSS
SWDCDC n.c.
(QPLL)n.c.
(RESET)n.c.
SWDCDC LRCLK DACPD n.c.
VREF MICN
OEN AUXL
MICP
AUXR
VB1V SCLK USB_ON VM
DVSDS SDI SDO VP
VPO PLDO3
VMO VTRM
PWRUP
UVDD
MCLK CSCL CSDA RCV DVSS DP DM
Figure 5 Fig ure of Pi n Config uration
Mechanical Dimensions for CA BGA 49
Figure 6 Mechanical Dimensions
ams AG
Technical content still valid
Product Brief AS 3510
Rev. 1v 2, June 2 004 CONFIDENTIAL Page 17 of 19
Abbreviations
ADC analog t o digital co nverter
AGC automatic gain control
DAC digital t o analog co nverter
dBFS dB full sc ale
DSP digital signalling processor
ENOB effectiv e number of bi ts
ESD electrosta tic discharg e
I2S inter I C sound
LDO low drop regulator
PDA personal digital assistanc e
PSRR power sup ply rejecti on ratio
SFDR spurious free dynami c range
SD sigma delta
SNR signal t o noise rati o
SINAD signal t o noise and distortion (=THD+N)
TA ambient temperature
THD total harmonic distor tion
uP microprocessor
Σ∆ sigma delta
ams AG
Technical content still valid
Product Brief AS 3510
Rev. 1v 2, June 2 004 CONFIDENTIAL Page 18 of 19
Ordering Information
Number Package Description
AS3510 LQFP 80 Thin Qua d Flat Pack - 80
leads (eval uation only)
CABGA 49 ChipArray Ball Grid Array – 49
balls, 0 .8mm pitch
Devices sold by austriamicrosystems AG are covered by
the warr anty and p atent identi fication prov isions a ppearing
in its Term of Sale. austriamicrosystems AG makes no
warranty , express , statutory , implied, or by desc ription
regardi ng the inf ormation set f orth he rein or reg arding the
freedom o f the desc ribed devic es from pa tent infrin gement.
austriamicrosystems AG reserves the right to change
specifi cations and prices at any time an d without notice.
Therefore, prior to designing this product into a system, it
is necessary to check with austriamicrosystems AG for
current i nformation. This prod uct is inte nded for us e in
normal c ommercial applicatio ns. Applic ations req uiring
extended temperature range, unusual environmental
requireme nts, or high reliability applica tions, such as
military, medical life-support or life-sustaining equipment
are speci fically not recomme nded witho ut additional
processing by austriamicrosystems AG for each
application.
Copyright
Copyright © 2004, austriamicrosystems AG, Schloss
Premstaetten, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material
herein may not be reproduced, adapted, merged,
translated, stored, or used without the prior written consent
of the c opyright ow ner.
The informatio n furnished here by austriamicrosystems AG
is believed to be correct a nd accurate. Ho wever,
austriamicrosystems AG shall not be liable to recipient or
any thi rd party fo r any damages , includi ng but not l imited
to pers onal injury , property damage, loss of profit s, loss of
use, inte rruption of business or indirect , special, i ncidental
or conse quential dam ages, of a ny kind, in c onnection wi th
or arisi ng out of t he furnishi ng, perfo rmance or us e of the
technical data herein. No obligation or liability to recipien t
or any third party shall aris e or flow out of
austriamicrosystems AG rendering of technical or other
services.
ams AG
Technical content still valid
Product Brief AS 3510
Rev. 1v 2, June 2 004 CONFIDENTIAL Page 19 of 19
Contact
Headquarter
austriamicrosystems AG
Business Unit Communications
A 8141 Sc hloss Premstät ten, Austri a
T. +43 (0) 3136 544 0
F. +43 (0) 3136 569 2
accento@austriamicrosystems.com
www.austriamicrosystems.com
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ams AG
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AS3510-T AS3510