To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 Mitsubishi microcomputers M16C / 62T Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description The M16C/62T group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin or a 80-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communications, industrial equipment, and other high-speed processing applications. The M16C/62T group includes a wide range of products with different internal memory types and sizes and various package types. Features * Memory capacity ..................................M30623M4T-XXXGP : ROM 32K bytes, RAM 3K bytes M30622M8T/M8V-XXXFP,M30623M8T/M8V-XXXGP : ROM 64K bytes, RAM 4K bytes M30622MCT/MCV-XXXFP,M30623MCT/MCV-XXXGP : ROM 128K bytes, RAM 5K bytes M30622ECT/ECV-XXXFP,M30623ECT/ECV-XXXGP : PROM 128K bytes, RAM 5K bytes * Shortest instruction execution time ......62.5ns (f(XIN)=16MHZ, VCC=5V) * Supply voltage ..................................... Mask ROM version : 4.2 to 5.5V (f(XIN )=16MHZ, without software wait) One-time PROM version : 4.5 to 5.5V (f(XIN)=16MHZ, without software wait) * Low power consumption ......................140mW (VCC = 5V, f(XIN)=16MHZ) * Interrupts 25 internal interrupt sources, 8 external interrupt sources (M30622(100-pin package)) /5 sources (M30623(80-pin package)), 4 software interrupt sources, 7 levels (including key input interrupt) * Multifunction 16-bit timer ......................5 I/O timers + 6 input timers(M30622(100-pin package)) 3 I/O timers + 5 input timers(M30623(80-pin package)) * Inside 16-bit timer ................................ 3 timers(only M30623(80-pin package))(Note 1) * Serial I/O .............................................. * M30622(100-pin package) : 3 for UART or clock synchronous + 2 for synchronous * M30623(80-pin package) : 3 for UART or clock synchronous(one of exclusive UART) + 2 for synchronous(one of exclusive transmission) * DMAC .................................................. 2 channels (trigger: 24 sources) * A-D converter ....................................... 10 bits X 8 channels (Expandable up to 26 channels) * D-A converter ....................................... 8 bits X 2 channels * CRC calculation circuit ......................... 1 circuit * Watchdog timer ....................................1 line * Programmable I/O ...............................87 lines(M30622(100-pin package)),70 lines(M30623(80-pin package)) _______ * Input port.............................................. 1 line (P85 shared with NMI pin) * Memory expansion .............................. Available (to 1.2M bytes or 4M bytes) * Chip select output ................................ 4 lines(only M30622(100-pin package))(Note 2) * Clock generating circuit ....................... 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) Note 1: In M30623(80-pin package), these timers have no corresponding external pin can be used as internal timers. Note 2: M30623(80-pin package) has no external pin for chip select output. Applications Audio, cameras, office equipment, communications equipment, portable equipment, cars, etc Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition. ------Table of Contents-----Central Processing Unit (CPU) ..................... 12 Reset ............................................................. 15 Processor Mode ............................................ 28 Clock Generating Circuit ............................... 40 Protection ...................................................... 49 Interrupts ....................................................... 50 Watchdog Timer ............................................ 70 DMAC ........................................................... 72 Timer ............................................................. 82 Timers' function for three-phase motor control.......... 100 Serial I/O ..................................................... 112 A-D Converter ............................................. 148 D-A Converter ............................................. 159 CRC Calculation Circuit .............................. 161 Programmable I/O Ports ............................. 163 Electrical characteristics ............................. 178 1 Mitsubishi microcomputers M16C / 62T Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Configuration Figures 1.1.1 show the pin configurations (top view) of M30622(100-pin package) and 1.1.2 show the pin configurations (top view) of M30623(80-pin package). 51 53 52 54 56 55 57 58 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 P42/A18 P43/A19 59 60 62 61 VSS P30/A8(/-/D7) VCC P31/A9 63 65 64 66 68 67 69 70 P20/AN20/A0(/D0/-) P21/AN21/A1(/D1/D0) P22/AN22/A2(/D2/D1) P23/AN23/A3(/D3/D2) P24/AN24/A4(/D4/D3) P25/AN25/A5(/D5/D4) P26/AN26/A6(/D6/D5) P27/AN27/A7(/D7/D6) 71 72 74 73 75 76 P12/D10 P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 78 77 P10/D8 P11/D9 79 80 PIN CONFIGURATION (top view) P07/AN07/D7 81 50 P44/CS0 P06/AN06/D6 P05/AN05/D5 P04/AN04/D4 82 49 83 48 84 47 P45/CS1 P46/CS2 P47/CS3 P03/AN03/D3 P02/AN02/D2 P01/AN01/D1 85 46 86 45 87 44 P00/AN00/D0 P107/AN7/KI3 P106/AN6/KI2 88 43 89 42 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 91 93 38 P102/AN2 P101/AN1 AVSS 94 37 95 36 96 35 P100/AN0 VREF AVCC 97 34 98 33 99 32 P64/CTS1/RTS1/CTS0/CLKS1 P65/CLK1 P66/RxD1 P97/ADTRG/SIN4 100 31 P67/TxD1 90 41 P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TxD0 30 29 28 27 26 P53/BCLK P54/HLDA P55/HOLD P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V P72/CLK2/TA1OUT/V P71/RxD2/SCL/TA0IN/TB5IN P70/TxD2/SDA/TA0OUT 25 39 24 23 22 21 40 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W 19 20 18 17 15 16 VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 14 13 11 12 RESET XOUT VSS XIN 9 10 8 BYTE CNVSS P87/XCIN P86/XCOUT 5 6 P91/TB1IN/SIN3 P90/TB0IN/CLK3 4 P95/ANEX0/CLK4 P94/DA1/TB4IN P93/DA0/TB3IN P92/TB2IN/SOUT3 3 1 2 P96/ANEX1/SOUT4 92 7 M16C/62T Group P50/WRL/WR P51/WRH/BHE P52/RD Package: 100P6S-A Figure 1.1.1. Pin configuration (top view) of M30622 (100-pin package) 2 Mitsubishi microcomputers M16C / 62T Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 42 41 43 45 44 46 47 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 P42/A18 48 49 51 50 52 54 53 55 57 56 58 60 59 P07/AN07/D7 P20/AN20/A0(/D0) P21/AN21/A1(/D1) P22/AN22/A2(/D2) P23/AN23/A3(/D3) P24/AN24/A4(/D4) P25/AN25/A5(/D5) P26/AN26/A6(/D6) P27/AN27/A7(/D7) P30/A8 P31/A9 PIN CONFIGURATION (top view) P06/AN06/D6 61 40 P43/A19 P05/AN05/D5 P04/AN04/D4 P03/AN03/D3 62 39 63 38 64 37 P50/WRL/WR P51/WRH/BHE P52/RD P02/AN02/D2 P01/AN01/D1 P00/AN00/D0 65 36 66 35 67 34 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 68 33 69 32 P104/AN4/KI0 P103/AN3 P102/AN2 71 73 28 P101/AN1 AVSS P100/AN0 74 27 75 26 76 25 VREF AVCC P97/ADTRG/SIN4 77 24 78 23 79 22 P67/TxD1 P70/TxD2/SDA/TA0OUT P71/RxD2/SCL/TA0IN/TB5IN P96/ANEX1/SOUT4 80 21 P76/TA3OUT 70 P61/CLK0 P62/RxD0 P63/TxD0 29 P64/CTS1/RTS1/CTS0/CLKS1 P65/CLK1 P66/RxD1 20 19 18 30 P81/TA4IN P80/TA4OUT P77/TA3IN 17 16 15 14 12 13 VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 11 9 10 RESET XOUT VSS XIN 8 7 6 5 4 3 1 2 P95/ANEX0/CLK4 P94/DA1/TB4IN P93/DA0/TB3IN P92/TB2IN/SOUT3 P90/TB0IN/CLK3 CNVSS(BYTE) P87/XCIN P86/XCOUT P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0 31 M16C/62T Group 72 P53/BCLK P54/HLDA P55/HOLD Package: 80P6S-A Figure 1.1.2. Pin configuration (top view) of M30623 (80-pin package) 3 Mitsubishi microcomputers M16C / 62T Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Block Diagram Figure 1.1.3 is block diagrams of M30622(100-pin package) and 1.1.4 is block diagrams of M30623(80-pin package). 8 Port P0 I/O ports Port P5 A-D converter (10 bits 8 channels Expandable up to 26 channels) System clock generator UART/clock synchronous SI/O (8 bits 3 channels) (Note 1) Clock synchronous SI/O (8 bits 2 channels) XIN-XOUT XCIN-XCOUT M16C/60series 16-bit CPU core Program conter R0H R0L R0H R0L R1H R1L R1H R1L R2 R2 R3 R3 A0 A0 A1 A1 FB FB PC Memory ROM (Note 2) Vector table INTB Sutack pointer RAM (Note 3) ISP USP Multiplier Figure 1.1.3. Block diagram of M30622 (100-pin package) 8 FLG SB Note 1: One of 3 channels also functions as IIC bus interface. Note 2: ROM size depends on MCU type. Note 3: RAM size depends on MCU type. 4 8 Registers 7 CRC arithmetic circuit (CCITT) (Polynominal: X 16+X12+X5+1) Port P6 Port P10 D-A converter (8 bits 2 channels) Port P4 8 Port P9 DMAC (2 channels) Port P3 8 Port P85 Watchdog timer (15 bits) Port P2 8 Port P8 Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer TA3 (16 bits) Timer TA4 (16 bits) Timer TB0 (16 bits) Timer TB1 (16 bits) Timer TB2 (16 bits) Timer TB3 (16 bits) Timer TB4 (16 bits) Timer TB5 (16 bits) Port P1 8 8 Timer 8 Port P7 Internal peripheral functions 8 Mitsubishi microcomputers M16C / 62T Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 8 Port P0 I/O ports System clock generator A-D converter (10 bits 8 channels Expandable up to 26 channels) XIN-XOUT XCIN-XCOUT Clock synchronous SI/O (8 bits 2 channels) (Note 2) UART/clock synchronous SI/O (8 bits 3 channels) (Note 1) M16C/60series 16-bit CPU core Program conter R0H R0L R0H R0L R1H R1L R1H R1L R2 R2 R3 R3 A0 A0 A1 A1 FB FB PC Memory ROM (Note 3) Vector table INTB Sutack pointer ISP USP FLG Multiplier 8 SB RAM (Note 4) 7 Registers 7 CRC arithmetic circuit (CCITT) (Polynominal: X 16+X12+X5+1) Port P6 Port P10 D-A converter (8 bits 2 channels) Port P5 Port P9 DMAC (2 channels) Port P4 8 Port P85 Watchdog timer (15 bits) Port P3 8 Port P8 Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer TA3 (16 bits) Timer TA4 (16 bits) Timer TB0 (16 bits) Timer TB1 (16 bits) Timer TB2 (16 bits) Timer TB3 (16 bits) Timer TB4 (16 bits) Timer TB5 (16 bits) 4 4 Timer Port P2 8 Port P7 Internal peripheral functions 8 Note 1: One of 3 channels is an exclusive UART, functions as IIC bus interface. Note 2: One of 3 channels is an exclusive transmission. Note 3: ROM size depends on MCU type. Note 4: RAM size depends on MCU type. Figure 1.1.4. Block diagram of M30623 (80-pin package) 5 Mitsubishi microcomputers M16C / 62T Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Performance Outline Table 1.1.1 is a performance outline of M16C/62T group. Table 1.1.1. Performance outline of M16C/62T group Item Number of basic instructions Shortest instruction execution time Memory ROM capacity RAM I/O port Input port Multifunction timer P0, P2, P3, P5, P6, P10 P1 P4, P7 P8 (except P85) P9 P85 TA0, A3, TA4 TA1, TA2 TB0, TB2 to TB5 TB1 Serial I/O UART0, UART1 UART2 SI/O3 SI/O4 A-D converter D-A converter DMAC CRC calculation circuit Watchdog timer Interrupt Clock generating circuit Supply voltage Power consumption I/O I/O withstand voltage characteristics Output current Memory expansion Operating ambient temperature Device configuration Package 6 Performance M30622(100-pin package) M30623(80-pin package) 91 instructions 62.5ns(f(XIN)=16MHZ, VCC=5V) 32Kbytes (M30623M4T-XXXGP) 64Kbytes (M30622M8T/M8V-XXXFP, M30623M8T/M8V-XXXGP) 128Kbytes (M30622MCT/MCV-XXXFP, M30623MCT/MCV-XXXGP, M30622ECT/ECV-XXXFP, M30623ECT/ECV-XXXGP) 3Kbytes (M30623M4T-XXXGP) 4Kbytes (M30622M8T/M8V-XXXFP, M30623M8T/M8V-XXXGP) 5Kbytes (M30622MCT/MCV-XXXFP, M30623MCT/MCV-XXXGP, M30622ECT/ECV-XXXFP, M30623ECT/ECV-XXXGP) 8 bits x 6 8 bits x 1 8 bits x 2 4 bits x 2 7 bits x 1 8 bits x 1 7 bits x 1 1 bit x 1 16 bits x 3 (cycle timer, external / internal event count, pulse output) 16 bits x 2 16 bits x 2 (cycle timer, external / internal event count, pulse output) (cycle timer, internal event count) 16 bits x 5 (cycle timer, external / internal event count, pulse period / pulse width measurement) 16 bits x 1 (cycle timer, external / internal event 16 bits x 1 count, pulse period / pulse width measurement) (cycle timer, internal event count) (UART or clock synchronous) x 2 (UART or clock synchronous) x 1 UART x 1 (Clock synchronous) x 1 (Clock synchronous) x 1 (exclusive transmission) (Clock synchronous) x 1 10 bits x (8 x 3 + 2) channels 8 bits x 2 channels 2 channels (trigger: 24 sources) CRC-CCITT 15 bits x 1 (with prescaler) 25 internal and 8 external sources, 25 internal and 5 external sources, 4 software sources, 7 levels 4 software sources, 7 levels 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) Mask ROM version : 4.2 to 5.5V (f(XIN)=16MHZ, without software wait) One-time PROM version : 4.5 to 5.5V (f(XIN)=16MHZ, without software wait) 140mW (VCC=5V, f(XIN) = 16MHZ) 5V 5mA Available (to 1.2M bytes or 4M bytes) (The M16C/62T group is not guaranteed to operate in memory expansion.) 85C guaranteed version : -40C to 85C, 125C guaranteed version : -40C to 125C CMOS high performance silicon gate 100-pin plastic mold QFP 80-pin plastic mold QFP Mitsubishi microcomputers M16C / 62T Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Mitsubishi plans to release the following products in the M16C/62T group: (1) Support for mask ROM version, one-time PROM version One-time PROM version has the equally functions mask ROM version, with the exception of built-in electolic-programming-possible PROM. (2) ROM capacity (3) Package(number of pin) 100P6S-A : 100-pin plastic molded QFP 80P6S-A : 80-pin plastic molded QFP (4) Support for 85C guaranteed version, 125C guaranteed version 125C guaranteed version M30622MxV/ECV-XXXFP, M30623MxV/ECV-XXXGP is suported. These are different from 85C guaranteed version M30622MxT/ECT-XXXFP, M30623MxT/ECT-XXXGP on operating ambient temperature and the terms of the use, and so please inquire. ROM size 100-pin packaege 128K bytes M30622MCT-XXXFP M30622MCV-XXXFP 64K bytes M30622M8T-XXXFP M30622M8V-XXXFP M30622ECT-XXXFP M30622ECTFP M30622ECV-XXXFP M30622ECVFP 80-pin packaege M30623MCT-XXXGP M30623MCV-XXXGP M30623ECT-XXXGP M30623ECTGP M30623ECV-XXXGP M30623ECVGP M30623M8T-XXXGP M30623M8V-XXXGP M30623M4T-XXXGP 32K bytes Mask ROM version One-time PROM version Mask ROM version One-time PROM version Shipped in blank Note 1: It may change in the future. Note 2: Use shipped in blank of one-time PROM version as the trial, development of program. In case of vehicle-mount test or mass production, use shipped in programming. Figure 1.1.5. ROM expansion Now: Mar.1999. 7 Mitsubishi microcomputers M16C / 62T Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The M16C/62T group products currently supported are listed in Table 1.1.2. Table 1.1.2. M16C/62T group Type No. M30622M8T-XXXFP M30622M8V-XXXFP M30622MCT-XXXFP RAM capacity Characteristic 64K bytes 4K bytes 85 C guaranteed version 125 C guaranteed version (Note 3) Package Remarks Mask ROM version Mask ROM version M30622ECT-XXXFP M30622ECTFP 128K bytes M30622MCV-XXXFP M30622ECV-XXXFP M30622ECVFP M30623M4T-XXXGP Now: Mar.1999. ROM capacity 85 C guaranteed version 100P6S-A 5K bytes 125 C guaranteed version (Note 3) 32K bytes M30623M8T-XXXGP 64K bytes M30623M8V-XXXGP M30623MCT-XXXGP M30623ECT-XXXGP M30623ECTGP 128K bytes M30623MCV-XXXGP M30623ECV-XXXGP M30623ECVGP 3K bytes 4K bytes One-time PROM version (programming) One-time PROM version (blank) Mask ROM version One-time PROM version (programming) One-time PROM version (blank) Mask ROM version 85 C guaranteed version 85 C guaranteed version 125 C guaranteed version (Note 3) Mask ROM version Mask ROM version 85 C guaranteed version 5K bytes 80P6S-A One-time PROM version (programming) One-time PROM version (blank) Mask ROM version 125 C guaranteed version (Note 3) One-time PROM version (programming) One-time PROM version (blank) Note 1: It may change in the future. Note 2: Use shipped in blank of one-time PROM version as the trial, development of program. In case of vehicle-mount test or mass production, use shipped in programming. Note 3: It is different from 85C guaranteed version on operating ambient temperature and the terms of the use, pleas inquire. Type No. M30 62 2 M C T - XXX FP Package type FP : Package 100P6S-A GP : 80P6S-A ROM No. Omitted for blank one-time PROM version and EPROM version Characteristic T : 85 C guaranteed version for automobile V : 125 C guaranteed version for automobile ROM capacity 4 : 32K bytes 8 : 64K bytes C : 128K bytes Memory type M : Mask ROM version E : EPROM or one-time PROM version Shows RAM capacity, pin count, etc (The value itself has no specific meaning) M16C/62 Group M16C Family Figure 1.1.6. Type No., memory size, and package 8 Mitsubishi microcomputers M16C / 62T Group Pin Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Description Pin name VCC, VSS Signal name Power supply input CNVSS Input RESET XIN XOUT Reset input Clock input Clock output Input Input Output BYTE External data bus width select input Input AVCC P00 to P07 Analog power supply input Analog power supply input Reference voltage input I/O port P0 D0 to D7 P10 to P17 I/O port P1 Input/output Input/output D8 to D15 P20 to P27 I/O port P2 Input/output Input/output CNVSS I/O type ____________ AVSS VREF Input Input/output A0 to A7 A0/D0 to A7/D7 Output Input/output A0, A1/D0 to A7/D6 Output Input/output P30 to P37 A8 to A15 A8/D7, A9 to A15 I/O port P3 Input/output Output Input/output Function Supply 4.2 V to 5.5 V to the VCC pin. Supply 0 V to the VSS pin. This pin switches between processor modes. Connect it to the VSS pin when operating in single-chip or memory expansion mode. Connect it to the VCC pin when operating in microprocessor mode. A "L" on this input resets the microcomputer. These pins are provided for the main clock generating circuit. Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. This pin selects the width of an external data bus. A 16-bit width is selected when this input is "L"; an 8-bit width is selected when this input is "H". This input must be fixed to either "H" or "L". When operating in single-chip mode, connect this pin to VSS . In M30623 (80-pin package), the BYTE signal is internally connected to the CNVSS signal. This pin is a power supply input for the A-D converter. Connect this pin to VCC. This pin is a power supply input for the A-D converter. Connect this pin to VSS. This pin is a reference voltage input for the A-D converter. This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When used for input in single-chip mode, the port can be set to have or not have a pull-up resistor in units of four bits by software. In memory expansion and microprocessor modes, selection of the internal pull-resistor is not available. Pins in this port also function as A-D converter extended input pins as selected by software when operating in single-chip mode. When set as a separate bus, these pins input and output data (D0-D7). This is an 8-bit I/O port equivalent to P0. Pins in this port also function as external interrupt pins as selected by software. When set as a separate bus, these pins input and output data (D8-D15). This is an 8-bit I/O port equivalent to P0. Pins in this port also function as A-D converter extended input pins as selected by software when operating in single-chip mode. These pins output 8 low-order address bits (A0-A7). If the external bus is set as an 8-bit wide multiplexed bus, these pins input and output data (D0-D7) and output 8 low-order address bits (A0-A7) separated in time by multiplexing. If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D 0 -D 6 ) and output address (A 1 -A 7 ) separated in time by multiplexing. They also output address (A0). This is an 8-bit I/O port equivalent to P0. These pins output 8 middle-order address bits (A8-A15). If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D7) and output address (A8) separated in time by multiplexing. They also output address (A9-A15). 9 Mitsubishi microcomputers M16C / 62T Group Pin Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Description Pin name P4 0 to P47 ______ ______ CS0 to CS3, A16 to A19 Signal name I/O port P4 I/O type Input/output Output Output P50 to P57 I/O port P5 Input/output ________ ______ WRL/WR, WRH/BHE, RD, BCLK, __________ HLDA, __________ HOLD, Output Output Output Output Output Input ALE, RDY Output Input _________ _______ ________ P60 to P67 I/O port P6 Input/output P70 to P77 I/O port P7 Input/output P80 to P84, P86, P87, P85 I/O port P8 I/O port P85 Input/output Input/output Input/output Input P90 to P97 I/O port P9 Input/output P100 to P107 I/O port P10 Input/output Function This is an 8-bit I/O port equivalent to P0. ______ ______ _______ _______ These pins output CS0-CS3 signals and A16-A 19. CS0 -CS3 are chip select signals used to specify an access space. A16-A19 are 4 high-order address bits. This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of the same frequency as XCIN _______ as selected by software. ________ ______ _____ __________ ________ Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE ________ _________ _______ ______ signals. WRL and WRH, and BHE and WR can be switched using software control. _____ ________ ________ WRL, WRH, and RD selected With a 16-bit external data bus, data is written to even addresses ________ when the WRL signal is "L" and to the odd addresses when the ________ _____ WRH signal is "L". Data is read when RD is "L". ______ _______ _____ WR, BHE, and RD selected ______ _____ Data is written when WR is "L". Data is read when RD is "L". Odd _______ addresses are accessed when BHE is "L". Use this mode when using an 8-bit external data__________ bus. While the input level at the HOLD pin is "L", the microcomputer is __________ placed in the hold state. While in the hold state, HLDA outputs a "L" level. ALE is used to latch the address. While the input level of _______ the RDY pin is "L", the microcomputer is in the ready state. This is an 8-bit I/O port equivalent to P0. When used for input in single-chip, memory expansion, and microprocessor modes, the port can be set to have or not have a pull-up resistor in units of four bits by software. Pins in this port also function as UART0 and UART1 I/O pins as selected by software. This is an 8-bit I/O port equivalent to P6 (P70 and P71 are N channel open-drain output). Pins in this port also function as timer A0-A 3, timer B5 or UART2 I/O pins as selected by software. P80 to P84, P86 and P87 are I/O ports with the same functions as P6. Using software, they can be made to function as the I/O pins for timer A4 and the input pins for external interrupts. P86 and P87 can be set using software to function as the I/O pins for a sub clock generation circuit. In this case, connect a quartz oscillator between P87 (XCIN pin). P85 is an input-only port that P86 (XCOUT pin) and _______ _______ also functions for NMI. The NMI interrupt is generated when the _______ input at this pin changes from "H" to "L". The NMI function cannot be cancelled using software. The pull-up cannot be set for this pin. This is an 8-bit I/O port equivalent to P6. Pins in this port also function as SI/O 3, 4 I/O pins, timer B0-B4 input pins, D-A converter output pins, A-D converter extended input pins, or A-D trigger input pins as selected by software. This is an 8-bit I/O port equivalent to P6. Pins in this port also funciton as A-D converter input pins. Furthermore, P104-P107 also function as input pins for the key input interrupt function. Note 1: In M30623(80-pin package), the following signals do not have the corresponding external pin. _______ _______ P10/D 8 to P14/D12, P15/D13/INT3 to P17/D15/INT5 _______ _______ P44/CS0 to P47/CS3 ________ ________ __ ___ P72/CLK2/TA1OUT /V, P73/CST2/RTS2/TA1IN/V, P74/TA2OUT /W, P75/TA2IN/W P91/TB1IN /SIN3 Note 2: The M16C/62T group is not guaranteed to operate in memory expansion and microprocessor modes. 10 Mitsubishi microcomputers M16C / 62T Group Memory SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Operation of Functional Blocks The M16C/62T group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC calculation circuit, A-D converter, and I/O ports. The following explains each unit. Memory Figure 1.4.1 is a memory map of the M16C/62T group. The address space extends the 1M bytes from address 0000016 to FFFFF16. Internal ROM is located as the following, in M30623M4T-XXXGP from address F8000 16 to FFFFF16 (32K bytes), in M30622M8T/M8V-XXXFP and M30623M8T/M8V-XXXGP from address F000016 to FFFFF16 (64K bytes), in M30622MCT/MCV-XXXFP and M30623MCT/MCV-XXXGP from address E000016 to FFFFF16 (128K bytes). _______ The vector table for fixed interrupts such as the reset and NMI are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details. Internal RAM is located as the following, in M30623M4T-XXXGP from address 0040016 to 00FFF 16 (3K bytes), in M30622M8T/M8V-XXXFP and M30623M8T/M8V-XXXGP from address 0040016 to 013FF16 (4K bytes), in M30622MCT/MCV-XXXFP and M30623MCT/MCV-XXXGP from address 0040016 to 017FF16 (5K bytes). In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated. The SFR area is mapped to 00000 16 to 003FF 16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Figures 1.7.1 to 1.7.3 are location of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes. The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps. In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be used. For example, in the M30623MCT/MCV-XXXGP, the following spaces cannot be used. * The space between 0100016 and 03FFF 16 (Memory expansion and microprocessor modes) * The space between D000016 and D7FFF16 (Memory expansion mode) But the M16C/62T group is not guaranteed to operate in memory expansion and microprocessor modes. 0000016 SFR area For details, see Figures 1.7.1 to 1.7.3 0040016 XXXXX16 FFE0016 Internal RAM area Special page vector table Internal reserved area (Note 1) 0400016 External area D000016 Internal reserved area (Note 1) YYYYY16 FFFDC16 Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer Internal RAM area FFFFF16 FFFFF16 DBC NMI Reset Note 1. In memory expansion and microprocessor modes, can not be used. Note 2. In memory expansion mode, can not be used. Note 3. The M16C/62T group is not guaranteed to operate in memory expansion and microprocessor modes. Type No. M30623M4T-XXXGP M30622M8T/M8V-XXXFP M30623M8T/M8V-XXXGP M30622MCT/MCV-XXXFP M30623MCT/MCV-XXXGP XXXXX16 YYYYY16 00FFF16 F800016 013FF16 F000016 017FF16 E000016 Figure 1.4.1. Memory map 11 Mitsubishi microcomputers M16C / 62T Group CPU SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Central Processing Unit (CPU) The CPU has a total of 13 registers shown in Figure 1.5.1. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks. AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA b15 R0(Note) b8 b7 b15 R1(Note) b15 R3(Note) b15 A0(Note) b15 A1(Note) b15 FB(Note) b8 b7 H b15 R2(Note) b0 L H b19 b0 L Program counter Data registers b0 b19 INTB b0 Interrupt table register L H b15 b0 b0 User stack pointer USP b15 b0 b0 b0 PC b0 Interrupt stack pointer ISP Address registers b15 b0 Static base register SB b15 b0 Frame base registers b0 FLG Flag register A AAAAAAA AA A AA A AA AA AA A AAAAAAAAAAAAAA A AAAAAA IPL U I O B S Z D C Note: These registers consist of two register banks. Figure 1.5.1. Central processing unit register (1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3) Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0/R3R1). (2) Address registers (A0 and A1) Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). 12 Mitsubishi microcomputers M16C / 62T Group CPU SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (3) Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. (4) Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed. (5) Interrupt table register (INTB) Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) Stack pointer (USP/ISP) Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG). (7) Static base register (SB) Static base register (SB) is configured with 16 bits, and is used for SB relative addressing. (8) Flag register (FLG) Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.5.2 shows the flag register (FLG). The following explains the function of each flag: * Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. * Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is "1", a single-step interrupt is generated after instruction execution. This flag is cleared to "0" when the interrupt is acknowledged. * Bit 2: Zero flag (Z flag) This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, cleared to "0". * Bit 3: Sign flag (S flag) This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, cleared to "0". * Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is "0" ; register bank 1 is selected when this flag is "1". * Bit 5: Overflow flag (O flag) This flag is set to "1" when an arithmetic operation resulted in overflow; otherwise, cleared to "0". * Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is "0", and is enabled when this flag is "1". This flag is cleared to "0" when the interrupt is acknowledged. 13 Mitsubishi microcomputers M16C / 62T Group CPU SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER * Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is "0" ; user stack pointer (USP) is selected when this flag is "1". This flag is cleared to "0" when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed. * Bits 8 to 11: Reserved area * Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled. * Bit 15: Reserved area The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details. AA AAAAAAA AA AA A AA AA AA A AA AAAAAAAAAAAAAA AAAA AA A AA b15 b0 IPL U I O B S Z D C Flag register (FLG) Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Figure 1.5.2. Flag register (FLG) 14 Mitsubishi microcomputers M16C / 62T Group Reset SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Reset There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See "Software Reset" for details of software resets.) This section explains on hardware resets. When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level "L" (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the "H" level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. Figure 1.6.1 shows the example reset circuit. Figure 1.6.2 shows the reset sequence. Example when Vcc=5V. 5V 4.0V Vcc RESET 0V 5V Vcc RESET 0.8V More than 20 cycles of XIN are needed. 0V Figure 1.6.1. Example reset circuit XIN More than 20 cycles are needed Microprocessor mode BYTE = "H" RESET BCLK 24 cycles BCLK Address FFFFC16 FFFFD16 FFFFE16 Content of reset vector RD WR ("H") CS0 Microprocessor mode BYTE = "L" Address FFFFC16 FFFFE16 Content of reset vector RD WR ("H") CS0 Single chip mode Address FFFFC16 Content of reset vector FFFFE16 Note 1: In M30623(80-pin package), the BYTE signal has no external pin, and is internally connected to the CNVSS signal. Accordingly, in the microprocessor mode, BYTE = CNVSS = Vcc. Note 2: M16C/62T group is not guaranteed to operate in memory expansion and microprocessor modes. Note 3: M30623(80-pin package) is not provided with the chip select signals (CS0 to CS3). Figure 1.6.2. Reset sequence 15 Mitsubishi microcomputers M16C / 62T Group Reset SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ____________ Table 1.6.1 shows the statuses of the other pins while the RESET pin level is "L". Figures 1.6.3 and 1.6.4 show the internal status of the microcomputer immediately after the reset is cancelled. ____________ Table 1.6.1. Pin status when RESET pin level is "L" Status Pin name CNVSS = VCC CNVSS = VSS BYTE = VSS (Note 1) BYTE = VCC P0 Input port (floating) Data input (floating) Data input (floating) P1 Input port (floating) Data input (floating) Input port (floating) Address output (undefined) Address output (undefined) P2, P3, P40 to P43 Input port (floating) P44 Input port (floating) CS0 output ("H" level is output) CS0 output ("H" level is output) P45 to P47 Input port (floating) (pull-up resistor is on) Input port (floating) (pull-up resistor is on) Input port (floating) (pull-up resistor is on) P50 Input port (floating) WR output ("H" level is output) WR output ("H" level is output) P51 Input port (floating) BHE output (undefined) BHE output (undefined) P52 Input port (floating) RD output ("H" level is output) RD output ("H" level is output) P53 Input port (floating) BCLK output BCLK output P54 Input port (floating) HLDA output (The output value HLDA output (The output value depends on the input to the depends on the input to the HOLD pin) HOLD pin) P55 Input port (floating) HOLD input (floating) HOLD input (floating) P56 Input port (floating) ALE output ("L" level is output) ALE output ("L" level is output) P57 Input port (floating) RDY input (floating) RDY input (floating) Input port (floating) Input port (floating) P6, P7, P80 to P84, P86, P87, P9, P10 Input port (floating) Note 1: In M30623(80-pin package), the BYTE signal has no external pin, and is internally connected to the CNVSS signal. Accordingly, in the microprocessor mode, BYTE = CNVSS = VCC. Note 2: In M30623(80-pin package), Port P1, P44 to P47, P72 to P75 and P91 have no external pin, and are internally the above conditions. After reset, set these ports to one of the following conditions. * Be output mode, and output "L" level. * Pull-up resister is on. 16 Mitsubishi microcomputers M16C / 62T Group Reset SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Processor mode register 0 (Note 1) (000416)*** (2) Processor mode register 1 (000516)*** 0 0 0 0 0 0016 (24) A-D conversion interrupt control register (004E16)*** ? 0 0 0 (25) UART2 transmit interrupt control register (004F16)*** ? 0 0 0 (3) System clock control register 0 (4) System clock control register 1 (000616)*** 0 1 0 0 1 0 0 0 (26) UART2 receive interrupt control register (005016)*** ? 0 0 0 (000716)*** 0 0 1 0 0 0 0 0 (27) UART0 transmit interrupt control register (005116)*** ? 0 0 0 (5) Chip select control register (000816)*** 0 0 0 0 0 0 0 1 (28) UART0 receive interrupt control register (005216)*** ? 0 0 0 (6) Address match interrupt enable register (000916)*** (29) UART1 transmit interrupt control register (005316)*** ? 0 0 0 (30) UART1 receive interrupt control register (005416)*** ? 0 0 0 (31) Timer A0 interrupt control register (005516)*** ? 0 0 0 0 0 0 (7) Protect register (000A16)*** (8) Data bank register (000B16)*** (9) Watchdog timer control register (000F16)*** 0 0 ? ? ? ? ? (32) Timer A1 interrupt control register (005616)*** ? 0 0 0 (001016)*** 0016 (33) Timer A2 interrupt control register (005716)*** ? 0 0 0 (001116)*** 0016 (34) Timer A3 interrupt control register (005816)*** ? 0 0 0 (35) Timer A4 interrupt control register (005916)*** ? 0 0 0 (10) Address match interrupt register 0 (001216)*** (11) Address match interrupt register 1 0 0 0 0016 0 0 0 0 (001416)*** 0016 (36) Timer B0 interrupt control register (005A16)*** ? 0 0 0 (001516)*** 0016 (37) Timer B1 interrupt control register (005B16)*** ? 0 0 0 (38) Timer B2 interrupt control register (005C16)*** ? 0 0 0 (12) DMA0 control register (002C16)*** 0 0 0 0 0 ? 0 0 (001616)*** 0 0 0 0 (39) INT0 interrupt control register (005D16)*** 0 0 ? 0 0 0 (13) DMA1 control register (003C16)*** 0 0 0 0 0 ? 0 0 (40) INT1 interrupt control register (005E16)*** 0 0 ? 0 0 0 (14) INT3 interrupt control register (004416)*** 0 0 ? 0 0 0 (41) INT2 interrupt control register (005F16)*** 0 0 ? 0 0 0 (15) Timer B5 interrupt control register (004516)*** ? 0 0 0 (42) Timer B3,4,5 count start flag (034016)*** 0 0 0 (16) Timer B4 interrupt control register (004616)*** ? 0 0 0 (43) Three-phase PWM control register 0 (034816)*** 0016 (17) Timer B3 interrupt control register (004716)*** ? 0 0 0 (44) Three-phase PWM control register 1 (034916)*** 0016 (18) SI/O4 interrupt control register (004816)*** 0 0 ? 0 0 0 (45) Three-phase output buffer register 0 (034A16)*** 0016 (19) SI/O3 interrupt control register (004916)*** 0 0 ? 0 0 0 (46) Three-phase output buffer register 1 (034B16)*** 0016 (20) Bus collision detection interrupt control register (004A16)*** ? 0 0 0 (47) Timer B3 mode register (035B16)*** 0 0 ? 0 0 0 0 (21) DMA0 interrupt control register (004B16)*** ? 0 0 0 (48) Timer B4 mode register (035C16)*** 0 0 ? 0 0 0 0 (22) DMA1 interrupt control register (004C16)*** ? 0 0 0 (49) Timer B5 mode register (035D16)*** 0 0 ? 0 0 0 0 (23) Key input interrupt control register (004D16)*** ? 0 0 0 (50) Interrupt cause select register (035F16)*** 0016 : This bit is the cold start / warm start flag, is set to "0" at power on reset (refer to Page 71). : Nothing is mapped to this bit. ? : Undefined The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. Note 1 : When the VCC level is applied to the CNVSS pin, it is 0316 at a reset. Figure 1.6.3. Device's internal status after a reset is cleared 17 Mitsubishi microcomputers M16C / 62T Group Reset SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (51) SI/O3 control register (036216)*** 0 1 0 0 0 0 0 0 (79) A-D control register 2 (03D416)*** 0 0 0 0 (52) SI/O4 control register (036616)*** 0 1 0 0 0 0 0 0 (80) A-D control register 0 (03D616)*** 0 0 0 0 0 ? ? ? (53) UART2 special mode register (037716)*** 0016 (81) A-D control register 1 (03D716)*** 0016 (54) UART2 transmit/receive mode register (037816)*** 0016 (82) D-A control register (03DC16)*** 0016 (55) UART2 transmit/receive control register 0 (037C16)*** 0 0 0 0 1 0 0 0 (83) Port P0 direction register (03E216)*** 0016 (56) UART2 transmit/receive control register 1 (037D16)*** 0 0 0 0 0 0 1 0 (84) Port P1 direction register (03E316)*** 0016 (57) Count start flag (038016)*** (85) Port P2 direction register (03E616)*** 0016 (58) Clock prescaler reset flag (038116)*** 0 (86) Port P3 direction register (03E716)*** 0016 (59) One-shot start flag (038216)*** 0 0 0 0 0 0 0 (87) Port P4 direction register (03EA16)*** 0016 (60) Trigger select flag (038316)*** 0016 (88) Port P5 direction register (03EB16)*** 0016 (61) Up-down flag (038416)*** 0016 (89) Port P6 direction register (03EE16)*** 0016 (62) Timer A0 mode register (039616)*** 0016 (90) Port P7 direction register (03EF16)*** 0016 (63) Timer A1 mode register (039716)*** 0016 (91) Port P8 direction register (03F216)*** 0 0 0 0 0 0 0 (64) Timer A2 mode register (039816)*** 0016 (92) Port P9 direction register (03F316)*** 0016 (65) Timer A3 mode register (039916)*** 0016 (93) Port P10 direction register (03F616)*** 0016 (66) Timer A4 mode register (039A16)*** 0016 (94) Pull-up control register 0 (03FC16)*** 0016 0016 (67) Timer B0 mode register (039B16)*** 0 0 ? 0 0 0 0 (95) Pull-up control register 1 (Note 1) (03FD16)*** 0016 (68) Timer B1 mode register (039C16)*** 0 0 ? 0 0 0 0 (96) Pull-up control register 2 (03FE16)*** 0016 (69) Timer B2 mode register (039D16)*** 0 0 ? 0 0 0 0 (97) Port control register (03FF16)*** 0016 (70) UART0 transmit/receive mode register (03A016)*** (98) Data registers (R0/R1/R2/R3) 000016 (71) UART0 transmit/receive control register 0 (03A416)*** 0 0 0 0 1 0 0 0 (99) Address registers(A0/A1) 000016 (72) UART0 transmit/receive control register 1 (03A516)*** 0 0 0 0 0 0 1 0 (100) Frame base register (FB) 000016 (73) UART1 transmit/receive mode register (101) Interrupt table register (INTB) 000016 (74) UART1 transmit/receive control register 0 (03AC16)*** 0 0 0 0 1 0 0 0 (102) User stack pointer (USP) 000016 (75) UART1 transmit/receive control register 1 (03AD16)*** 0 0 0 0 0 0 1 0 (103) Interrupt stack pointer (ISP) 000016 (76) UART transmit/receive control register 2 (03B016)*** (104) Static base register (SB) 000016 (77) DMA0 cause select register (03B816)*** 0016 (105) Flag register(FLG) 000016 (78) DMA1 cause select register (03BA16)*** 0016 (03A816)*** 0016 0016 0 0 0 0 0 0 0 : Nothing is mapped to this bit. ? : Undefined The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. Note 1 : When the VCC level is applied to the CNVSS pin, it is 0216 at a reset. Figure 1.6.4. Device's internal status after a reset is cleared 18 0 Mitsubishi microcomputers M16C / 62T Group SFR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 000016 004016 000116 004116 000216 004216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 004316 Processor mode register 0 (PM0) Processor mode register 1(PM1) System clock control register 0 (CM0) System clock control register 1 (CM1) Chip select control register (CSR) Address match interrupt enable register (AIER) Protect register (PRCR) Data bank register (DBR) INT3 interrupt control register (INT3IC) Timer B5 interrupt control register (TB5IC) Timer B4 interrupt control register (TB4IC) Timer B3 interrupt control register (TB3IC) SI/O4 interrupt control register (S4IC) INT5 interrupt control register (INT5IC) SI/O3 interrupt control register (S3IC) INT4 interrupt control register (INT4IC) 004416 004516 004616 004716 004816 004916 000C16 004A16 Bus collision detection interrupt control register (BCNIC) 000D16 004B16 DMA0 interrupt control register (DM0IC) DMA1 interrupt control register (DM1IC) Key input interrupt control register (KUPIC) A-D conversion interrupt control register (ADIC) 000E16 000F16 Watchdog timer start register (WDTS) Watchdog timer control register (WDC) 001016 001116 004C16 004D16 004E16 Address match interrupt register 0 (RMAD0) 004F16 001216 005016 001316 005116 001416 001516 005216 Address match interrupt register 1 (RMAD1) 005316 001616 005416 001716 005516 001816 005616 001916 005716 001A16 005816 001B16 005916 001C16 005A16 001D16 005B16 001E16 005C16 001F16 005D16 005E16 002016 002116 DMA0 source pointer (SAR0) 005F16 002216 006016 002316 006116 DMA0 destination pointer (DAR0) 006316 002616 006416 002716 006516 002816 002916 Timer A0 interrupt control register (TA0IC) Timer A1 interrupt control register (TA1IC) Timer A2 interrupt control register (TA2IC) Timer A3 interrupt control register (TA3IC) Timer A4 interrupt control register (TA4IC) Timer B0 interrupt control register (TB0IC) Timer B1 interrupt control register (TB1IC) Timer B2 interrupt control register (TB2IC) INT0 interrupt control register (INT0IC) INT1 interrupt control register (INT1IC) INT2 interrupt control register (INT2IC) 006216 002416 002516 UART2 transmit interrupt control register (S2TIC) UART2 receive interrupt control register (S2RIC) UART0 transmit interrupt control register (S0TIC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control register (S1TIC) UART1 receive interrupt control register (S1RIC) DMA0 transfer counter (TCR0) 002A16 002B16 002C16 DMA0 control register (DM0CON) 032A16 002D16 032B16 002E16 032C16 002F16 032D16 032E16 003016 003116 DMA1 source pointer (SAR1) 032F16 003216 033016 003316 033116 033216 003416 003516 DMA1 destination pointer (DAR1) 033316 003616 033416 003716 033516 003816 003916 DMA1 transfer counter (TCR1) 033716 033816 003A16 033916 003B16 003C16 033616 DMA1 control register (DM1CON) 033A16 003D16 033B16 003E16 033C16 003F16 033D16 033E16 033F16 Figure 1.7.1. Location of peripheral unit control registers (1) 19 Mitsubishi microcomputers M16C / 62T Group SFR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 034016 Timer B3, 4, 5 count start flag (TBSR) 034216 034316 034416 034516 034616 034716 038016 038116 034116 Timer A1-1 register (TA11) Timer A2-1 register (TA21) Timer A4-1 register (TA41) 038216 038316 038416 038516 038616 038716 034C16 Three-phase PWM control register 0(INVC0) Three-phase PWM control register 1(INVC1) Three-phase output buffer register 0(IDB0) Three-phase output buffer register 1(IDB1) Dead time timer(DTT) 038816 034D16 Timer B2 interrupt occurrence frequency set counter(ICTB2) 038D16 034816 034916 034A16 034B16 038916 038A16 038B16 038C16 034E16 038E16 034F16 038F16 035016 039016 035116 035216 035316 035416 035516 Timer B3 register (TB3) Timer B4 register (TB4) Timer B5 register (TB5) 039116 039216 039316 039416 039516 035616 039616 035716 039716 035816 039816 035916 039916 039A16 035A16 035B16 035C16 035D16 Timer B3 mode register (TB3MR) Timer B4 mode register (TB4MR) Timer B5 mode register (TB5MR) 036016 Interrupt cause select register (IFSR) SI/O3 transmit/receive register (S3TRR) 036116 036216 036316 036416 SI/O3 control register (S3C) SI/O3 bit rate generator (S3BRG) SI/O4 transmit/receive register (S4TRR) 036716 039C16 039D16 Timer A1 (TA1) Timer A2 (TA2) Timer A3 (TA3) Timer A4 (TA4) Timer B0 (TB0) Timer B1 (TB1) Timer B2 (TB2) Timer A0 mode register (TA0MR) Timer A1 mode register (TA1MR) Timer A2 mode register (TA2MR) Timer A3 mode register (TA3MR) Timer A4 mode register (TA4MR) Timer B0 mode register (TB0MR) Timer B1 mode register (TB1MR) Timer B2 mode register (TB2MR) 039F16 03A016 UART0 transmit/receive mode register (U0MR) 03A116 UART0 bit rate generator (U0BRG) 03A216 03A316 03A416 03A516 036516 036616 039B16 Timer A0 (TA0) 039E16 035E16 035F16 Count start flag (TABSR) Clock prescaler reset flag (CPSRF) One-shot start flag (ONSF) Trigger select register (TRGSR) Up-down flag (UDF) SI/O4 control register (S4C) SI/O4 bit rate generator (S4BRG) 03A616 03A716 UART0 transmit buffer register (U0TB) UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1) UART0 receive buffer register (U0RB) 036816 03A816 UART1 transmit/receive mode register (U1MR) 036916 03A916 UART1 bit rate generator (U1BRG) 036A16 03AA16 036B16 03AB16 036C16 03AC16 036D16 03AD16 036E16 03AE16 036F16 03AF16 037016 03B016 037116 03B116 037216 03B216 037316 03B316 037416 03B416 037516 03B516 037716 UART2 special mode register (U2SMR) 03B716 037816 UART2 transmit/receive mode register (U2MR) UART2 bit rate generator (U2BRG) 03B816 037A16 037B16 037C16 037D16 037E16 037F16 UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1) UART1 receive buffer register (U1RB) UART transmit/receive control register 2 (UCON) 03B616 037616 037916 UART1 transmit buffer register (U1TB) UART2 transmit buffer register (U2TB) UART2 transmit/receive control register 0 (U2C0) UART2 transmit/receive control register 1 (U2C1) UART2 receive buffer register (U2RB) DMA0 request cause select register (DM0SL) 03B916 03BA16 DMA1 request cause select register (DM1SL) 03BB16 03BC16 03BD16 03BE16 CRC data register (CRCD) CRC input register (CRCIN) 03BF16 Figure 1.7.2. Location of peripheral unit control registers (2) 20 Mitsubishi microcomputers M16C / 62T Group SFR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 A-D register 0 (AD0) A-D register 1 (AD1) A-D register 2 (AD2) A-D register 3 (AD3) A-D register 4 (AD4) A-D register 5 (AD5) A-D register 6 (AD6) A-D register 7 (AD7) 03D016 03D116 03D216 03D316 03D416 A-D control register 2 (ADCON2) 03D516 03D616 03D716 03D816 A-D control register 0 (ADCON0) A-D control register 1 (ADCON1) D-A register 0 (DA0) 03D916 03DA16 D-A register 1 (DA1) 03DB16 03DC16 D-A control register (DACON) 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 Port P0 (P0) Port P1 (P1) Port P0 direction register (PD0) Port P1 direction register (PD1) Port P2 (P2) Port P3 (P3) Port P2 direction register (PD2) Port P3 direction register (PD3) Port P4 (P4) Port P5 (P5) Port P4 direction register (PD4) Port P5 direction register (PD5) Port P6 (P6) Port P7 (P7) Port P6 direction register (PD6) Port P7 direction register (PD7) Port P8 (P8) Port P9 (P9) Port P8 direction register (PD8) Port P9 direction register (PD9) Port P10 (P10) 03F516 03F616 Port P10 direction register (PD10) 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Pull-up control register 2 (PUR2) Port control register (PCR) Figure 1.7.3. Location of peripheral unit control registers (3) 21 Mitsubishi microcomputers M16C / 62T Group Memory Space Expansion Functions SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Space Expansion Features Here follows the description of the memory space expansion function. With the processor running in memory expansion mode or in microprocessor mode, the memory space expansion features provide the means of expanding the accessible space. The memory space expansion features run in one of the three modes given below. (1) Normal mode (no expansion) (2) Memory space expansion mode 1 (to be referred as expansion mode 1) (3) Memory space expansion mode 2 (to be referred as expansion mode 2) Use bits 5 and 4 (PM15, PM14) of processor mode register 1 to select a desired mode. The external memory area the chip select signal indicates is different in each mode so that the accessible memory space varies. Table 1.8.1 shows how to set individual modes and corresponding accessible memory spaces. For external memory area the chip select signal indicates, see Table 1.12.1 on page 33. But M30623 (80-pin package) is not provided with the output pin for the chip select signal. And, the M16C/62T group is not guaranteed to operate in memory expansion and microprocessor modes. Table 1.8.1. The way of setting memory space expansion modes and corresponding memory spaces Expansion mode How to set PM15 and PM14 Accessible memory space Normal mode (no expansion) 0, 0 Up to 1M byte Expansion mode 1 1, 0 Up to 1.2M bytes Expansion mode 2 1, 1 Up to 4M bytes Here follows the description of individual modes. (1) Normal mode (a mode with memory not expanded) `Normal mode' means a mode in which memory is not expanded. Figure 1.8.1 shows the memory maps and the chip select areas in normal mode. Normal mode (memory area = 1M bytes for PM15 = 0, PM14 = 0) Memory expansion mode 0000016 SFR area 0040016 AAAAA AAAAA AAAAA AAAAA AAAAA Internal RAM area XXXXX16 Internal area reserved 0400016 0800016 2800016 3000016 External area D000016 Internal area reserved YYYYY16 Internal ROM area FFFFF16 Microprocessor mode SFR area AAAA AAAA AAAA AAAA AAAA AAAA AAAA Internal RAMarea Type No. M30623M4T-XXXGP M30622M8T/M8V-XXXFP M30623M8T/M8V-XXXGP M30622MCT/MCV-XXXFP M30623MCT/MCV-XXXGP XXXXX16 YYYYY16 00FFF16 F800016 013FF16 F000016 017FF16 E000016 Internal area reserved External area CS3 (16K bytes) CS2 (128K bytes) CS1 (32K bytes) CS0 Memory expansion mode: 640K bytes Microprocessor mode: 832K bytes Note 1. M30623(80-pin package) is not provided with the output pins for chip select signals. Note 2. The M16C/62T group is not guaranteed to operatein memory expansion and microprocessor modes. Note 3. The memory maps in single-chip mode are omitted. Figure 1.8.1. The memory maps and the chip select areas in normal mode 22 Mitsubishi microcomputers M16C / 62T Group Memory Space Expansion Functions SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (2) Expansion mode 1 In this mode, the memory space can be expanded by 176K bytes in addition to that in normal mode. Figure 1.8.2 shows the memory location and chip select area in expansion mode 1. _______ _______ _______ In accessing data in expansion mode 1, CS3, CS2, and CS1 go active in the area from 0400016 through _______ 2FFFF16; in fetching a program, CS0 goes active. That is, the address space is expanded by using the ________ _______ _______ area from 04000 16 through 2FFFF16 (176K bytes) appropriately for accessing data (CS3, CS2, CS1) _______ and fetching a program (CS0). Expansion mode 1 (memory space = 1.2M bytes for PM15 = 1, PM14 = 0) Memory expansion mode 0000016 0040016 SFR area SFR area Internal RAM area Internal RAM area Internal area reserved Internal area reserved AAAA AAAA AAAA AAAA AAAA XXXXX16 Microprocessor mode 0400016 CS3 (16K bytes) CS2 (128 Kbytes) 0400016 to 2FFFF16 CS1 (32K bytes) CS0:active in fetching a program CS1, CS2, CS3:active in accessing data 0800016 2800016 176K bytes = the extent of memory expanded 3000016 External area D000016 YYYYY16 FFFFF16 External area Internal area reserved Internal ROM area Type No. M30623M4T-XXXGP M30622M8T/M8V-XXXFP M30623M8T/M8V-XXXGP M30622MCT/MCV-XXXFP M30623MCT/MCV-XXXGP XXXXX16 YYYYY16 00FFF16 F800016 013FF16 F000016 017FF16 E000016 CS0 Memory expansion mode: 816K bytes Microprocessor mode: 1008K bytes 3000016 to FFFFF16 CS0:active both in fetching a program and in accessing data Note 1. M30623(80-pin package) is not provided with the output pin for the chip select signal. Note 2. The M16C/62T group is not guaranteed to operate in memory expansion and microprocessor modes. Note 3. The memory maps in single-chip mode are omitted. Figure 1.8.2. Memory location and chip select area in expansion mode 1 23 Mitsubishi microcomputers M16C / 62T Group Memory Space Expansion Functions SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A connection example Figure 1.8.3 shows a connection example of the MCU with the external memories in expansion mode 1. _______ _______ In this example, CS0 is connected with a 1-M byte flash ROM and CS2 is connected with a 128-K byte SRAM. An example of connecting the MCU with external memories in expa nsion mode 1 (An example of using M30622MC in microprocessor mode) 8 D0 to D7 AD0 to AD16 AD17 AD18 AD19 A18 A19 1M byte flash ROM M30622MC A17 CS1 CS2 CS3 RD OE CS0 CS WR DQ0 to D Q7 AD0 to AD16 OE S2 S1 W 0000016 0040016 017FF16 128K bytes SRAM A0 to A16 DQ0 to D Q7 17 SFR area Internal RAM area Fl ash ROM (1M byte) Internal area reserved SRAM (128K bytes) 0400016 0800016 Usable for data only 2800016 Usable for programs only CS2 (128K bytes) 3000016 CS0 External area D000016 (1008K bytes) Usable both for programs and for data FFFFF16 Note 1. M30623(80-pin package) is not provided with the ou tput pin for the chip select signal. Note 2. The M16C/62T group is not guaranteed to operate in memory expansion and microprocessor modes. Figure 1.8.3. External memory connect example in expansion mode 1 24 Mitsubishi microcomputers M16C / 62T Group Memory Space Expansion Functions SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (3) Expansion mode 2 In expansion mode 2, the data bank register (0000B 16) goes effective. Figure 1.8.4 shows the data bank register. Data bank register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DBR Address 000B16 Bit symbol When reset 0016 Bit name Description R W Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". 0: Not offset 1: Offset OFS Offset bit BSR Bank selection bits b5 b4 b3 b5 b4 b3 0 0 0: Bank 0 0 1 0: Bank 2 1 0 0: Bank 4 1 1 0: Bank 6 0 0 1: Bank 1 0 1 1: Bank 3 1 0 1: Bank 5 1 1 1: Bank 7 Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". Figure 1.8.4. Data bank register Expansion mode 2 (memory space = 4M bytes for PM15 = 1, PM14 = 1) Memory expansion mode 0000016 0040016 XXXXX16 0400016 0800016 SFR area Microprocessor mode SFR area AAAA AAAAA AAAA AAAAA AAAAAAAAA AAAA AAAAA AAAA AAAAA AAAAAAAAA AAAAA AAAAA Internal RAM area Internal RAM area Internal area reserved Internal area reserved CS3 (16K bytes) CS2 (128K bytes) 2800016 4000016 CS1 (96K bytes) External area D000016 YYYYY16 External area Internal area reserved Internal ROM area FFFFF16 Type No. XXXXX16 YYYYY16 M30623M4T-XXXGP 00FFF16 F800016 M30622M8T/M8V-XXXFP 013FF16 F000016 M30623M8T/M8V-XXXGP M30622MCT/MCV-XXXFP 017FF16 E000016 M30623MCT/MCV-XXXGP CS0 Memory expansion mode: 512K bytes x 7banks + 256K bytes Microprocessor mode: 512K bytes x 8banks Addresses from 4000016 through BFFFF16 Bank 7 in fetching a program A bank selected by use of the bank selection bits in accessing data Addresses from C000016 through FFFFF16 Bank 7 invariably Bank number is output to CS3 to CS1 Note 1. M30623(80-pin package) is not provided with the output pin for the chip select signal. Note 2. The M16C/62T group is not guaranteed to operate in memory expansion and microprocessor modes. Note 3. The memory maps in single-chip mode are omitted. Figure 1.8.5. Memory location and chip select area in expansion mode 2 25 Mitsubishi microcomputers M16C / 62T Group Memory Space Expansion Functions SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The data bank register is made up of the bank selection bits (bits 5 through 3) and the offset bit (bit 2). The bank selection bits are used to set a bank number for accessing data lying between 4000016 and BFFFF 16. Assigning 1 to the offset bit provides the means to set offsets covering 4000016. Figure 1.8.5 shows the memory location and chip select areas in expansion mode 2. _______ The area relevant to CS0 ranges from 4000016 through FFFFF16. As for the area from 4000016 through _______ BFFFF16, the bank number set by use of the bank selection bits are output from the output terminals CS3 _______ _______ _______ - CS1 only in accessing data. In fetching a program, bank 7 (1112) is output from CS3 - CS1. As for the _______ _______ area from C0000 16 through FFFFF16, bank 7 (1112) is output from CS3 - CS1 without regard to accessing data or to fetching a program. _______ _______ _______ In accessing an area irrelevant to CS0, a chip select signal CS3 (4000 16 - 7FFF16), CS2 (800016 _______ 27FFF16), and CS1 (2800016 - 3FFFF16) is output depending on the address as in the past. Figure 1.8.6 shows an example of connecting the MCU with a 4-M byte ROM and to a 128-K byte SRAM. _______ _______ _______ _______ Connect the chip select of 4-M byte ROM with CS0. Connect M16C's CS3, CS2, and CS1 with address inputs AD21, AD20, and A19 respectively. Connect M16C's output AD19 with address input AD18. Figure 1.8.7 shows the relationship between addresses of the 4-M byte ROM and those of M16C. 26 An example of connecting the MCU with external memories in expansion mode 2 (M30622MC, Microprocessor mode) 8 DQ0 to DQ7 AD0 to AD16 A17 AD17 A19 AD18 CS1 AD19 CS2 AD20 AD21 OE CS3 RD CS0 WR 4-M byte ROM A0 to A16 17 CS DQ0 to DQ7 AD0 to AD16 OE S2 S1 W 128-K byte SRAM D0 to D7 M30622MCT-XXXFP In this mode, memory is banked every 512 K bytes, so that data access in different banks requires switching over banks. However, data on bank boundaries when offset bit = 0 can be accessed successively by setting the offset bit to 1, because in which case the memory address is offset by 40000 16. For example, two bytes of data located at addresses 0FFFFF 16 and 100000 16 of 4Mbyte ROM can be accessed successively without having to change the bank bit by setting the offset bit to 1 and then accessing addresses 07FFFF 16 and 80000016. On the other hand, the SRAM's _______ chip select assumes that CS0=1 _______ (not selected) and CS2=0 (se_______ lected), so connect CS0 with S2 _______ ____ and CS2 with S1. If the SRAM doesn't have a bipolar chip select _______ input terminal, decode CS0 and _______ CS2 externally. Note 1. If only one chip select terminal (S1 or S2) is present, decoding by use of an external circuit is required. Note 2. M30623(80-pin package) is not provided with the output pin for the chip select signal. Note 3. The M16C/62T group is not guaranteed to operate in memory expansion and microprocessor modes. Figure 1.8.6. An example of connecting the MCU with external memories in expansion mode 2 Mitsubishi microcomputers M16C / 62T Group Memory Space Expansion Functions SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Address area map of 4-M byte ROM AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA ROM address M16C address Offset bit = 0 000000 Offset bit = 1 40000 Bank 0 040000 080000 40000 BFFFF 40000 Bank 0 BFFFF 40000 Bank 1 0C0000 100000 BFFFF 40000 Bank 1 Data area 180000 Areas used for data only 00000016 to 38000016 BFFFF 40000 Bank 2 140000 BFFFF 40000 Bank 2 BFFFF 40000 Bank 3 1C0000 200000 BFFFF 40000 Bank 3 BFFFF Bank 4 240000 280000 40000 BFFFF 40000 Bank 4 BFFFF 40000 Bank 5 2C0000 300000 BFFFF 40000 Bank 5 Data area Area commonly used for data and programs 38000016 to 3BFFFF16 380000 Area commonly used for data and programs 3C000016 to 3FFFFF16 3C0000 BFFFF 40000 Bank 6 340000 Program/ data area Bank 7 BFFFF 40000 Bank 6 7FFFF C0000 BFFFF Program/ data area 3FFFFF FFFFF Figure 1.8.7. Relationship between addresses on 4-M byte ROM and those on M16C 27 Mitsubishi microcomputers M16C / 62T Group Software Reset SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Software Reset Writing "1" to bit 3 of the processor mode register 0 (address 0004 16) applies a (software) reset to the microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal RAM are preserved. Processor Mode (1) Types of Processor Mode One of three processor modes can be selected: single-chip mode, memory expansion mode, and microprocessor mode. The functions of some pins, the memory map, and the access space differ according to the selected processor mode. But M16C/62T group is not guaranteed to operate in memory expansion and microprocessor modes. * Single-chip mode In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be accessed. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal peripheral functions. * Memory expansion mode In memory expansion mode, external memory can be accessed in addition to the internal memory space (SFR, internal RAM, and internal ROM). In this mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus and register settings. (See "Bus Settings" for details.) * Microprocessor mode In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The internal ROM area cannot be accessed. In this mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus and register settings. (See "Bus Settings" for details.) (2) Setting Processor Modes The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address 000416). Do not set the processor mode bits to "102". Regardless of the level of the CNV SS pin, changing the processor mode bits selects the mode. Therefore, never change the processor mode bits when changing the contents of other bits. Also do not attempt to shift to or from the microprocessor mode within the program stored in the internal ROM area. * Applying VSS to CNVSS pin The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode is selected by writing "012" to the processor mode is selected bits. * Applying VCC to CNVSS pin The microcomputer starts to operate in microprocessor mode after being reset. Figure 1.9.1 shows the processor mode register 0 and 1. Figure 1.10.1 shows the memory maps applicable for each of the modes when memory area dose not be expanded (normal mode). 28 Mitsubishi microcomputers M16C / 62T Group Processor Mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Processor mode register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PM0 Address 000416 Bit symbol When reset 0016 (Note 2) Bit name Function Processor mode bit b1 b0 PM02 R/W mode select bit 0 : RD,BHE,WR 1 : RD,WRH,WRL PM03 Software reset bit The device is reset when this bit is set to "1". The value of this bit is "0" when read. PM04 Multiplexed bus space select bit b5 b4 PM06 Port P40 to P43 function select bit (Note 3) 0 : Address output 1 : Port function (Address is not output) PM07 BCLK output disable bit 0 : BCLK is output 1 : BCLK is not output (Pin is left floating) PM00 PM01 PM05 0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Inhibited 1 1: Microprocessor mode 0 0 : Multiplexed bus is not used 0 1 : Allocated to CS2 space 1 0 : Allocated to CS1 space 1 1 : Allocated to entire space (Note4) A A A A A A A A A R W Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register. Note 2: If the VCC voltage is applied to the CNVSS, the value of this register when reset is 0316. (PM00 and PM01 both are set to "1".) Note 3: Valid in microprocessor and memory expansion modes. Note 4: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width. The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. Note 5: The M16C/62T group is not guaranteed to operate in memory expansion and microprocessor modes. Processor mode register 1 (Note 1) b7 b6 0 b5 b4 b3 0 b2 b1 b0 0 Symbol PM1 Address 000516 Bit symbol When reset 00000XX02 Bit name Function Must always be set to "0" Reserved bit Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. Reserved bit PM14 Must always be set to "0" Memory area expansion bit (Note 2) b5 b4 PM15 0 0 : Normal mode (Do not expand) 0 1 : Inhibited 1 0 : Memory area expansion mode 1 1 1 : Memory area expansion mode 2 Reserved bit Must always be set to "0" PM17 Wait bit 0 : No wait state 1 : Wait state inserted AA AA A AA A AA A AA AA A AA R W Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register. Note 2: With the processor running in memory expansion mode or in microprocessor mode, setting this bit provides the means of expanding the external memory area. (Normal mode: up to 1M byte, expansion mode 1: up to 1.2 M bytes, expansion mode 2: up to 4M bytes) For details, see "Memory space expansion functions". Note 3: The M16C/62T group is not guaranteed to operate in memory expansion and microprocessor modes. Figure 1.9.1. Processor mode register 0 and 1 29 Mitsubishi microcomputers M16C / 62T Group Processor Mode Single-chip mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory expansion mode Microprocessor mode 0000016 SFR area SFR area SFR area Internal RAM area Internal RAM area Internal RAM area Internally reserved area Internally reserved area External area External area 0040016 XXXXX16 0400016 Inhibited D000016 Internally reserved area YYYYY16 Internal ROM area Internal ROM area FFFFF16 Type No. XXXXX16 YYYYY16 M30623M4T-XXXGP 00FFF16 F800016 M30622M8T/M8V-XXXFP 013FF16 F000016 M30623M8T/M8V-XXXGP M30622MCT/MCV-XXXFP 017FF16 E000016 M30623MCT/MCV-XXXGP External area : Accessing this area allows the user to access a device connected externally to the microcomputer. Note: The M16C/62T group is not guaranteed to operate in memory expansion and microprocessor modes. Figure 1.10.1. Memory maps in each processor mode (without memeory area expansion, normal mode) 30 Mitsubishi microcomputers M16C / 62T Group Bus Settings SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Bus Settings The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 000416) are used to change the bus settings. In M30623(80-pin package), the BYTE signal has no external pin, and is internally connected to the CNVSS signal. Accordingly, the external data bus width can be used only 8 bits. M16C/62T group is not guaranteed to operate in memory expansion and microprocessor modes. Table 1.11.1 shows the factors used to change the bus settings. Table 1.11.1. Factors for switching bus settings Bus setting Switching factor Bit 6 of processor mode register 0 Switching external address bus width Switching external data bus width BYTE pin Switching between separate and multiplex bus Bits 4 and 5 of processor mode register 0 Note 1: In M30623(80-pin package), the external data bus width cannot be switched (be fixed 8 bits). (1) Selecting external address bus width The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K bytes address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register 0 is set to "1", the external address bus width is set to 16 bits, and P2 and P3 become part of the address bus. P40 to P43 can be used as programmable I/O ports. When bit 6 of processor mode register 0 is set to "0", the external address bus width is set to 20 bits, and P2, P3, and P40 to P43 become part of the address bus. (2) Selecting external data bus width The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can be set.) When the BYTE pin is "L", the bus width is set to 16 bits; when "H", it is set to 8 bits. (The internal bus width is permanently set to 16 bits.) While operating, fix the BYTE pin either to "H" or to "L". (3) Selecting separate/multiplex bus The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0. * Separate bus In this mode, the data and address are input and output separately. The data bus can be set using the BYTE pin to be 8 or 16 bits. When the BYTE pin is "H", the data bus is set to 8 bits and P0 functions as the data bus and P1 as a programmable I/O port. When the BYTE pin is "L", the data bus is set to 16 bits and P0 and P1 are both used for the data bus. When the separate bus is used for access, a software wait can be selected. * Multiplex bus In this mode, data and address I/O are time multiplexed. With an 8-bit data bus selected (BYTE pin = "H"), the 8 bits from D 0 to D7 are multiplexed with A0 to A 7. With a 16-bit data bus selected (BYTE pin = "L"), the 8 bits from D0 to D7 are multiplexed with A1 to A8. D8 to D15 are not multiplexed. In this case, the external devices connected to the multiplexed bus are mapped to the microcomputer's even addresses (every 2nd address). To access these external devices, access the even addresses as bytes. The ALE signal latches the address. It is output from P56. Before using the multiplex bus for access, be sure to insert a software wait. If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width. The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. 31 Mitsubishi microcomputers M16C / 62T Group Bus Settings SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.11.2. Pin functions for each processor mode Processor mode Single-chip mode Multiplexed bus space select bit Data bus width BYTE pin level Memory expansion mode (Note 1) Memory expansion / microprocessor modes "01", "10" "00" "11" (Note 2) Either CS1 or CS2 is for multiplexed bus and others are for separate bus (separate bus) multiplexed bus for the entire space 8 bits "H" 16 bits "L" 8 bits "H" 16 bits "L" 8 bits "H" P00 to P07 I/O port Data bus Data bus Data bus Data bus I/O port P10 to P17 I/O port I/O port Data bus I/O port Data bus I/O port P20 I/O port Address bus/ data bus (Note 3) Address bus Address bus Address bus Address bus /data bus P21 to P27 I/O port Address bus/ Address bus/ data bus (Note 3) data bus (Note 3) Address bus Address bus Address bus /data bus P30 I/O port Address bus Address bus/ data bus (Note 3) Address bus Address bus A8/D7 P31 to P37 I/O port Address bus Address bus Address bus Address bus I/O port I/O port I/O port I/O port I/O port I/O port I/O port Port P40 to P43 function select bit = 0 I/O port Address bus Address bus Address bus Address bus I/O port P44 to P47 I/O port CS (chip select) or programmable I/O port (For details, refer to "Bus control".) P50 to P53 I/O port Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK (For details, refer to "Bus control".) P54 I/O port HLDA HLDA HLDA HLDA HLDA P55 I/O port HOLD HOLD HOLD HOLD HOLD P56 I/O port ALE ALE ALE ALE ALE P57 I/O port RDY RDY RDY RDY RDY P40 to P43 Port P40 to P43 function select bit = 1 P40 to P43 Note 1: In M30623(80-pin package), set the data bus width to 8 bits by any of the following operations, to transfer the microcomputer to memory expansion mode correctly. * At reset, input "H" to the CNVSS (BYTE) pin to start the program in microprocessor mode. Then, set the processor mode bit to memory expansion mode. * At reset, input "L" to the CNVSS (BYTE) pin to start the program in single-chip mode, and input "H" to this pin. Then, set the processor mode bit to memory expansion mode. Note 2: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width. The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. Note 3: Address bus when in separate bus mode. Note 4: In M30623(80-pin package), P1, P44 to P47 have no corresponding external pin. Note 5: M16C/62T group is not guaranteed to operate in memory expansion and microprocessor modes. 32 Mitsubishi microcomputers M16C / 62T Group Bus Control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Bus Control The following explains the signals required for accessing external devices and software waits. The signals required for accessing the external devices are valid when the processor mode is set to memory expansion mode and microprocessor mode. The software waits are valid in all processor modes. M30623(80-pin package), in which the BYTE pin is connected to the CNVSS pin, and the external data bus width can be used 8 bits. M16C/62T group is not guaranteed to operate in memory expansion and microprocessor modes. (1) Address bus/data bus The address bus consists of the 20 pins A 0 to A19 for accessing the 1M bytes of address space. The data bus consists of the pins for data I/O. When the BYTE pin is "H", the 8 ports D0 to D7 function as the data bus. When BYTE is "L", the 16 ports D0 to D15 function as the data bus. When a change is made from single-chip mode to memory expansion mode, the value of the address bus is undefined until external memory is accessed. (2) Chip select signalIn (In M30623(80-pin package), the chip select signals have no corresponding external pin.) The chip select signal is output using the same pins as P4 4 to P47. Bits 0 to 3 of the chip select control register (address 000816) set each pin to function as a port or to output the chip select signal. The chip select control register is valid in memory expansion mode and microprocessor mode. In single-chip mode, P44 to P47 function as programmable I/O ports regardless of the value in the chip select control register. _______ In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been can_______ _______ celled. CS1 to CS3 function as input ports. Figure 1.12.1 shows the chip select control register. The chip select signal can be used to split the external area into as many as four blocks. Tables 1.12.1 and 1.12.2 show the external memory areas specified using the chip select signal. Table 1.12.1. External areas specified by the chip select signals Memory space expansion mode Specified address range Normal mode (PM15,14=0,0) Expansion mode 1 (PM15,14=1,0) Expansion mode 2 (PM15,14=1,1) Chip select signal Processor mode Memory expansion mode CS0 3000016 to CFFFF16 (640K bytes) Microprocessor mode 3000016 to FFFFF16 (832K bytes) Memory expansion mode 0400016 to CFFFF16 (816K bytes) Microprocessor mode 0400016 to FFFFF16 (1008K bytes) 4000016 to BFFFF16 Memory expansion (512K bytes 7 mode + 256K bytes) Microprocessor mode 4000016 to FFFFF16 (512K bytes 8) CS1 CS2 CS3 0800016 to 27FFF16 (128K bytes) 0400016 to 07FFF16 (16K bytes) 2800016 to 2FFFF16 (32K bytes) 2800016 to 3FFFF16 (96K bytes) Note 1: In M30623(80-pin package), the chip select signals have no corresponding external pin. Note 2: The M16C/62T Group is not guaranteed to operate in memory expansion and microprocessor modes. 33 Mitsubishi microcomputers M16C / 62T Group Bus Control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Chip select control register b7 b6 b5 b4 b3 b2 b1 Symbol CSR b0 Address 000816 When reset 0116 Bit name Bit symbol CS0 CS0 output enable bit CS1 CS1 output enable bit CS2 CS2 output enable bit CS3 CS3 output enable bit CS0W CS0 wait bit CS1W CS1 wait bit CS2W CS2 wait bit CS3W CS3 wait bit Function 0 : Chip select output disabled (Normal port pin) 1 : Chip select output enabled 0 : Wait state inserted 1 : No wait state AA AA AA AA AA AA RW Note: In M30623(80-pin package), the chip select signals has no corresponding external pin. So, this register is invalid. Figure 1.12.1. Chip select control register (3) Read/write signals With a 16-bit data bus (BYTE pin ="L"), bit 2 of the processor mode register 0 (address 0004 16) select the _____ ________ ______ _____ ________ _________ combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE _____ ______ _______ pin = "H"), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0 (address 000416) to "0".) Tables 1.12.2 and 1.12.3 show the operation of these signals. _____ ______ ________ After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected. _____ _________ _________ When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the processor mode register 0 (address 000416) has been set (Note 1). Note 1: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000A16) to "1". _____ ________ _________ Table 1.12.2. Operation of RD, WRL, and WRH signals Status of external data bus Data bus width RD WRL WRH Read data L H H Write 1 byte of data to even address H L H 16-bit (BYTE = "L") Write 1 byte of data to odd address L H H Write data to both even and odd addresses H L L _____ ______ ________ Table 1.12.3. Operation of RD, WR, and BHE signals Data bus width 16-bit (BYTE = "L") 8-bit (BYTE = "H") RD H L H L H L H L WR L H L H L H L H BHE L L H H L L Not used Not used A0 H H L L L L H/L H/L Status of external data bus Write 1 byte of data to odd address Read 1 byte of data from odd address Write 1 byte of data to even address Read 1 byte of data from even address Write data to both even and odd addresses Read data from both even and odd addresses Write 1 byte of data Read 1 byte of data Note 1: M30623(80-pin package) can operate only when BYTE = ``H''. 34 Mitsubishi microcomputers M16C / 62T Group Bus Control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (4) ALE signal The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the ALE signal falls. When BYTE pin = "L" When BYTE pin = "H" ALE ALE Address D0/A0 to D7/A7 A0 Data (Note 1) D0/A1 to D7/A8 A8 to A19 Address Address Data (Note 1) Address (Note 2) A9 to A19 Address Note 1: Floating when reading. Note 2: When multiplexed bus for the entire space is selected, these are I/O ports. Note 3: In M30623 (80-pin package), P10 to P17 which are in common with D8 to D15 are available. So, M30623 (80-pin package) can operate only when BYTE pin = "H" (the width of external data bus is 16-bit). Figure 1.12.2. ALE signal and address/data bus ________ (5) The RDY signal ________ RDY is a signal that facilitates access to an external device that requires long access time. As shown in ________ Figure 1.12.3, if an "L" is being input to the RDY at the BCLK falling edge, the bus turns to the wait state. If ________ an "H" is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table 1.12.4 shows the state of the microcomputer with the bus in the wait state, and Figure 1.12.3 shows an example in ____ ________ which the RD signal is prolonged by the RDY signal. ________ The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the ________ chip select control register (address 000816) are set to "0". The RDY signal is invalid when setting "1" to all ________ bits 4 to 7 of the chip select control register (address 000816), but the RDY pin should be treated as properly as in non-using. Table 1.12.4. Microcomputer status in ready state (Note 1) Item Oscillation On ___ _____ R/W signal, address bus, data bus, CS __________ ALE signal, HLDA, programmable I/O ports Internal peripheral circuits Status ________ Maintain status when RDY signal received On ________ Note 1: The RDY signal cannot be received immediately prior to a software wait. _____ Note 2: In M30623(80-pin package), CS signals have no corresponding external pin. 35 Mitsubishi microcomputers M16C / 62T Group Bus Control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In an instance of separate bus BCLK AAA RD CSi (i=0 to 3) (Note) RDY tsu(RDY - BCLK) Accept timing of RDY signal In an instance of multiplexed bus BCLK AAAAAA RD CSi (i=0 to 3) (Note) RDY tsu(RDY - BCLK) AA AA : Wait using RDY signal Accept timing of RDY signal : Wait using software Note: In M30623(80-pin package), the CSi signal (i = 0 to 3) has no corresponding exte _____ ________ Figure 1.12.3. Example of RD signal extended by RDY signal (6) Hold signal The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting "L" to __________ the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status __________ __________ is maintained and "L" is output from the HLDA pin as long as "L" is input to the HOLD pin. Table 1.12.5 shows the microcomputer status in the hold state. __________ Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence. __________ HOLD > DMAC > CPU Figure 1.12.4. Bus-using priorities Table 1.12.5. Microcomputer status in hold state Item Oscillation ___ _____ Status ON _______ R/W signal, address bus, data bus, CS, BHE Programmable I/O ports P0, P1, P2, P3, P4, P5 P6, P7, P8, P9, P10 Floating Floating Maintains status when hold signal is received __________ HLDA Output "L" Internal peripheral circuits ON (but watchdog timer stops) ALE signal Undefined ______ ______ Note 1: In M30623(80-pin package), P1, P44 to P47(CS0 to CS3) and P72 to P75, P91 have no corresponding external pin, but are internally the above conditions. 36 Mitsubishi microcomputers M16C / 62T Group Bus Control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (7) External bus status when the internal area is accessed Table 1.12.6 shows the external bus status when the internal area is accessed. Table 1.12.6. External bus status when the internal area is accessed Item SFR accessed Internal ROM/RAM accessed Address bus Address output Maintain status before accessed address of external area Data bus When read Floating Floating When write Output data Undefined RD, WR, WRL, WRH RD, WR, WRL, WRH output Output "H" BHE BHE output Maintain status before accessed status of external area CS Output "H" Output "H" ALE Output "L" Output "L" _____ Note 1: In M30623(80-pin package), CS signals have no corresponding external pin. (8) BCLK output The user can choose the BCLK output by use of bit 7 of processor mode register 0 (000416) (Note). When set to "1", the output floating. Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000A16) to "1". 37 Mitsubishi microcomputers M16C / 62T Group Bus Control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (9) Software wait A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 000516) (Note) and bits 4 to 7 of the chip select control register (address 0008 16). A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the wait bit of the processor mode register 1. When set to "0", each bus cycle is executed in one BCLK cycle. When set to "1", each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been reset, this bit defaults to "0". When set to "1", a wait is applied to all memory areas (two or three BCLK cycles), regardless of the contents of bits 4 to 7 of the chip select control register. Set this bit after referring to the recommended operating conditions (main clock input oscillation frequency) of the electric characteristics. However, when the user is using the RDY signal, the relevant bit in the chip select control register's bits 4 to 7 must be set to "0". When the wait bit of the processor mode register 1 is "0", software waits can be set independently for each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register _______ _______ correspond to chip selects CS0 to CS3. When one of these bits is set to "1", the bus cycle is executed in one BCLK cycle. When set to "0", the bus cycle is executed in two or three BCLK cycles. These bits default to "0" after the microcomputer has been reset. The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also, insert a software wait if using the multiplex bus to access the external memory area. Table 1.12.7 shows the software wait and bus cycles. Figure 1.12.5 shows example bus timing when using software waits. Note 1: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000A 16) to "1". Note 2: In M30623(80-pin package), the chip select signals have no corresponding external pin. Table 1.12.7. Software waits and bus cycles Area Wait bit Bits 4 to 7 of chip select control register Invalid Invalid 2 BCLK cycles 0 Invalid 1 BCLK cycle 1 Invalid 2 BCLK cycles Separate bus 0 1 1 BCLK cycle Separate bus 0 0 2 BCLK cycles Separate bus 1 0 (Note) 2 BCLK cycles Multiplex bus 0 0 3 BCLK cycles Multiplex bus 1 0 (Note) 3 BCLK cycles Bus status SFR Internal ROM/RAM External memory area Note: When using the RDY signal, always set to "0". 38 Bus cycle Mitsubishi microcomputers M16C / 62T Group Bus Control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER < Separate bus (no wait) > Bus cycle BCLK Write signal Read signal Output Data bus Address bus Address Input Address Chip select < Separate bus (with wait) > Bus cycle BCLK Write signal Read signal Input Output Data bus Address bus Address Address Chip select < Multiplexed bus > Bus cycle BCLK Write signal Read signal ALE Address bus Address bus/ Data bus Address Address Address Data output Address Input Chip select Note 1: In M30623(80-pin package), the chip select signals have no corresponding external pin. Figure 1.12.5. Typical bus timings using software wait 39 Mitsubishi microcomputers M16C / 62T Group Clock Generating Circuit SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Generating Circuit The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units. Table 1.13.1. Main clock and sub clock generating circuits Main clock generating circuit Sub clock generating circuit Use of clock * CPU's operating clock source * CPU's operating clock source * Internal peripheral units' * Timer A/B's count clock operating clock source source Usable oscillator Ceramic or crystal oscillator Crystal oscillator Pins to connect oscillator X IN, XOUT XCIN, XCOUT Oscillation stop/restart function Available Available Oscillator status immediately after reset Oscillating Stopped Other Externally derived clock can be input Example of oscillator circuit Figure 1.13.1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Figure 1.13.2 shows some examples of sub clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Circuit constants in Figures 1.13.1 and 1.13.2 vary with each oscillator used. Use the values recommended by the manufacturer of your oscillator. Microcomputer Microcomputer (Built-in feedback resistor) (Built-in feedback resistor) XIN XIN XOUT XOUT Open (Note) Rd Externally derived clock CIN COUT Vcc Vss Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN and XOUT following the instruction. Figure 1.13.1. Examples of main clock Microcomputer Microcomputer (Built-in feedback resistor) (Built-in feedback resistor) XCIN XCOUT XCIN XCOUT Open (Note) RCd Externally derived clock CCIN CCOUT Vcc Vss Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN and XCOUT following the instruction. Figure 1.13.2. Examples of sub clock 40 Mitsubishi microcomputers M16C / 62T Group Clock Generating Circuit SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Control Figure 1.13.3 shows the block diagram of the clock generating circuit. XCIN XCOUT fC32 1/32 f1 CM04 f1SIO2 fAD fC f8SIO2 f8 Sub clock f32SIO2 CM10 "1" Write signal f32 S Q XIN XOUT a RESET Software reset Main clock CM02 CM05 NMI Interrupt request level judgment output AAA AAA b R c Divider d CM07=0 BCLK fC CM07=1 S Q WAIT instruction R c b a 1/2 1/2 1/2 1/2 1/2 CM06=0 CM17,CM16=11 CM06=1 CM06=0 CM17,CM16=10 d CM06=0 CM17,CM16=01 CM06=0 CM17,CM16=00 CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 WDCi : Bit i at address 000F16 Details of divider Figure 1.13.3. Clock generating circuit 41 Mitsubishi microcomputers M16C / 62T Group Clock Generating Circuit SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The following paragraphs describes the clocks generated by the clock generating circuit. (1) Main clock The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (2) Sub-clock The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset. After oscillation is started using the port Xc select bit (bit 4 at address 0006 16), the sub-clock can be selected as the BCLK by using the system clock select bit (bit 7 at address 0006 16). However, be sure that the sub-clock oscillation has fully stabilized before switching. After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit changes to "1" when shifting to stop mode and at a reset. (3) BCLK The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal can be output from BCLK pin by the BCLK output disable bit (bit 7 at address 0004 16) in the memory expansion and the microprocessor modes. The main clock division select bit 0(bit 6 at address 000616) changes to "1" when shifting from highspeed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (4) Peripheral function clock(f1, f8, f32, f1SIO2, f8SIO2,f32SIO2,fAD) The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 000616) to "1" and then executing a WAIT instruction. (5) fC32 This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts. (6) fC This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer. 42 Mitsubishi microcomputers M16C / 62T Group Clock Generating Circuit SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.13.4 shows the system clock control registers 0 and 1. System clock control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol CM0 Address 000616 Bit symbol When reset 4816 Bit name Function b1 b0 AA AA AA AA AA AA AA AA RW Clock output function select bit (Valid only in single-chip mode) 0 0 : I/O port P57 0 1 : fC output 1 0 : f8 output 1 1 : f32 output WAIT peripheral function clock stop bit XCIN-XCOUT drive capacity select bit (Note 2) 0 : Do not stop peripheral function clock in wait mode 1 : Stop peripheral function clock in wait mode (Note 8) 0 : LOW 1 : HIGH CM04 Port XC select bit 0 : I/O port 1 : XCIN-XCOUT generation CM05 Main clock (XIN-XOUT) stop bit (Note 3, 4, 5) 0 : On 1 : Off CM06 Main clock division select bit 0 (Note 7) 0 : CM16 and CM17 valid 1 : Division by 8 mode CM07 System clock select bit (Note 6) 0 : XIN, XOUT 1 : XCIN, XCOUT CM00 CM01 CM02 CM03 Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register. Note 2: Changes to "1" when shiffing to stop mode and at a reset. Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop mode and operating with XIN, set this bit to "0". When main clock oscillation is operating by itself, set system clock select bit (CM07) to "1" before setting this bit to "1". Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. Note 5: If this bit is set to "1", XOUT turns "H". The built-in feedback resistor remains being connected, so XIN turns pulled up to XOUT ("H") via the feedback resistor. Note 6: Set port Xc select bit (CM04) to "1" and stabilize the sub-clock oscillating before setting to this bit from "0" to "1". Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to "0" and stabilize the main clock oscillating before setting this bit from "1" to "0". Note 7: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 8: fC32 is not included. System clock control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 0 0 0 0 b0 Symbol CM1 Address 000716 Bit symbol CM10 When reset 2016 Bit name All clock stop control bit (Note4) Function 0 : Clock on 1 : All clocks off (stop mode) Reserved bit Always set to "0" Reserved bit Always set to "0" Reserved bit Always set to "0" Reserved bit Always set to "0" CM15 XIN-XOUT drive capacity select bit (Note 2) CM16 Main clock division select bit 1 (Note 3) 0 : LOW 1 : HIGH b7 b6 CM17 0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode AA AA AA AAAA AA AA AAAA RW Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register. Note 2: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is "0". If "1", division mode is fixed at 8. Note 4: If this bit is set to "1", XOUT turns "H", and the built-in feedback resistor is cut off. XCIN and XCOUT turn highimpedance state. Figure 1.13.4. Clock control registers 0 and 1 43 Mitsubishi microcomputers M16C / 62T Group Clock Generating Circuit SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Output In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32, or fc to be output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address 000616) is set to "1", the output of f8 and f32 stops when a WAIT instruction is executed. Stop Mode Writing "1" to the all-clock stop control bit (bit 0 at address 0007 16) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V. Because the oscillation , BCLK, f1 to f32, f1SIO2 to f32SIO2 , fC, fC32, and fAD stops in stop mode, peripheral functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2), SI/O3, 4 functions provided an external clock is selected. Table 1.13.2 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed. When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division select bit 0 (bit 6 at address 000616) is set to "1". When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Table 1.13.2. Port status during stop mode Memory expansion mode Pin Microprocessor mode _______ _______ Address bus, data bus, CS0 to CS3 _____ ______ ________ ________ Single-chip mode Retains status before stop mode _________ RD, WR, BHE, WRL, WRH "H" __________ HLDA, BCLK "H" ALE "H" Port CLKOUT When fc selected When f 8, f32 selected ______ Retains status before stop mode Valid only in single-chip mode Valid only in single-chip mode Retains status before stop mode "H" Retains status before stop mode ______ Note 1: In M30623(80-pin package), CS0 to CS3 have no corresponding external pin, but are internally the above conditions. 44 Mitsubishi microcomputers M16C / 62T Group Wait Mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Wait Mode When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but the BCLK and watchdog timer stop. Writing "1" to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. Table 1.13.3 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, the microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the WAIT instruction was executed. Table 1.13.3. Port status during wait mode Memory expansion mode Pin Microprocessor mode _______ _______ Address bus, data bus, CS0 to CS3 _____ Single-chip mode Retains status before wait mode ______ ________ ________ _________ RD, WR, BHE, WRL, WRH "H" __________ HLDA,BCLK ALE Port CLKOUT When f C selected When f 8, f32 selected ______ "H" "H" Retains status before wait mode Retains status before wait mode Valid only in single-chip mode Does not stop Valid only in single-chip mode Does not stop when the WAIT peripheral function clock stop bit is "0". When the WAIT peripheral function clock stop bit is "1", the status immediately prior to entering wait mode is maintained. ______ Note 1: In M30623(80-pin package), CS0 to CS3 have no corresponding external pin, but are internally the above conditions. 45 Mitsubishi microcomputers M16C / 62T Group Status Transition of BCLK SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Status Transition Of BCLK Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 1.13.4 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address 000616) changes to "1" when shifting from high-speed/medium-speed to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. The following shows the operational modes of BCLK. (1) Division by 2 mode The main clock is divided by 2 to obtain the BCLK. (2) Division by 4 mode The main clock is divided by 4 to obtain the BCLK. (3) Division by 8 mode The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption mode, make sure the sub-clock is oscillating stably. (4) Division by 16 mode The main clock is divided by 16 to obtain the BCLK. (5) No-division mode The main clock is divided by 1 to obtain the BCLK. (6) Low-speed mode fC is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the subclock starts. Therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (7) Low power dissipation mode fC is the BCLK and the main clock is stopped. Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Allow a wait time in software for the oscillation to stabilize before switching over the clock. Table 1.13.4. Operating modes dictated by settings of system clock control registers 0 and 1 CM17 CM16 CM07 CM06 CM05 CM04 Operating mode of BCLK 0 1 Invalid 1 0 Invalid Invalid 46 1 0 Invalid 1 0 Invalid Invalid 0 0 0 0 0 1 1 0 0 1 0 0 Invalid Invalid 0 0 0 0 0 0 1 Invalid Invalid Invalid Invalid Invalid 1 1 Division by 2 mode Division by 4 mode Division by 8 mode Division by 16 mode No-division mode Low-speed mode Low power dissipation mode Mitsubishi microcomputers M16C / 62T Group Power control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Power control The following is a description of the three available power control modes: Modes Power control is available in three modes. (a) Normal operation mode * High-speed mode Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal clock selected. Each peripheral function operates according to its assigned clock. * Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK. The CPU operates according to the internal clock selected. Each peripheral function operates according to its assigned clock. * Low-speed mode fC becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the secondary clock. Each peripheral function operates according to its assigned clock. * Low power consumption mode The main clock operating in low-speed mode is stopped. The CPU operates according to the fC clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate are those with the sub-clock selected as the count source. (b) Wait mode The CPU operation is stopped. The oscillators do not stop. (c) Stop mode All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three modes listed here, is the most effective in decreasing power consumption. Figure 1.13.5 is the state transition diagram of the above modes. 47 Mitsubishi microcomputers M16C / 62T Group Power control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Transition of stop mode, wait mode Reset All oscillators stopped Stop mode CM10 = "1" Interrupt All oscillators stopped Stop mode Stop mode Interrupt CPU operation stopped WAIT instruction High-speed/mediumspeed mode Wait mode Interrupt All oscillators stopped CM10 = "1" Wait mode Interrupt Interrupt CM10 = "1" CPU operation stopped WAIT instruction Medium-speed mode (divided-by-8 mode) CPU operation stopped WAIT instruction Low-speed/low power dissipation mode Wait mode Interrupt Normal mode (Refer to the following for the transition of normal mode.) Transition of normal mode Main clock is oscillating Sub clock is stopped Medium-speed mode (divided-by-8 mode) CM06 = "1" BCLK : f(XIN)/8 CM07 = "0" CM06 = "1" Main clock is oscillating CM04 = "0" Sub clock is oscillating CM07 = "0" (Note 1) CM06 = "1" CM04 = "0" CM04 = "1" (Notes 1, 3) High-speed mode Medium-speed mode (divided-by-2 mode) BCLK : f(XIN) CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "0" BCLK : f(XIN)/2 CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "1" Medium-speed mode (divided-by-8 mode) Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/8 CM07 = "0" CM06 = "1" Medium-speed mode (divided-by-4 mode) BCLK : f(XIN)/4 CM07 = "0" CM06 = "0" CM17 = "1" CM16 = "0" BCLK : f(XIN)/16 CM07 = "0" CM06 = "0" CM17 = "1" CM16 = "1" Main clock is oscillating Sub clock is oscillating Low-speed mode CM07 = "0" (Note 1, 3) BCLK : f(XCIN) CM07 = "1" CM07 = "1" (Note 2) CM05 = "0" CM04 = "0" CM06 = "0" (Notes 1,3) Main clock is oscillating Sub clock is stopped CM04 = "1" High-speed mode Medium-speed mode (divided-by-2 mode) BCLK : f(XIN) CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "0" BCLK : f(XIN)/2 CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "1" Medium-speed mode (divided-by-4 mode) Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/4 CM07 = "0" CM06 = "0" CM17 = "1" CM16 = "0" BCLK : f(XIN)/16 CM07 = "0" CM06 = "0" CM17 = "1" CM16 = "1" Main clock is stopped Sub clock is oscillating Low power dissipation mode CM07 = "1" (Note 2) CM05 = "1" BCLK : f(XCIN) CM07 = "1" CM07 = "0" (Note 1) CM06 = "0" (Note 3) CM04 = "1" Note 1: Switch clock after oscillation of main clock is sufficiently stable. Note 2: Switch clock after oscillation of sub clock is sufficiently stable. Note 3: Change CM06 after changing CM17 and CM16. Note 4: Transit in accordance with arrow. Figure 1.13.5. State transition diagram of Power control mode 48 CM05 = "1" Mitsubishi microcomputers M16C / 62T Group Protection SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.13.6 shows the protect register. The values in the processor mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716), port P9 direction register (address 03F316) , SI/O3 control register (address 036216) and SI/O4 control register (address 036616) can only be changed when the respective bit in the protect register is set to "1". Therefore, important outputs can be allocated to port P9. If, after "1" (write-enabled) has been written to the port P9 direction register and SI/Oi control register (i=3,4) write-enable bit (bit 2 at address 000A16), a value is written to any address, the bit automatically reverts to "0" (write-inhibited). However, the system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return to "0" after a value has been written to an address. The program must therefore be written to return these bits to "0". Protect register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PRCR Bit symbol Address 000A16 When reset XXXXX0002 Bit name Function PRC0 Enables writing to system clock control registers 0 and 1 (addresses 0 : Write-inhibited 1 : Write-enabled 000616 and 000716) PRC1 Enables writing to processor mode 0 : Write-inhibited registers 0 and 1 (addresses 000416 1 : Write-enabled and 000516) PRC2 Enables writing to port P9 direction register (address 03F316) and SI/Oi control register (i=3,4) (addresses 036216 and 036616) (Note) 0 : Write-inhibited 1 : Write-enabled A A A AA A AA AA R W Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. Note: Writing a value to an address after "1" is written to this bit returns the bit to "0" . Other bits do not automatically return to "0" and they must therefore be reset by the program. Figure 1.13.6. Protect register 49 Mitsubishi microcomputers M16C / 62T Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Overview of Interrupt Type of Interrupts Figure 1.14.1 lists the types of interrupts. Hardware Special Peripheral I/O (Note) Interrupt Software Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Reset NMI ________ DBC Watchdog timer Single step Address matched _______ Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system. Figure 1.14.1. Classification of interrupts * Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level. * Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level. 50 Mitsubishi microcomputers M16C / 62T Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. * Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction. * Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to "1". The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB * BRK interrupt A BRK interrupt occurs when executing the BRK instruction. * INT interrupt An INT interrupt occurs when specifying one of software interrupt numbers 0 through 63 and executing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O interrupt does. The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is involved. So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to "0" and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift. 51 Mitsubishi microcomputers M16C / 62T Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Hardware Interrupts Hardware interrupts are classified into two types -- special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts. * Reset ____________ Reset occurs if an "L" is input to the RESET pin. _______ * NMI interrupt _______ _______ An NMI interrupt occurs if an "L" is input to the NMI pin. ________ * DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. * Watchdog timer interrupt Generated by the watchdog timer. * Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to "1", a single-step interrupt occurs after one instruction is executed. * Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to "1". If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. For address match interrupt, see 2.11 Address match Interrupt. (2) Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral functions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts. * Bus collision detection interrupt This is an interrupt that the serial I/O bus collision detection generates. * DMA0 interrupt, DMA1 interrupt These are interrupts that DMA generates. * Key-input interrupt ___ A key-input interrupt occurs if an "L" is input to the KI pin. * A-D conversion interrupt This is an interrupt that the A-D converter generates. * UART0, UART1, UART2/NACK, SI/O3 and SI/O4 transmission interrupt These are interrupts that the serial I/O transmission generates. * UART0, UART1, UART2/ACK, SI/O3 and SI/O4 reception interrupt These are interrupts that the serial I/O reception generates. * Timer A0 interrupt through timer A4 interrupt These are interrupts that timer A generates * Timer B0 interrupt through timer B5 interrupt These are interrupts that timer B generates. ________ ________ * INT0 interrupt through INT5 interrupt ______ ______ An INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to the INT pin. _______ _______ Note 1: In M30623 (80-pin package), can not use INT 3 to INT5 as the interrupt factors, because _______ _______ P15/D13/INT3 to P17/D15/INT5 have no corresponding external pin. 52 Mitsubishi microcomputers M16C / 62T Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts and Interrupt Vector Tables If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure 1.14.2 shows the format for specifying the address. Two types of interrupt vector tables are available -- fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA MSB LSB Vector address + 0 Low address Vector address + 1 Mid address Vector address + 2 0000 High address Vector address + 3 0000 0000 Figure 1.14.2. Format for specifying interrupt vector addresses * Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC 16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 1.14.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. Table 1.14.1. Interrupts assigned to the fixed vector tables and addresses of vector tables Interrupt source Undefined instruction Overflow BRK instruction Vector table addresses Address (L) to address (H) FFFDC16 to FFFDF16 FFFE016 to FFFE316 FFFE416 to FFFE716 Remarks Interrupt on UND instruction Interrupt on INTO instruction If the vector contains FF16, program execution starts from the address shown by the vector in the variable vector table There is an address-matching interrupt enable bit Do not use Address match FFFE816 to FFFEB16 Single step (Note) FFFEC16 to FFFEF16 Watchdog timer FFFF016 to FFFF316 ________ DBC (Note) FFFF416 to FFFF716 Do not use _______ NMI FFFF816 to FFFFB16 External interrupt by input to NMI pin Reset FFFFC16 to FFFFF16 Note: Interrupts used for debugging purposes only. 53 Mitsubishi microcomputers M16C / 62T Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER * Variable vector tables The addresses in the variable vector table can be modified, according to the user's settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 1.14.2 shows the interrupts assigned to the variable vector tables and addresses of vector tables. Table 1.14.2. Interrupts assigned to the variable vector tables and addresses of vector tables Software interrupt number Vector table address Interrupt source Address (L) to address (H) Software interrupt number 0 +0 to +3 (Note 1) BRK instruction Software interrupt number 4 +16 to +19 (Note 1) INT3 Software interrupt number 5 +20 to +23 (Note 1) Timer B5 Software interrupt number 6 +24 to +27 (Note 1) Timer B4 Software interrupt number 7 +28 to +31 (Note 1) Timer B3 Software interrupt number 8 +32 to +35 (Note 1) SI/O4/INT5 (Note 2, Note 4) Software interrupt number 9 +36 to +39 (Note 1) SI/O3/INT4 (Note 2, Note 4) Remarks Cannot be masked I flag (Note 4) Software interrupt number 10 +40 to +43 (Note 1) Bus collision detection Software interrupt number 11 +44 to +47 (Note 1) DMA0 Software interrupt number 12 +48 to +51 (Note 1) DMA1 Software interrupt number 13 +52 to +55 (Note 1) Key input interrupt Software interrupt number 14 +56 to +59 (Note 1) A-D Software interrupt number 15 +60 to +63 (Note 1) UART2 transmit/NACK (Note 3) Software interrupt number 16 +64 to +67 (Note 1) UART2 receive/ACK (Note 3) Software interrupt number 17 +68 to +71 (Note 1) UART0 transmit Software interrupt number 18 +72 to +75 (Note 1) UART0 receive Software interrupt number 19 +76 to +79 (Note 1) UART1 transmit Software interrupt number 20 +80 to +83 (Note 1) UART1 receive Software interrupt number 21 +84 to +87 (Note 1) Timer A0 Software interrupt number 22 +88 to +91 (Note 1) Timer A1 Software interrupt number 23 +92 to +95 (Note 1) Timer A2 Software interrupt number 24 +96 to +99 (Note 1) Timer A3 Software interrupt number 2 5 Software interrupt number 26 +100 to +103 (Note 1) Timer A4 +104 to +107 (Note 1) Timer B0 Software interrupt number 27 +108 to +111 (Note 1) Timer B1 Software interrupt number 28 +112 to +115 (Note 1) Timer B2 Software interrupt number 29 +116 to +119 (Note 1) INT0 Software interrupt number 30 +120 to +123 (Note 1) INT1 Software interrupt number 31 +124 to +127 (Note 1) INT2 Software interrupt number 32 +128 to +131 (Note 1) to Software interrupt number 63 to +252 to +255 (Note 1) Software interrupt Cannot be masked I flag Note 1: Address relative to address in interrupt table register (INTB). Note 2: It is selected by interrupt request cause bit (bit 6, 7 in address 035F16 ). Note 3: When IIC mode is selected, NACK and ACK interrupts are selected. Note 4: In M30623 (80-pin package), can not use INT3 to INT5 as the interrupt factor, because P15/D13/INT3 to P17/D15/INT5 have no corresponding external pin. 54 Mitsubishi microcomputers M16C / 62T Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Figure 1.14.3 shows the memory map of the interrupt control registers. 55 Mitsubishi microcomputers M16C / 62T Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt control register AAA AA A AAA AA A b7 b6 b5 b4 b3 b2 b1 b0 Symbol TBiIC(i=3 to 5) BCNIC DMiIC(i=0, 1) KUPIC ADIC SiTIC(i=0 to 2) SiRIC(i=0 to 2) TAiIC(i=0 to 4) TBiIC(i=0 to 2) Bit symbol ILVL0 Address 004516 to 004716 004A16 004B16, 004C16 004D16 004E16 005116, 005316, 004F16 005216, 005416, 005016 005516 to 005916 005A16 to 005C16 Bit name level Interrupt priority select bit ILVL2 I R Functio n b2 b1 b0 000: 001: 010: 011: 100: 101: 110: 111: ILVL1 Interrupt request bit When reset XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 AA AA AA AA AA AA AA AA AA AA AA AA R W Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 0 : Interrupt not requested 1 : Interrupt requested Nothing is assigned. (Note 1) In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts. AA b7 b6 b5 0 b4 b3 b2 b1 b0 Symbol Address INTiIC (i=3) 004416 SiIC/INTjIC (i=4, 3) 004816, 004916 (j=4, 5) INTiIC (i=0 to 2) 005D16 to 005F16 Bit symbol ILVL0 ILVL2 POL XX00X0002 Bit name level Interrupt priority select bit ILVL1 IR When reset XX00X0002 XX00X0002 Interrupt request bit Polarity select bit Reserved bit Nothing is assigned. Functio n b2 b1 b0 AA AA AA A A AA AA AA AA AA AA AA AA AA AA R W 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Always set to "0" (Note 1) In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: In M30623(80-pin package), can not use INT3 to INT5 interrupts. Always set INT3IC to ``00''. Each of INT4IC and INT5IC is shared with S3IC and S4IC, but in case of not using as S3IC and S4IC, always set to ``00''. Note 3: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts. Figure 1.14.3. Interrupt control registers 56 Mitsubishi microcomputers M16C / 62T Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Enable Flag (I flag) The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to "1" enables all maskable interrupts; setting it to "0" disables all maskable interrupts. This flag is set to "0" after reset. Interrupt Request Bit The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1"). Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to "0" disables the interrupt. Table 1.14.3 shows the settings of interrupt priority levels and Table 1.14.4 shows the interrupt levels enabled, according to the consist of the IPL. The following are conditions under which an interrupt is accepted: * interrupt enable flag (I flag) = 1 * interrupt request bit = 1 * interrupt priority level > IPL The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another. Table 1.14.3. Settings of interrupt priority levels Interrupt priority level select bit Interrupt priority level Table 1.14.4. Interrupt levels enabled according to the contents of the IPL Priority order b2 b1 b0 IPL Enabled interrupt priority levels IPL2 IPL1 IPL0 0 0 0 Level 0 (interrupt disabled) 0 0 1 Level 1 0 1 0 0 1 1 0 0 0 Interrupt levels 1 and above are enabled 0 0 1 Interrupt levels 2 and above are enabled Level 2 0 1 0 Interrupt levels 3 and above are enabled 1 Level 3 0 1 1 Interrupt levels 4 and above are enabled 0 0 Level 4 1 0 0 Interrupt levels 5 and above are enabled 1 0 1 Level 5 1 0 1 Interrupt levels 6 and above are enabled 1 1 0 Level 6 1 1 0 Interrupt levels 7 and above are enabled 1 1 1 Level 7 1 1 1 All maskable interrupts are disabled Low High 57 Mitsubishi microcomputers M16C / 62T Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rewrite the interrupt control register To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: Example 1: INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET 58 Mitsubishi microcomputers M16C / 62T Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Sequence An interrupt sequence -- what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed -- is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given: (1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 0000016. (2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to "0" (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed) (4) Saves the content of the temporary register (Note) within the CPU in the stack area. (5) Saves the content of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL. After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user. Interrupt Response Time 'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure 1.14.4 shows the interrupt response time. Interrupt request generated Interrupt request acknowledged Time Instruction Interrupt sequence (a) Instruction in interrupt routine (b) Interrupt response time Figure 1.14.4. Interrupt response time 59 Mitsubishi microcomputers M16C / 62T Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time (b) is as shown in Table 1.14.5. Table 1.14.5. Time required for executing the interrupt sequence Interrupt vector address Stack pointer (SP) value 16-Bit bus, without wait 8-Bit bus, without wait Even Even 18 cycles (Note 1) 20 cycles (Note 1) Even Odd 19 cycles (Note 1) 20 cycles (Note 1) Odd (Note 2) Even 19 cycles (Note 1) 20 cycles (Note 1) Odd (Note 2) Odd 20 cycles (Note 1) 20 cycles (Note 1) ________ Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence interrupt or of a single-step interrupt. Note 2: Locate an interrupt vector address in an even address, if possible. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 BCLK Address bus Address 0000 Interrupt information Data bus R Indeterminate Indeterminate SP-2 SP-4 SP-2 contents vec SP-4 contents vec+2 vec contents PC vec+2 contents Indeterminate W The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. Figure 1.14.5. Time required for executing the interrupt sequence Variation of IPL when Interrupt Request is Accepted If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table 1.14.6 is set in the IPL. Table 1.14.6. Relationship between interrupts without interrupt priority levels and IPL Interrupt sources without priority levels Value set in the IPL _______ 60 Watchdog timer, NMI 7 Reset 0 Other Not changed Mitsubishi microcomputers M16C / 62T Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Saving Registers In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. Figure 1.14.6 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM instruction alone can save all the registers except the stack pointer (SP). Address MSB Stack area Address MSB LSB Stack area LSB m-4 m-4 Program counter (PCL) m-3 m-3 Program counter (PCM) m-2 m-2 Flag register (FLGL) m-1 m-1 m Content of previous stack m+1 Content of previous stack Stack status before interrupt request is acknowledged [SP] Stack pointer value before interrupt occurs Flag register (FLGH) [SP] New stack pointer value Program counter (PCH) m Content of previous stack m+1 Content of previous stack Stack status after interrupt request is acknowledged Figure 1.14.6. State of stack before and after acceptance of interrupt request 61 Mitsubishi microcomputers M16C / 62T Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Figure 1.14.7 shows the operation of the saving registers. Note: Stack pointer indicated by U flag. (1) Stack pointer (SP) contains even number Address Stack area Sequence in which order registers are saved [SP] - 5 (Odd) [SP] - 4 (Even) Program counter (PCL) [SP] - 3(Odd) Program counter (PCM) [SP] - 2 (Even) Flag register (FLGL) [SP] - 1(Odd) [SP] Flag register (FLGH) Program counter (PCH) (2) Saved simultaneously, all 16 bits (1) Saved simultaneously, all 16 bits (Even) Finished saving registers in two operations. (2) Stack pointer (SP) contains odd number Address Stack area Sequence in which order registers are saved [SP] - 5 (Even) [SP] - 4(Odd) Program counter (PCL) (3) [SP] - 3 (Even) Program counter (PCM) (4) [SP] - 2(Odd) Flag register (FLGL) [SP] - 1 (Even) [SP] Flag register (FLGH) Program counter (PCH) Saved simultaneously, all 8 bits (1) (2) (Odd) Finished saving registers in four operations. Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. Figure 1.14.7. Operation of saving registers 62 Mitsubishi microcomputers M16C / 62T Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Returning from an Interrupt Routine Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter (PC), both of which have been saved in the stack area. Then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. Return the other registers saved by software within the interrupt routine using the POPM or similar instruction before executing the REIT instruction. Interrupt Priority If there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. Figure 1.14.8 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine. _______ ________ Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match Figure 1.14.8. Hardware interrupts priorities Interrupt resolution circuit When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. Figure 1.14.9 shows the circuit that judges the interrupt priority level. 63 Mitsubishi microcomputers M16C / 62T Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Priority level of each interrupt INT1 Level 0 (initial value) High Timer B2 Timer B0 Timer A3 Timer A1 Timer B4 INT3 INT2 INT0 Timer B1 Timer A4 Timer A2 Timer B3 Timer B5 UART1 reception UART0 reception Priority of peripheral I/O interrupts (if priority levels are same) UART2 reception/ACK A-D conversion DMA1 Bus collision detection Serial I/O4/INT5 Timer A0 UART1 transmission UART0 transmission UART2 transmission/NACK Key input interrupt DMA0 Serial I/O3/INT4 Processor interrupt priority level (IPL) Interrupt enable flag (I flag) Address match Low Interrupt request accepted Watchdog timer DBC NMI Reset Note 1: In M30623 (80-pin package), can not use INT3 to INT5 as the interrupt factors, because P15/D13/INT3 to P17/D15/INT5 have no corresponding external pin. Figure 1.14.9. Maskable interrupts priorities (peripheral I/O interrupts) 64 Mitsubishi microcomputers M16C / 62T Group ______ INT Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ______ INT Interrupt ________ ________ INT0 to INT5 are triggered by the edges of external inputs. The edge polarity is selected using the polarity select bit. ________ Of interrupt control registers, 004816 is used both as serial I/O4 and external interrupt INT5 input control ________ register, and 004916 is used both as serial I/O3 and as external interrupt INT4 input control register. Use the interrupt request cause select bits - bits 6 and 7 of the interrupt request cause select register (035F16) - to specify which interrupt request cause to select. After having set an interrupt request cause, be sure to clear the corresponding interrupt request bit before enabling an interrupt. Either of the interrupt control registers - 004816, 004916 - has the polarity-switching bit. Be sure to set this bit to "0" to select an serial I/O as the interrupt request cause. As for external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge by setting "1" in the INTi interrupt polarity switching bit of the interrupt request cause select register (035F16). To select both edges, set the polarity switching bit of the corresponding interrupt control register to `falling edge' ("0"). Figure 1.14.10 shows the Interrupt request cause select register. _______ _______ Note 1: In M30623(80-pin package), can not use INT3 to INT5 as the interrupt factor, because _______ _______ P15/D13/INT3 to P17/D15/INT5 have no corresponding external pin. AA A AA A AAAA AA Interrupt request cause select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol IFSR Bit symbol Address 035F16 When reset 0016 Bit name Fumction IFSR0 INT0 interrupt polarity swiching bit 0 : One edge 1 : Two edges IFSR1 INT1 interrupt polarity swiching bit 0 : One edge 1 : Two edges IFSR2 INT2 interrupt polarity swiching bit 0 : One edge 1 : Two edges IFSR3 INT3 interrupt polarity swiching bit 0 : One edge 1 : Two edges IFSR4 INT4 interrupt polarity swiching bit 0 : One edge 1 : Two edges IFSR5 INT5 interrupt polarity swiching bit 0 : One edge 1 : Two edges IFSR6 Interrupt request cause select bit 0 : SIO3 1 : INT4 IFSR7 Interrupt request cause select bit 0 : SIO4 1 : INT5 Note 1: In M30623(80-pin package), can not use INT3 to INT5 interrupts, so setting data of these bits are invalid. Note 2: In M30623(80-pin package), can not use INT3 to INT5 interrupts. A A A A AA AA AA AA AA A A AA AA R W Figure 1.14.10. Interrupt request cause select register 65 Mitsubishi microcomputers M16C / 62T Group _______ NMI Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ______ NMI Interrupt ______ ______ ______ An NMI interrupt is generated when the input to the P85/NMI pin changes from "H" to "L". The NMI interrupt is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address 03F016). This pin cannot be used as a normal port input. Key Input Interrupt If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to P107 as A-D input ports. Figure 1.14.11 shows the block diagram of the key input interrupt. Note that if an "L" level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt. Port P104-P107 pull-up select bit Pull-up transistor Key input interrupt control register Port P107 direction register (address 004D16) Port P107 direction register P107/KI3 Pull-up transistor Port P106 direction register Interrupt control circuit P106/KI2 Pull-up transistor Port P105 direction register P105/KI1 Pull-up transistor Port P104 direction register P104/KI0 Figure 1.14.11. Block diagram of key input interrupt 66 Key input interrupt request Mitsubishi microcomputers M16C / 62T Group Address Match Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Address Match Interrupt An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the program counter (PC) for an address match interrupt varies depending on the instruction being executed. Figure 1.14.12 shows the address match interrupt-related registers. Address match interrupt enable register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Address 000916 When reset XXXXXX002 AAAAAAAAAAAAAA AAAAAAAAAAAAAA AA A AAAAAAAAAAAAAA AA A AAAAAAAAAAAAAA AAAAAAAAAAAAAA Bit symbol Bit name Function AIER0 Address match interrupt 0 enable bit 0 : Interrupt disabled 1 : Interrupt enabled AIER1 Address match interrupt 1 enable bit 0 : Interrupt disabled 1 : Interrupt enabled RW Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminated. Address match interrupt register i (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol RMAD0 RMAD1 Address 001216 to 001016 001616 to 001416 Function Address setting register for address match interrupt When reset X0000016 X0000016 AA A AA A Values that can be set R W 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminated. Figure 1.14.12. Address match interrupt-related registers 67 Mitsubishi microcomputers M16C / 62T Group Precautions for Interrupts SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Precautions for Interrupts (1) Reading address 0000016 * When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to "0". Reading address 0000016 by software sets enabled highest priority interrupt source request bit to "0". Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 0000016 by software. (2) Setting the stack pointer * The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in _______ the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point at the beginning of a program. Concerning the first instruction immediately after reset, generating any _______ interrupts including the NMI interrupt is prohibited. _______ (3) The NMI interrupt _______ * As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the Vcc pin via a resistor (pull-up) if unused. Be sure to work on it. _______ * The NMI pin also serves as P85 , which is exclusively input. Reading the contents of the P8 register allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time _______ when the NMI interrupt is input. _______ * Do not reset the CPU with the input to the NMI pin being in the "L" state. _______ * Do not attempt to go into stop mode with the input to the NMI pin being in the "L" state. With the input to _______ the NMI being in the "L" state, the CM10 is fixed to "0", so attempting to go into stop mode is turned down. _______ * Do not attempt to go into wait mode with the input to the NMI pin being in the "L" state. With the input to _______ the NMI pin being in the "L" state, the CPU stops but the oscillation does not stop, so no power is saved. In this instance, the CPU is returned to the normal state by a later interrupt. _______ * Signals input to the NMI pin require an "L" level of 1 clock or more, from the operation clock of the CPU. (4) External interrupt ________ * Either an "L" level or an "H" level of at least 250 ns width is necessary for the signal input to pins INT0 ________ through INT5 regardless of the CPU operation clock. ________ ________ * When the polarity of the INT 0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". Figure 1.14.13 shows the procedure for ______ changing the INT interrupt generate factor. _______ _______ Note 1: In M30623(80-pin package), can not use INT3 to INT5 as the interrupt factor,because _______ _______ P15/D13/INT3 to P17/D15/INT5 have no corresponding external pin. 68 Mitsubishi microcomputers M16C / 62T Group Precautions for Interrupts SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clear the interrupt enable flag to "0" (Disable interrupt) Set the interrupt priority level to level 0 (Disable INTi interrupt) Set the polarity select bit Clear the interrupt request bit to "0" Set the interrupt priority level to level 1 to 7 (Enable the accepting of INTi interrupt request) Set the interrupt enable flag to "1" (Enable interrupt) ______ Figure 1.14.13. Switching condition of INT interrupt request (5) Rewrite the interrupt control register * To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: Example 1: INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. * When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET 69 Mitsubishi microcomputers M16C / 62T Group Watchdog Timer SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Watchdog Timer The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. When X IN is selected for the BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). When X CIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). Thus the watchdog timer's period can be calculated as given below. The watchdog timer's period is, however, subject to an error due to the pre-scaler. With XIN chosen for BCLK Watchdog timer period = pre-scaler dividing ratio (16 or 128) X watchdog timer count (32768) BCLK With XCIN chosen for BCLK Watchdog timer period = pre-scaler dividing ratio (2) X watchdog timer count (32768) BCLK For example, suppose that BCLK runs at 16 MHz and that 16 has been chosen for the dividing ratio of the pre-scaler, then the watchdog timer's period becomes approximately 32.8 ms. The watchdog timer is initialized by writing to the watchdog timer start register (address 000E 16) and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E16). Figure 1.15.1 shows the block diagram of the watchdog timer. Figure 1.15.2 shows the watchdog timerrelated registers. Prescaler 1/16 BCLK 1/128 "CM07 = 0" "WDC7 = 0" "CM07 = 0" "WDC7 = 1" Watchdog timer HOLD "CM07 = 1" 1/2 Write to the watchdog timer start register (address 000E16) RESET Figure 1.15.1. Block diagram of watchdog timer 70 Set to "7FFF16" Watchdog timer interrupt request Mitsubishi microcomputers M16C / 62T Group Watchdog Timer SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol WDC 0 0 Bit symbol Address 000F16 When reset 00XXXXX2 Bit name Function High-order bit of watchdog timer WDV5 Cold start / warm start 0 : Cold start discrimination flag (Note 1) 1 : Warm start Reserved bit WDC7 Must always be set to "0" Prescaler select bit 0 : Divided by 16 1 : Divided by 128 Note 1: When this flag is written ``0'' or ``1'', it is set ``1'' automatically . : This bit is not under the influence of a reset. A A A A R W Watchdog timer start register b7 b0 Symbol WDTS Address 000E16 When reset Indeterminate Function RW AA The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to "7FFF16" regardless of whatever value is written. Figure 1.15.2. Watchdog timer control and start registers Cold start / Warm start The cold start/warm start discrimination flag(bit 5 at 000F16) indicates the last reset by power on(cold start) or by reset signal(warm start). The cold start/warm start discrimination flag is set ``0'' at power on, and is set ``1'' at writing any data to the watchdog timer control register(address is 000F16). The flag is not set to ``0'' by the software reset and the input of reset signal. ``5V'' Vcc ``0V'' ``5V'' RESET 0.2Vcc ``0V'' Set to ``1'' by software Cold start / Warm start discrimination flag (WDC5) ``1'' ``0'' Figure 1.15.3. Cold sgtart / Warm start 71 Mitsubishi microcomputers M16C / 62T Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 1.16.1 shows the block diagram of the DMAC. Table 1.16.1 shows the DMAC specifications. Figures 1.16.2 to 1.16.4 show the registers used by the DMAC. AA AAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAA A A A AAA AA A AAA A AA AA A AA AA AA AA A A AA A AA AA A AAA A AA AAAA AA AA AA AA AA A A AA AA A A A AA A A AA AA AA AA Address bus DMA0 source pointer SAR0(20) (addresses 002216 to 002016) DMA0 destination pointer DAR0 (20) (addresses 002616 to 002416) DMA0 forward address pointer (20) (Note) DMA0 transfer counter reload register TCR0 (16) (addresses 002916, 002816) DMA0 transfer counter TCR0 (16) DMA1 source pointer SAR1 (20) (addresses 003216 to 003016) DMA1 destination pointer DAR1 (20) (addresses 003616 to 003416) DMA1 transfer counter reload register TCR1 (16) DMA1 forward address pointer (20) (Note) (addresses 003916, 003816) DMA1 transfer counter TCR1 (16) DMA latch high-order bits DMA latch low-order bits Data bus low-order bits Data bus high-order bits Note: Pointer is incremented by a DMA request. Figure 1.16.1. Block diagram of DMAC Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level. The DMA transfer doesn't affect any interrupts either. If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the number of transfers. For details, see the description of the DMA request bit. 72 Mitsubishi microcomputers M16C / 62T Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.16.1. DMAC specifications Item No. of channels Transfer memory space Maximum No. of bytes transferred Specification 2 (cycle steal method) * From any address in the 1M bytes space to a fixed address * From a fixed address to any address in the 1M bytes space * From a fixed address to a fixed address (Note that DMA-related registers [002016 to 003F16] cannot be accessed) 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers) ________ ________ ________ ________ DMA request factors (Note) Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 by DMA1) or both edge Timer A0 to timer A4 interrupt requests Timer B0 to timer B5 interrupt requests UART0 transfer and reception interrupt requests UART1 transfer and reception interrupt requests UART2 transfer and reception interrupt requests Serial I/O3, 4 interrpt requests A-D conversion interrupt requests Software triggers Channel priority DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously Transfer unit 8 bits or 16 bits Transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) Transfer mode * Single transfer mode After the transfer counter underflows, the DMA enable bit turns to "0", and the DMAC turns inactive * Repeat transfer mode After the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. The DMAC remains active unless a "0" is written to the DMA enable bit. DMA interrupt request generation timing When an underflow occurs in the transfer counter Active When the DMA enable bit is set to "1", the DMAC is active. When the DMAC is active, data transfer starts every time a DMA transfer request signal occurs. Inactive * When the DMA enable bit is set to "0", the DMAC is inactive. * After the transfer counter underflows in single transfer mode At the time of starting data transfer immediately after turning the DMAC active, the Forward address pointer and value of one of source pointer and destination pointer - the one specified for the reload timing for transfer forward direction - is reloaded to the forward direction address pointer,and the value counter of the transfer counter reload register is reloaded to the transfer counter. Writing to register Registers specified for forward direction transfer are always write enabled. Registers specified for fixed address transfer are write-enabled when the DMA enable bit is "0". Reading the register Can be read at any time. However, when the DMA enable bit is "1", reading the register set up as the forward register is the same as reading the value of the forward address pointer. Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level. 73 Mitsubishi microcomputers M16C / 62T Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMA0 request cause select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM0SL Bit symbol DSEL0 Address 03B816 When reset 0016 Function Bit name DMA request cause select bit DSEL1 DSEL2 DSEL3 b3 b2 b1 b0 DSR Figure 1.16.2. DMAC register (1) 74 W 0 0 0 0 : Falling edge of INT0 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3 0 1 1 0 : Timer A4 (DMS=0) /two edges of INT0 pin (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) Timer B3 (DMS=1) 1 0 0 0 : Timer B1 (DMS=0) Timer B4 (DMS=1) 1 0 0 1 : Timer B2 (DMS=0) Timer B5 (DMS=1) 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 transmit Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". DMS AA AA AA AA R DMA request cause expansion bit 0 : Normal 1 : Expanded cause Software DMA request bit If software trigger is selected, a DMA request is generated by setting this bit to "1" (When read, the value of this bit is always "0") AA A A AA Mitsubishi microcomputers M16C / 62T Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMA1 request cause select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM1SL Address 03BA16 Function Bit name Bit symbol DSEL0 When reset 0016 DMA request cause select bit DSEL1 DSEL2 DSEL3 b3 b2 b1 b0 0 0 0 0 : Falling edge of INT1 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3(DMS=0) /serial I/O3 (DMS=1) 0 1 1 0 : Timer A4 (DMS=0) /serial I/O4 (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) /two edges of INT1 (DMS=1) 1 0 0 0 : Timer B1 1 0 0 1 : Timer B2 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 receive Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". DMS DMA request cause expansion bit 0 : Normal 1 : Expanded cause DSR Software DMA request bit If software trigger is selected, a DMA request is generated by setting this bit to "1" (When read, the value of this bit is always "0") AA A AA A AA AA AA A A AA R W DMAi control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DMiCON(i=0,1) Bit symbol Address 002C16, 003C16 When reset 00000X002 Bit name Function DMBIT Transfer unit bit select bit 0 : 16 bits 1 : 8 bits DMASL Repeat transfer mode select bit 0 : Single transfer 1 : Repeat transfer DMAS DMA request bit (Note 1) 0 : DMA not requested 1 : DMA requested DMAE DMA enable bit 0 : Disabled 1 : Enabled DSD Source address direction select bit (Note 3) 0 : Fixed 1 : Forward DAD Destination address 0 : Fixed direction select bit (Note 3) 1 : Forward Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". AA AA AA AA AA AA AA R W (Note 2) Note 1: DMA request can be cleared by resetting the bit. Note 2: This bit can only be set to "0". Note 3: Source address direction select bit and destination address direction select bit cannot be set to "1" simultaneously. Figure 1.16.3. DMAC register (2) 75 Mitsubishi microcomputers M16C / 62T Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAi source pointer (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol SAR0 SAR1 Address 002216 to 002016 003216 to 003016 When reset Indeterminate Indeterminate Transfer count specification Function * Source pointer Stores the source address R W AA 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". DMAi destination pointer (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol DAR0 DAR1 Address 002616 to 002416 003616 to 003416 When reset Indeterminate Indeterminate Transfer count specification Function * Destination pointer Stores the destination address AAAA R W 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". DMAi transfer counter (i = 0, 1) (b15) b7 (b8) b0 b7 b0 Symbol TCR0 TCR1 Address 002916, 002816 003916, 003816 Function * Transfer counter Set a value one less than the transfer count Figure 1.16.4. DMAC register (3) 76 When reset Indeterminate Indeterminate Transfer count specification 000016 to FFFF16 AA R W Mitsubishi microcomputers M16C / 62T Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Transfer cycle The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to the SFR area (destination write). The number of read and write bus cycles depends on the source and destination addresses. In memory expansion mode and microprocessor mode, the number of read and write bus cycles also depends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted. (a) Effect of source and destination addresses When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. (b) Effect of BYTE pin level When transferring 16-bit data over an 8-bit data bus (BYTE pin = "H") in memory expansion mode and microprocessor mode, the 16 bits of data are sent in two 8-bit blocks. Therefore, two bus cycles are required for reading the data and two are required for writing the data. Also, in contrast to when the CPU accesses internal memory, when the DMAC accesses internal memory (internal ROM, internal RAM, and SFR), these areas are accessed using the data size selected by the BYTE pin. (c) Effect of software wait When the SFR area or a memory area with a software wait is accessed, the number of cycles is increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK. Figure 1.16.5 shows the example of the transfer cycles for a source read. For convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle. For example (2) in Figure 1.16.5, if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the source read cycle and the destination write cycle. Note 1: M30623(80-pin package), in case of access to the external bus area, can be used only when 8-bit bus mode. 77 Mitsubishi microcomputers M16C / 62T Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) 8-bit transfers 16-bit transfers from even address and the source address is even. BCLK Address bus CPU use Source Destination Dummy cycle CPU use RD signal WR signal Data bus CPU use Dummy Destination cycle Source CPU use (2) 16-bit transfers and the source address is odd Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination write cycles). BCLK Address bus CPU use Source Source + 1 Destination Dummy cycle CPU use RD signal WR signal Data bus CPU use Source + 1 Destination Dummy cycle Source CPU use (3) One wait is inserted into the source read under the conditions in (1) BCLK Address bus CPU use Source Destination Dummy cycle CPU use RD signal WR signal Data bus CPU use Source Destination Dummy cycle CPU use (4) One wait is inserted into the source read under the conditions in (2) (When 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles). BCLK Address bus CPU use Source Source + 1 Destination Dummy cycle CPU use RD signal WR signal Data bus CPU use Source Source + 1 Destination Dummy cycle CPU use Note 1: The same timing changes occur with the respective conditions at the destination as at the source. Note 2: M30623(80-pin package), in case of access to the external bus area, can be used only when 8-bit bus mode. Figure 1.16.5. Example of the transfer cycles for a source read 78 Mitsubishi microcomputers M16C / 62T Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (2) DMAC transfer cycles Any combination of even or odd transfer read and write addresses is possible. Table 1.16.2 shows the number of DMAC transfer cycles. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k Table 1.16.2. No. of DMAC transfer cycles Single-chip mode Transfer unit 8-bit transfers (DMBIT= "1") 16-bit transfers (DMBIT= "0") Bus width Access address 16-bit (BYTE= "L") 8-bit (BYTE = "H") 16-bit (BYTE = "L") 8-bit (BYTE = "H") Even Odd Even Odd Even Odd Even Odd Memory expansion mode Microprocessor mode No. of read No. of write No. of read No. of write cycles cycles cycles cycles 1 1 1 1 1 1 1 1 -- -- 1 1 -- -- 1 1 1 1 1 1 2 2 2 2 -- -- 2 2 -- -- 2 2 Coefficient j, k Internal memory Internal ROM/RAM Internal ROM/RAM No wait With wait 1 2 SFR area 2 External memory Separate bus Separate bus No wait With wait 1 2 Multiplex bus 3 Note 1: M30623(80-pin package), in case of access to the external bus area, can be used only when 8-bit bus mode. 79 Mitsubishi microcomputers M16C / 62T Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMA enable bit Setting the DMA enable bit to "1" makes the DMAC active. The DMAC carries out the following operations at the time data transfer starts immediately after DMAC is turned active. (1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the forward direction - to the forward direction address pointer. (2) Reloads the value of the transfer counter reload register to the transfer counter. Thus overwriting "1" to the DMA enable bit with the DMAC being active carries out the operations given above, so the DMAC operates again from the initial state at the instant "1" is overwritten to the DMA enable bit. DMA request bit The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of DMA request factors for each channel. DMA request factors include the following. * Factors effected by using the interrupt request signals from the built-in peripheral functions and software DMA factors (internal factors) effected by a program. * External factors effected by utilizing the input from external interrupt signals. For the selection of DMA request factors, see the descriptions of the DMAi factor selection register. The DMA request bit turns to "1" if the DMA transfer request signal occurs regardless of the DMAC's state (regardless of whether the DMA enable bit is set "1" or to "0"). It turns to "0" immediately before data transfer starts. In addition, it can be set to "0" by use of a program, but cannot be set to "1". There can be instances in which a change in DMA request factor selection bit causes the DMA request bit to turn to "1". So be sure to set the DMA request bit to "0" after the DMA request factor selection bit is changed. The DMA request bit turns to "1" if a DMA transfer request signal occurs, and turns to "0" immediately before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the DMA request bit, if read by use of a program, turns out to be "0" in most cases. To examine whether the DMAC is active, read the DMA enable bit. Here follows the timing of changes in the DMA request bit. (1) Internal factors Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to "1" due to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to turn to "1" due to several factors. Turning the DMA request bit to "1" due to an internal factor is timed to be effected immediately before the transfer starts. (2) External factors An external factor is a factor caused to occur by the leading edge of input from the INTi pin (i depends on which DMAC channel is used). Selecting the INTi pins as external factors using the DMA request factor selection bit causes input from these pins to become the DMA transfer request signals. The timing for the DMA request bit to turn to "1" when an external factor is selected synchronizes with the signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes with the trailing edge of the input signal to each INTi pin, for example). With an external factor selected, the DMA request bit is timed to turn to "0" immediately before data transfer starts similarly to the state in which an internal factor is selected. 80 Mitsubishi microcomputers M16C / 62T Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (3) The priorities of channels and DMA transfer timing If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels concurrently turn to "1". If the channels are active at that moment, DMA0 is given a high priority to start data transfer. When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus access, then DMA1 starts data transfer and gives the bus right to the CPU. An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer request signals due to external factors concurrently occur. Figure 1.16.6 An example of DMA transfer effected by external factors. An example in which DMA transmission is carried out in minimum cycles at the time when DMA transmission request signals due to external factors concurrently occur. BCLK DMA0 DMA1 CPU INT0 AAAA AAAA AAAA AAA AAAAAA AAAAAA AA AAAAAA AAA AAAAAA AA Obtainm ent of the bus right DMA0 request bit INT1 DMA1 request bit Figure 1.16.6. An example of DMA transfer effected by external factors 81 Mitsubishi microcomputers M16C / 62T Group Timer SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers B (six). All these timers function independently. Figures 1.17.1 and 1.17.2 show the block diagram of timers. Clock prescaler f1 XIN f8 1/8 1/4 f32 1/32 XCIN Clock prescaler reset flag (bit 7 at address 038116) set to "1" fC32 Reset f1 f8 f32 fC32 * Timer mode * One-shot mode * PWM mode Timer A0 interrupt TA0IN Noise filter Timer A0 * Event counter mode * Timer mode * One-shot mode * PWM mode TA1IN Noise filter Timer A1 interrupt Timer A1 * Event counter mode * Timer mode * One-shot mode * PWM mode Timer A2 interrupt TA2IN Noise filter Timer A2 * Event counter mode * Timer mode * One-shot mode * PWM mode Timer A3 interrupt TA3IN Noise filter Timer A3 * Event counter mode * Timer mode * One-shot mode * PWM mode Timer A4 interrupt TA4IN Noise filter Timer A4 * Event counter mode Timer B2 overflow Note 1: In M30623(80-pin package), do not use TA1IN and TA2IN as the event input, because these are not connected to the external pin. And these pins have to do connection of unused pins (refer to Page 170). Note 2: The TA0IN pin (P71) is shared with RxD2 and the TB5IN pin. Figure 1.17.1. Timer A block diagram 82 Mitsubishi microcomputers M16C / 62T Group Timer SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock prescaler f1 XIN f8 1/8 1/4 f32 fC32 1/32 XCIN Clock prescaler reset flag (bit 7 at address 038116) set to "1" Reset f1 f8 f32 fC32 Timer A * Timer mode * Pulse width measuring mode TB0IN Timer B0 interrupt Noise filter Timer B0 * Event counter mode * Timer mode * Pulse width measuring mode TB1IN Noise filter Timer B1 Timer B1 interrupt * Event counter mode * Timer mode * Pulse width measuring mode TB2IN Noise filter Timer B2 interrupt Timer B2 * Event counter mode * Timer mode * Pulse width measuring mode TB3IN Noise filter Timer B3 interrupt Timer B3 * Event counter mode * Timer mode * Pulse width measuring mode TB4IN Noise filter Timer B4 interrupt Timer B4 * Event counter mode * Timer mode * Pulse width measuring mode TB5IN Noise filter Timer B5 interrupt Timer B5 * Event counter mode Note 1: In M30623(80-pin package), do not use TB1IN as the event input, because it is not connected to the external pin. And these pins have to do connection of unused pins (refer to Page 170). Note 2: The TB5IN pin (P71) is shared with RxD2 and the TA0IN pin. Figure 1.17.2. Timer B block diagram 83 Mitsubishi microcomputers M16C / 62T Group Timer A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Figure 1.17.3 shows the block diagram of timer A. Figures 1.17.4 to 1.17.6 show the timer A-related registers. Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. But M30623(80-pin package), timer A1 and A2 have no I/O pin, so it operate as only internal timer. Timer A has the four operation modes listed as follows: * Timer mode: The timer counts an internal count source. * Event counter mode: The timer counts pulses from an external source or a timer over flow. * One-shot timer mode: The timer stops counting when the count reaches "0000 16". * Pulse width modulation (PWM) mode: The timer outputs pulses of a given width. Data bus high-order bits Clock source selection Data bus low-order bits * Timer * One shot * PWM f1 f8 f32 Low-order 8 bits * Timer (gate function) fC32 AA AA Reload register (16) * Event counter TAiIN AAA AAA High-order 8 bits Counter (16) Polarity selection Up count/down count Clock selection (i = 0 to 4) Always down count except in event counter mode Count start flag (Address 038016) Down count TB2 overflow External trigger TAj overflow (j = i - 1. Note, however, that j = 4 when i = 0) Up/down flag (Address 038416) TAi Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Addresses 038716 038616 038916 038816 038B16 038A16 038D16 038C16 038F16 038E16 TAj Timer A4 Timer A0 Timer A1 Timer A2 Timer A3 TAk Timer A1 Timer A2 Timer A3 Timer A4 Timer A0 TAk overflow (k = i + 1. Note, however, that k = 0 when i = 4) Pulse output TAiOUT (i = 0 to 4) Toggle flip-flop Note 1: In M30623(80-pin package), do not select the function using TA1IN, TA1OUT, or TA2IN, and TA2OUT because these are not connected to the external pin. Note 2: The TA0IN pin (P71) is shared with the TB5IN pin, RxD2, and SCL pin. Figure 1.17.3. Block diagram of timer A Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 Bit name Operation mode select bit TMOD1 MR0 MR1 Address When reset 0016 039616 to 039A16 Function b1 b0 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode Function varies with each operation mode MR2 MR3 TCK0 TCK1 Count source select bit (Function varies with each operation mode) Figure 1.17.4. Timer A-related registers (1) 84 AA AA AA AAA AAA AA AA RW Mitsubishi microcomputers M16C / 62T Group Timer A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer Ai register (Note) (b15) b7 (b8) b0 b7 b0 Symbol TA0 TA1 TA2 TA3 TA4 Address 038716,0386 16 038916,0388 16 038B16,038A 16 038D16,038C 16 038F16,038E 16 When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Function Values that can be set * Timer mode Counts an internal count source 000016 to FFFF16 * Event counter mode Counts pulses from an external source or timer overflow 000016 to FFFF16 * One-shot timer mode Counts a one shot width 0000 16 to FFFF 16 * Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator 000016 to FFFE 16 * Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 0016 to FE 16 (Both high-order and low-order addresses) RW Note: Read and write data in 16-bit units. Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Bit symbol Address 0380 16 When reset 0016 Bit name TA0S Timer A0 count start flag TA1S Timer A1 count start flag TA2S Timer A2 count start flag TA3S Timer A3 count start flag TA4S Timer A4 count start flag TB0S Timer B0 count start flag TB1S Timer B1 count start flag TB2S Timer B2 count start flag Function RW 0 : Stops counting 1 : Starts counting Up/down flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol UDF Bit symbol Address 038416 Bit name TA0UD Timer A0 up/down flag TA1UD Timer A1 up/down flag TA2UD Timer A2 up/down flag TA3UD Timer A3 up/down flag TA4UD Timer A4 up/down flag TA2P TA3P TA4P When reset 0016 Function RW 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause Timer A2 two-phase pulse 0 : two-phase pulse signal signal processing select bit processing disabled (Note 1) 1 : two-phase pulse signal processing enabled Timer A3 two-phase pulse signal processing select bit When not using the two-phase Timer A4 two-phase pulse pulse signal processing function, signal processing select bit set the select bit to "0" Note 1: M30623(80-pin package) does not have I/O pins for TA2, so set this bit to "0''. Figure 1.17.5. Timer A-related registers (2) 85 Mitsubishi microcomputers M16C / 62T Group Timer A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER One-shot start flag b7 b6 b5 b4 b3 b2 b1 Symbol ONSF b0 Address 038216 When reset 00X000002 Bit symbol Bit name Function TA0OS Timer A0 one-shot start flag TA1OS Timer A1 one-shot start flag TA2OS Timer A2 one-shot start flag TA3OS Timer A3 one-shot start flag TA4OS Timer A4 one-shot start flag 1 : Timer start When read, the value is "0" AA A AA A A A AA A AA A A A AA A AA RW Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. TA0TGL Timer A0 event/trigger select bit TA0TGH b7 b6 0 0 : Input on TA0IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA4 overflow is selected 1 1 : TA1 overflow is selected Note: Set the corresponding port direction register to "0". Trigger select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRGSR Bit symbol TA1TGL Address 038316 Bit name Timer A1 event/trigger select bit TA1TGH TA2TGL Timer A2 event/trigger select bit TA2TGH TA3TGL Timer A3 event/trigger select bit TA3TGH TA4TGL Timer A4 event/trigger select bit TA4TGH When reset 0016 Function b1 b0 A A A AA A AA A AA A A A A A A A A AA R W 0 0 : Input on TA1IN is selected (Note 1, 2) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected b3 b2 0 0 : Input on TA2IN is selected (Note 1, 2) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected b5 b4 0 0 : Input on TA3IN is selected (Note 1) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected b7 b6 0 0 : Input on TA4IN is selected (Note 1) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected Note 1: Set the corresponding port direction register to "0". Note 2: In M30623(80-pin package), do not select the function using TA1IN and TA2IN, because these are not connected to the external pin. Clock prescaler reset flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Address 038116 Bit symbol Bit name When reset 0XXXXXXX2 Function Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. RW AAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAA A AA CPSR Clock prescaler reset flag Figure 1.17.6. Timer A-related registers (3) 86 0 : No effect 1 : Prescaler is reset (When read, the value is "0") Mitsubishi microcomputers M16C / 62T Group Timer A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 1.17.1.) Figure 1.17.7 shows the timer Ai mode register in timer mode. Table 1.17.1. Specifications of timer mode Item Count source Count operation Specification f1, f8, f32, fC32 * Down count * When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing When the timer underflows TAiIN pin function Programmable I/O port or gate input TAiOUT pin function Programmable I/O port or pulse output Read from timer Count value can be read out by reading timer Ai register Write to timer * When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter * When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Select function * Gate function Counting can be started and stopped by the TAiIN pin's input signal * Pulse output function Each time the timer underflows, the TAiOUT pin's polarity is reversed Note 1: M30623(80-pin package) does not have I/O pins(TAiIN,TAiOUT) for timer A1 and A2. Timer Ai mode register b7 b6 b5 0 b4 b3 b2 b1 b0 0 0 Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0 MR1 Address When reset 0016 039616 to 039A16 Bit name Operation mode select bit Function b1 b0 0 0 : Timer mode AAAA AAAA AAAA AAAA AA RW Pulse output function 0 : Pulse is not output select bit (Note 4) (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin) b4 b3 Gate function select bit 0 X (Note 2): Gate function not available (Note 4) (TAiIN pin is a normal port pin) 1 0 : Timer counts only when TAiIN pin is held "L" (Note 3) 1 1 : Timer counts only when TAiIN pin is held "H" (Note 3) MR2 MR3 0 (Must always be fixed to "0" in timer mode) TCK0 Count source select bit TCK1 b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: The bit can be "0" or "1". Note 3: Set the corresponding port direction register to "0". Note 4: In timer A1 and A2 mode register of M30623(80-pin package), set these bits to "0". Figure 1.17.7. Timer Ai mode register in timer mode 87 Mitsubishi microcomputers M16C / 62T Group Timer A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (2) Event counter mode In this mode, the timer counts an external signal or an internal timer's overflow. Timers A0 and A1 can count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase external signal. Table 1.17.2 lists timer specifications when counting a single-phase external signal. Figure 1.17.8 shows the timer Ai mode register in event counter mode. Table 1.17.3 lists timer specifications when counting a two-phase external signal. Figure 1.17.9 shows the timer Ai mode register in event counter mode. Table 1.17.2. Timer specifications in event counter mode (when not processing two-phase pulse signal) Item Specification Count source * External signals input to TAiIN pin (effective edge can be selected by software) * TB2 overflow, TAj overflow Count operation * Up count or down count can be selected by external signal or software * When the timer overflows or underflows, it reloads the reload register con tents before continuing counting (Note) Divide ratio 1/ (FFFF16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer overflows or underflows TAiIN pin function Programmable I/O port or count source input TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input Read from timer Count value can be read out by reading timer Ai register Write to timer * When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter * When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Select function * Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it * Pulse output function Each time the timer overflows or underflows, the TAiOUT pin's polarity is reversed Note 1: This does not apply when the free-run function is selected. Note 2: M30623(80-pin package) does not have I/O pins(TAiIN,TAiOUT) for timer A1 and A2. Timer Ai mode register b7 b6 b5 0 b4 b3 b2 b1 b0 Symbol TAiMR(i = 0, 1) 0 1 Address 039616, 039716 When reset 0016 Bit symbol Bit name TMOD0 Operation mode select bit b1 b0 Function MR0 Pulse output function select bit (Note 5) 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 2) (TAiOUT pin is a pulse output pin) MR1 Count polarity select bit (Note 3,Note 5) 0 : Counts external signal's falling edge 1 : Counts external signal's rising edge MR2 Up/down switching cause select bit (Note 5) 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 4) 0 1 : Event counter mode (Note 1) TMOD1 MR3 0 (Must always be fixed to "0" in event counter mode) TCK0 Count operation type select bit TCK1 Invalid in event counter mode Can be "0" or "1" 0 : Reload type 1 : Free-run type AAAA AA AA AAA AAAA A AAAA AA AA RW Note 1: In event counter mode, the count source is selected by the event / trigger select bit (addresses 038216 and 038316). Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Valid only when counting an external signal. Note 4: When an "L" signal is input to the TAiOUT pin, the downcount is activated. When "H", the upcount is activated. Set the corresponding port direction register to "0". Note 5: In Timer A1 and A2 mode register of M30623(80-pin package), set these bits to "0". Figure 1.17.8. Timer Ai mode register in event counter mode 88 Mitsubishi microcomputers M16C / 62T Group Timer A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.17.3. Timer specifications in event counter mode (when processing two-phase pulse signal with timers A2, A3, and A4) Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Select function Specification * Two-phase pulse signals input to TAiIN or TAiOUT pin * Up count or down count can be selected by two-phase pulse signal * When the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (Note) 1/ (FFFF16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) Timer overflows or underflows Two-phase pulse input Two-phase pulse input Count value can be read out by reading timer A2, A3, or A4 register * When counting stopped When a value is written to timer A2, A3, or A4 register, it is written to both reload register and counter * When counting in progress When a value is written to timer A2, A3, or A4 register, it is written to only reload register. (Transferred to counter at next reload time.) * Normal processing operation The timer counts up rising edges or counts down falling edges on the TAiIN pin when input signal on the TAiOUT pin is "H" TAiOUT TAiIN (i=2,3) Up count Up count Up Down count count Down count Down count * Multiply-by-4 processing operation If the phase relationship is such that the TAiIN pin goes "H" when the input signal on the TAiOUT pin is "H", the timer counts up rising and falling edges on the TAiOUT and TAiIN pins. If the phase relationship is such that the TAiIN pin goes "L" when the input signal on the TAi OUT pin is "H", the timer counts down rising and falling edges on the TAiOUT and TAiIN pins. TAiOUT Count up all edges Count down all edges Count up all edges Count down all edges TAiIN (i=3,4) Note 1: This does not apply when the free-run function is selected. Note 2: M30623(80-pin package) does not have I/O pins(TAiIN,TAiOUT) for timer A1 and A2. 89 Mitsubishi microcomputers M16C / 62T Group Timer A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer Ai mode register (When not using two-phase pulse signal processing) b7 b6 b5 b4 b3 b2 0 b1 b0 0 1 Symbol Address When reset TAiMR(i = 2 to 4) 039816 to 039A16 0016 Bit symbol TMOD0 Bit name Operation mode select bit TMOD1 Function b1 b0 0 1 : Event counter mode AA A AA A AA AA AA AA AA AA R W MR0 Pulse output function select bit (Note 5) 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin) MR1 Count polarity select bit (Note 2,Note 5) 0 : Counts external signal's falling edges 1 : Counts external signal's rising edges MR2 Up/down switching cause select bit (Note 5) 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 3) MR3 0 : (Must always be "0" in event counter mode) TCK0 Count operation type select bit 0 : Reload type 1 : Free-run type TCK1 Two-phase pulse signal processing operation select bit (Note 4) 0 : Normal processing operation 1 : Multiply-by-4 processing operation Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: This bit is valid when only counting an external signal. Note 3: Set the corresponding port direction register to "0". Note 4: This bit is valid for the timer A3 mode register. For timer A2 and A4 mode registers, this bit can be "0 "or "1". Note 5: Set these bits to "0", in timer A2 mode register of M30623(80-pin package). Timer Ai mode register (When using two-phase pulse signal processing) b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 0 0 1 Symbol Address When reset TAiMR(i = 2 to 4) 039816 to 039A16 0016 Bit symbol Bit name TMOD0 TMOD1 Operation mode select bit Function b1 b0 0 1 : Event counter mode MR0 0 (Must always be "0" when using two-phase pulse signal processing) MR1 0 (Must always be "0" when using two-phase pulse signal processing) MR2 1 (Must always be "1" when using two-phase pulse signal processing) MR3 0 (Must always be "0" when using two-phase pulse signal processing) TCK0 Count operation type select bit 0 : Reload type 1 : Free-run type TCK1 Two-phase pulse processing operation select bit (Note 1)(Note 2) 0 : Normal processing operation 1 : Multiply-by-4 processing operation A AA AAA A AA AA AA AA AA AA RW Note 1: This bit is valid for timer A3 mode register. For timer A2 and A4 mode registers, this bit can be "0" or "1". Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 038416) is set to "1". Also, always be sure to set the event/trigger select bit (addresses 038216 and 038316) to "00". Note 3: In M30623(80-pin package), do not use timer A2 for the two-phase pulse signal processing. Figure 1.17.9. Timer Ai mode register in event counter mode 90 Mitsubishi microcomputers M16C / 62T Group Timer A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (3) One-shot timer mode In this mode, the timer operates only once. (See Table 1.17.4.) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.17.10 shows the timer Ai mode register in one-shot timer mode. Table1.17.4. Timer specifications in one-shot timer mode Item Count source Count operation Specification f1, f8, f32, fC32 * The timer counts down * When the count reaches 000016, the timer stops counting after reloading a new count * If a trigger occurs when counting, the timer reloads a new count and restarts counting Divide ratio 1/n n : Set value Count start condition * An external trigger is input * The timer overflows * The one-shot start flag is set (= 1) Count stop condition * A new count is reloaded after the count has reached 000016 * The count start flag is reset (= 0) Interrupt request generation timing The count reaches 000016 TAiIN pin function Programmable I/O port or trigger input TAiOUT pin function Programmable I/O port or pulse output Read from timer When timer Ai register is read, it indicates an indeterminate value Write to timer * When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter * When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Note 1: M30623(80-pin package) does not have I/O pins(TAiIN,TAiOUT) for timer A1 and A2. Timer Ai mode register b7 b6 b5 0 b4 b3 b2 b1 b0 1 0 Symbol Address When reset 0016 TAiMR(i = 0 to 4) 039616 to 039A16 AA A A AA A AA A AA A AA A AA A AA A AA AAA Bit symbol Bit name TMOD0 Operation mode select bit b1 b0 MR0 Pulse output function select bit (Note 4) 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin) MR1 External trigger select bit (Note 2) (Note 4) 0 : Falling edge of TAiIN pin's input signal (Note 3) 1 : Rising edge of TAiIN pin's input signal (Note 3) MR2 Trigger select bit 0 : One-shot start flag is valid 1 : Selected by event/trigger select register MR3 0 (Must always be "0" in one-shot timer mode) TCK0 Count source select bit TMOD1 TCK1 Function 1 0 : One-shot timer mode b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 RW Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 038216 and 038316). If timer overflow is selected, this bit can be "1" or "0". Note 3: Set the corresponding port direction register to "0". Note 4: Set these bits to "0", in timer A1 and A2 mode register of M30623(80-pin package). Figure 1.17.10. Timer Ai mode register in one-shot timer mode 91 Mitsubishi microcomputers M16C / 62T Group Timer A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (4) Pulse width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession. (See Table 1.17.5.) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.17.11 shows the timer Ai mode register in pulse width modulation mode. Figure 1.17.12 shows the example of how a 16-bit pulse width modulator operates. Figure 1.17.13 shows the example of how an 8bit pulse width modulator operates. Table 1.17.5. Timer specifications in pulse width modulation mode Item Specification Count source Count operation f1, f8, f32, fC32 * The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) * The timer reloads a new count at a rising edge of PWM pulse and continues counting * The timer is not affected by a trigger that occurs when counting 16-bit PWM * High level width n / fi n : Set value * Cycle time (216-1) / fi fixed 8-bit PWM * High level width n (m+1) / fi n : values set to timer Ai register's high-order address * Cycle time (28-1) (m+1) / fi m : values set to timer Ai register's low-order address Count start condition * External trigger is input * The timer overflows * The count start flag is set (= 1) Count stop condition * The count start flag is reset (= 0) Interrupt request generation timing PWM pulse goes "L" TAiIN pin function Programmable I/O port or trigger input TAiOUT pin function Pulse output Read from timer When timer Ai register is read, it indicates an indeterminate value Write to timer * When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter * When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Note 1: M30623(80-pin package) does not have I/O pins(TAiIN,TAiOUT) for timer A1 and A2. Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 Address When reset 0016 039616 to 039A16 Bit name Operation mode select bit Function b1 b0 1 1 : PWM mode MR0 1 (Must always be "1" in PWM mode) (Note 3) MR1 External trigger select bit (Note 1) (Note 3) MR2 Trigger select bit 0: Count start flag is valid 1: Selected by event/trigger select register MR3 16/8-bit PWM mode select bit 0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator TCK0 Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 0: Falling edge of TAiIN pin's input signal (Note 2) 1: Rising edge of TAiIN pin's input signal (Note 2) b7 b6 TCK1 AA AA AA A A AA AA AA AA AA R W Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 038216 and 038316). If timer overflow is selected, this bit can be "1" or "0". Note 2: Set the corresponding port direction register to "0". Note 3: Set these bits to "0", in timer A1 and A2 mode register of M30623(80-pin package). Figure 1.17.11. Timer Ai mode register in pulse width modulation mode 92 Mitsubishi microcomputers M16C / 62T Group Timer A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Condition : Reload register = 000316, when external trigger (rising edge of TAiIN pin input signal) is selected 1 / fi X (2 16 - 1) Count source "H" TAiIN pin input signal "L" Trigger is not generated by this signal 1 / fi X n PWM pulse output from TAiOUT pin "H" Timer Ai interrupt request bit "1" "L" "0" fi : Frequency of count source (f1, f8, f32, fC32) Cleared to "0" when interrupt request is accepted, or cleared by software Note 1: M30623(80-pin package) does not have I/O pins(TAiIN,TAiOUT) for timer A1 and A2. Note 2: n = 000016 to FFFE16. Figure 1.17.12. Example of how a 16-bit pulse width modulator operates Condition : Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 External trigger (falling edge of TAiIN pin input signal) is selected 1 / fi X (m + 1) X (2 8 - 1) Count source (Note1) TAiIN pin input signal "H" (Note 3) "L" AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA 1 / fi X (m + 1) "H" Underflow signal of 8-bit prescaler (Note2) "L" 1 / fi X (m + 1) X n "H" PWM pulse output from TAiOUT pin(Note 3) "L" Timer Ai interrupt request bit "1" "0" fi : Frequency of count source (f1, f8, f32, fC32) Cleared to "0" when interrupt request is accepted, or cleaerd by software Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: M30623(80-pin package) does not have no I/O pins(TAiIN,TAiOUT) for timer A1 and A2. Note 4: m = 0016 to FE16; n = 0016 to FE16. Figure 1.17.13. Example of how an 8-bit pulse width modulator operates 93 Mitsubishi microcomputers M16C / 62T Group Timer B SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B Figure 1.17.14 shows the block diagram of timer B. Figures 1.17.15 and 1.17.16 show the timer B-related registers. Use the timer Bi mode register (i = 0 to 2) bits 0 and 1 to choose the desired mode. Timer B has three operation modes listed as follows: * Timer mode: The timer counts an internal count source. * Event counter mode: The timer counts pulses from an external source or a timer overflow. * Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or pulse width. But, M30623(80-pin package), timer B1 has no input pin, so funcs as the internal timer. Data bus high-order bits Data bus low-order bits Clock source selection High-order 8 bits Low-order 8 bits f1 * Timer * Pulse period/pulse width measurement f8 f32 fC32 Counter (16) * Event counter TBi Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 Timer B5 Count start flag Polarity switching and edge pulse TBiIN (i = 0 to 5) Reload register (16) (address 038016) Counter reset circuit Can be selected in only event counter mode TBj overflow (j = i - 1. Note, however, j = 2 when i = 0, j = 5 when i = 3) Address 039116 039016 039316 039216 039516 039416 035116 035016 035316 035216 035516 035416 TBj Timer B2 Timer B0 Timer B1 Timer B5 Timer B3 Timer B4 Note 1: In M30623(80-pin package), do not select the function using TB1IN, because it is not connected to the external pin. Note 2: The TB5IN pin is shared with the TA0IN pin, RxD2, and SCL pin. Figure 1.17.14. Block diagram of timer B Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address TBiMR(i = 0 to 5) 039B16 to 039D16 035B16 to 035D16 Bit symbol TMOD0 Function Bit name Operation mode select bit TMOD1 MR0 When reset 00XX00002 00XX00002 b1 b0 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/pulse width measurement mode (Note 3) 1 1 : Inhibited Function varies with each operation mode MR1 MR2 AA A A A A AA AA A A AA AA R (Note 1) (Note 2) MR3 TCK0 TCK1 Count source select bit (Function varies with each operation mode) Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5. Note 3: In the timer B1 mode register of M30623(80-pin package), do not use this mode, because timer B1 has no input pin. Figure 1.17.15. Timer B-related registers (1) 94 W Mitsubishi microcomputers M16C / 62T Group Timer B SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Symbol TB0 TB1 TB2 TB3 TB4 TB5 Timer Bi register (Note) (b15) b7 (b8) b0 b7 b0 Address 039116, 039016 039316, 039216 039516, 039416 035116, 035016 035316, 035216 035516, 035416 Function When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate AA A A A A Values that can be set * Timer mode Counts the timer's period 000016 to FFFF16 * Event counter mode Counts external pulses input or a timer overflow 000016 to FFFF16 (Note 2) * Pulse period / pulse width measurement mode Measures a pulse period or width (Note 3) RW Note 1: Read and write data in 16-bit units. Note 2: In the timer B1 of M30623(80-pin package), do not select the external pulses input as count source, because timer B1 has no input pin. Note 3: In the timer B1 of M30623(80-pin package), this mode does not function, because timer B1 has no input pin. Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Address 038016 When reset 0016 AAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAA A AA Bit name Bit symbol TA0S Timer A0 count start flag TA1S Timer A1 count start flag TA2S Timer A2 count start flag TA3S Timer A3 count start flag TA4S Timer A4 count start flag TB0S Timer B0 count start flag TB1S Timer B1 count start flag TB2S Timer B2 count start flag Function RW 0 : Stops counting 1 : Starts counting Timer B3, 4, 5 count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TBSR Address 034016 When reset 0016 AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAA A AA Bit symbol Bit name Function RW Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". TB3S Timer B3 count start flag TB4S Timer B4 count start flag TB5S Timer B5 count start flag 0 : Stops counting 1 : Starts counting Clock prescaler reset flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Address 038116 Bit symbol Bit name When reset 0XXXXXXX2 Function R W AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAA Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is "0") Figure 1.17.16. Timer B-related registers (2) 95 Mitsubishi microcomputers M16C / 62T Group Timer B SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 1.17.6.) Figure 1.17.17 shows the timer Bi mode register in timer mode. Table 1.17.6. Timer specifications in timer mode Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request generation timing TBiIN pin function Read from timer Write to timer Specification f1, f8, f32, fC32 * Counts down * When the timer underflows, it reloads the reload register contents before continuing counting 1/(n+1) n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) The timer underflows Programmable I/O port Count value is read out by reading timer Bi register * When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter * When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) Note 1: M30623(80-pin package) does not have the input pin(TB1IN) of timer B1. AA A AA A Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol TBiMR(i=0 to 5) Bit symbol TMOD0 Address 039B16 to 039D16 035B16 to 035D16 Bit name Operation mode select bit TMOD1 MR0 MR1 MR2 When reset 00XX00002 00XX00002 Function b1 b0 0 0 : Timer mode Invalid in timer mode Can be "0" or "1" 0 (Fixed to "0" in timer mode ; i = 0, 3) Nothing is assiigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. MR3 Invalid in timer mode. In an attempt to write to this bit, write "0". The value, if read in timer mode, turns out to be indeterminate. TCK0 Count source select bit TCK1 b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5. Figure 1.17.17. Timer Bi mode register in timer mode 96 AAA AAA AAA AAA AA AAA AAA R (Note 1) (Note 2) W Mitsubishi microcomputers M16C / 62T Group Timer B SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (2) Event counter mode In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.17.7.) Figure 1.17.18 shows the timer Bi mode register in event counter mode. Table 1.17.7. Timer specifications in event counter mode Item Count source Specification * External signals input to TBiIN pin * Effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software Count operation * Counts down * When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer underflows TBiIN pin function Count source input Read from timer Count value can be read out by reading timer Bi register Write to timer * When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter * When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) Note 1: M30623(80-pin package) does not have the input pin(TB1IN) of timer B1. AA AA Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 0 1 Symbol TBiMR(i=0 to 5) Address 039B16 to 039D16 035B16 to 035D16 Bit symbol Bit name TMOD0 Operation mode select bit TMOD1 MR0 Count polarity select bit (Note 1) MR1 MR2 MR3 When reset 00XX00002 00XX00002 Function b1 b0 0 1 : Event counter mode b3 b2 0 0 : Counts external signal's falling edges 0 1 : Counts external signal's rising edges 1 0 : Counts external signal's falling and rising edges 1 1 : Inhibited 0 (Fixed to "0" in event counter mode; i = 0, 3) Nothing is assigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. Invalid in event counter mode. In an attempt to write to this bit, write "0". The value, if read in event counter mode, turns out to be indeterminate. TCK0 Invalid in event counter mode. Can be "0" or "1". TCK1 Event clock select 0 : Input from TBiIN pin (Note 4) 1 : TBj overflow (j = i - 1; however, j = 2 when i = 0, j = 5 when i = 3) A A A A A A AA AA A A A A A AA R W (Note 2) (Note 3) Note 1: Valid only when input from the TBiIN pin is selected as the event clock. If timer's overflow is selected, this bit can be "0" or "1". In timer B1 mode register of M30623(80-pin package), this bit is invalid. Note 2: Timer B0, timer B3. Note 3: Timer B1, timer B2, timer B4, timer B5. Note 4: Set the corresponding port direction register to "0". In M30623(80-pin package), do not use the input from TB1IN pin as event clock, because there is no TB1IN pin. Figure 1.17.18. Timer Bi mode register in event counter mode 97 Mitsubishi microcomputers M16C / 62T Group Timer B SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (3) Pulse period/pulse width measurement mode In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.17.8.) M30623(80-pin package), timer B1 has no input pin, so can not use this function. Figure 1.17.19 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure 1.17.20 shows the operation timing when measuring a pulse period. Figure 1.17.21 shows the operation timing when measuring a pulse width Table 1.17.8. Timer specifications in pulse period/pulse width measurement mode Item Count source Count operation Specification f1, f8, f32, fC32 * Up count * Counter value "000016" is transferred to reload register at measurement pulse's effective edge and the timer continues counting Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing * When measurement pulse's effective edge is input (Note 1) * When an overflow occurs. (Simultaneously, the timer Bi overflow flag changes to "1". The timer Bi overflow flag changes to "0" when the count start flag is "1" and a value is written to the timer Bi mode register.) TBiIN pin function Measurement pulse input Read from timer When timer Bi register is read, it indicates the reload register's content (measurement result) (Note 2) Write to timer Cannot be written to Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting. Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer. Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol TBiMR(i=0 to 5) Bit symbol TMOD0 TMOD1 MR0 Address 039B16 to 039D16 035B16 to 035D16 Function Bit name Operation mode select bit Measurement mode select bit MR1 MR2 When reset 00XX00002 00XX00002 b1 b0 1 0 : Pulse period / pulse width measurement mode b3 b2 Nothing is assigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. Timer Bi overflow flag ( Note 1) TCK0 Count source select bit TCK1 W 0 0 : Pulse period measurement (Interval between measurement pulse's falling edge to falling edge) 0 1 : Pulse period measurement (Interval between measurement pulse's rising edge to rising edge) 1 0 : Pulse width measurement (Interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : Inhibited 0 (Fixed to "0" in pulse period/pulse width measurement mode; i = 0, 3) MR3 A AA A AA AAA AAA AAA AA A AA A AA AAA R 0 : Timer did not overflow 1 : Timer has overflowed b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 (Note 2) (Note 3) Note 1: The timer Bi overflow flag changes to "0" when the count start flag is "1" and a value is written to the timer Bi mode register. This flag cannot be set to "1" by software. Note 2: Timer B0, timer B3. Note 3: Timer B1, timer B2, timer B4, timer B5. Figure 1.17.19. Timer Bi mode register in pulse period/pulse width measurement mode 98 Mitsubishi microcomputers M16C / 62T Group Timer B SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER When measuring measurement pulse time interval from falling edge to falling edge Count source Measurement pulse Reload register transfer timing "H" "L" Transfer (indeterminate value) Transfer (measured value) counter (Note 1) (Note 1) (Note 2) Timing at which counter reaches "000016" "1" Count start flag "0" Timer Bi interrupt request bit "1" Timer Bi overflow flag "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software. "0" Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. Figure 1.17.20. Operation timing when measuring a pulse period Count source Measurement pulse Reload register transfer timing "H" "L" counter Transfer (indeterminate value) (Note 1) Transfer (measured value) Transfer (measured value) (Note 1) (Note 1) Transfer (measured value) (Note 1) (Note 2) Timing at which counter reaches "000016" Count start flag "1" "0" Timer Bi interrupt request bit "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software. Timer Bi overflow flag "1" "0" Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. Figure 1.17.21. Operation timing when measuring a pulse width 99 Mitsubishi microcomputers M16C / 62T Group Timers' functions for three-phase motor control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timers' functions for three-phase motor control Use of more than one built-in timer A and timer B provides the means of outputting three-phase motor driving waveforms. __ ___ In M30623(80-pin package), the pins V, V, W, and W for three-phase motor control have no corresponding external pin. So, do not use this function. Figures 1.18.1 to 1.18.3 show registers related to timers for three-phase motor control. Three-phase PWM control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address When reset INVC0 034816 0016 Bit symbol INV00 Bit name Description R W Effective interrupt output 0: A timer B2 interrupt occurs when the timer A1 reload control signal is "1". polarity select bit 1: A timer B2 interrupt occurs when the timer (Note4) A1 reload control signal is "0". Effective only in three-phase mode 1 INV01 Effective interrupt output 0: Not specified. 1: Selected by the effective interrupt output specification bit polarity selection bit. (Note4) Effective only in three-phase mode 1 INV02 Mode select bit (Note 2) 0: Normal mode 1: Three-phase PWM output mode INV03 Output control bit 0: Output disabled 1: Output enabled INV04 Positive and negative phases concurrent L output disable function enable bit 0: Feature disabled 1: Feature enabled INV05 Positive and negative phases concurrent L output detect flag 0: Not detected yet 1: Already detected INV06 Modulation mode select 0: Triangular wave modulation mode 1: Sawtooth wave modulation mode bit (Note 3) INV07 Software trigger bit (Note 1) 1: Trigger generated The value, when read, is "0". Note 1: No value other than "0" can be written. Note 2: Selecting three-phase PWM output mode causes P80, P81, and P72 through P75 to output U, U, V, V, W, and W, and works the timer for setting short circuit prevention time, the U, V, W phase output control circuits, and the circuit for setting timer B2 interrupt frequency. Note 3: In triangular wave modulation mode: The short circuit prevention timer starts in synchronization with the falling edge of timer Ai output. The data transfer from the three-phase buffer register to the three-phase output shift register is made only once in synchronization with the transfer trigger signal after writing to the three-phase output buffer register. In sawtooth wave modulation mode: The short circuit prevention timer starts in synchronization with the falling edge of timer A output and with the transfer trigger signal. The data transfer from the three-phase output buffer register to the three-phase output shift register is made with respect to every transfer trigger. Note 4: To write "1" both to bit 0 (INV00) and bit 1 (INV01) of the three-phase PWM control register, set in advance the content of the timer B2 interrupt occurrences frequency set counter. Three-phase PWM control register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol Address When reset INVC1 034916 0016 Bit symbol Bit name Description INV10 Timer Ai start trigger signal select bit 0: Timer B2 overflow signal 1: Timer B2 overflow signal, signal for writing to timer B2 INV11 Timer A1-1, A2-1, A4-1 control bit 0: Three-phase mode 0 1: Three-phase mode 1 INV12 Short circuit timer count source select bit 0 : Not to be used 1 : f1/2 Noting is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be "0". Reserved bit Always set to "0" Noting is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". Note 1: To use three-phase PWM output mode, write "1" to INV12. Figure1.18.1. Registers related to timers for three-phase motor control 100 R W Mitsubishi microcomputers M16C / 62T Group Timers' functions for three-phase motor control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Three-phase output buffer register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol IDB0 Address 034A16 When reset 0016 Bit Symbol Bit name Function DU0 U phase output buffer 0 Setting in U phase output buffer 0 DUB0 U phase output buffer 0 Setting in U phase output buffer 0 DV0 V phase output buffer 0 Setting in V phase output buffer 0 DVB0 V phase output buffer 0 Setting in V phase output buffer 0 DW0 W phase output buffer 0 Setting in W phase output buffer 0 DWB0 W phase output buffer 0 Setting in W phase output buffer 0 R W Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". Note: When executing read instruction of this register, the contents of three-phase shift register is read out. Three-phase output buffer register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol IDB1 Address 034B16 When reset 0016 Bit Symbol Bit name DU1 U phase output buffer 1 Setting in U phase output buffer 1 Function DUB1 U phase output buffer 1 Setting in U phase output buffer 1 DV1 V phase output buffer 1 Setting in V phase output buffer 1 DVB1 V phase output buffer 1 Setting in V phase output buffer 1 DW1 W phase output buffer 1 Setting in W phase output buffer 1 DWB1 W phase output buffer 1 Setting in W phase output buffer 1 R W Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". Note: When executing read instruction of this register, the contents of three-phase shift register is read out. Dead time timer b7 b0 Symbol DTT Address 034C16 Function When reset Indeterminate Values that can be set Set dead time timer R W 1 to 255 Timer B2 interrupt occurrences frequency set counter b3 b0 Symbol ICTB2 Address 034D16 Function Set occurrence frequency of timer B2 interrupt request When reset Indeterminate Values that can be set R W 1 to 15 Note1: In setting 1 to bit 1 (INV01) - the effective interrupt output specification bit - of threephase PWM control register 0, do not change the B2 interrupt occurrences frequency set counter to deal with the timer function for three-phase motor control. Note2: Do not write at the timing of an overflow occurrence in timer B2. Figure 1.18.2. Registers related to timers for three-phase motor control 101 Mitsubishi microcomputers M16C / 62T Group Timers' functions for three-phase motor control Timer Ai register (Note) (b15) b7 (b8) b0 b7 b0 Symbol TA1 TA2 TA4 TB2 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Address 038916,038816 038B16,038A16 038F16,038E16 039516,039416 When reset Indeterminate Indeterminate Indeterminate Indeterminate Function Values that can be set * Timer mode Counts an internal count source 000016 to FFFF16 * One-shot timer mode Counts a one shot width 000016 to FFFF16 Note: Read and write data in 16-bit units. A A R W Timer Ai-1 register (Note) (b15) b7 (b8) b0 b7 b0 Symbol TA11 TA21 TA41 Address 034316,034216 034516,034416 034716,034616 Function When reset Indeterminate Indeterminate Indeterminate Values that can be set Counts an internal count source 000016 to FFFF16 Note: Read and write data in 16-bit units. A R W Trigger select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRGSR Address 038316 Bit symbol TA1TGL Bit name Timer A1 event/trigger select bit TA1TGH TA2TGL Timer A2 event/trigger select bit TA2TGH TA3TGL Timer A3 event/trigger select bit TA3TGH TA4TGL When reset 0016 Timer A4 event/trigger select bit TA4TGH Function 0 0 : Input on TA1IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected b3 b2 0 0 : Input on TA2IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected b5 b4 0 0 : Input on TA3IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected b7 b6 0 0 : Input on TA4IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected Note: Set the corresponding port direction register to "0". A A A A A A A AA A AA A AA A AA AA AA R W b1 b0 Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Address 038016 When reset 0016 A A A AA A A A AA AAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAA AA AA Bit symbol Bit name TA0S Timer A0 count start flag TA1S Timer A1 count start flag TA2S Timer A2 count start flag TA3S Timer A3 count start flag TA4S Timer A4 count start flag TB0S Timer B0 count start flag TB1S Timer B1 count start flag TB2S Timer B2 count start flag Function 0 : Stops counting 1 : Starts counting Figure 1.18.3. Registers related to timers for three-phase motor control 102 R W Mitsubishi microcomputers M16C / 62T Group Timers' functions for three-phase motor control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Three-phase motor driving waveform output mode (three-phase waveform mode) Setting "1" in the mode select bit (bit 2 at 034816) shown in Figure 1.18.1 - causes three-phase waveform mode that uses four timers A1, A2, A4, and B2 to be selected. As shown in Figure 1.18.4, set timers A1, A2, and A4 in one-shot timer mode, set the trigger in timer B2, and set timer B2 in timer mode using the respective timer mode registers. Timer Ai mode register Symbol TA1MR TA2MR TA3MR b7 b6 b5 b4 b3 b2 b1 b0 0 1 1 0 Bit symbol TMOD0 Address 039716 039816 039A16 When reset 0016 0016 0016 A A AA AA AA AA AA AA AA RW b1 b0 MR0 Pulse output function select bit 0 (Must always be "0" in three-phase PWM output mode) MR1 External trigger select bit Invalid in three-phase PWM output mode Can be "0" or "1" MR2 Trigger select bit 1 : Selected by event/trigger select register MR3 0 (Must always be "0" in one-shot timer mode) TCK0 Count source select bit TMOD1 TCK1 AA Function Bit name Operation mode select bit 1 0 : One-shot timer mode b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Timer B2 mode register b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 Symbol TB2MR Address 039D16 Bit symbol Bit name TMOD0 Operation mode select bit TMOD1 MR0 When reset 00XX00002 Function b1 b0 0 0 : Timer mode MR1 Invalid in timer mode Can be "0" or "1" MR2 0 (Fixed to "0" in timer mode ; i = 0) MR3 Invalid in timer mode. This bit can neither be set nor reset. When read in timer mode, its content is indeterminate. TCK0 Count source select bit TCK1 b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 AA AA AAA A AAA AA RW Figure 1.18.4. Timer mode registers in three-phase waveform mode 103 Mitsubishi microcomputers M16C / 62T Group Timers' functions for three-phase motor control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.18.5 shows the block diagram for three-phase waveform mode. In three-phase waveform mode, ___ ___ the positive-phase waveforms (U phase, V phase, and W phase) and negative waveforms (U phase, V ___ phase, and W phase), six waveforms in total, are output from P80,P81, P72, P73, P7 4, and P75 as active ___ on the "L" level. Of the timers used in this mode, timer A4 controls the U phase and U phase, timer A1 ___ ___ controls the V phase and V phase, and timer A2 controls the W phase and W phase respectively; timer B2 controls the periods of one-shot pulse output from timers A4, A1, and A2. In outputting a waveform, dead time can be set so as to cause the "L" level of the positive waveform ___ output (U phase, V phase, and W phase) not to lap over the "L" level of the negative waveform output (U ___ ___ phase, V phase, and W phase). To set short circuit time, use three 8-bit timers sharing the reload register for setting dead time. A value from 1 through 255 can be set as the count of the timer for setting dead time. The timer for setting dead time works as a one-shot timer. If a value is written to the dead timer (034C16), the value is written to the reload register shared by the three timers for setting dead time. Any of the timers for setting dead time takes the value of the reload register into its counter, if a start trigger comes from its corresponding timer, and performs a down count in line with the clock source selected by the dead time timer count source select bit (bit 2 at 0349 16). The timer can receive another trigger again before the workings due to the previous trigger are completed. In this instance, the timer performs a down count from the reload register's content after its transfer, provoked by the trigger, to the timer for setting dead time. Since the timer for setting dead time works as a one-shot timer, it starts outputting pulses if a trigger comes; it stops outputting pulses as soon as its content becomes 00 16, and waits for the next trigger to come. ___ ___ The positive waveforms (U phase, V phase, and W phase) and the negative waveforms (U phase, V ___ phase, and W phase) in three-phase waveform mode are output from respective ports by means of setting "1" in the output control bit (bit 3 at 0348 16). Setting "0" in this bit causes the ports to be the state of set by port direction register. This bit can be set to "0" not only by use of the applicable instruction, but _______ by entering a falling edge in the NMI terminal or by resetting. Also, if "1" is set in the positive and negative phases concurrent L output disable function enable bit (bit 4 at 0348 16) causes one of the pairs of U ___ ___ ___ phase and U phase, V phase and V phase, and W phase and W phase concurrently go to "L", as a result, the port become the state of set by port direction register. 104 (Timer mode) Timer B2 Timer A4-1 T Q INV11 (One-shot timer mode) Timer A4 counter Reload Timer A1-1 (One-shot timer mode) Timer A1 counter Reload Timer A2 counter Reload Timer A2-1 1 INV06 INV06 Note: To use three-phase output mode, write "1" to INV12. (One-shot timer mode) INV11 T Q To be set to "0" when timer A2 stops Trigger Timer A2 1/2 Trigger signal for transfer INV06 f1 A T Q T Q T Q D Q For short circuit prevention V phase output signal V phase output signal W phase output signal W phase output signal n = 1 to 255 Dead time timer setting (8) U phase output control circuit Trigger Trigger U phase output signal Three-phase output shift register (U phase) INV05 INV04 RESET NMI R INV03 D Q W(P75) W(P74) V(P73) V(P72) U(P81) U(P80) Diagram for switching to P80, P81, and to P72 - P75 is not shown. T D Q D Q T D Q T D Q T T D Q D Q T Interrupt request bit U phase output signal Dead time timer setting (8) n = 1 to 255 T DUB0 D DU0 V phase output control circuit Trigger Trigger D DUB1 D DU1 Bit 0 at 034B16 Bit 0 at 034A16 Dead time timer setting n = 1 to 255 n = 1 to 255 Reload register Interrupt occurrence frequency set counter n = 1 to 15 U phase output control circuit Trigger Trigger INV12 (Note) 0 1 Circuit foriInterrupt occurrence frequency set counter Timers' functions for three-phase motor control INV11 T Q To be set to "0" when timer A1 stops Trigger Timer A1 To be set to "0" when timer A4 stops Trigger Timer A4 INV07 INV00 Control signal for timer A4 reload Trigger signal for timer Ai start Signal to be written to B2 INV10 Overflow INV01 INV11 Mitsubishi microcomputers SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER M16C / 62T Group Figure 1.18.5. Block diagram for three-phase waveform mode 105 Mitsubishi microcomputers M16C / 62T Group Timers' functions for three-phase motor control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Triangular wave modulation To generate a PWM waveform of triangular wave modulation, set "0" in the modulation mode select bit (bit 6 at 034816). Also, set "1" in the timers A4-1, A1-1, A2-1 control bit (bit 1 at 034916). In this mode, each of timers A4, A1, and A2 has two timer registers, and alternately reloads the timer register's content to the counter every time timer B2 counter's content becomes 0000 16. If "1" is set to the effective interrupt output specification bit (bit 1 at 034816), the frequency of interrupt requests that occur every time the timer B2 counter's value becomes 000016 can be set by use of the timer B2 counter (034D16) for setting the frequency of interrupt occurrences. The frequency of occurrences is given by (setting; setting 0). Setting "1" in the effective interrupt output specification bit (bit 1 at 034816) provides the means to choose which value of the timer A1 reload control signal to use, "0" or "1", to cause timer B2's interrupt request to occur. To make this selection, use the effective interrupt output polarity selection bit (bit 0 at 0348 16). An example of U phase waveform is shown in Figure 1.18.6, and the description of waveform output workings is given below. Set "1" in DU0 (bit 0 at 034A 16). And set "0" in DUB0 (bit 1 at 034A 16). In addition, set "0" in DU1 (bit 0 at 034B 16) and set "1" in DUB1 (bit 1 at 034B16). Also, set "0" in the effective interrupt output specification bit (bit 1 at 0348 16) to set a value in the timer B2 interrupt occurrence frequency set counter. By this setting, a timer B2 interrupt occurs when the timer B2 counter's content becomes 000016 as many as (setting) times. Furthermore, set "1" in the effective interrupt output specification bit (bit 1 at 0348 16), set in the effective interrupt polarity select bit (bit 0 at 034816) and set "1" in the interrupt occurrence frequency set counter(034D16). These settings cause a timer B2 interrupt to occur every other interval when the U phase output goes to "H". When the timer B2 counter's content becomes 000016, timer A4 starts outputting one-shot pulses. In this instance, the content of DU1 (bit 0 at 034B 16) and that of DU0 (bit 0 at 034A 16) are set in the three-phase output shift register (U phase), the content of DUB1 (bit 1 at 034B16) and that of DUB0 (bit 1 at 034A16) ___ are set in the three-phase shift register (U phase). After triangular wave modulation mode is selected, however, no setting is made in the shift register even though the timer B2 counter's content becomes 000016. ___ The value of DU0 and that of DUB0 are output to the U terminal (P8 0) and to the U terminal (P81 ) respectively. When the timer A4 counter counts the value written to timer A4 (038F 16, 038E 16) and when timer A4 finishes outputting one-shot pulses, the three-phase shift register's content is shifted one posi___ tion, and the value of DU1 and that of DUB1 are output to the U phase output signal and to U phase output signal respectively. At this time, one-shot pulses are output from the timer for setting dead time used for ___ setting the time over which the "L" level of the U phase waveform does not lap over the "L" level of the U phase waveform, which has the opposite phase of the former. The U phase waveform output that started from the "H" level keeps its level until the timer for setting dead time finishes outputting one-shot pulses even though the three-phase output shift register's content changes from "1" to "0" by the effect of the one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses, "0" already shifted in the three-phase shift register goes effective, and the U phase waveform changes to the "L" level. When the timer B2 counter's content becomes 000016, the timer A4 counter starts counting the value written to timer A4-1 (0347 16, 034616), and starts outputting one-shot pulses. When timer A4 finishes outputting one-shot pulses, the three-phase shift register's content is shifted one position, but if the three-phase output shift register's content changes from "0" to "1" as a result of the shift, the output level changes from "L" to "H" without waiting for the timer for setting dead time to finish outputting one-shot pulses. A U phase waveform is generated by these workings repeatedly. With the exception that the three-phase output shift register on the U phase side is used, the workings in generating a U phase waveform, which has the opposite phase of the U phase waveform, are the same as in generating a U 106 Mitsubishi microcomputers M16C / 62T Group Timers' functions for three-phase motor control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER phase waveform. In this way, a waveform can be picked up from the applicable terminal in a manner in which the "L" level of the U phase waveform doesn't lap over that of the U phase waveform, which has the opposite phase of the U phase waveform. The width of the "L" level too can be adjusted by varying the ___ ___ values of timer B2, timer A4, and timer A4-1. In dealing with the V and W phases, and V and W phases, the latter are of opposite phase of the former, have the corresponding timers work similarly to dealing with ___ the U and U phases to generate an intended waveform. A carrier wave of triangular waveform Carrier wave Signal wave B2 Timber B2 interrupt occurres Rewriting timer A4 and timer A4-1. Possible to set the number of overflows to generate an interrupt by use of the interrupt occurrences frequency set circuit Trigger signal for timer Ai start (timer B2 overflow signal) Timer A4 output m n m n m p Control signal for timer A4 reload o The three-phase shift register shifts in synchronization with the falling edge of the A4 output. U phase output signal U phase output signal U phase U phase Dead time Note: Set to triangular wave modulation mode and to three-phase mode 1. Figure 1.18.6. Timing chart of operation (1) 107 Mitsubishi microcomputers M16C / 62T Group Timers' functions for three-phase motor control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Assigning certain values to DU0 (bit 0 at 034A16) and DUB0 (bit 1 at 034A16), and to DU1 (bit 0 at 034B16) and DUB1 (bit 1 at 034B16) allows the user to output the waveforms as shown in Figure 1.18.7, that is, to ___ ___ output the U phase alone, to fix U phase to "H", to fix the U phase to "H," or to output the U phase alone. A carrier wave of triangular waveform Carrier wave Signal wave Timer B2 Rewriting timer A4 every timer B2 interrupt occurres. Timer B2 interrupt occurres. Rewriting three-phase buffer register. Trigger signal for timer Ai start (timer B2 overflow signal) Timer A4 output m n m n m p Control signal for timer A4 reload U phase output signal U phase output signal U phase U phase Dead time Note: Set to triangular wave modulation mode and to three-phase mode 0. Figure 1.18.7. Timing chart of operation (2) 108 o Mitsubishi microcomputers M16C / 62T Group Timers' functions for three-phase motor control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Sawtooth modulation To generate a PWM waveform of sawtooth wave modulation, set "1" in the modulation mode select bit (bit 6 at 034816). Also, set "0" in the timers A4-1, A1-1, and A2-1 control bit (bit 1 at 034916). In this mode, the timer registers of timers A4, A1, and A2 comprise conventional timers A4, A1, and A2 alone, and reload the corresponding timer register's content to the counter every time the timer B2 counter's content becomes 000016. The effective interrupt output specification bit (bit 1 at 034816) and the effective interrupt output polarity select bit (bit 0 at 0348 16) go nullified. An example of U phase waveform is shown in Figure 75, and the description of waveform output workings is given below. Set "1" in DU0 (bit 0 at 034A16), and set "0" in DUB0 (bit 1 at 034A16). In addition, set "0" in DU1 (bit 0 at 034A16) and set "1" in DUB1 (bit 1 at 034A16). When the timber B2 counter's content becomes 0000 16, timer B2 generates an interrupt, and timer A4 starts outputting one-shot pulses at the same time. In this instance, the contents of the three-phase buffer registers DU1 and DU0 are set in the three-phase output shift register (U phase), and the contents of DUB1 and DUB0 are set in the three-phase output register (U phase). After this, the three-phase buffer register's content is set in the three-phase shift register every time the timer B2 counter's content becomes 000016. ___ The value of DU0 and that of DUB0 are output to the U terminal (P80 ) and to the U terminal (P81) respectively. When the timer A4 counter counts the value written to timer A4 (038F16, 038E16) and when timer A4 finishes outputting one-shot pulses, the three-phase output shift register's content is shifted one ___ position, and the value of DU1 and that of DUB1 are output to the U phase output signal and to the U output signal respectively. At this time, one-shot pulses are output from the timer for setting dead time used for setting the time over which the "L" level of the U phase waveform doesn't lap over the "L" level of ___ the U phase waveform, which has the opposite phase of the former. The U phase waveform output that started from the "H" level keeps its level until the timer for setting dead time finishes outputting one-shot pulses even though the three-phase output shift register's content changes from "1" to "0 "by the effect of the one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses, 0 already shifted in the three-phase shift register goes effective, and the U phase waveform changes to the "L" level. When the timer B2 counter's content becomes 000016 , the contents of the three-phase buffer registers DU1 and DU0 are set in the three-phase shift register (U phase), and the contents of DUB1 and ___ DUB0 are set in the three-phase shift register (U phase) again. A U phase waveform is generated by these workings repeatedly. With the exception that the three-phase ___ ___ output shift register on the U phase side is used, the workings in generating a U phase waveform, which has the opposite phase of the U phase waveform, are the same as in generating a U phase waveform. In this way, a waveform can be picked up from the applicable terminal in a manner in which the "L" level of the U phase waveform doesn't lap over that of the U phase waveform, which has the opposite phase of the U phase waveform. The width of the "L" level too can be adjusted by varying the values of timer B2 ___ ___ and timer A4. In dealing with the V and W phases, and V and W phases, the latter are of opposite phase ___ of the former, have the corresponding timers work similarly to dealing with the U and U phases to generate an intended waveform. ___ Setting "1" both in DUB0 and in DUB1 provides a means to output the U phase alone and to fix the U phase output to "H" as shown in Figure 1.18.8. 109 Mitsubishi microcomputers M16C / 62T Group Timers' functions for three-phase motor control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A carrier wave of sawtooth waveform Carrier wave Signal wave Timer B2 Interrupt occurres. Rewriting the value of timer A4. Trigger signal for timer Ai start (timer B2 overflow signal) Timer A4 output m n Data transfer is made from the threephase buffer register to the threephase shift register in step with the timing of the timer B overflow. o U phase output signal U phase output signal U phase U phase Dead time Note: Set to sawtooth modulation mode and to three-phase mode 0. Figure 1.18.8. Timing chart of operation (3) 110 p The three-phase shift register shifts in synchronization with the falling edge of timer A4. Mitsubishi microcomputers M16C / 62T Group Timers' functions for three-phase motor control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A carrier wave of sawtooth waveform Carrier wave Signal wave Timer B2 Interrupt occurres. Rewriting the value of timer A4. Trigger signal for timer Ai start (timer B2 overflow signal) Timer A4 output Interrupt occurres. Rewriting the value of timer A4. Rewriting three-phase output buffer register m n Data transfer is made from the threephase buffer register to the threephase shift register in step with the timing of the timer B overflow. p The three-phase shift register shifts in synchronization with the falling edge of timer A4. U phase output signal U phase output signal U phase U phase Dead time Note: Set to sawtooth modulation mode and to three-phase mode 0. Figure 1.18.9. Timing chart of operation (4) 111 Mitsubishi microcomputers M16C / 62T Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O Serial I/O is configured as five channels: UART0, UART1, UART2, S I/O3 and S I/O4. UART0 to 2 UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 1.19.1 shows the block diagram of UART0, UART1 and UART2. Figures 1.19.2 and 1.19.3 show the block diagram of the transmit/receive unit. UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 03A0 16, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART. Although a few functions are different, UART0, UART1 and UART2 have almost the same functions. UART0 through UART2 are almost equal in their functions with minor exceptions. UART2, in particular, is compliant with the SIM interface with some extra settings added in clock-asynchronous serial I/O mode (Note). It also has the bus collision detection function that generates an interrupt request if the TxD pin and the RxD pin are different in level. In M30623(80-pin package), UART2 has the clock-asynchronous serial I/O mode and IIC mode. Table 1.19.1 shows the comparison of functions of UART0 through UART2, and Figures 1.19.4 to 1.19.8 show the registers related to UARTi. Note: SIM : Subscriber Identity Module Table 1.19.1. Comparison of functions of UART0 through UART2 UART1 M30622 (100pin-package) M30623 (80pin-package) CLK polarity selection Possible (Note 1) Possible (Note 1) Possible (Note 1) Impossible (Note 5) LSB first / MSB first selection Possible (Note 1) Possible (Note 1) Possible (Note 2) Continuous receive mode selection Possible (Note 1) Possible (Note 1) Possible (Note 1) Transfer clock output from multiple pins selection Impossible Possible Impossible Separate CTS/RTS pins Possible Impossible Impossible Serial data logic switch Impossible Impossible Possible Sleep mode selection Possible (Note 3) Possible TxD, RxD I/O polarity switch Impossible Impossible Possible TxD, RxD port output format CMOS output CMOS output N-channel open-drain output (Note 6) Parity error signal output Impossible Impossible Possible (Note 4) Bus collision detection Impossible Impossible Possible (Note 7) Note Note Note Note Note Note Note 112 UART2 UART0 Function 1: 2: 3: 4: 5: 6: 7: (Note 1) (Note 3) (Note 4) Impossible Only when clock synchronous serial I/O mode. Only when clock synchronous serial I/O mode and 8-bit UART mode. Only when UART mode. Using for SIM interface. In M30623(80-pin package), do not use this function, because CLK2 and CTS2/RTS2 have no external pin. Connect via pull-up resistor to VCC outside. Generally, it use in case of IE bus-emulation. Mitsubishi microcomputers M16C / 62T Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (UART0) RxD0 TxD0 UART reception 1/16 Clock source selection Reception control circuit Clock synchronous type Bit rate generator Internal (address 03A116) f1 f8 f32 1 / (n0+1) UART transmission 1/16 Transmission control circuit Clock synchronous type External Receive clock Transmit/ receive unit Transmit clock Clock synchronous type (when internal clock is selected) 1/2 Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) CLK polarity reversing circuit CLK0 CTS/RTS disabled CTS/RTS selected RTS0 CTS0 / RTS0 Vcc CTS/RTS disabled CTS0 CTS/RTS separated CTS0 from UART1 (UART1) RxD1 TxD1 1/16 Clock source selection Bit rate generator Internal (address 03A916) f1 f8 f32 UART reception 1 / (n1+1) UART transmission 1/16 CTS1 / RTS1 / CTS0 / CLKS1 Clock synchronous type (when internal clock is selected) Transmit clock Clock synchronous type (when external clock is selected) CTS/RTS disabled CTS/RTS separated Clock output pin select switch Transmit/ receive unit (when internal clock is selected) 1/2 CLK1 Transmission control circuit Clock synchronous type Clock synchronous type External CLK polarity reversing circuit Reception control circuit Clock synchronous type Receive clock RTS1 VCC CTS/RTS disabled CTS0 CTS1 CTS0 to UART0 (UART2) TxD polarity reversing circuit RxD polarity reversing circuit RxD2 UART reception 1/16 Clock source selection Bit rate generator Internal (address 037916) f1 f8 f32 1 / (n2+1) Clock synchronous type UART transmission 1/16 Clock synchronous type External Reception control circuit Transmission control circuit Receive clock TxD2 Transmit/ receive unit Transmit clock Clock synchronous type 1/2 CLK2 CLK polarity reversing circuit (when internal clock is selected) Clock synchronous type (when internal clock is selected) CTS/RTS selected Clock synchronous type (when external clock is selected) CTS/RTS disabled RTS2 CTS2 / RTS2 Vcc CTS/RTS disabled CTS2 n0 : Values set to UART0 bit rate generator (BRG0) n1 : Values set to UART1 bit rate generator (BRG1) n2 : Values set to UART2 bit rate generator (BRG2) Note 1: In M30623(80-pin package), CLK2 and CTS2/RTS2 have no external pin. Note 2: In M30623(80-pin package), do not use UART2 as clock synchronous serial I/O. Figure 1.19.1. Block diagram of UARTi (i = 0 to 2) 113 Mitsubishi microcomputers M16C / 62T Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous type PAR disabled 1SP RxDi SP SP UART (7 bits) UART (8 bits) Clock synchronous type UARTi receive register UART (7 bits) PAR 2SP PAR enabled UART UART (9 bits) Clock synchronous type UART (8 bits) UART (9 bits) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UARTi receive buffer register Address 03A616 Address 03A716 Address 03AE16 Address 03AF16 MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits MSB/LSB conversion circuit D7 D8 D6 D5 D4 D3 D2 D1 UART (9 bits) 2SP SP SP Clock synchronous type UART TxDi PAR 1SP PAR disabled "0" Clock synchronous type UART (7 bits) UARTi transmit register UART (7 bits) UART (8 bits) Clock synchronous type Figure 1.19.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit 114 UARTi transmit buffer register Address 03A216 Address 03A316 Address 03AA16 Address 03AB16 UART (8 bits) UART (9 bits) PAR enabled D0 SP: Stop bit PAR: Parity bit Mitsubishi microcomputers M16C / 62T Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER No reverse RxD data reverse circuit RxD2 Reverse Clock synchronous type PAR disabled 1SP SP SP UART2 receive register UART(7 bits) PAR 2SP PAR enabled 0 UART (7 bits) UART (8 bits) Clock synchronous type 0 0 0 UART 0 Clock synchronous type UART (9 bits) 0 0 UART (8 bits) UART (9 bits) D8 D0 UART2 receive buffer register Logic reverse circuit + MSB/LSB conversion circuit Address 037E16 Address 037F16 D7 D6 D5 D4 D3 D2 D1 Data bus high-order bits Data bus low-order bits Logic reverse circuit + MSB/LSB conversion circuit D7 D8 D6 D5 D4 D3 D2 D1 D0 UART2 transmit buffer register Address 037A16 Address 037B16 UART (8 bits) UART (9 bits) PAR enabled 2SP SP SP UART (9 bits) Clock synchronous type UART PAR 1SP PAR disabled "0" Clock synchronous type UART (7 bits) UART (8 bits) UART2 transmit register UART(7 bits) Clock synchronous type Error signal output disable No reverse TxD data reverse circuit Error signal output circuit Error signal output enable TxD2 Reverse SP: Stop bit PAR: Parity bit Note 1: In M30623(80-pin package), do not use UART2 as clock synchronous serial I/O. Figure 1.19.3. Block diagram of UART2 transmit/receive unit 115 Mitsubishi microcomputers M16C / 62T Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit buffer register (b15) b7 (b8) b0 b7 b0 Symbol U0TB U1TB U2TB Address 03A3 16, 03A2 16 03AB 16, 03AA 16 037B 16, 037A 16 When reset Indeterminate Indeterminate Indeterminate Function R W Transmit data Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turn out to be indeterminate. UARTi receive buffer register (b15) b7 (b8) b0 b7 b0 Symbol U0RB U1RB U2RB Bit symbol Address 03A716, 03A6 16 03AF16, 03AE 16 037F16, 037E 16 When reset Indeterminate Indeterminate Indeterminate Function (During clock synchronous serial I/O mode) Bit name Receive data Function (During UART mode) R W Receive data Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". ABT Arbitration lost detecting flag (Note 2) 0 : Not detected 1 : Detected Invalid OER Overrun error flag (Note 1) 0 : No overrun error 1 : Overrun error found 0 : No overrun error 1 : Overrun error found FER Framing error flag (Note 1) Invalid PER Parity error flag (Note 1) Invalid 0 : No parity error 1 : Parity error found SUM Error sum flag (Note 1) Invalid 0 : No error 1 : Error found 0 : No framing error 1 : Framing error found Note 1: Bits 15 through 12 are set to "0" when the serial I/O mode select bit (bits 2 to 0 at addresses 03A0 16, 03A816 and 0378 16) are set to "000 2" or the receive enable bit is set to "0". (Bit 15 is set to "0" when bits 14 to 12 all are set to "0".) Bits 14 and 13 are also set to "0" when the lower byte of the UARTi receive buffer register (addresses 03A6 16, 03AE 16 and 037E 16) is read out. Note 2: Arbitration lost detecting flag is allocated to U2RB and noting but "0" may be written. Nothing is assigned in bit 11 of U0RB and U1RB. These bits can neither be set or reset. When read, the value of this bit is "0". UARTi bit rate generator b7 b0 Symbol U0BRG U1BRG U2BRG Address 03A1 16 03A9 16 0379 16 When reset Indeterminate Indeterminate Indeterminate Function Assuming that set value = n, BRGi divides the count source by n+1 Figure 1.19.4. Serial I/O-related registers (1) 116 Values that can be set 0016 to FF16 R W Mitsubishi microcomputers M16C / 62T Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 Symbol UiMR(i=0,1) b0 Address 03A016, 03A816 When reset 0016 Function (During clock synchronous serial I/O mode) Bit symbol Bit name SMD0 Serial I/O mode select bit Must be fixed to 001 b2 b1 b0 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited SMD1 SMD2 Function (During UART mode) b2 b1 b0 AA A A AA AA AA AA AA AA AA AA R W 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited CKDIR Internal/external clock select bit 0 : Internal clock 1 : External clock 0 : Internal clock 1 : External clock STPS Stop bit length select bit Invalid 0 : One stop bit 1 : Two stop bits PRY Odd/even parity select bit Invalid PRYE Parity enable bit Invalid 0 : Parity disabled 1 : Parity enabled SLEP Sleep select bit Must always be "0" 0 : Sleep mode deselected 1 : Sleep mode selected Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity UART2 transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 Symbol U2MR b0 Address 037816 Bit symbol Bit name SMD0 Serial I/O mode select bit When reset 0016 Function (Note 2) (During clock synchronous serial I/O mode) Must be fixed to 001 b2 b1 b0 0 0 0 : Serial I/O invalid 0 1 0 : (Note) 0 1 1 : Inhibited 1 1 1 : Inhibited SMD1 SMD2 Function (During UART mode) b2 b1 b0 AA AA AA AA AA AA AA A A AA AA R W 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited CKDIR Internal/external clock select bit 0 : Internal clock 1 : External clock Must always be fixed to "1" STPS Stop bit length select bit Invalid 0 : One stop bit 1 : Two stop bits PRY Odd/even parity select bit Invalid Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity PRYE Parity enable bit Invalid 0 : Parity disabled 1 : Parity enabled IOPOL TxD, RxD I/O polarity reverse bit 0 : No reverse 1 : Reverse Usually set to "0" 0 : No reverse 1 : Reverse Usually set to "0" Note 1: Bit 2 to bit 0 are set to "0102" when IIC mode is used. Note 2: In M30623(80-pin package), do not use UART2 as clock synchronous serial I/O. Figure 1.19.5. Serial I/O-related registers (2) 117 Mitsubishi microcomputers M16C / 62T Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiC0(i=0,1) Bit symbol CLK0 Address When reset 0816 03A416, 03AC16 Function (During clock synchronous serial I/O mode) Bit name b1 b0 BRG count source select bit CLK1 CRS TXEPT CTS/RTS function select bit Function (During UART mode) b1 b0 R W AA A AA A AAA AA AA A AAA AA A AAA AA A AAA 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited Valid when bit 4 = "0" Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 : Data present in transmit 0 : Data present in transmit register Transmit register empty register (during transmission) (during transmission) flag 1 : No data present in transmit 1 : No data present in transmit register (transmission completed) register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) CRD CTS/RTS disable bit 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) NCH Data output select bit 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output CKPOL CLK polarity select bit 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge Must always be "0" UFORM Transfer format select bit 0 : LSB first 1 : MSB first Must always be "0" Note 1: Set the corresponding port direction register to "0". Note 2: The settings of the corresponding port register and port direction register are invalid. UART2 transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2C0 Bit symbol CLK0 Address 037C16 Bit name BRG count source select bit CLK1 CRS TXEPT CTS/RTS function select bit (Note 4) When reset 0816 Function (Note 5) (During clock synchronous serial I/O mode) b1 b0 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited Valid when bit 4 = "0" Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 : Data present in transmit 0 : Data present in transmit register Transmit register empty register (during transmission) (during transmission) flag 1 : No data present in transmit 1 : No data present in transmit CTS/RTS disable bit (Note 4) Nothing is assigned. register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) 0 : TXDi pin is CMOS output 0: TXDi pin is CMOS output : TXDi pinvalue, is N-channel 1: TXDi is N-channel In an attempt to write to this bit, write1"0". The if read, turns out to bepin"0". CKPOL R W AA A AA A AAA AA AAA AA A AA A AA A AAA b1 b0 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited register (transmission completed) CRD Function (During UART mode) CLK polarity select bit (Note 4) open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge UFORM Transfer format select bit 0 : LSB first 1 : MSB first (Note 3) open-drain output Must always be "0" 0 : LSB first 1 : MSB first Note 1: Set the corresponding port direction register to "0". Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid. Note 4: In M30623(80-pin package), these bits are invalid, because CLK2 and CTS2/RTS2 have no external pin. Note 5: In M30623(80-pin package), do not use UART2 as clock synchronous serial I/O. Figure 1.19.6. Serial I/O-related registers (3) 118 Mitsubishi microcomputers M16C / 62T Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 Symbol UiC1(i=0,1) b0 Bit symbol Address 03A516,03AD16 When reset 0216 Function (During clock synchronous serial I/O mode) Bit name Function (During UART mode) R W AA A AA AA A AA TE Transmit enable bit 0 : Transmission disabled 1 : Transmission enabled 0 : Transmission disabled 1 : Transmission enabled TI Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register RE Receive enable bit 0 : Reception disabled 1 : Reception enabled 0 : Reception disabled 1 : Reception enabled RI Receive complete flag 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". UART2 transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 Symbol U2C1 b0 Bit symbol Address 037D16 Bit name When reset 0216 Function (Note 1) (During clock synchronous serial I/O mode) Function (During UART mode) AA A AA AA A AA A AA AA A AA A AA A AA A AA A TE Transmit enable bit 0 : Transmission disabled 1 : Transmission enabled 0 : Transmission disabled 1 : Transmission enabled TI Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register RE Receive enable bit 0 : Reception disabled 1 : Reception enabled 0 : Reception disabled 1 : Reception enabled RI Receive complete flag 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) U2RRM UART2 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Invalid U2LCH Data logic select bit 0 : No reverse 1 : Reverse 0 : No reverse 1 : Reverse U2ERE Error signal output enable bit Must be fixed to "0" 0 : Output disabled 1 : Output enabled U2IRS UART2 transmit interrupt cause select bit R W Note 1: In M30623(80-pin package), do not use UART2 as clock synchronous serial I/O. Figure 1.19.7. Serial I/O-related registers (4) 119 Mitsubishi microcomputers M16C / 62T Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART transmit/receive control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UCON Bit symbol U0IRS Address 03B016 When reset X00000002 Function (During clock synchronous serial I/O mode) Bit name UART0 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) U1IRS (TXEPT = 1) Function (During UART mode) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Continuous receive mode disabled 1 : Continuous receive mode enable Invalid U1RRM UART1 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Invalid CLKMD0 CLK/CLKS select bit 0 Valid when bit 5 = "1" 0 : Clock output to CLK1 1 : Clock output to CLKS1 Invalid CLKMD1 CLK/CLKS select bit 1 (Note) 0 : Normal mode Must always be "0" (CLK output is CLK1 only) 1 : Transfer clock output from multiple pins function selected Separate CTS/RTS bit 0 : CTS/RTS shared pin 1 : CTS/RTS separated AA AA A AA A AA AA AA A A AA 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) U0RRM UART0 continuous receive mode enable bit RCSP RW 0 : CTS/RTS shared pin 1 : CTS/RTS separated Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. Note: When using multiple pins to output the transfer clock, the following requirements must be met: * UART1 internal/external clock select bit (bit 3 at address 03A816) = "0". UART2 special mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR 0 Bit symbol Address 037716 Bit name When reset 0016 Function (Note 1) (During clock synchronous serial I/O mode) Function (During UART mode) IIC mode selection bit 0 : Normal mode 1 : IIC mode Must always be "0" ABC Arbitration lost detecting flag control bit 0 : Update per bit 1 : Update per byte Must always be "0" BBS Bus busy flag 0 : STOP condition detected 1 : START condition detected Must always be "0" SCLL sync output enable bit 0 : Disabled 1 : Enabled Must always be "0" ABSCS Bus collision detect sampling clock select bit Must always be "0" 0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 ACSE Auto clear function select bit of transmit enable bit Must always be "0" 0 : No auto clear function 1 : Auto clear at occurrence of bus collision SSS Transmit start condition select bit Must always be "0" 0 : Ordinary 1 : Falling edge of RxD2 LSYN Reserved bit (Note 2) Always set to "0" Note 1: In M30623(80-pin package), do not use UART2 as clock synchronous serial I/O. Note 2: Nothing but "0" may be written. Figure 1.19.8. Serial I/O-related registers (5) 120 AA A AA A AA A AA AA A A AA AA A AA A AA A IICM R W Mitsubishi microcomputers M16C / 62T Group Clock synchronous serial I/O mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Clock synchronous serial I/O mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.19.2 and 1.19.3 list the specifications of the clock synchronous serial I/O mode. Figure 1.19.9 shows the UARTi transmit/receive mode register. In M30623(80-pin package), do not use UART2 as clock synchronous serial I/O. Table 1.19.2. Specifications of clock synchronous serial I/O mode (1) Item Transfer data format Transfer clock Specification * Transfer data length: 8 bits * When internal clock is selected (bit 3 at addresses 03A016, 03A816, 0378 16 = "0") : fi/ 2(n+1) (Note 1) fi = f1, f8, f32 * When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = "1") : Input from CLKi pin _______ _______ _______ _______ Transmission/reception control * CTS function/ RTS function/CTS, RTS function chosen to be invalid Transmission start condition * To start transmission, the following requirements must be met: _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = "1" _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16 , 037D16) = "0" _______ _______ _ When CTS function selected, CTS input level = "L" * Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "0": CLKi input level = "H" _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "1": CLKi input level = "L" Reception start condition * To start reception, the following requirements must be met: _ Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = "1" _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = "1" _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16 , 037D16) = "0" * Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "0": CLKi input level = "H" _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "1": CLKi input level = "L" * When transmitting Interrupt request _ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at generation timing address 037D16) = "0": Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed _ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at address 037D16) = "1": Interrupts requested when data transmission from UARTi transfer register is completed * When receiving _ Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Error detection * Overrun error (Note 2) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out Note 1: "n" denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit is not set to "1". 121 Mitsubishi microcomputers M16C / 62T Group Clock synchronous serial I/O mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.19.4. Specifications of clock synchronous serial I/O mode (2) Item Select function Specification * CLK polarity selection Whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected * LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected * Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register * Transfer clock output from multiple pins selection (UART1) (Note) UART1 transfer clock can be chosen by software to be output from one of the two pins set _______ _______ * Separate CTS/RTS pins (UART0) (Note) _______ _______ UART0 CTS and RTS pins each can be assigned to separate pins * Switching serial data logic (UART2) Whether to reverse data in writing to the transmission buffer register or reading the reception buffer register can be selected. * TxD, RxD I/O polarity reverse (UART2) This function is reversing TxD port output and RxD port input. All I/O data level is reversed. _______ _______ Note: The transfer clock output from multiple pins and the separate CTS/RTS pins functions cannot be selected simultaneously. 122 Mitsubishi microcomputers M16C / 62T Group Clock synchronous serial I/O mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive mode registers b7 b6 b5 b4 b3 0 b2 b1 b0 0 0 1 Symbol UiMR(i=0,1) Bit symbol SMD0 Address 03A016, 03A816 When reset 0016 Bit name Serial I/O mode select bit SMD1 SMD2 CKDIR Internal/external clock select bit Function b2 b1 b0 0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock 1 : External clock STPS PRY Invalid in clock synchronous serial I/O mode PRYE 0 (Must always be "0" in clock synchronous serial I/O mode) SLEP A A A A A A RW UART2 transmit/receive mode register b7 0 b6 b5 b4 b3 b2 b1 b0 0 0 1 Symbol U2MR Address 037816 Bit symbol SMD0 Bit name Serial I/O mode select bit SMD1 SMD2 CKDIR When reset 0016 Internal/external clock select bit Function b2 b1 b0 0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock 1 : External clock STPS PRY Invalid in clock synchronous serial I/O mode PRYE IOPOL TxD, RxD I/O polarity reverse bit (Note) Note: Usually set to "0". 0 : No reverse 1 : Reverse A A A A A A A RW Figure 1.19.9. UARTi transmit/receive mode register in clock synchronous serial I/O mode 123 Mitsubishi microcomputers M16C / 62T Group Clock synchronous serial I/O mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.19.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This _______ table shows the pin functions when the transfer clock output from multiple pins and the separate CTS/ _______ RTS pins functions are not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a "H". (If the N-channel open-drain is selected, this pin is in floating state.) Table 1.19.4. Input/output pin functions in clock synchronous serial I/O mode Pin name Function Method of selection TxDi Serial data output (P63, P67, P70) (Outputs dummy data when performing reception only) Serial data input RxDi (P62, P66, P71) Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16, bit 1 at address 03EF16)= "0" (Can be used as an input port when performing transmission only) CLKi Transfer clock output (P61, P65, P72) Transfer clock input Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = "0" CTSi/RTSi CTS input (P60, P64, P73) Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = "1" Port P61, P65 and P72 direction register (bits 1 and 5 at address 03EE16, bit 2 at address 03EF16) = "0" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) ="0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = "0" Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16, bit 3 at address 03EF16) = "0" RTS output CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = "1" Programmable I/O port CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "1" _______ _______ (when transfer clock output from multiple pins and separate CTS/RTS pins functions are not selected) 124 Mitsubishi microcomputers M16C / 62T Group Clock synchronous serial I/O mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER * Example of transmit timing (when internal clock is selected) Tc Transfer clock Transmit enable bit (TE) Transmit buffer empty flag (Tl) "1" "0" Data is set in UARTi transmit buffer register "1" "0" Transferred from UARTi transmit buffer register to UARTi transmit register "H" CTSi TCLK "L" Stopped pulsing because CTS = "H" Stopped pulsing because transfer enable bit = "0" CLKi TxDi D0 D1 D2 D3 D4 D5 D6 D7 Transmit register empty flag (TXEPT) "1" Transmit interrupt request bit (IR) "1" D0 D 1 D2 D3 D4 D5 D6 D7 D0 D1 D 2 D 3 D4 D5 D6 D7 "0" "0" Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: * Internal clock is selected. * CTS function is selected. * CLK polarity select bit = "0". * Transmit interrupt cause select bit = "0" Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f 1, f8, f32) n: value set to BRGi * Example of receive timing (when external clock is selected) Receive enable bit (RE) Transmit enable bit (TE) Transmit buffer empty flag (Tl) "1" "0" "1" "0" "0" "H" RTSi Dummy data is set in UARTi transmit buffer register "1" Transferred from UARTi transmit buffer register to UARTi transmit register "L" 1 / fEXT CLKi Receive data is taken in D0 D1 D2 D3 D4 D5 D6 D7 RxDi "1" Receive complete "0" flag (Rl) Receive interrupt request bit (IR) Transferred from UARTi receive register to UARTi receive buffer register D 0 D1 D2 D3 D4 D5 Read out from UARTi receive buffer register "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: * External clock is selected. * RTS function is selected. * CLK polarity select bit = "0". Meet the following conditions are met when the CLK input before data reception = "H" * Transmit enable bit "1" * Receive enable bit "1" * Dummy data write to UARTi transmit buffer register fEXT: frequency of external clock Figure 1.19.10. Typical transmit/receive timings in clock synchronous serial I/O mode 125 Mitsubishi microcomputers M16C / 62T Group Clock synchronous serial I/O mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (a) Polarity select function As shown in Figure 1.19.11, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) allows selection of the polarity of the transfer clock. * When CLK polarity select bit = "0" CLKi TXDi D0 D1 D2 D3 D4 D5 D6 D7 RXDi D0 D1 D2 D3 D4 D5 D6 D7 Note 1: The CLK pin level when not transferring data is "H". * When CLK polarity select bit = "1" CLKi TXDi D0 D1 D2 D3 D4 D5 D6 D7 RXDi D0 D1 D2 D3 D4 D5 D6 D7 Note 2: The CLK pin level when not transferring data is "L". Figure 1.19.11. Polarity of transfer clock (b) LSB first/MSB first select function As shown in Figure 1.19.12, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16, 037C16) = "0", the transfer format is "LSB first"; when the bit = "1", the transfer format is "MSB first". * When transfer format select bit = "0" CLKi TXDi D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 LSB first RXDi * When transfer format select bit = "1" CLKi TXDi D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 MSB first RXDi Note: This applies when the CLK polarity select bit = "0". Figure 1.19.12. Transfer format 126 Mitsubishi microcomputers M16C / 62T Group Clock synchronous serial I/O mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (c) Transfer clock output from multiple pins function (UART1) This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B0 16). (See Figure 1.19.3.) The multiple pins function is valid only when the internal clock is selected for UART1. Note that when _______ _______ this function is selected, UART1 CTS/RTS function cannot be used. Microcomputer TXD1 (P67) CLKS1 (P64) CLK1 (P65) IN IN CLK CLK Note: This applies when the internal clock is selected and transmission is performed only in clock synchronous serial I/O mode. Figure 1.19.13. The transfer clock output from the multiple pins function usage (d) Continuous receive mode If the continuous receive mode enable bit (bits 2 and 3 at address 03B0 16, bit 5 at address 037D16) is set to "1", the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. _______ _______ (e) Separate CTS/RTS pins function (UART0) This function works the same way as in the clock asynchronous serial I/O (UART) mode. The method of setting and the input/output pin functions are both the same, so refer to select function in the next section, "(2) Clock asynchronous serial I/O (UART) mode." Note that this function is invalid if the transfer clock output from the multiple pins function is selected. (f) Serial data logic switch function (UART2) When the data logic select bit (bit6 at address 037D16) = "1", and writing to transmit buffer register or reading from receive buffer register, data is reversed. Figure 1.19.14 shows the example of serial data logic switch timing. *When LSB first Transfer clock "H" "L" TxD2 "H" (no reverse) "L" TxD2 "H" (reverse) "L" D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Figure 1.19.14. Serial data logic switch timing 127 Mitsubishi microcomputers M16C / 62T Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (2) Clock asynchronous serial I/O (UART) mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables 1.19.5 and 1.19.6 list the specifications of the UART mode. Figure 1.19.15 shows the UARTi transmit/receive mode register. Table 1.19.5. Specifications of UART Mode (1) Item Transfer data format Transfer clock Specification * Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected * Start bit: 1 bit * Parity bit: Odd, even, or nothing as selected * Stop bit: 1 bit or 2 bits as selected * When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = "0") : fi/16(n+1) (Note 1) fi = f1, f8, f32 * When external clock is selected (bit 3 at addresses 03A016, 03A816 ="1") : fEXT/16(n+1) (Note 1) (Note 2) (Do not set external clock for UART2) _______ _______ _______ _______ Transmission/reception control * CTS function/RTS function/CTS, RTS function chosen to be invalid (Note 4) Transmission start condition * To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = "1" - Transmit buffer empty flag (bit 1_______ at addresses 03A516, 03AD16, 037D16) = "0" _______ - When CTS function selected, CTS input level = "L" (Note 4) Reception start condition * To start reception, the following requirements must be met: - Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = "1" - Start bit detection Interrupt request * When transmitting generation timing - Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at address 037D16) = "0": Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed - Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at address 037D16) = "1": Interrupts requested when data transmission from UARTi transfer register is completed * When receiving - Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Error detection * Overrun error (Note 3) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out * Framing error This error occurs when the number of stop bits set is not detected * Parity error This error occurs when if parity is enabled, the number of 1's in parity and character bits does not match the number of 1's set * Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered Note 1: `n' denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: fEXT is input from the CLKi pin. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit is not set to "1". ________ ________ Note 4: In M30623(80-pin package), do not use these functions, because there is no external pin of CTS 2/RTS2. 128 Mitsubishi microcomputers M16C / 62T Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.19.6. Specifications of UART Mode (2) Item Specification _______ _______ Select function * Separate CTS/RTS pins (UART0) _______ _______ UART0 CTS and RTS pins each can be assigned to separate pins * Sleep mode selection (UART0, UART1) This mode is used to transfer data to and from one of multiple slave microcomputers * Serial data logic switch (UART2) This function is reversing logic value of transferring data. Start bit, parity bit and stop bit are not reversed. * T XD, R XD I/O polarity switch This function is reversing TXD port output and RXD port input. All I/O data level is reversed. 129 Mitsubishi microcomputers M16C / 62T Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit / receive mode registers b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiMR(i=0,1) Bit symbol SMD0 Address 03A016, 03A816 Bit name Serial I/O mode select bit SMD1 SMD2 CKDIR When reset 0016 Function b2 b1 b0 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long Internal / external clock select bit Stop bit length select bit 0 : Internal clock 1 : External clock 0 : One stop bit 1 : Two stop bits PRY Odd / even parity select bit Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity PRYE Parity enable bit 0 : Parity disabled 1 : Parity enabled SLEP Sleep select bit 0 : Sleep mode deselected 1 : Sleep mode selected STPS AA AA AA AA A A A A AA AA RW UART2 transmit / receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2MR Bit symbol SMD0 Address 037816 Bit name Serial I/O mode select bit SMD1 SMD2 CKDIR When reset 0016 Function b2 b1 b0 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long Internal / external clock select bit Stop bit length select bit 0 : Internal clock 1 : External clock (Note 2) 0 : One stop bit 1 : Two stop bits PRY Odd / even parity select bit Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity PRYE Parity enable bit 0 : Parity disabled 1 : Parity enabled STPS IOPOL A A A AA A AA AA AA AA AA A A AA RW TxD, RxD I/O polarity 0 : No reverse reverse bit (Note 1) 1 : Reverse Note 1: Usually set to "0". Note 2: In M30623(80-pin package), do not select the external clock as transfer clock, because there is no external pin of CLK2. Figure 1.19.15. UARTi transmit/receive mode register in UART mode 130 Mitsubishi microcomputers M16C / 62T Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.19.7 lists the functions of the input/output pins during UART mode. This table shows the pin _______ _______ functions when the separate CTS/RTS pins function is not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a "H". (If the N-channel open-drain is selected, this pin is in floating state.) Table 1.19.7. Input/output pin functions in UART mode Pin name Function TxDi Serial data output (P63, P67, P70) Method of selection RxDi Serial data input (P62, P66, P71) Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16, bit 1 at address 03EF16)= "0" (Can be used as an input port when performing transmission only) CLKi Programmable I/O port (P61, P65, P72) Transfer clock input Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = "0" (Note 1) CTSi/RTSi CTS input (P60, P64, P73) (Note 2) Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = "1" Port P61, P65 direction register (bits 1 and 5 at address 03EE16) = "0" (Do not set external clock for UART2) CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) ="0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = "0" Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16, bit 3 at address 03EF16) = "0" RTS output CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = "1" Programmable I/O port CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "1" ________ _______ (when separate CTS/RTS pins function is not selected) Note 1: M30623(80-pin package) has no external pin of CLK2(P72). Note 2: In M30623(80-pin package), UART2 does not have these functions, because there is no external pin ________ _______ of CTS2/RTS2(P7 3). 131 Mitsubishi microcomputers M16C / 62T Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER * Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) The transfer clock stops momentarily as CTS is "H" when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTS changes to "L". Tc Transfer clock Transmit enable bit(TE) "1" Transmit buffer empty flag(TI) "1" "0" Data is set in UARTi transmit buffer register. "0" Transferred from UARTi transmit buffer register to UARTi transmit register "H" CTSi "L" Start bit TxDi Parity bit ST D0 D1 D2 D3 D4 D5 D6 D7 P Stopped pulsing because transmit enable bit = "0" Stop bit SP ST D0 D1 D2 D3 D4 D5 D6 D7 P ST D0 D1 SP "1" Transmit register empty flag (TXEPT) "0" Transmit interrupt request bit (IR) "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * CTS function is selected. * Transmit interrupt cause select bit = "1". Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Note 1: In M30623(80-pin package), there is no external pin of CTS2, so do not use the function using this pin. * Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) Tc Transfer clock Transmit enable bit(TE) "1" Transmit buffer empty flag(TI) "1" "0" Data is set in UARTi transmit buffer register "0" Transferred from UARTi transmit buffer register to UARTi transmit register Start bit TxDi Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP ST D0 D1 "1" Transmit register empty flag (TXEPT) "0" Transmit interrupt request bit (IR) "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is disabled. * Two stop bits. * CTS function is disabled. * Transmit interrupt cause select bit = "0". Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Figure 1.19.16. Typical transmit timings in UART mode (UART0, UART1) 132 Mitsubishi microcomputers M16C / 62T Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER * Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) Tc Transfer clock Transmit enable bit(TE) "1" Transmit buffer empty flag(TI) "1" "0" Data is set in UARTi transmit buffer register Note "0" Transferred from UART2 transmit buffer register to UART2 transmit register Start bit TxD2 Parity bit ST D0 D1 D2 D3 D4 D5 D6 D7 P Stop bit SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP "1" Transmit register empty flag (TXEPT) "0" Transmit interrupt request bit (IR) "1" "0" Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = "1". Cleared to "0" when interrupt request is accepted, or cleared by software Tc = 16 (n + 1) / fi fi : frequency of BRGi count source (f1, f8, f32) n : value set to BRGi Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing. Figure 1.19.17. Typical transmit timings in UART mode (UART2) 133 Mitsubishi microcomputers M16C / 62T Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER * Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) BRGi count source Receive enable bit "1" "0" Stop bit Start bit RxDi D1 D0 D7 Sampled "L" Receive data taken in Transfer clock Receive complete flag RTSi Receive interrupt request bit Reception triggered when transfer clock "1" is generated by falling edge of start bit Transferred from UARTi receive register to UARTi receive buffer register "0" "H" "L" "1" "0" The above timing applies to the following settings : *Parity is disabled. Cleared to "0" when interrupt request is accepted, or cleared by software *One stop bit. *RTS function is selected. Note 1: In M30623(80-pin package), there is no external pin of RTS 2, so do not use the function using this pin. Figure 1.19.18. Typical receive timing in UART mode _______ _______ (a) Separate CTS/RTS pins function (UART0) _______ _______ _______ Setting the CTS/RTS separate bit (bit 6 of address 03B016) to "1" inputs/outputs the CTS signal and _______ _______ _______ _______ _______ RTS signal from different pins. Choose which to use, CTS or RTS, by use of the CTS/RTS function select bit (bit 2 of address 03A416). This function is effective in UART0 only. With this function cho_______ _______ _______ _______ sen, the user cannot use the CTS/RTS function. Set "0" both to the CTS/RTS function select bit (bit _______ _______ 2 of address 03AC16) and to the CTS/RTS disable bit (bit 4 of address 03AC16). Microcomputer IC TXD0 (P63) IN RXD0 (P62) OUT RTS0 (P60) CTS CTS0 (P64) RTS Note : The user cannot use CTS and RTS at the same time. _______ _______ Figure 1.19.19. The separate CTS/RTS pins function usage (b) Sleep mode (UART0, UART1) This mode is used to transfer data between specific microcomputers among multiple microcomputers connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A016, 03A816) is set to "1" during reception. In this mode, the unit performs receive operation when the MSB of the received data = "1" and does not perform receive operation when the MSB = "0". 134 Mitsubishi microcomputers M16C / 62T Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (c) Function for switching serial data logic (UART2) When the data logic select bit (bit 6 of address 037D 16) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. Figure 1.19.20 shows the example of timing for switching serial data logic. (d) TxD, RxD I/O polarity reverse function (UART2) This function is to reverse T XD pin output and RXD pin input. The level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. Set this function to "0" (not to reverse) for usual use. Figure 1.19.20 shows the example of timing for I/O polarity reverse. * When LSB first, parity enabled, one stop bit Transfer clock "H" "L" TxD2 No logic reverse "H" No polarity reverse "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP TxD2 Logic reverse "H" No polarity reverse "L" TxD2 No logic reverse Polarity reverse TxD2 Logic reverse Polarity reverse "H" "L" "H" "L" ST : Start bit P : Even parity SP : Stop bit Figure 1.19.20. Timing for switching serial data logic, and I/O polarity reverse (e) Bus collision detection function (UART2) This function is to sample the output level of the TXD pin and the input level of the R XD pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.19.21 shows the example of detection timing of a buss collision (in UART mode). Transfer clock "H" "L" TxD2 "H" ST SP ST SP "L" RxD2 "H" "L" Bus collision detection interrupt request signal "1" Bus collision detection interrupt request bit "1" "0" "0" ST : Start bit SP : Stop bit Figure 1.19.21. Detection timing of a bus collision (in UART mode) 135 Mitsubishi microcomputers M16C / 62T Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (3) Clock-asynchronous serial I/O mode (compliant with the SIM interface) The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table 1.19.8 shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface). Table 1.19.8. Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface) Item Transfer data format Transfer clock Specification * Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = "1012") * One stop bit (bit 4 of address 0378 16 = "0") * With the direct format chosen Set parity to "even" (bit 5 and bit 6 of address 0378 16 = "1" and "1" respectively) Set data logic to "direct" (bit 6 of address 037D16 = "0"). Set transfer format to LSB (bit 7 of address 037C16 = "0"). * With the inverse format chosen Set parity to "odd" (bit 5 and bit 6 of address 037816 = "0" and "1" respectively) Set data logic to "inverse" (bit 6 of address 037D16 = "1") Set transfer format to MSB (bit 7 of address 037C16 = "1") * With the internal clock chosen (bit 3 of address 037816 = "0") : fi / 16 (n + 1) (Note 1) : fi=f1, f8, f32 (Do not set external clock for UART2) _______ _______ Transmission / reception control * Disable the CTS and RTS function (bit 4 of address 037C16 = "1") Other settings * The sleep mode select function is not available for UART2 * Set transmission interrupt factor to "transmission completed" (bit 4 of address 037D16 = "1") Transmission start condition * To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 of address 037D16) = "1" - Transmit buffer empty flag (bit 1 of address 037D16) = "0" Reception start condition * To start reception, the following requirements must be met: - Reception enable bit (bit 2 of address 037D16) = "1" - Detection of a start bit Interrupt request * When transmitting generation timing When data transmission from the UART2 transfer register is completed (bit 4 of address 037D16 = "1") * When receiving When data transfer from the UART2 receive register to the UART2 receive buffer register is completed Error detection * Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2) * Framing error (see the specifications of clock-asynchronous serial I/O) * Parity error (see the specifications of clock-asynchronous serial I/O) - On the reception side, an "L" level is output from the TXD2 pin by use of the parity error signal output function (bit 7 of address 037D16 = "1") when a parity error is detected - On the transmission side, a parity error is detected by the level of input to the RXD2 pin when a transmission interrupt occurs * The error sum flag (see the specifications of clock-asynchronous serial I/O) Note 1: `n' denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit is not set to "1". 136 Mitsubishi microcomputers M16C / 62T Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Tc Transfer clock Transmit enable bit(TE) "1" Transmit buffer empty flag(TI) "1" "0" Data is set in UARTi transmit buffer register Note "0" Transferred from UART2 transmit buffer register to UART2 transmit register Start bit TxD2 Parity bit ST D0 D1 D2 D3 D4 D5 D6 D7 P Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 SP P SP P SP RxD2 A "L" level returns from TxD2 due to the occurrence of a parity error. Signal conductor level (Note 1) ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 The level is detected by the interrupt routine. The level is detected by the interrupt routine. "1" Transmit register empty flag (TXEPT) "0" Transmit interrupt request bit (IR) "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = "1". Tc = 16 (n + 1) / fi fi : frequency of BRGi count source (f1, f8, f32) n : value set to BRGi Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing. Tc Transfer clock Receive enable bit (RE) "1" "0" Start bit RxD2 Parity bit ST D0 D1 D2 D3 D4 D5 D6 D7 P Stop bit SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP TxD2 A "L" level returns from TxD2 due to the occurrence of a parity error. Signal conductor level (Note 1) Receive complete flag (RI) "1" Receive interrupt request bit (IR) "1" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP "0" Read to receive buffer Read to receive buffer "0" Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = "0". Cleared to "0" when interrupt request is accepted, or cleared by software Tc = 16 (n + 1) / fi fi : frequency of BRGi count source (f1, f8, f32) n : value set to BRGi Note: Equal in waveform because TxD2 and RxD2 are connected. Figure 1.19.22. Typical transmit/receive timing in UART mode (compliant with the SIM interface) 137 Mitsubishi microcomputers M16C / 62T Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (a) Function for outputting a parity error signal With the error signal output enable bit (bit 7 of address 037D16) assigned "1", you can output an "L" level from the TxD2 pin when a parity error is detected. In step with this function, the generation timing of a transmission completion interrupt changes to the detection timing of a parity error signal. Figure 1.19.23 shows the output timing of the parity error signal. * LSB first Transfer clock "H" RxD2 "H" TxD2 "H" Receive complete flag "1" "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP "L" Hi-Z "L" "0" ST : Start bit P : Even Parity SP : Stop bit Figure 1.19.23. Output timing of the parity error signal (b) Direct format/inverse format Connecting the SIM card allows you to switch between direct format and inverse format. If you choose the direct format, D0 data is output from TxD2. If you choose the inverse format, D7 data is inverted and output from TxD2. Figure 1.19.24 shows the SIM interface format. Transfer clcck TxD2 (direct) D0 D1 D2 D3 D4 D5 D6 D7 P TxD2 (inverse) D7 D6 D5 D4 D3 D2 D1 D0 P P : Even parity Figure 1.19.24. SIM interface format 138 Mitsubishi microcomputers M16C / 62T Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.19.25 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pull-up. Microcomputer SIM card TxD2 RxD2 Figure 1.19.25. Connecting the SIM interface 139 Mitsubishi microcomputers M16C / 62T Group UART2 Special Mode Register SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART2 Special Mode Register The UART2 special mode register (address 037716) is used to control UART2 in various ways. Figure 1.19.26 shows the UART2 special mode register. UART2 special mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR 0 Bit symbol Address 037716 When reset 0016 Function (During clock synchronous serial I/O mode) Bit name Function (During UART mode) IICM IIC mode selection bit 0 : Normal mode 1 : IIC mode Must always be "0" ABC Arbitration lost detecting flag control bit 0 : Update per bit 1 : Update per byte Must always be "0" BBS Bus busy flag 0 : STOP condition detected 1 : START condition detected Must always be "0" LSYN SCLL sync output enable bit 0 : Disabled 1 : Enabled Must always be "0" ABSCS Bus collision detect sampling clock select bit Must always be "0" 0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 ACSE Auto clear function select bit of transmit enable bit Must always be "0" 0 : No auto clear function 1 : Auto clear at occurrence of bus collision Transmit start condition select bit Must always be "0" 0 : Ordinary 1 : Falling edge of RxD2 SSS (Note) Always set to "0" Reserved bit AAA AA AA AAA AA AAA AAA AA A AA AAA AA A AA R W Note: Nothing but "0" may be written. Figure 1.19.26. UART2 special mode register Table 1.19.9. Features in IIC mode Function Normal mode IIC mode (Note 1) Start condition detection or stop condition detection 1 Factor of interrupt number 10 (Note 2) Bus collision detection 2 Factor of interrupt number 15 (Note 2) UART2 transmission No acknowledgment detection (NACK) 3 Factor of interrupt number 16 (Note 2) UART2 reception Acknowledgment detection (ACK) 4 UART2 transmission output delay Not delayed Delayed 5 P70 at the time when UART2 is in use TxD2 (output) SDA (input/output) (Note 3) 6 P71 at the time when UART2 is in use RxD2 (input) SCL (input/output) 7 P72 at the time when UART2 is in use CLK2 P72 8 DMA1 factor at the time when 1 1 0 1 is assigned to the DMA request factor selection bits UART2 reception Acknowledgment detection (ACK) 9 Noise filter width (Note 4) 15ns 50ns 10 Reading P71 Reading the terminal when 0 is assigned to the direction register Reading the terminal regardless of the value of the direction register 11 Initial value of UART2 output H level (when 0 is assigned to the CLK polarity select bit) The value set in latch P70 when the port is selected Note 1: Make the settings given below when IIC mode is in use. Set 0 1 0 in bits 2, 1, 0 of the UART2 transmission/reception mode register. Disable the RTS/CTS function. Choose the LSB First function. Note 2: Follow the steps given below to switch from a factor to another. 1. Disable the interrupt of the corresponding number. 2. Switch from a factor to another. 3. Reset the interrupt request flag of the corresponding number. 4. Set an interrupt level of the corresponding number. Note 3: Set an initial value of SDA transmission output when serial I/O is invalid. Note 4: In M30623(80-pin package), P72 is not connected to external pin. 140 Mitsubishi microcomputers M16C / 62T Group UART2 Special Mode Register SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In the first place, the control bits related to the IIC bus(simplified IIC bus) interface are explained. Bit 0 of the UART special mode register (037716) is used as the IIC mode selection bit. Setting "1" in the IIC mode select bit (bit 0) goes the circuit to achieve the IIC bus interface effective. Table 1.19.9 shows the relation between the IIC mode select bit and respective control workings. Since this function uses clock-synchronous serial I/O mode, set this bit to "0" in UART mode. P70 through P72 conforming to the simplified IIC bus P70/TxD2/SDA To DMA0, DMA1 Timer Selector IICM=1 I/O UART2 IICM=0 D Q Noize Filter IICM=0 Transmission register delay IICM=1 UART2 To DMA0 Arbitration T IICM=1 Timer UART2 transmission/ NACK interrupt request IICM=0 Reception register UART2 IICM=0 UART2 reception/ACK interrupt request DMA1 request IICM=1 Start condition detection S Stop condition detection I/O D Q T Data bus ACK 9th pulse IICM=1 Internal clock CLK IICM=1 Noize Filter Noize Filter NACK Q T (Port P71 output data latch) UART2 IICM=1 P72/CLK2 D R Q Selector Bus busy L-synchronous output enabling bit Falling edge detection P71/RxD2/SCL R Q Bus collision detection Bus collision/start, stop condition detection interrupt request IICM=0 External clock IICM=0 UART2 IICM=0 Selector I/O Timer UART2 Port reading * With IICM set to 1, the port terminal is to be readable even if 1 is assigned to P71 of the direction register. Note 1: In M30623(80-pin package), P72/CLK2 is not connected to external pin. Figure 1.19.27. Functional block diagram for IIC mode Figure 1.19.27 shows the functional block diagram for IIC mode. Setting "1" in the IIC mode selection bit (IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock inputoutput terminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission output, so the SDA output changes after SCL fully goes to "L". An attempt to read Port P7 1 (SCL) results in getting the terminal's level regardless of the content of the port direction register. The initial value of SDA transmission output in this mode goes to the value set in port P70. The interrupt factors of the bus collision detection interrupt, UART2 transmission interrupt, and of UART2 reception interrupt turn to the start/stop condition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment detection interrupt respectively. The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA terminal (P70) is detected with the SCL terminal (P71) staying "H". The stop condition detection interrupt refers to the interrupt that occurs when the rising edge of the SDA terminal (P70) is detected with the SCL terminal (P71) staying "H". The bus busy flag (bit 2 of the UART2 special mode register) is set to "1" by the start condition detection, and set to "0" by the stop condition detection. 141 Mitsubishi microcomputers M16C / 62T Group UART2 Special Mode Register SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA terminal level is detected still staying "H" at the rising edge of the 9th transmission clock. The acknowledgment detection interrupt refers to the interrupt that occurs when SDA terminal's level is detected already went to "L" at the 9th transmission clock. Also, assigning 1 1 0 1 (UART2 reception) to the DMA1 request factor select bits provides the means to start up the DMA transfer by the effect of acknowledgment detection. Bit 1 of the UART2 special mode register (037716) is used as the arbitration loss detecting flag control bit. Arbitration means the act of detecting the nonconformity between transmission data and SDA terminal data at the timing of the SCL rising edge. This detecting flag is located at bit 3 of the UART2 reception buffer register (037F 16), and "1" is set in this flag when nonconformity is detected. Use the arbitration lost detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by byte. When setting this bit to "1" and updated the flag byte by byte if nonconformity is detected, the arbitration lost detecting flag is set to "1" at the falling edge of the 9th transmission clock. If update the flag byte by byte, must judge and clear ("0") the arbitration lost detecting flag after completing the first byte acknowledge detect and before starting the next one byte transmission. Bit 3 of the UART2 special mode register is used as SCL- and L-synchronous output enable bit. Setting this bit to "1" goes the P7 1 data register to "0" in synchronization with the SCL terminal level going to "L". 142 Mitsubishi microcomputers M16C / 62T Group UART2 Special Mode Register SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Some other functions added are explained here. Figure 1.19.28 shows their workings. Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit. The bus collision detect interrupt occurs when the RxD2 level and TxD2 level do not match, but the nonconformity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to "0". If this bit is set to "1", the nonconformity is detected at the timing of the overflow of timer A0 rather than at the rising edge of the transfer clock. Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enable bit. Setting this bit to "1" automatically resets the transmit enable bit to "0" when "1" is set in the bus collision detect interrupt request bit (nonconformity). Bit 6 of the UART2 special mode register is used as the transmit start condition select bit. Setting this bit to "1" starts the TxD transmission in synchronization with the falling edge of the RxD terminal. 1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register) 0: Rising edges of the transfer clock CLK TxD/RxD 1: Timer A0 overflow Timer A0 2. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register) CLK TxD/RxD Bus collision detect interrupt request bit Transmit enable bit 3. Transmit start condition select bit (Bit 6 of the UART2 special mode register) 0: In normal state CLK TxD Enabling transmission With "1: falling edge of RxD2" selected CLK TxD RxD Note 1: In M30623(80-pin package), P72/CLK2 is not connected to external pin. Figure 1.19.28. Some other functions added 143 Mitsubishi microcomputers M16C / 62T Group S I/O3, 4 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER S I/O3, 4 S I/O3 and S I/O4 are exclusive clock-synchronous serial I/Os. In M30623(80-pin package), S IN3 is not connected to external pin, so S I/O3 is exclusive transmission. Figure 1.19.29 shows the S I/O3, 4 block diagram, and Figure 1.19.30 shows the S I/O3, 4 related register. Table 1.19.10 shows the specifications of S I/O3, 4. f1 Data bus SMi1 SMi0 f8 f32 Synchronous circuit SMi3 SMi6 1/2 1/(ni+1) Transfer rate register (8) SMi6 P90/CLK3 (P95/CLK4) S I/O counter i (3) SMi2 SMi3 P92/SOUT3 (P96/SOUT4) P91/SIN3 (P97/SIN4) SMi5 LSB MSB S I/Oi transmission/reception register (8) 8 Note 1: In M30623(80-pin package), P91/SIN3 is not connected to external pin. Note 2: i = 3, 4. ni = A value set in the S I/O transfer rate register i (036316, 036716). Figure 1.19.29. S I/O3, 4 block diagram 144 S I/Oi interrupt request Mitsubishi microcomputers M16C / 62T Group S I/O3, 4 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER S I/Oi control register (i = 3, 4) (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol SiC Bit symbol Address 036216, 036616 When reset 4016 Description Bit name R W Internal synchronous clock select bit b1 b0 SMi2 SOUTi output disable bit 0 : SOUTi output 1 : SOUTi output disable(high impedance) SMi3 S I/Oi port select bit (Note 2) 0 : Input-output port 1 : SOUTi output, CLK function SMi0 0 0 : Selecting f1 0 1 : Selecting f8 1 0 : Selecting f32 1 1 : Not to be used SMi1 Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be "0". SMi5 Transfer direction lect bit 0 : LSB first 1 : MSB first SMi6 Synchronous clock select bit (Note 2) 0 : External clock 1 : Internal clock SOUTi initial value set bit Effective when SMi3 = 0 0 : L output 1 : H output Note 1: Set "1" in bit 2 of the protection register (000A16) in advance to write to the S I/Oi control register (i = 3, 4). Note 2: When using the port as an input/output port by setting the S I/Oi port select bit (i = 3, 4) to "1", be sure to set the sync clock select bit to "1" . SMi7 SI/Oi bit rate generator b7 Symbol S3BRG S4BRG b0 Address 036316 036716 When reset Indeterminate Indeterminate Values that can be set Indeterminate Assuming that set value = n, BRGi divides the count source by n + 1 R W 0016 to FF16 SI/Oi transmit/receive register b7 b7 b0 Symbol S3TRR S4TRR Address 036016 036416 When reset Indeterminate Indeterminate Indeterminate R W Transmission/reception starts by writing data to this register. After transmission/reception finishes, reception data is input. (Note 1) Note 1: In M30623(80-package), S I/O3 is exclusive transmission. Figure 1.19.30. SI/Oi related register 145 Mitsubishi microcomputers M16C / 62T Group S I/O3, 4 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.19.10. Specifications of S I/O3, 4 Item Specifications Transfer data format * Transfer data length: 8 bits Transfer clock * With the internal clock selected (bit 6 of 036216, 036616 = "1"): f1/2(ni+1), f8/2(ni+1), f32/2(ni+1) (Note 1) * With the external clock selected (bit 6 of 036216, 036616 = 0):Input from the CLKi terminal (Note 2) Conditions for * To start transmit/reception, the following requirements must be met: transmission/ - Select the synchronous clock (use bit 6 of 036216, 036616). reception start Select a frequency dividing ratio if the internal clock has been selected (use bits 0 and 1 of 036216, 036616). - SOUTi initial value set bit (use bit 7 of 036216, 036616)= 1. - S I/Oi port select bit (bit 3 of 036216, 036616) = 1. - Select the transfer direction (use bit 5 of 036216, 036616). - Write transfer data to SI/Oi transmit/receive register (036016, 036416). * To use S I/Oi interrupts, the following requirements must be met: - Clear the SI/Oi interrupt request bit before writing transfer data to the SI/O transmit/receive register (bit 3 of 004916, 004816) = 0. Interrupt request * Rising edge of the last transfer clock. (Note 3) generation timing Select function * LSB first or MSB first selection Whether transmission/reception begins with bit 0 (LSB) or bit 7 (MSB) can be selected. * Function for setting an SOUTi initial value selection When using an external clock for the transfer clock, the user can choose the S OUTi pin output level during a non-transfer time. For details on how to set, see Figure 1.19.31. Precaution * Unlike UART0-2, SI/Oi (i = 3, 4) is not divided for transfer register and buffer. Therefore, do not write the next transfer data to the SI/Oi transmit/receive register (addresses 036016, 036416) during a transfer. When the internal clock is selected for the transfer clock, S OUTi holds the last data for a 1/2 transfer clock period afeter it finished transferring and then goes to a high-impedance state. However, if the transfer data is written to the SI/Oi transmit/receive register (addresses 0360 16, 036416) during this time, SOUT i is placed in the high-impedance state immediately upon writing and the data hold time is thereby reduced. Note 1: n is a value from 0016 through FF16 set in the S I/Oi transfer rate register (i = 3, 4). Note 2: With the external clock selected: * Before data can be written to the SI/Oi transmit/receive register (addresses 0360 16, 036416), the CLKi pin input must be in the low state. Also, before rewriting the SI/O Control Register (addresses 036216, 036616)'s bit 7 (SOUTi initial value set bit), make sure the CLKi pin input is held low. * The S I/Oi circuit keeps on with the shift operation as long as the synchronous clock is entered in it, so stop the synchronous clock at the instant when it counts to eight. The internal clock, if selected, automatically stops. Note 3: If the internal clock is used for the synchronous clock, the transfer clock signal stops at the "H" state. Note 4: In M30623(80-pin package), S I/O3 is exclusive transmission, because SIN3 is not connected to external pin. 146 Mitsubishi microcomputers M16C / 62T Group S I/O3, 4 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Functions for setting an SOUTi initial value When using an external clock for the transfer clock, the SOUTi pin output level during a non-transfer time can be set to the high or the low state. Figure 1.19.31 shows the timing chart for setting at SOUTi initial value and how to set it. (Example) With "H" selected for SOUTi: S I/Oi port select bit SMi3 = 0 Signal written to the S I/Oi transmission/reception register SOUTi initial value select bit SMi7 = 1 "H" level) (SOUTi: Internal SOUTi's initial value set bit (SMi7) S I/Oi port select bit SMi3 = 0 1 (Port select: Normal port SOUTi) S I/Oi port select bit (SMi3) D0 SOUTi (internal) SOUTi terminal = "H" output D0 Port output SOUTi terminal output Signal written to the S I/Oi register ="L" "H" "L" (Falling edge) Initial value = "H" (Note) (i = 3, 4) Setting the SOUTi initial value to H Port selection (normal port SOUTi) SOUTi terminal = Outputting stored data in the S I/Oi transmission/ reception register Note: The set value is output only when the external clock has been selected. When initializing SOUTi, make sure the CLKi pin input is held "L" level. If the internal clock has been selected or if SOUT output disable has been set, this output goes to the high-impedance state. Figure 1.19.31. Timing chart for setting SOUTi's initial value and how to set it S I/Oi operation timing Figure 1.19.32 shows the S I/Oi operation timing 1.5 cycle (max) Transfer clock "H" (Note 1) "L" Transfer clock "H" (Note 1) "L" Signal written to the S I/Oi register "H" S I/Oi output SOUTi "H" "L" (i= 3, 4) "L" S I/Oi input SINi (Note 3) D0 D1 D2 D3 D4 D5 D6 D7 (Note 2) Hiz "H" (i= 3, 4) "L" Setting the S I/Oi interrupt request bit "1" "0" (i= 3, 4) Note 1: With the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using bits 0 and 1 of the S I/Oi control register. (No frequency division, 8-division frequency, 32-division frequency.) Note 2: With the internal clock selected for the transfer clock, the SOUTi terminal becomes to the high-impedance state after the transfer finishes. Note 3: In M30623(80-pin package), the input pin SIN3 of S I/O3 is not connected to external pin. Note 4: Shown above is the case where the SOUTi (i = 3, 4) port select bit = "1". Figure 1.19.32. S I/Oi operation timing chart 147 Mitsubishi microcomputers M16C / 62T Group A-D Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P100 to P10 7, P95, P96, P0 0 to P07, and P20 to P27 also function as the analog signal input pins. The direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D7 16) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from V REF, reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF . The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Table 1.20.1 shows the performance of the A-D converter. Figure 1.20.1 shows the block diagram of the A-D converter, and Figures 1.20.2 and 1.20.3 show the A-D converter-related registers. Table 1.20.1. Performance of A-D converter Item Performance Method of A-D conversion Successive approximation (capacitive coupling amplifier) Analog input voltage (Note 1) 0V to AVCC (VCC) Operating clock AD (Note 2) fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN) (VCC = 5V) Resolution 8-bit or 10-bit (selectable) Absolute precision 8-bit resolution 2LSB 10-bit resolution 3LSB When the extended analog input pins ANEX0, ANEX1, AN00 to AN07, and AN20 to AN27 are used as the external operation amp connection mode: 7LSB Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 Analog input pins 8 pins (AN 0 to AN7) + 2 pins (ANEX0 and ANEX1) + 16 pins (AN00 to AN07, AN20 to AN27) (Note 3) A-D conversion start condition * Software trigger A-D conversion starts when the A-D conversion start flag changes to "1" * External trigger (can be retriggered) A-D conversion starts when the A-D conversion start flag is "1" and the ___________ ADTRG/P97 input changes from "H" to "L" Conversion speed per pin * Without sample and hold function 8-bit resolution: 49 AD cycles, 10-bit resolution: 59 AD cycles * With sample and hold function 8-bit resolution: 28 AD cycles, 10-bit resolution: 33 AD cycles Note 1: Does not depend on use of sample and hold function. Note 2: Divide the frequency if f(XIN) exceeds 10MHZ, and make AD frequency equal to 10MHZ. Without sample and hold function, set the AD frequency to 250kHZ min. With the sample and hold function, set the AD frequency to 1MH Z min. Note 3: The pins are not used as the analog input pins can be used as normal I/O ports, or I/O pins of each peripheral function. 148 Mitsubishi microcomputers M16C / 62T Group A-D Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D conversion rate selection fAD 1/2 VREF CKS1 = 0 CKS0 = 0 Resistor ladder VCUT = 0 AVSS AD CKS1 = 1 CKS0 = 1 1/2 VCUT = 1 Successive conversion register A-D control register 1 (address 03D7 16) A-D control register 0 (address 03D6 16) Addresses (03C116, 03C016) (03C316, 03C216) (03C516, 03C416) (03C716, 03C616) (03C916, 03C816) (03CB 16, 03CA16) (03CD16, 03CC16) (03CF 16, 03CE16) A-D register 0 (16) A-D register 1 (16) A-D register 2 (16) A-D register 3 (16) A-D register 4 (16) A-D register 5 (16) A-D register 6 (16) A-D register 7 (16) Decoder for A-D register Data bus high-order Data bus low-order A-D control register 2 (address 03D4 16) PM00 PM01 Vref Decoder for channel selection Comparator VIN CH2,CH1,CH0 = 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111 Port P10 group Port P0 group P00/AN00 P01/AN01 P02/AN02 P03/AN03 P04/AN04 P05/AN05 P06/AN06 P07/AN07 Port P2 group P20/AN20 P21/AN21 P22/AN22 P23/AN23 P24/AN24 P25/AN25 P26/AN26 P27/AN27 PM01,PM00,CH2,CH1,CH0 = 00000 = 00001 = 00010 = 00011 = 00100 = 00101 = 00110 = 00111 PM01,PM00,CH2,CH1,CH0 = 00000 = 00001 = 00010 = 00011 = 00100 = 00101 = 00110 = 00111 P10 0/AN0 P10 1/AN1 P10 2/AN2 P10 3/AN3 P10 4/AN4 P10 5/AN5 P10 6/AN6 P10 7/AN7 ANEX 1 PM01,PM00 = 00 ADGSEL1,ADGSEL0 = 10 OPA1,OPA0 = 00 PM01,PM00 = 00 ADGSEL1,ADGSEL0 = 11 OPA1,OPA0 = 00 ADGSEL1,ADGSEL0 = 00 OPA1,OPA0 = 11 PM01,PM00 = 00 ADGSEL1,ADGSEL0 = 10 OPA1,OPA0 = 11 PM01,PM00 = 00 ADGSEL1,ADGSEL0 = 11 OPA1,OPA0 = 11 ANEX 0 ADGSEL1,ADGSEL0 = 00 OPA1,OPA0 = 00 OPA0 = 1 OPA1,OPA0 = 01 OPA1 = 1 OPA1 = 1 Figure 1.20.1. Block diagram of A-D converter 149 Mitsubishi microcomputers M16C / 62T Group A-D Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON0 Bit symbol Address 03D616 When reset 00000XXX2 Bit name RW Function b2 b1 b0 CH0 Analog input pin select bit CH1 CH2 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected (Note 2) (Note 3) b4 b3 MD0 MD1 A-D operation mode select 0 0 : One-shot mode bit 0 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1 TR G Trigger select bit 0 : Software trigger 1 : ADTRG trigger ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started CKS0 Frequency select bit 0 0 : fAD/4 is selected 1 : fAD/2 is selected (Note 3) Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN00 to AN07, and AN20 to AN27 can be used the same as AN0 to AN7. Note 3: When changing A-D operation mode, set analog input pin again. A-D control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON1 Bit symbol Address 03D716 When reset 0016 Bit name A-D sweep pin select bit SCAN0 Function RW When single sweep and repeat sweep mode 0 are selected b1 b0 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) When repeat sweep mode 1 is selected SCAN1 b1 b0 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) MD2 BITS CKS1 VCUT OPA0 (Note 3) A-D operation mode select bit 1 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 (Note 2) 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected Vref connect bit 0 : Vref not connected 1 : Vref connected External op-amp connection mode bit b7 b6 OPA1 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2 : Divide the frequency if f(XIN) exceeds 10MHz, and make AD frequency equal to 10 MHz. Note 3 : AN00 to AN07, and AN20 to AN27 can be used the same as AN0 to AN7. Figure 1.20.2. A-D converter-related registers (1) 150 Mitsubishi microcomputers M16C / 62T Group A-D Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D control register 2 (Note) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol Address When reset ADCON2 03D416 0016 Bit symbol SMP Bit name A-D conversion method select bit Function 0 : Without sample and hold 1 : With sample and hold b2 b1 ADGSEL0 Analog input group select bit ADGSEL1 Reserved bit 00 : Port10 group is selected 01 : Not use 10 : Port0 group is selected 11 : Port1 group is selected Always set to "0" Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". AA AA AA RW Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Symbol A-D register i (b15) b7 ADi(i=0 to 7) (b8) b0 b7 Address When reset 03C016 to 03CF16 Indeterminate b0 Function Eight low-order bits of A-D conversion result * During 10-bit mode Two high-order bits of A-D conversion result * During 8-bit mode When read, the content is indeterminate A A R W Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". Figure 1.20.3. A-D converter-related registers (2) 151 Mitsubishi microcomputers M16C / 62T Group A-D Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) One-shot mode In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conversion. Table 1.20.2 shows the specifications of one-shot mode. Figure 1.20.4 shows the A-D control register in one-shot mode. Table 1.20.2. One-shot mode specifications Item Specification Function Start condition The pin selected by the analog input pin select bit is used for one A-D conversion Writing "1" to A-D conversion start flag Stop condition * End of A-D conversion (A-D conversion start flag changes to "0", except when external trigger is selected) * Writing "0" to A-D conversion start flag Interrupt request generation timing Input pin End of A-D conversion One of AN0 to AN7, as selected (Note 1) Reading of result of A-D converter Read A-D register corresponding to selected pin Note 1: AN00 to AN07, and AN20 to AN27 can be used the same as AN 0 to AN7. A-D control register 0 (Note 1) b7 b6 b5 b4 b3 0 0 b2 b1 b0 Symbol ADCON0 Bit symbol CH0 Address 03D616 When reset 00000XXX2 Bit name Function 0 0 0 0 1 1 1 1 CH1 CH2 0 0 1 1 0 0 1 1 MD1 A-D operation mode select bit 0 b4 b3 TRG Trigger select bit ADST A-D conversion start flag CKS0 Frequency select bit 0 0 1 0 1 0 1 MD0 0 1 0 1 0 1 0 1 : : : : : : : : AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 is is is is is is is is selected selected selected selected selected selected selected selected 0 0 : One-shot mode : : : : : : AAA A AA AAA AAA AAA AAA AAA AAA RW b2 b1 b0 Analog input pin select bit (Note 2) (Note 3) (Note 3) Software trigger ADTRG trigger A-D conversion disabled A-D conversion started fAD/4 is selected fAD/2 is selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN00 to AN07, and AN20 to AN27 can be used the same as AN0 to AN7. Note 3: When changing A-D operation mode, set analog input pin again. A-D control register 1 (Note 1) b7 b6 b5 1 b4 b3 b2 0 b1 b0 Symbol ADCON1 Address 03D716 When reset 0016 Function AAA AAA AAA AAA AAA AAA AAA AAA Bit symbol Bit name SCAN0 A-D sweep pin select bit Invalid in one-shot mode A-D operation mode select bit 1 0 : Any mode other than repeat sweep mode 1 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode SCAN1 MD2 BITS CKS1 0 : fAD/2 or fAD/4 is selected Frequency select bit 1 (Note 2) 1 : fAD is selected VCUT Vref connect bit OPA0 External op-amp connection mode bit OPA1 1 : Vref connected b7 b6 0 0 1 1 0 1 0 1 : : : : ANEX0 and ANEX1 are not used ANEX0 input is A-D converted ANEX1 input is A-D converted External op-amp connection mode RW Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: Divide the frequency if f(XIN) exceeds 10MHz, and make AD frequency equal to 10MHz. Figure 1.20.4. A-D conversion register in one-shot mode 152 Mitsubishi microcomputers M16C / 62T Group A-D Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (2) Repeat mode In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. Table 1.20.3 shows the specifications of repeat mode. Figure 1.20.5 shows the A-D control register in repeat mode. Table 1.20.3. Repeat mode specifications Item Function Star condition Specification The pin selected by the analog input pin select bit is used for repeated A-D conversion Writing "1" to A-D conversion start flag Stop condition Interrupt request generation timing Input pin Writing "0" to A-D conversion start flag None generated One of AN0 to AN7, as selected (Note 1) Reading of result of A-D converter Read A-D register corresponding to selected pin Note 1: AN00 to AN07, and AN20 to AN27 can be used the same as AN0 to AN7. A-D control register 0 (Note 1) b7 b6 b5 b4 b3 0 1 b2 b1 b0 Symbol ADCON0 Bit symbol CH0 Address 03D616 When reset 00000XXX2 Bit name Function 0 0 0 0 1 1 1 1 CH1 CH2 0 0 1 1 0 0 1 1 A-D operation mode select bit 0 b4 b3 MD1 TRG Trigger select bit ADST A-D conversion start flag CKS0 Frequency select bit 0 0 1 0 1 0 1 MD0 0 1 0 1 0 1 0 1 : : : : : : : : AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 is is is is is is is is selected selected selected selected selected selected selected selected 0 1 : Repeat mode : : : : : : AAA AAA AAA AAA AAA AAA AAA RW b2 b1 b0 Analog input pin select bit (Note 2) (Note 3) (Note 3) Software trigger ADTRG trigger A-D conversion disabled A-D conversion started fAD/4 is selected fAD/2 is selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN00 to AN07, and AN20 to AN27 can be used the same as AN0 to AN7. Note 3: When changing A-D operation mode, set analog input pin again. A-D control register 1 (Note 1) b7 b6 b5 1 b4 b3 b2 0 b1 b0 Symbol ADCON1 Address 03D716 When reset 0016 Bit symbol Bit name SCAN0 A-D sweep pin select bit Invalid in repeat mode Function A-D operation mode select bit 1 0 : Any mode other than repeat sweep mode 1 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode SCAN1 MD2 BITS CKS1 0 : fAD/2 or fAD/4 is selected Frequency select bit 1 (Note 2) 1 : fAD is selected VCUT Vref connect bit OPA0 External op-amp connection mode bit OPA1 1 : Vref connected b7 b6 0 0 1 1 0 1 0 1 : : : : ANEX0 and ANEX1 are not used ANEX0 input is A-D converted ANEX1 input is A-D converted External op-amp connection mode AAA AAA AAA AAA AAA AAA AAA AAA RW Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: Divide the frequency if f(XIN) exceeds 10MHz, and make AD frequency equal to 10MHz. Figure 1.20.5. A-D conversion register in repeat mode 153 Mitsubishi microcomputers M16C / 62T Group A-D Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (3) Single sweep mode In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D conversion. Table 1.20.4 shows the specifications of single sweep mode. Figure 1.20.6 shows the A-D control register in single sweep mode. Table 1.20.4. Single sweep mode specifications Item Function Specification The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion Start condition Stop condition Writing "1" to A-D converter start flag * End of A-D conversion (A-D conversion start flag changes to "0", except when external trigger is selected) * Writing "0" to A-D conversion start flag Interrupt request generation timing End of A-D conversion Input pin Reading of result of A-D converter AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) (Note 1) Read A-D register corresponding to selected pin Note 1: AN00 to AN07, and AN20 to AN27 can be used the same as AN 0 to AN7. A-D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON0 Bit symbol CH0 Address 03D616 When reset 00000XXX2 Bit name Function RW Analog input pin select bit Invalid in single sweep mode CH1 CH2 M D0 A-D operation mode select bit 0 b4 b3 1 0 : Single sweep mode M D1 TR G Trigger select bit 0 : Software trigger 1 : ADTRG trigger ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started CKS0 Frequency select bit 0 0 : fAD/4 is selected 1 : fAD/2 is selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D control register 1 (Note 1) b7 b6 b5 1 b4 b3 b2 0 b1 b0 Symbol ADCON1 Bit symbol SCAN0 Address 03D716 When reset 0016 Bit name A-D sweep pin select bit Function R W When single sweep and repeat sweep mode 0 are selected b1 b0 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) SCAN1 (Note 3) M D2 A-D operation mode select bit 1 0 : Any mode other than repeat sweep mode 1 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode CKS1 Frequency select bit 1 (Note 2) 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected VCUT Vref connect bit 1 : Vref connected OPA0 External op-amp connection mode bit (Note 4) b7 b6 OPA1 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: Divide the frequency if f(XIN) exceeds 10MHz, and make AD frequency equal t 10MH Figure 1.20.6. A-D conversion register in single sweep mode 154 Mitsubishi microcomputers M16C / 62T Group A-D Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (4) Repeat sweep mode 0 In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep A-D conversion. Table 1.20.5 shows the specifications of repeat sweep mode 0. Figure 1.20.7 shows the A-D control register in repeat sweep mode 0. Table 1.20.5. Repeat sweep mode 0 specifications Item Function Start condition Stop condition Interrupt request generation timing Specification The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion Writing "1" to A-D conversion start flag Writing "0" to A-D conversion start flag None generated Input pin AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) (Note 1) Reading of result of A-D converter Read A-D register corresponding to selected pin (at any time) Note 1: AN00 to AN07, and AN20 to AN27 can be used the same as AN0 to AN7. A-D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol ADCON0 Bit symbol CH0 Address 03D616 When reset 00000XXX2 Bit name A A A A A A A Function RW Analog input pin select bit Invalid in repeat sweep mode 0 CH1 CH2 MD0 A-D operation mode select bit 0 b4 b3 1 1 : Repeat sweep mode 0 MD1 TRG Trigger select bit ADST A-D conversion start flag CKS0 Frequency select bit 0 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D control register 1 (Note 1) b7 b6 b5 1 b4 b3 b2 0 b1 b0 Symbol ADCON1 Bit symbol SCAN0 Address 03D716 When reset 0016 Bit name A-D sweep pin select bit Function b1 b0 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) SCAN1 MD2 BITS CKS1 A-D operation mode select bit 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected Frequency select bit 1 (Note 2) 1 : fAD is selected VCUT Vref connect bit OPA0 External op-amp connection mode bit (Note 4) OPA1 (Note 3) 0 : Any mode other than repeat sweep mode 1 8/10-bit mode select bit 1 : Vref connected b7 b6 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode A A A A A A A A R W When single sweep and repeat sweep mode 0 are selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: Divide the frequency if f(XIN) exceeds 10MHz, and make AD frequency equal to 10MHz. Note 3: AN00 to AN07, and AN20 to AN27 can be used the same as AN0 to AN7. Note 4: Neither "01" nor "10" can be selected with the external op-amp connection mode bit. Figure 1.20.7. A-D conversion register in repeat sweep mode 0 155 Mitsubishi microcomputers M16C / 62T Group A-D Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (5) Repeat sweep mode 1 In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the A-D sweep pin select bit. Table 1.20.6 shows the specifications of repeat sweep mode 1. Figure 1.20.8 shows the A-D control register in repeat sweep mode 1. Table 1.20.6. Repeat sweep mode 1 specifications Item Specification All pins perform repeat sweep A-D conversion, with emphasis on the pin or pins selected by the A-D sweep pin select bit Example : AN0 selected AN0 AN1 AN0 AN2 AN0 AN3, etc Writing "1" to A-D conversion start flag Writing "0" to A-D conversion start flag None generated Function Start condition Stop condition Interrupt request generation timing Input pin AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins) (Note1 ) Reading of result of A-D converter Read A-D register corresponding to selected pin (at any time) Note 1: AN00 to AN07, and AN20 to AN27 can be used the same as AN 0 to AN7. A-D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol ADCON0 Address 03D616 Bit symbol CH0 When reset 00000XXX2 Bit name Function Analog input pin select bit Invalid in repeat sweep mode 1 CH1 CH2 MD0 A-D operation mode select bit 0 b4 b3 1 1 : Repeat sweep mode 1 MD1 TRG Trigger select bit ADST A-D conversion start flag CKS0 Frequency select bit 0 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected A AAAA A AA AAAA AAAA AA RW Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D control register 1 (Note 1) b7 b6 b5 1 b4 b3 b2 1 b1 b0 Symbol ADCON1 Address 03D716 Bit symbol Bit name SCAN0 A-D sweep pin select bit Function When repeat sweep mode 1 is selected b1 b0 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) SCAN1 MD2 When reset 0016 A-D operation mode select bit 1 8/10-bit mode select bit 1 : Repeat sweep mode 1 CKS1 Frequency select bit 1 (Note 2) 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected VCUT Vref connect bit 1 : Vref connected OPA0 External op-amp connection mode bit (Note 4) BITS OPA1 b7 b6 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode A AAAA AAA AAA AAA A AAA AAAA R W (Note 3) Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: Divide the frequency if f(XIN) exceeds 10MHz, and make AD frequency equal to 10MHz. Note 3: AN00 to AN07, and AN20 to AN27 can be used the same as AN0 to AN7. Note 4: Neither `01' nor `10' can be selected with the external op-amp connection mode bit. Figure 1.20.8. A-D conversion register in repeat sweep mode 1 156 Mitsubishi microcomputers M16C / 62T Group A-D Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (a) Sample and hold Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to "1". When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 AD cycle is achieved with 8-bit resolution and 33 AD with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold is to be used. (b) Extended analog input pins In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can also be converted from analog to digital. When bit 6 of the A-D control register 1 (address 03D716) is "1" and bit 7 is "0", input via ANEX0 is converted from analog to digital. The result of conversion is stored in A-D register 0. When bit 6 of the A-D control register 1 (address 03D716) is "0" and bit 7 is "1", input via ANEX1 is converted from analog to digital. The result of conversion is stored in A-D register 1. Furthermore, the input via 16pins of the extended analog input pins AN00 to AN07, AN20 to AN27 can be converted from analog to digital. These pins can be used the same as AN 0 to AN7. Use the A-D control register 2 (address 03D416) bit 1 and bit 2 to select the pin group AN0 to AN 7, AN00 to AN07, AN 20 to AN27. In the selected pin group, the pins is not used as the analog input pin, can be used as normal I/O ports, or I/O pins of each peripheral function. (c) External operation amp connection mode In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can be amplified together by just one operation amp and used as the input for A-D conversion. When bit 6 of the A-D control register 1 (address 03D716) is "1" and bit 7 is "1", input via AN0 to AN 7(Note 1) is output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in the corresponding A-D register. The speed of A-D conversion depends on the response of the external operation amp. Do not connect the ANEX0 and ANEX1 pins directly. Figure 1.20.9 is an example of how to connect the pins in external operation amp mode. Note 1: AN00 to AN07, AN 20 to AN27 can be used the same as AN0 to AN7. (d) Caution of using A-D converter (1) Set the direction register of the following ports to input: the port corresponding to a pin to be used as an analog input pin and external trigger input pin(P9 7). (2) In using a key-input interrupt, none of 4 pins (AN4 through AN7) can be used as an A-D conversion port (if the A-D input voltage goes to ``L'' level, a key-input interrupt occurs). (3) Insert the capacitor between AVcc and AVss, between V REF and AVss, and between the analog input pin (ANi) and AVss, to prevent a malfunction or program runaway, and to reduce conversion error, due to noise. Figure 1.20.10 is an example connection of each pin. 157 Mitsubishi microcomputers M16C / 62T Group A-D Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ADGSEL1,ADGSEL0 = 0,0 Port P10 group Analog input pins AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Resistor ladder Successive conversion register ADGSEL1,ADGSEL0 = 1,0 Port P0 group Analog input pins AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 Port P2 group Analog input pins AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 ADGSEL1,ADGSEL0 = 1,1 ANEX0 ANEX1 Comparator External op-amp Figure 1.20.9. Example of external op-amp connection mode Microcomputer VCC C4 AVCC VREF VSS AVSS C1 C2 C3 A Ni Note 1: C10.47F, C20.47F, C3100pF, C40.1F Note 2: Use thick and shortest possible wiring to connect capacitors. Figure 1.20.10. Example connection of VCC, VSS, AVCC, AV SS, VREF and ANi 158 Mitsubishi microcomputers M16C / 62T Group D-A Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER D-A Converter This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of this type. D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the target port to output mode if D-A conversion is to be performed. Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register. V = VREF X n/ 256 (n = 0 to 255) V REF : reference voltage Table 1.21.1 lists the performance of the D-A converter. Figure 1.21.1 shows the block diagram of the D-A converter. Figure 1.21.2 shows the D-A control register. Figure 1.21.3 shows the D-A converter equivalent circuit. Table 1.21.1. Performance of D-A converter Item Conversion method Resolution Analog output pin Performance R-2R method 8 bits 2 channels Data bus low-order bits D-A register0 (8) (Address 03D816) D-A0 output enable bit R-2R resistor ladder D-A register1 (8) AAA P93/DA0 (Address 03DA16) D-A1 output enable bit R-2R resistor ladder AAA P94/DA1 Figure 1.21.1. Block diagram of D-A converter 159 Mitsubishi microcomputers M16C / 62T Group D-A Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER D-A control register b7 b6 b5 b4 b3 b2 b1 Symbol DACON b0 Address 03DC16 Bit symbol When reset 0016 Bit name AA A AA A Function DA0E D-A0 output enable bit 0 : Output disabled 1 : Output enabled DA1E D-A1 output enable bit 0 : Output disabled 1 : Output enabled RW Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0" D-A register b7 Symbol DAi (i = 0,1) b0 Address 03D816, 03DA16 When reset Indeterminate AA A AA A Function RW R W Output value of D-A conversion Figure 1.21.2. D-A control register D-A0 output enable bit "0" R R R R 2R 2R 2R 2R R R R 2R DA0 "1" 2R 2R 2R 2R MSB D-A0 register0 AVSS VREF Note 1: The above diagram shows an instance in which the D-A register is assigned 2A16. Note 2: The same circuit as this is also used for D-A1. Note 3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to 0 and set the D-A register to 0016 so that no current flows in the resistors Rs and 2Rs. Figure 1.21.3. D-A converter equivalent circuit 160 LSB Mitsubishi microcomputers M16C / 62T Group CRC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CRC Calculation Circuit The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcomputer uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code. The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC code is set in a CRC data register each time one byte of data is transferred to a CRC input register after writing an initial value into the CRC data register. Generation of CRC code for one byte of data is completed in two machine cycles. Figure 1.22.1 shows the block diagram of the CRC circuit. Figure 1.22.2 shows the CRC-related registers. Figure 1.22.3 shows the calculation example using the CRC calculation circuit Data bus high-order bits Data bus low-order bits AAAAAA AAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAA AAAAAA Eight low-order bits Eight high-order bits CRC data register (16) (Addresses 03BD16, 03BC16) CRC code generating circuit x16 + x12 + x5 + 1 CRC input register (8) (Address 03BE16) Figure 1.22.1. Block diagram of CRC circuit CRC data register (b15) b7 (b8) b0 b7 b0 Symbol CRCD Address 03BD16, 03BC16 When reset Indeterminate Values that can be set Function CRC calculation result output register 000016 to FFFF16 A RW CRC input register b7 Symbo CRCIN b0 Function Data input register Address 03BE16 When reset Indeterminate Values that can be set 0016 to FF16 A RW Figure 1.22.2. CRC-related registers 161 Mitsubishi microcomputers M16C / 62T Group CRC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER b15 b0 CRC data register CRCD [03BD16, 03BC16] (1) Setting 000016 b7 b0 CRC input register (2) Setting 0116 CRCIN [03BE16] 2 cycles After CRC calculation is complete b15 b0 CRC data register 118916 CRCD [03BD16, 03BC16] Stores CRC code The code resulting from sending 0116 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial, (X16 + X12 + X5 + 1), becomes the remainder resulting from dividing (1000 0000) X16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. LSB MSB Modulo-2 operation is operation that complies with the law given below. 1000 1000 1 0001 0000 0010 0001 9 1000 0000 0000 1000 1000 0001 1000 0001 1000 1000 1001 LSB 8 1 0000 0000 0000 0001 0001 0000 1 1000 0000 1000 0000 0+0=0 0+1=1 1+0=1 1+1=0 -1 = 1 0 1 1000 MSB 1 Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000) corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC operation. Also switch between the MSB and LSB of the result as stored in CRC data. b7 b0 CRC input register (3) Setting 2316 CRCIN [03BE16] After CRC calculation is complete b15 b0 0A4116 CRC data register CRCD [03BD16, 03BC16] Stores CRC code Figure 1.22.3. Calculation example using the CRC calculation circuit 162 Mitsubishi microcomputers M16C / 62T Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Ports M30622(100-pin package) has 87 programmable I/O ports: P0 to P10 (excluding P8 5). M30623(80-pin package) has 70 (P1, P44 to P4 7, P72 to P7 5, P91 are not connected to external pin). Each port can be set independently for input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P85 is an input-only port and has no built-in pull-up resistance. Figures 1.23.1 to 1.23.3 show the programmable I/O ports. Figure 1.23.4 shows the I/O pins. Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices. To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A converter), they function as outputs regardless of the contents of the direction registers. When pins are to be used as the outputs for the D-A converter, do not set the direction registers to output mode. See the descriptions of the respective functions for how to set up the built-in peripheral devices. (1) Direction registers Figure 1.23.5 shows the direction registers. These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin. Note: There is no direction register bit for P85. (2) Port registers Figure 1.23.6 shows the port registers. These registers are used to write and read data for input and output to and from an external device. A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port registers corresponds one for one to each I/O pin. (3) Pull-up control registers Figure 1.23.7 shows the pull-up control registers. The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. However, in memory expansion mode and microprocessor mode, P0 to P5 operate as the bus and the pull-up control register setting is invalid. (4) Port control register Figure 1.23.8 shows the port control register. The bit 0 of port control resister is used to read port P1 as follows: 0 : When port P1 is input port, port input level is read. When port P1 is output port , the contents of port P1 register is read. 1 : The contents of port P1 register is read always. This register is valid in the following: * External bus width is 8 bits in microprocessor mode or memory expansion mode. * Port P1 can be used as a port in multiplexed bus for the entire space. 163 Mitsubishi microcomputers M16C / 62T Group Programmable I/O Port P00 to P07, P20 to P27 P30 to P37, P40 to P47, P50 to P54, P56 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up selection inside dotted-line included Direction register inside dotted-line not included Data bus Port latch (Note 1) Analog Input Pull-up selection P10 to P14(inside dotted-line not included) P15 to P17(inside dotted-line included) Direction register Port P1 control register Data bus Port latch (Note 1) Input to respective peripheral functions Pull-up selection P55, P62, P66, P77, P91, P97 Direction register Data bus Port latch (Note 1) Input to respective peripheral functions P63, P67(inside dotted-line not included) P57, P60, P61, inside dotted-line P64, P65, included P72 to P76, P80, P81, P90, P92 Data bus Pull-up selection Direction register "1" Output Port latch (Note 1) Input to respective peripheral functions Note 1: symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. Note 2: In M30623(80-pin package), P10 to P17, P44 to P47, P72 to P75, and P91 are not connected to external pin. Figure 1.23.1. Programmable I/O ports (1) 164 Mitsubishi microcomputers M16C / 62T Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Direction register P70, P71 "1" Port latch Data bus Output (Note 2) Input to respective peripheral functions P82 to P84 Pull-up selection Direction register Data bus Port latch (Note 1) Input to respective peripheral functions P86 Pull-up selection Direction register "1" Data bus Port latch Output (Note 1) Rd Rf Pull-up selection P87 Direction register Data bus fc Port latch (Note 1) Note 1: symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. Note 2: symbolizes a parasitic diode. Note 3: In M30623(80-pin package), P10 to P17, P44 to P47, P72 to P75, and P91 are not connected to external pin. Figure 1.23.2. Programmable I/O ports (2) 165 Mitsubishi microcomputers M16C / 62T Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER P85 Data bus (Note 1) NMI interrupt input P93, P94 Pull-up selection D-A output enabled Direction register Data bus Port latch (Note 1) Input to respective peripheral functions Analog output D-A output enabled P95(inside dotted-line included) P96(inside dotted-line not included) Pull-up selection Direction register "1" Data bus Port latch Output (Note 1) Analog input Input to respective peripheral functions P100 to P103 (inside dotted-line not included) P104 to P107 (inside dotted-line included) Data bus Pull-up selection Direction register Port latch (Note 1) Analog input Input to respective peripheral functions Note 1: symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. Note 2: In M30623(80-pin package), P10 to P17, P44 to P47, P72 to P75, and P91 are not connected to external pin. Figure 1.23.3. Programmable I/O ports (3) 166 Mitsubishi microcomputers M16C / 62T Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER RESET RESET signal input (Note 1) BYTE Mask ROM version(inside dotted-line not included) Onetime PROM version(inside dotted-line included) BYTE signal input (Note 1) CNVSS CNVSS signal input (Note 1) To circuit of PROM-programming Note 1: symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each pin. Figure 1.23.4. I/O pins 167 Mitsubishi microcomputers M16C / 62T Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Port Pi direction register (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PDi (i = 0 to 10, except 8) Bit symbol Address 03E216, 03E316, 03E616, 03E716, 03EA16 03EB16, 03EE16, 03EF16, 03F316, 03F616 Bit name PDi_0 Port Pi0 direction register PDi_1 Port Pi1 direction register PDi_2 Port Pi2 direction register PDi_3 PDi_4 Port Pi3 direction register Port Pi4 direction register PDi_5 Port Pi5 direction register PDi_6 Port Pi6 direction register PDi_7 Port Pi7 direction register Function When reset 0016 AA A A A A AA AA A A A AA A AA A A RW 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 0 to 10 except 8) Note 1: Set bit 2 of protect register (address 000A16) to "1" before rewriting to the port P9 direction register. Note 2: In M30623(80-pin package), P1, P44 to P47, P72 to P75, and P91 are not connected to external pin, But exist inside microcomputer. So set these ports for output mode. Port P8 direction register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PD8 Bit symbol PD8_0 Address 03F216 Bit name When reset 00X000002 Function Port P80 direction register PD8_1 Port P81 direction register PD8_2 Port P82 direction register PD8_3 Port P83 direction register 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) PD8_4 Port P84 direction register Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. PD8_6 Port P86 direction register PD8_7 Port P87 direction register Figure 1.23.5. Direction register 168 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) A A A AA A A AA A A AA A A AA RW Mitsubishi microcomputers M16C / 62T Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Port Pi register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Pi (i = 0 to 10, except 8) Bit symbol Address 03E016, 03E116, 03E416, 03E516, 03E816 03E916, 03EC16, 03ED16, 03F116, 03F416 Bit name Pi_0 Port Pi0 register Pi_1 Pi_2 Port Pi1 register Port Pi2 register Pi_3 Port Pi3 register Pi_4 Port Pi4 register Pi_5 Port Pi5 register Pi_6 Port Pi6 register Pi_7 Port Pi7 register Function Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : "L" level data 1 : "H" level data (Note) (i = 0 to 10 except 8) When reset Indeterminate Indeterminate A A A AA A AA A A A A AA RW Note 1: Since P70 and P71 are N-channel open drain ports, the data is high-impedance. Note 2: In M30623(80-pin package), P1, P44 to P47, P72 to P75, and P91 are not connected to external pin, But exist inside microcomputer. So set these ports for output mode. Port P8 register b7 b6 b5 b4 b3 b2 b1 b0 Symbol P8 Bit symbol Address 03F016 Bit name P8_0 Port P80 register P8_1 Port P81 register P8_2 Port P82 register P8_3 Port P83 register P8_4 Port P84 register P8_5 Port P85 register P8_6 Port P86 register P8_7 Port P87 register When reset Indeterminate Function Data is input and output to and from each pin by reading and writing to and from each corresponding bit (except for P85) 0 : "L" level data 1 : "H" level data A A A AA A AA A A A A AA A A A AA R W Figure 1.23.6. Port register 169 Mitsubishi microcomputers M16C / 62T Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR0 Address 03FC16 Bit symbol Bit name PU00 P00 to P03 pull-up PU01 P04 to P07 pull-up PU02 P10 to P13 pull-up PU03 P14 to P17 pull-up PU04 P20 to P23 pull-up PU05 P24 to P27 pull-up PU06 P30 to P33 pull-up PU07 P34 to P37 pull-up When reset 0016 Function AA A AA A AA A AA A AA A RW The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high Note 1: In M30623(80-pin package), P1 is not connected to external pin, but exist inside microcomputer. so set this port for output mode. Pull-up control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR1 Address 03FD16 Bit symbol Bit name PU10 P40 to P43 pull-up PU11 P44 to P47 pull-up PU12 P50 to P53 pull-up PU13 P54 to P57 pull-up PU14 P60 to P63 pull-up PU15 P64 to P67 pull-up PU16 P70 to P73 pull-up (Note 1) When reset 0016 (Note 2) Function AA A AA A AA A AA A AA A R W The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high PU17 P74 to P77 pull-up Note 1: Since P70 and P71 are N-channel open drain ports, pull-up is not available for them. Note 2: When the VCC level is being impressed to the CNVSS terminal, this register becomes to 0216 when reset (PU11 becomes to "1"). Note 3: In M30623(80-pin package), P44 to P47, and P72 to P75 are not connected to external pin, but exist inside microcomputer. So set these ports for output mode. Pull-up control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR2 Address 03FE16 Bit symbol Bit name PU20 P80 to P83 pull-up PU21 P84 to P87 pull-up (Except P85) PU22 P90 to P93 pull-up PU23 PU24 P94 to P97 pull-up P100 to P103 pull-up PU25 P104 to P107 pull-up When reset 0016 Function AA A AA A AA A AA A AA A RW The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". Note 1: In M30623(80-pin package), P1 is not connected to external pin, but exist inside microcomputer. so set this port for output mode. Figure 1.23.7. Pull-up control register 170 Mitsubishi microcomputers M16C / 62T Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Port control register b7 b6 b5 b4 b3 b2 b1 b0 Symbpl PCR Address 03FF16 Bit symbol PCR0 Bit name Port P1 control register When reset 0016 R W Function 0 : When input port, read port input level. When output port, read the contents of port P1 register. 1 : Read the contents of port P1 register though input/output port. AA A Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". Figure 1.23.8. Port control register 171 Mitsubishi microcomputers M16C / 62T Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.23.1. Example connection of unused pins in single-chip mode Pin name Connection Ports P0 to P10 (excluding P85) (Note 1) After setting for input mode, connect every pin to VSS or VCC via a resistor; or after setting for output mode, leave these pins open. XOUT Open (Note 2) ______ NMI Connect via resistor to VCC (pull-up) AVCC Connect to VCC AVSS , VREF, BYTE CNVSS Connect to VSS Connect via resistor to VSS (pull-down) Note 1: In M30623(80-pin package), P1 P44 to P47, P72 to P75, and P9 1 are not connected to external pin, but exist inside microcomputer. So set these ports for output mode. Note 2: With external clock input to XIN pin. Table 1.23.2. Example connection of unused pins in memory expansion mode and microprocessor mode Pin name Connection Ports P6 to P10 (excluding P85) (Note 1) After setting for input mode, connect every pin to VSS or VCC via a resistor; or after setting for output mode, leave these pins open. ______ ______ P45/CS1 to P47/CS3 _______ Sets ports to input mode, sets bits CS1 throuth CS3 to 0, and connects to VCC via resistors (pull-up). _________ BHE, ALE, HLDA, XOUT (Note 2), BCLK __________ _______ Open _______ HOLD, RDY, NMI AVCC Connect via resistor to VCC (pull-up) Connect to VCC AVSS , VREF CNVSS Connect to VSS Connect via resistor to VSS (pull-down) in the memory expansion mode. Connect via resistor to VCC (pull-up) in the microprocessor mode. Note 1: In M30623(80-pin package), P72 to P75, and P91 are not connected to external pin, but exist inside microcomputer. So set these ports for output mode. Note 2: With external clock input to XIN pin. Note 3: The M16C/62T group is not guaranteed to operate in memory expansion and microprocessor modes. Microcomputer Microcomputer Input mode Input mode Port P0 to P10 (except for P85) Input mode Output mode Port P6 to P10 (except for P85) Open NMI XOUT Port P45/CS1 to P47/CS3 Open VCC 0.47F In single-chip mode NMI BHE HLDA ALE XOUT BCLK HOLD RDY CNVSS(microprocessor mode) AVCC AVSS VREF CNVSS(memory expansion mode) AVCC BYTE AVSS VREF CNVSS Input mode Output mode VSS Open Open VCC 0.47F VSS In memory expansion mode or in microprocessor mode Note 1: In M30623(80-pin package), P1, P4 4 to P47, P72 to P75, and P91 are not connected to external pin, but exist inside microcomputer. So set these ports for output mode. Note 2: With external clock input to X IN pin. Note 3: The M16C/62T group is not guaranteed to operate in memory expansion and microprocessor modes. Figure 1.23.9. Example connection of unused pins 172 Mitsubishi microcomputers M16C / 62T Group Usage precaution SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Usage Precaution Timer A (timer mode) (1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing gets "FFFF 16". Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value. Timer A (event counter mode) (1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing gets "FFFF 16" by underflow or "000016" by overflow. Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value. (2) When stop counting in free run type, set timer again. Timer A (one-shot timer mode) (1) Setting the count start flag to "0" while a count is in progress causes as follows: * The counter stops counting and a content of reload register is reloaded. * The TAiOUT pin outputs "L" level. * The interrupt request generated and the timer Ai interrupt request bit goes to "1". (2) The timer Ai interrupt request bit goes to "1" if the timer's operation mode is set using any of the following procedures: * Selecting one-shot timer mode after reset. * Changing operation mode from timer mode to one-shot timer mode. * Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to "0" after the above listed changes have been made. Timer A (pulse width modulation mode) (1) The timer Ai interrupt request bit becomes "1" if setting operation mode of the timer in compliance with any of the following procedures: * Selecting PWM mode after reset. * Changing operation mode from timer mode to PWM mode. * Changing operation mode from event counter mode to PWM mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to "0" after the above listed changes have been made. (2) Setting the count start flag to "0" while PWM pulses are being output causes the counter to stop counting. If the TAi OUT pin is outputting an "H" level in this instance, the output level goes to "L", and the timer Ai interrupt request bit goes to "1". If the TAiOUT pin is outputting an "L" level in this instance, the level does not change, and the timer Ai interrupt request bit does not becomes "1". Timer B (timer mode, event counter mode) (1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. Reading the timer Bi register with the reload timing gets "FFFF 16". Reading the timer Bi register after setting a value in the timer Bi register with a count halted but before the counter starts counting gets a proper value. 173 Mitsubishi microcomputers M16C / 62T Group Usage precaution SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B (pulse period/pulse width measurement mode) (1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt request bit goes to "1". (2) When the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. At this time, timer Bi interrupt request is not generated. A-D Converter (1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs). In particular, when the Vref connection bit is changed from "0" to "1", start A-D conversion after an elapse of 1 s or longer. (2) When changing A-D operation mode, select analog input pin again. (3) Using one-shot mode or single sweep mode Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by AD conversion interrupt request bit.) (4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 Use the undivided main clock as the internal CPU clock. Stop Mode and Wait Mode ____________ (1) When returning from stop mode by hardware reset, RESET pin must be set to "L" level until main clock oscillation is stabilized. (2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the WAIT instruction or from the instruction that sets the every-clock stop bit to "1" within the instruction queue are prefetched and then the program stops. So put at least four NOPs in succession either to the WAIT instruction or to the instruction that sets the every-clock stop bit to "1". Interrupts (1) Reading address 00000 16 * When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 00000 16 will then be set to "0". Reading address 0000016 by software sets enabled highest priority interrupt source request bit to "0". Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 0000016 by software. (2) Setting the stack pointer * The value of the stack pointer immediately after reset is initialized to 0000 16. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. _______ When using the NMI interrupt, initialize the stack point at the beginning of a program. Concerning _______ the first instruction immediately after reset, generating any interrupts including the NMI interrupt is prohibited. _______ (3) The NMI interrupt _______ * As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the V CC pin via a resistor (pull-up) if unused. Be sure to work on it. _______ * Do not get either into stop mode with the NMI pin set to "L". 174 Mitsubishi microcomputers M16C / 62T Group Usage precaution SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (4) External interrupt _______ _______ * When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". _______ _______ Note 1: In M30623 (80-pin package), can not use INT3 to INT5 as the interrupt factors, because _______ _______ P15/D13/INT3 to P17/D15/INT5 have no corresponding external pin. (5) Rewrite the interrupt control register * To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: Example 1: INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. * When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET 175 Mitsubishi microcomputers M16C / 62T Group Usage precaution SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Usage precaution of built-in PROM version (1) All built-in PROM versions High voltage is required to program to the built-in PROM. Be careful not to apply excessive voltage. Be especially careful during power-on. (2) One Time PROM version One Time PROM versions shipped in blank (M30622ECTFP/ECVFP, M30623ECTGP/ECVGP), of which built-in PROMs are programmed by users, are also provided. For these microcomputers, a programming test and screening are not performed in the assembly process and the following processes. To improve their reliability after programming, we recommend to program and test as flow shown in Figure 1.24.1 before use. But, in case of using as the test of cars loading, mass production, correspond to programming PROM, and screened shipped in programming, please require. Programming with PROM programmer Screening (Note 1) (Leave at 150C for 40 hours) Verify test PROM programmer ROM data check in all numbers, target device (high temperature, low temperature) (Note 2) Vcc=5.5V, 5.0V, 4.5V Note 1: Never expose to 150C exceeding 100 hours. Note 2: Test in responce to using temperature limit. Figure 1.24.1. Programming and test flow for One Time PROM version 176 Mitsubishi microcomputers M16C / 62T Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Items to be submitted when ordering masked ROM version Please submit the following when ordering masked ROM products: (1) Mask ROM confirmation form (2) Mark specification sheet (3) ROM data : EPROMs or floppy disks *: In the case of EPROMs, there sets of EPROMs are required per pattern. *: In the case of floppy disks, 3.5-inch double-sided high-density disk (IBM format) is required per pattern. 177 Mitsubishi microcomputers M16C / 62T Group Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.26.1. Absolute maximum ratings Symbol Vcc AVcc VI Parameter Supply voltage Analog supply voltage RESET, VREF, XIN Input P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37, P40 to P43, P50 to P57, P60 to P67, P72 to P77, P80 to P87, P90 to P97, P100 to P107 P70, P71 CNVSS, BYTE Output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37,P40 to P43, P50 to P57, Condition AVCC=VCC, AVSS=VSS AVCC=VCC, AVSS=VSS 40C < Ta 85C 85C <Ta 125C Pd Power dissipation Topr Tstg Operating ambient temperature Storage temperature Unit Mask ROM version 0.3 to 6.5 0.3 to 6.5 V V 0.3 to Vcc+0.3 0.3 to Vcc+0.3 0.3 to 7 0.3 to 7 (Note 1) 0.3 to Vcc+0.3 V V 0.3 to Vcc+0.3 V 0.3 to 6.5 0.3 to Vcc+0.3 P60 to P67,P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107, XOUT P70, P71, VO Rated value One-time PROM version 0.3 to 7 0.3 to 7 0.3 to 7 300 200 V V 0.3 to 6.5 300 200 mW 40 to 125 (Note 2) 40 to 125 (Note 2) 65 to 150 65 to 150 C C Note 1: When writing to EPROM ,only CNVss is -0.3 to 13.5 (V) . Note 2: In case of 85C guaranteed version, -40C to 85C. In case of 125C guaranteed version, -40C to 125C. Note 3: In M30623(80-pin package), P10 to P17, P44 to P47,P7 2 to P75,and P9 1 are not connected to the external pin. Table 1.26.2. Recommended operating conditions (referenced to V CC = 4.2V (Note at Ta = - 40 oC to 125oC(Note 2) unless otherwise specified) Symbol Vcc AVcc Vss AVss VIH VIH VIL VIL Parameter Supply voltage Analog supply voltage Supply voltage Analog supply voltage HIGH input P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, voltage XIN, RESET, CNVSS, BYTE HIGH input voltage P00 to P07, P10 to P17 (during single-chip mode) 0.8Vcc Vcc V V 0 0.2Vcc V LOW input voltage 0 0.2Vcc V -10 mA -5 mA 10 mA 5 mA 16 MHz 50 kHz Subclock oscillation frequency I OL (avg) V V V V 5.0 Vcc 0 0 Vcc f (XcIN) I OL (peak) Unit 5.5 4.2 (Note 1) 0.8Vcc f (XIN) I OH (avg) Standard Typ. Max. to 5.5V LOW input P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, voltage XIN, RESET, CNVSS, BYTE P00 to P07, P10 to P17 (during single-chip mode) P00 to P07, P10 to P17, P20 to P27,P30 to P37, P40 to P47, P50 to P57, P60 to P67,P72 to P77, P80 to P84,P86,P87,P90 to P97,P100 to P107 (Note 4) HIGH average output P00 to P07, P20 to P27,P30 to P37, P40 to P47, P50 to P57, P60 to P67,P72 to P77, current P80 to P84,P86,P87,P90 to P97,P100 to P107 P00 to P07, P20 to P27,P30 to P37, LOW peak output P40 to P47, P50 to P57, P60 to P67,P70 to P77, current P80 to P84,P86,P87,P90 to P97,P100 to P107 (Note 4) P00 to P07, P20 to P27,P30 to P37, LOW average P40 to P47, P50 to P57, P60 to P67,P70 to P77, output current P80 to P84,P86,P87,P90 to P97,P100 to P107 Main clock input oscillation frequency Vcc=4.2V (Note 1) to 5.5V I OH (peak) Min 1) HIGH peak output current 32.768 Note 1: In case of One-time PROM version, 4.5V. Note 2: In case of 85C guaranteed version, -40C to 85C. In case of 125C guaranteed version, -40C to 125C. Note 3: The mean output current is the mean value within 100ms. Note 4: In M30622(100-pin package), the total IOL (peak) and the total IOH (peak) for ports P0, P1, P2, P8 6, P87, P9, and P10 and the total IOL (peak) and the total IOH (peak) for ports P3, P4, P5, P6, P7, and P80 to P84 severally must be 80mA max. In M30623(80-pin package), Vcc pin and Vss pin are each one pin, so the total IOL (peak) and the total I OH (peak) for all ports must be 80mA max. Note 5: The loss power effect of the whole part-port(the output port transistor and the pull-up resistor) must be 50mW max, so that power dissipation at Ta=125C(include Ta >85C) doesn't exceed absolute maximum ratings. Note 6: In M30623(80-pin package), P10 to P17, P44 to P47,P7 2 to P75, and P91 are not connected to the external pin. 178 Mitsubishi microcomputers M16C / 62T Group Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.26.3. Electrical characteristics (referenced to VCC = 5V, VSS = 0V at Ta = -40oC to 125oC(Note 1), f(XIN) = 16MHZ unless otherwise specified) Parameter Symbol Measuring condition Standard Min Typ. Max. Unit VOH HIGH output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37, P40 to P47, P50 to P57, IOH= 5mA P60 to P67, P72 to P77, P80 to P84, Vcc=4.0V to 5.5V P86, P87, P90 to P97, P100 to P107 0.6Vcc V VOH HIGH output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37, P40 to P47, P50 to P57, IOH= 200A P60 to P67, P72 to P77, P80 to P84, Vcc=4.0V to 5.5V P86, P87, P90 to P97, P100 to P107 0.9Vcc V VOH HIGH output voltage VOL VOL VOL 3.0 IOH= 1mA IOH= 0.5mA With no load applied HIGHPOWER HIGH output XCOUT LOWPOWER With no load applied voltage LOW output P00 to P07, P10 to P17, P20 to P27, IOL=5mA voltage P30 to P37, P40 to P47, P50 to P57, Vcc=4.0V to 5.5V P60 to P67, P70 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 LOW output P00 to P07, P10 to P17, P20 to P27, IOL=200A voltage P30 to P37, P40 to P47, P50 to P57, Vcc=4.0V to 5.5V P60 to P67, P70 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 LOWPOWER LOW output voltage XOUT LOW output voltage XCOUT Hysteresis VT+-VT- VT+-VT- Hysteresis VT+-VT- Hysteresis V 3.0 3.0 1.6 V 0.4Vcc V 0.1Vcc V HIGHPOWER IOL=1mA 2.0 LOWPOWER HIGHPOWER IOL=0.5mA With no load applied With no load applied 2.0 LOWPOWER 0 0 V V TA0IN to TA4IN, TA0OUT to TA4OUT, TB0IN to TB5IN, INT0 to INT5, P82 to P84, ADTRG, CTS0 to CTS2, CLK0 to CLK4, RXD0 to RXD2, SIN3, SIN4, KI0 to KI3, NMI 0.2 0.8 V RESET, CNVss, BYTE 0.5 1.5 V 0.2 0.8 V HIGH input current P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, VI=5V P90 to P97, P100 to P107, XIN, RESET, CNVss, BYTE 5 A LOW input current P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, No pull-up resistance P60 to P67, P70 to P77, P80 to P87, VI=0V P90 to P97, P100 to P107, XIN, RESET, CNVss, BYTE 5 A 150 A IIH I IL I IL HIGHPOWER XOUT LOW input current XIN P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, Pull-up resistance P60 to P67, P72 to P77, P80 to P84, VI=0V P86, P87, P90 to P97, P100 to P107 70 100 R fXIN R fXCIN Feedback resistance XIN 1.0 M Feedback resistance XCIN 6.0 M V RAM retention voltage RAM Icc Power supply current When clock is stopped In single-chip mode, the output pins are open and other pins are Vss 2 V f(XIN)=16MHz, Square wave, diveide-by-1, no-wait 28 f(XIN)=16kHz, Square wave, diveide-by-1, 1-wait 24 mA f(XIN)=16kHz, Square wave, diveide-by-8, no-wait 6.7 mA f(XCIN)=32kHz When a WAIT instruction is executed, Ta=25C Ta=25C when clock is stopped 38 A 4.0 2 Ta=85C when clock is stopped Ta=125C when clock is stopped mA 20 A 50 Note 1: In case of 85C guaranteed version, -40C to 85C. In case of 125C guaranteed version, -40C to 125C. Note 2: In M30623(80-pin package), P10 to P17, P44 to P47,P7 2 to P75, and P91 are not connected to the external pin. 179 Mitsubishi microcomputers M16C / 62T Group Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.26.4. A-D conversion characteristics (referenced to VCC = AVCC= 5V, Vss = AVSS = 0V, Ta = 25oC, f(XIN) = 16MHZ unless otherwise specified) Standard Symbol Parameter Measuring condition Unit Min. Typ. Max. 10 Bits Resolution VREF = VCC = 5V LSB VREF = AVCC = VCC = 5V, AD10MHz Absolute accuracy(8bit) 2 Sample & hold function not available Absolute accuracy Sample & hold function available (10bit) RLADDER Ladder resistance VREF = AVCC = VCC = 5V, AD10MHz VREF=AVCC AN0 to AN7,AN00 to AN07, =VCC AN20 to AN27, =5V ANEX0, ANEX1 input AD10MHz External op-amp connection mode VREF = VCC = 5V f(XIN)=16MHz, AD = fAD/2 = 8MHz tCONV Conversion time(10bit) tCONV Conversion time(8bit) tSAMP Sampling time f(XIN)=10MHz, AD = fAD = 10MHz f(XIN)=16MHz, AD = fAD/2 = 8MHz f(XIN)=10MHz, AD = AD = 10MHz f(XIN)=16MHz, AD = fAD/2 = 8MHz f(XIN)=10MHz, AD = fAD = 10MHz 10 3 LSB 3 LSB 7 LSB 40 k 4.125 3.3 3.5 2.8 0.375 0.3 2 0 s s s VCC Reference voltage VREF Analog input voltage Note 1: Divide the frequency if f(XIN) exceeds 10 MHz, and make AD equal to or lower than 10 MHz. VREF VIA V V Table 1.26.5. D-A conversion characteristics (referenced to V CC = 5V, V SS = AV SS = 0V, VREF = 5V at Ta = 25oC, f(XIN) = 16MHZ unless otherwise specified) Symbol Parameter Measuring condition Min. Standard Typ. Max. Unit Resolution Bits 8 % 1.0 Absolute accuracy tsu s 3 Setup time RO Output resistance 4 10 20 k IVREF mA 1.5 Reference power supply input current (Note 1) Note 1: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to "0016". The A-D converter's ladder resistance is not included. Note 2: When the Vref is unconnected at the A-D control register, I VREF is sent. When not using D-A converter, with the D-A register for the unused D-A converter set to "0016", so that prevent dissipation of unnecessary reference power supply current. 180 Mitsubishi microcomputers M16C / 62T Group Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing requirements Referenced to VCC = 5V, VSS = 0V at Ta = -40oC to 85oC (85oC guaranteed version), or Ta = -40oC to 125oC (125oC guaranteed version) unless otherwise specified. Table 1.26.6. External clock input Symbol Parameter tc External clock input cycle time tw(H) tw(L) External clock input HIGH pulse width tr tf External clock input LOW pulse width External clock rise time External clock fall time Standard Min. Max. Unit ns 62.5 25 25 ns ns 15 15 ns ns _______ Table 1.26.7. External interrupt INTi inputs Symbol Parameter tw(INH) INTi input HIGH pulse width tw(INL) INTi input LOW pulse width Standard Min. Max. 250 250 Unit ns ns Table 1.26.8. Timer A input (counter input in event counter mode) Symbol Parameter tc(TA) TAiIN input cycle time tw(TAH) TAiIN input HIGH pulse width tw(TAL) TAiIN input LOW pulse width Standard Min. Max. 150 60 60 Unit ns ns ns Table 1.26.9. Timer A input (gating input in timer mode) Symbol Parameter tc(TA) TAiIN input cycle time tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Standard Min. Max. 400 200 200 Unit ns ns ns Table 1.26.10. Timer A input (external trigger input in one-shot timer mode) Symbol tc(TA) tw(TAH) tw(TAL) Parameter Standard Min. Max. Unit TAiIN input cycle time 200 ns TAiIN input HIGH pulse width TAiIN input LOW pulse width 100 100 ns ns Table 1.26.11. Timer A input (external trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) Parameter TAiIN input HIGH pulse width TAiIN input LOW pulse width Standard Min. Max. 100 100 Unit ns ns Table 1.26.12. Timer A input (up/down input in event counter mode) tc(UP) TAiOUT input cycle time Standard Min. Max. 2000 tw(UPH) TAiOUT input HIGH pulse width 1000 ns tw(UPL) tsu(UP-TIN) TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time 1000 400 ns Symbol th(TIN-UP) Parameter 400 Unit ns ns ns 181 Mitsubishi microcomputers M16C / 62T Group Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing requirements Referenced to V CC = 5V, V SS = 0V at Ta = - 40o C to 85o C(85oC guaranteed version), or Ta = - 40oC to 125oC(125oC guaranteed version) unless otherwise specified. Table 1.26.13. Timer B input (counter input in event counter mode) Symbol Standard Parameter Min. Max. Unit 150 ns TBiIN input HIGH pulse width (counted on one edge) 60 ns TBiIN input LOW pulse width (counted on one edge) ns TBiIN input cycle time (counted on both edges) 60 300 TBiIN input HIGH pulse width (counted on both edges) 120 ns TBiIN input LOW pulse width (counted on both edges) 120 ns tc(TB) TBiIN input cycle time (counted on one edge) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) ns Table 1.26.14. Timer B input (pulse period measurement mode) Symbol Standard Parameter Min. Max. Unit tc(TB) TBiIN input cycle time 400 ns tw(TBH) tw(TBL) TBiIN input HIGH pulse width TBiIN input LOW pulse width 200 200 ns ns Table 1.26.15. Timer B input (pulse width measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) Standard Parameter Min. Max. Unit ns TBiIN input cycle time 400 TBiIN input HIGH pulse width 200 ns 200 ns TBiIN input LOW pulse width Table 1.26.16. Serial I/O Symbol tc(CK) tw(CKH) Standard Parameter Min. Max. Unit CLKi input cycle time 250 ns CLKi input HIGH pulse width 125 ns CLKi input LOW pulse width 125 tw(CKL) td(C-Q) TxDi / SOUTi output delay time th(C-Q) TxDi / SOUTi hold time tsu(D-C) RxDi / SINi input setup time When external clock is selected When external clock is selected th(C-D) RxDi / SINi input hold time When external clock is selected When external clock is selected ns 100 ns ns 0 45 120 120 ns ns ns ns 45 Table 1.26.17. A-D trigger input Symbol tc(AD) tw(ADL) 182 Parameter ADTRG input cycle time (trigger able minimum) ADTRG input LOW pulse width Standard Min. 1000 125 Max. Unit ns ns Mitsubishi microcomputers M16C / 62T Group Timing Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER P0 P1 P2 30pF P3 P4 P5 P6 P7 P8 P9 P10 Figure 1.26.1. Port P0 to P10 measurement circuit 183 Mitsubishi microcomputers M16C / 62T Group Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Vcc=5V tw(INL) INTi input tw(INH) tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input th(TIN-UP) (When count on falling edge is selected) tsu(UP-TIN) TAiIN input (When count on rising edge is selected) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(CK) tw(CKH) CLKi tw(CKL) th(C-Q) TxDi / SOUTi td(C-Q) RxDi / SINi tc(AD) tw(ADL) ADTRG input Figure 1.26.2. Timing 184 tsu(D-C) th(C-D) Mitsubishi microcomputers M16C / 62T Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Differences between M16C/62T group and M16C/61T group Group M16C/62T group M16C/61T group Memory space (Note 1) Memory expansion is possible 1.2M bytes mode 4M bytes mode 1M byte fixed Timer B 6 channels 3 channels Serial I/O UART/clocked SI/O * * * * * 3 channel UART/clocked SI/O * * * * * 3 channels (80-pin package: One of exclusive UART) (80-pin package: One of exclusive UART) Clocked SI/O * * * * * * * * * * 2 channel (80-pin package: One of exclusive transmission) IIC bus mode UART2 used IIC bus interface can be performed with software Impossible Port function P90 P91 P92 P93 P94 P95 P96 P97 P15 P16 P17 P71 P90 P91 P92 P93 P94 P95 P96 P97 P15 P16 P17 P71 Interrupt cause Internal 25 sources, External 8 sources (80-pin package: 5 sources), Software 4 sources (Added 2 Serial I/O, 3 timers and 3external interrupts (Note 2)) * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * TB0IN/CLK3 TB1IN/SIN3 TB2IN/SOUT3 TB3IN/DA0 TB4IN/DA1 ANEX0/CLK4 ANEX1/SOUT4 ADTRG/SIN4 (Note 2) D13/INT3 (Note 2) D14/INT4 (Note 2) D15/INT5 RXD2/TA0IN/TB5IN * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * TB0IN TB1IN TB2IN DA0 DA1 ANEX0 ANEX1 ADTRG D13 (Note 2) D14 (Note 2) D15 (Note 2) RXD2/TA0IN Internal 20 sources External 5 sources Software 4 sources Chip select M16C/61T type (wrinting the right) and (Note 1) (Note 2) the type as below can be switched (Besides 4M-byte mode is possible.) CS0 : 0400016 to 3FFFF16 (fetch) 4000016 to FFFFF16 (data/facth) CS1 : 2800016 to 2FFFF16 (data) CS2 : 0800016 to 27FFF16 (data) CS3 : 0400016 to 07FFF16 (data) CS0 : 3000016 CS1 : 2800016 CS2 : 0800016 CS3 : 0400016 Three-phase inverter control circuit (Note 2) PWM output for three-phase inverter can be performed using timer A4, A1 and A2. Output port is arranged to P72 to P75, P80 and P81. Impossible Read port P1 By setting to register, the state of port register can be read always. The state of port when input mode. The state of port register when output mode. (Note 2) If a Vcc level is applied to the CNVss P44/CS0 - P47/CS3 pin, bit 2 (PU11) of pull-up control (Note 1) (Note 2) register 1 turns to "1" when reset, and P44/ CS0 - P47/ CS3 turn involved in pull-up. to to to to FFFFF16 2FFFF16 27FFF16 07FFF16 Bit 2 (PU11) of the pull-up control register 1 turns to "0" when reset, and P44/ CS0 - P47/ CS3 turn free from pullup. Note 1: M16C/61T group, and M16C/62T group are not guaranteed operating of memory expansion, but it is mentioned in the table for clear the difference of capacity. Note 2: In 80-pin package(M30613, M30623), pins of a part are not connected to the external pin, so do not use these functions and pins. 185 Mitsubishi microcomputers M16C / 62T Group Revision History SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Version Rev.A1 Contents for change Page 133 Add Figure 1.19.17. Page 145 Figure 1.19.30. Add to "SI/Oi bit rate generator" and "SI/Oi transmit/receive register." Revision history 186 M16C/62T Group data sheet Revision date 1999.8.30 MITSUBISHI SEMICONDUCTORS M16C/62T Group Tentative Specification REV.A1 Aug First Edition 1999 Editioned by Committee of editing of Mitsubishi Semiconductor Published by Mitsubishi Electric Corp., Kitaitami Works This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. (c)1999 MITSUBISHI ELECTRIC CORPORATION