D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D 32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash and 8 kB SRAM R R R D D D F FT FT A A Objective data sheet A Rev. 00.11 -- 13 November 2009 FT FT FT FT FT LPC1111/12/13/14 D FT FT A A R R D D D R A FT 1. General description D R The LPC1111/12/13/14 operate at CPU frequencies of up to 50 MHz. The peripheral complement of the LPC1111/12/13/14 includes up to 32 kB of flash memory, up to 8 kB of data memory, one Fast-mode Plus I2C-bus interface, one RS-485/EIA-485 UART, up to two SPI interfaces with SSP features, four general purpose timers, a 10-bit ADC, and up to 42 general purpose I/O pins. 2. Features ARM Cortex-M0 processor, running at frequencies of up to 50 MHz. ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC). 32 kB (LPC1114), 24 kB (LPC1113), 16 kB (LPC1112), or 8 kB (LPC1111) on-chip flash programming memory. 8 kB, 4 kB, or 2 kB SRAM. In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. Serial interfaces: UART with fractional baud rate generation, internal FIFO, and RS-485 support. Two SPI controllers with SSP features and with FIFO and multi-protocol capabilities (second SPI on LQFP48 and PLCC44 packages only). I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode. Other peripherals: Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors. Four general purpose timers/counters with a total of four capture inputs and 13 match outputs. Programmable WatchDog Timer (WDT). System tick timer. Serial Wire Debug. High-current output driver (20 mA) on one pin. High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus. A The LPC1111/12/13/14 are a ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. D D R R R R R D D D A A A A A FT FT FT FT FT LPC1111/12/13/14 D R R A A FT FT FT FT A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, and Deep power-down modes. Three reduced power modes: Sleep, Deep-sleep, and Deep power-down. Single 3.3 V power supply (1.8 V to 3.6 V). 10-bit ADC with input multiplexing among 8 pins. GPIO pins can be used as edge and level sensitive interrupt sources. Clock output function with divider that can reflect the system oscillator clock, IRC clock, CPU clock, and the Watchdog clock. Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 13 of the functional pins. Brownout detect with four separate thresholds for interrupt and one threshold for forced reset. Power-On Reset (POR). Crystal oscillator with an operating range of 1 MHz to 25 MHz. 12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock. PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the watchdog oscillator. Available as 48-pin LQFP package, 33-pin HVQFN package, and 44-pin PLCC package. D FT FT A A R R D D D R A Table 1. Ordering information Type number Package Name Description Version LPC1111FHN33/101 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1111FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1112FHN33/101 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1112FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1113FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1113FHN33/301 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 2 of 53 A 4. Ordering information R eMetering Lighting Industrial networking Alarm systems White goods D FT 3. Applications D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1114FHN33/301 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm n/a LPC1113FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x sot313-2 1.4 mm LPC1114FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x sot313-2 1.4 mm LPC1114FA44/301 PLCC44 PLCC44; plastic leaded chip carrier; 44 leads F HVQFN33 R LPC1114FHN33/201 FT FT A A R Version D D Description D D R A FT D R A sot187-2 4.1 Ordering options Ordering options Flash Total SRAM UART RS-485 I2C/ Fast+ SPI ADC channels Package LPC1111FHN33/101 8 kB 2 kB 1 1 1 8 HVQFN33 LPC1111FHN33/201 8 kB 4 kB 1 1 1 8 HVQFN33 LPC1112FHN33/101 16 kB 2 kB 1 1 1 8 HVQFN33 LPC1112FHN33/201 16 kB 4 kB 1 1 1 8 HVQFN33 LPC1113FHN33/201 24 kB 4 kB 1 1 1 8 HVQFN33 LPC1113FHN33/301 24 kB 8 kB 1 1 1 8 HVQFN33 LPC1113FBD48/301 24 kB 8 kB 1 1 2 8 LQFP48 LPC1114FHN33/201 32 kB 4 kB 1 1 1 8 HVQFN33 LPC1114FHN33/301 32 kB 8 kB 1 1 1 8 HVQFN33 LPC1114FBD48/301 32 kB 8 kB 1 1 2 8 LQFP48 LPC1114FA44/301 32 kB 8 kB 1 1 2 8 PLCC44 LPC1111 LPC1112 LPC1113 LPC1114 LPC1111_12_13_14_0 Objective data sheet A FT FT A A R R D D D Name Type number FT FT FT FT FT Package Table 2. A A A A A Ordering information ...continued Type number R R R R R Table 1. D D D D D LPC1111/12/13/14 NXP Semiconductors (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 3 of 53 D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 5. Block diagram FT FT FT FT FT LPC1111/12/13/14 NXP Semiconductors D FT FT A A R R D D D XTALIN XTALOUT RESET R SWD A FT D R A LPC1111/12/13/14 IRC TEST/DEBUG INTERFACE CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS POR ARM CORTEX-M0 clocks and controls FLASH 8/16/24/32 kB system bus slave GPIO ports PIO0/1/2/3 HIGH-SPEED GPIO CLKOUT SRAM 2/4/8 kB slave ROM slave slave AHB-LITE BUS slave AHB TO APB BRIDGE RXD TXD DTR, DSR(1), CTS, DCD(1), RI(1), RTS CT32B0_MAT[3:0] CT32B0_CAP0 CT32B1_MAT[3:0] CT32B1_CAP0 CT16B0_MAT[2:0] CT16B0_CAP0 CT16B1_MAT[1:0] CT16B1_CAP0 UART AD[7:0] 10-bit ADC SPI0 SCK0, SSEL0 MISO0, MOSI0 SPI1(1) SCK1, SSEL1 MISO1, MOSI1 32-bit COUNTER/TIMER 0 32-bit COUNTER/TIMER 1 SCL SDA I2C-BUS 16-bit COUNTER/TIMER 0 16-bit COUNTER/TIMER 1 WDT IOCONFIG SYSTEM CONTROL PMU 002aae696 (1) LQFP48 and PLCC44 packages only. Fig 1. LPC1111/12/13/14 block diagram LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 4 of 53 D D R R R R R D D D A A A A A FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R F D FT FT A A R R D 6.1 Pinning A FT FT A A R R D D D 6. Pinning information FT FT FT FT LPC1111/12/13/14 NXP Semiconductors D D R 37 PIO3_1/DSR 38 PIO2_3/RI/MOSI1 39 SWDIO/PIO1_3/AD4/CT32B1_MAT2 40 PIO1_4/AD5/CT32B1_MAT3/WAKEUP 41 VSS 42 PIO1_11/AD7 43 PIO3_2/DCD 44 VDD(3V3) 45 PIO1_5/RTS/CT32B0_CAP0 A 46 PIO1_6/RXD/CT32B0_MAT0 R 47 PIO1_7/TXD/CT32B0_MAT1 D 1 36 PIO3_0/DTR 2 35 TRST/PIO1_2/AD3/CT32B1_MAT1 RESET/PIO0_0 3 34 TDO/PIO1_1/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2 4 33 TMS/PIO1_0/AD1/CT32B1_CAP0 VSSIO 5 XTALIN 6 XTALOUT 7 VDD(IO) 8 29 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO1_8/CT16B1_CAP0 9 28 PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0 10 27 PIO0_8/MISO0/CT16B0_MAT0 32 TDI/PIO0_11/AD0/CT32B0_MAT3 31 PIO2_11/SCK0 LPC1113FBD48/301 LPC1114FBD48/301 30 PIO1_10/AD6/CT16B1_MAT1 PIO2_9 24 PIO0_7/CTS 23 PIO0_6/SCK0 22 PIO3_5 21 PIO2_5 20 PIO2_4 19 PIO3_4 18 PIO1_9/CT16B1_MAT0 17 PIO0_5/SDA 16 25 PIO2_10 PIO0_4/SCL 15 26 PIO2_2/DCD/MISO1 PIO2_8 12 PIO0_3 14 PIO2_7 11 PIO2_1/DSR/SCK1 13 Fig 2. FT 48 PIO3_3/RI A PIO2_6 PIO2_0/DTR/SSEL1 002aae697 Pin configuration LQFP48 package LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 5 of 53 R R R R R D R R 40 PIO2_3/RI/MOSI1 R A 41 SWDIO/PIO1_3/AD4/CT32B1_MAT2 D 42 PIO1_4/AD5/CT32B1_MAT3/WAKEUP FT 43 VSS A VDD(3v3) R 44 PIO1_11/AD7 D D PIO1_5/RTS/CT32B0_CAP0 FT FT 1 A A PIO1_6/RXD/CT32B0_MAT0 R R 9 37 TMS/PIO1_0/AD1/CT32B1_CAP0 XTALIN 10 36 TDI/PIO0_11/AD0/CT32B0_MAT3 35 PIO2_11/SCK0 LPC1114FA44/301 34 PIO1_10/AD6/CT16B1_MAT1 PIO1_8/CT16B1_CAP0 13 33 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO0_2/SSEL0/CT16B0_CAP0 14 32 PIO0_9/MOSI0/CT16B0_MAT1 PIO2_7 15 31 PIO0_8/MISO0/CT16B0_MAT0 PIO2_8 16 30 PIO2_2/DCD/MISO1 PIO2_1/DSR/SCK1 17 PIO2_9 28 PIO0_7/CTS 27 PIO3_5 25 PIO0_6/SCK0 26 PIO2_5 24 PIO2_4 23 PIO3_4 22 PIO1_9/CT16B1_MAT0 21 PIO0_5/SDA 20 29 PIO2_10 PIO0_3 18 F D D 38 TDO/PIO1_1/AD2/CT32B1_MAT0 VSSIO PIO0_4/SCL 19 A FT FT 2 R A A PIO1_7/TXD/CT32B0_MAT1 D R R 3 FT D D PIO2_6 A FT FT 4 R R A A PIO2_0/DTR/SSEL1 D D R R 5 FT FT D D 6 A A FT FT A A R R D D D 39 TRST/PIO1_2/AD3/CT32B1_MAT1 8 VDD(IO) 12 FT FT FT FT FT 7 002aaf020 Pin configuration PLCC44 package LPC1111_12_13_14_0 Objective data sheet A A A A A RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 XTALOUT 11 Fig 3. D D D D D LPC1111/12/13/14 NXP Semiconductors (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 6 of 53 D D R R R R R D D D D R R PIO1_11/AD7 PIO1_4/AD5/CT32B1_MAT3/WAKEUP SWDIO/PIO1_3/AD4/CT32B1_MAT2 27 26 25 A VDD(3V3) R PIO3_2 D 28 FT PIO1_5/RTS/CT32B0_CAP0 A 29 R 21 TDI/PIO0_11/AD0/CT32B0_MAT3 XTALOUT 5 20 PIO1_10/AD6/CT16B1_MAT1 VDD(IO) 6 19 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO1_8/CT16B1_CAP0 7 18 PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0 8 17 PIO0_8/MISO0/CT16B0_MAT0 14 15 16 PIO3_5 PIO0_7/CTS 13 PIO3_4 PIO0_6/SCK0 12 D D 4 PIO1_9/CT16B1_MAT0 FT FT PIO1_6/RXD/CT32B0_MAT0 A A 30 R R TMS/PIO1_0/AD1/CT32B1_CAP0 XTALIN 11 F D D 22 002aae698 Transparent top view Pin configuration HVQFN 33 package LPC1111_12_13_14_0 Objective data sheet A FT FT 3 PIO0_5/SDA R A A PIO1_7/TXD/CT32B0_MAT1 D R R 31 FT D D 32 A FT FT TDO/PIO1_1/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2 9 R R A A TRST/PIO1_2/AD3/CT32B1_MAT1 23 10 D D R R 24 2 PIO0_3 FT FT D D 1 PIO0_4/SCL A A FT FT A A R R D D D PIO2_0/DTR RESET/PIO0_0 33 VSS FT FT FT FT FT terminal 1 index area Fig 4. A A A A A LPC1111/12/13/14 NXP Semiconductors (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 7 of 53 D D R R R R D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R F D A A R R D Description I/O Port 0 -- Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. I RESET -- External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. I/O PIO0_0 -- General purpose digital input/output pin. I/O PIO0_1 -- General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. O CLKOUT -- Clockout pin. O CT32B0_MAT2 -- Match output 2 for 32-bit timer 0. I/O PIO0_2 -- General purpose digital input/output pin. O SSEL0 -- Slave Select for SPI0. FT Type FT D D R PIO0_0 to PIO0_11 A FT FT A A R R D D D Pin FT FT FT FT FT LPC1113/14 pin description table (LQFP48 package) Symbol A A A A A 6.2 Pin description Table 3. R D D D LPC1111/12/13/14 NXP Semiconductors A FT D R 3 PIO0_1/CLKOUT/ CT32B0_MAT2 4[1] A RESET/PIO0_0 PIO0_2/SSEL0/ CT16B0_CAP0 10[1] I CT16B0_CAP0 -- Capture input 0 for 16-bit timer 0. PIO0_3 14[1] I/O PIO0_3 -- General purpose digital input/output pin. PIO0_4/SCL 15[2] I/O PIO0_4 -- General purpose digital input/output pin. I/O SCL -- I2C-bus clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O PIO0_5 -- General purpose digital input/output pin. I/O SDA -- I2C-bus data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O PIO0_6 -- General purpose digital input/output pin. I/O SCK0 -- Serial clock for SPI0. PIO0_7/CTS 23[1] I/O PIO0_7 -- General purpose digital input/output pin (high-current output driver). I CTS -- Clear To Send input for UART. PIO0_8/MISO0/ CT16B0_MAT0 27[1] I/O PIO0_8 -- General purpose digital input/output pin. I/O MISO0 -- Master In Slave Out for SPI0. O CT16B0_MAT0 -- Match output 0 for 16-bit timer 0. PIO0_9/MOSI0/ CT16B0_MAT1 28[1] I/O PIO0_9 -- General purpose digital input/output pin. I/O MOSI0 -- Master Out Slave In for SPI0. O CT16B0_MAT1 -- Match output 1 for 16-bit timer 0. SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 29[1] I SWCLK -- Serial wire clock and test clock TCK for JTAG interface. PIO0_5/SDA PIO0_6/SCK0 TDI/PIO0_11/ AD0/CT32B0_MAT3 16[2] 22[1] 32[3] I/O PIO0_10 -- General purpose digital input/output pin. I/O SCK0 -- Serial clock for SPI0. O CT16B0_MAT2 -- Match output 2 for 16-bit timer 0. I TDI -- Test Data In for JTAG interface. I/O PIO0_11 -- General purpose digital input/output pin. I AD0 -- A/D converter, input 0. O CT32B0_MAT3 -- Match output 3 for 32-bit timer 0. LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 8 of 53 FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R Description I/O Port 1 -- Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. I TMS -- Test Mode Select for JTAG interface. I/O PIO1_0 -- General purpose digital input/output pin. I AD1 -- A/D converter, input 1. F FT FT Type A A A R R D D D D FT FT A A R R D PIO1_0 to PIO1_11 FT FT FT FT Pin A A A A A LPC1113/14 pin description table (LQFP48 package) ...continued Symbol R R R R R Table 3. D D D D D LPC1111/12/13/14 NXP Semiconductors D D PIO1_5/RTS/ CT32B0_CAP0 45[1] PIO1_6/RXD/ CT32B0_MAT0 46[1] PIO1_7/TXD/ CT32B0_MAT1 47[1] PIO1_8/CT16B1_CAP0 9[1] PIO1_9/CT16B1_MAT0 17[1] PIO1_10/AD6/ CT16B1_MAT1 30[3] PIO1_11/AD7 42[3] PIO1_1 -- General purpose digital input/output pin. I AD2 -- A/D converter, input 2. O CT32B1_MAT0 -- Match output 0 for 32-bit timer 1. I TRST -- Test Reset for JTAG interface. I/O PIO1_2 -- General purpose digital input/output pin. I AD3 -- A/D converter, input 3. O CT32B1_MAT1 -- Match output 1 for 32-bit timer 1. I/O SWDIO -- Serial wire debug input/output. I/O PIO1_3 -- General purpose digital input/output pin. I AD4 -- A/D converter, input 4. O CT32B1_MAT2 -- Match output 2 for 32-bit timer 1. I/O PIO1_4 -- General purpose digital input/output pin. I AD5 -- A/D converter, input 5. O CT32B1_MAT3 -- Match output 3 for 32-bit timer 1. I WAKEUP -- Deep power-down mode wake-up pin. I/O PIO1_5 -- General purpose digital input/output pin. O RTS -- Request To Send output for UART. I CT32B0_CAP0 -- Capture input 0 for 32-bit timer 0. I/O PIO1_6 -- General purpose digital input/output pin. I RXD -- Receiver input for UART. O CT32B0_MAT0 -- Match output 0 for 32-bit timer 0. I/O PIO1_7 -- General purpose digital input/output pin. O TXD -- Transmitter output for UART. O CT32B0_MAT1 -- Match output 1 for 32-bit timer 0. I/O PIO1_8 -- General purpose digital input/output pin. I CT16B1_CAP0 -- Capture input 0 for 16-bit timer 1. I/O PIO1_9 -- General purpose digital input/output pin. O CT16B1_MAT0 -- Match output 0 for 16-bit timer 1. I/O PIO1_10 -- General purpose digital input/output pin. I AD6 -- A/D converter, input 6. O CT16B1_MAT1 -- Match output 1 for 16-bit timer 1. I/O PIO1_11 -- General purpose digital input/output pin. I AD7 -- A/D converter, input 7. LPC1111_12_13_14_0 Objective data sheet A PIO1_4/AD5/ 40[3] CT32B1_MAT3/WAKEUP I/O R 39[3] CT32B1_CAP0 -- Capture input 0 for 32-bit timer 1. TDO -- Test Data Out for JTAG interface. D SWDIO/PIO1_3/AD4/ CT32B1_MAT2 35[3] I O FT TRST/PIO1_2/ AD3/CT32B1_MAT1 34[3] A TDO/PIO1_1/ AD2/CT32B1_MAT0 33[3] R TMS/PIO1_0/ AD1/CT32B1_CAP0 (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 9 of 53 FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R Description I/O Port 2 -- Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. I/O PIO2_0 -- General purpose digital input/output pin. O DTR -- Data Terminal Ready output for UART. O SSEL1 -- Slave Select for SPI1. I/O PIO2_1 -- General purpose digital input/output pin. I DSR -- Data Set Ready input for UART. I/O SCK1 -- Serial clock for SPI1. I/O PIO2_2 -- General purpose digital input/output pin. F FT FT Type A A A R R D D D D FT FT A A R R D PIO2_0 to PIO2_11 FT FT FT FT Pin A A A A A LPC1113/14 pin description table (LQFP48 package) ...continued Symbol R R R R R Table 3. D D D D D LPC1111/12/13/14 NXP Semiconductors D D I/O PIO2_3 -- General purpose digital input/output pin. I RI -- Ring Indicator input for UART. A DCD -- Data Carrier Detect input for UART. MISO1 -- Master In Slave Out for SPI1. R 38[1] I I/O D PIO2_3/RI/MOSI1 26[1] FT PIO2_2/DCD/MISO1 13[1] A PIO2_1/DSR/SCK1 2[1] R PIO2_0/DTR/SSEL1 I/O MOSI1 -- Master Out Slave In for SPI1. PIO2_4 19[1] I/O PIO2_4 -- General purpose digital input/output pin. PIO2_5 20[1] I/O PIO2_5 -- General purpose digital input/output pin. PIO2_6 1[1] I/O PIO2_6 -- General purpose digital input/output pin. PIO2_7 11[1] I/O PIO2_7 -- General purpose digital input/output pin. PIO2_8 12[1] I/O PIO2_8 -- General purpose digital input/output pin. PIO2_9 24[1] I/O PIO2_9 -- General purpose digital input/output pin. PIO2_10 25[1] I/O PIO2_10 -- General purpose digital input/output pin. PIO2_11/SCK0 31[1] I/O PIO2_11 -- General purpose digital input/output pin. I/O SCK0 -- Serial clock for SPI0. I/O Port 3 -- Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins PIO3_6 to PIO3_11 are not available. I/O PIO3_0 -- General purpose digital input/output pin. O DTR -- Data Terminal Ready output for UART. I/O PIO3_1 -- General purpose digital input/output pin. I DSR -- Data Set Ready input for UART. I/O PIO3_2 -- General purpose digital input/output pin. I DCD -- Data Carrier Detect input for UART. I/O PIO3_3 -- General purpose digital input/output pin. I RI -- Ring Indicator input for UART. PIO3_4 18[1] I/O PIO3_4 -- General purpose digital input/output pin. PIO3_5 21[1] I/O PIO3_5 -- General purpose digital input/output pin. VDD(IO) 8[4] I 3.3 V input/output supply voltage. VDD(3V3) 44[4] I 3.3 V supply voltage to the internal regulator and the ADC. Also used as the ADC reference voltage. VSSIO 5 I Ground. PIO3_0 to PIO3_5 PIO3_0/DTR 36[1] PIO3_1/DSR 37[1] PIO3_2/DCD 43[1] PIO3_3/RI 48[1] LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 10 of 53 R R R R R A A A A A FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R Pin Type Description XTALIN 6[5] I Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 7[5] O Output from the oscillator amplifier. VSS 41 I Ground. F FT FT Symbol A A A R R D D D LPC1113/14 pin description table (LQFP48 package) ...continued FT FT FT FT Table 3. D D D D D LPC1111/12/13/14 NXP Semiconductors D FT FT A A R R D D D R A FT D R A [1] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. [2] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant. [4] Tie together VDD(3V3) and VDD(IO) externally. If separate supplies are used for VDD(3V3) and VDD(IO), ensure that the voltage difference between both supplies is smaller than or equal to 0.5 V. [5] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. Table 4. LPC1114 pin description table (PLCC44 package) Symbol Pin PIO0_0 to PIO0_11 RESET/PIO0_0 7 PIO0_1/CLKOUT/ CT32B0_MAT2 8[1] PIO0_2/SSEL0/ CT16B0_CAP0 14[1] Type Description I/O Port 0 -- Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. I RESET -- External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. I/O PIO0_0 -- General purpose digital input/output pin. I/O PIO0_1 -- General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. O CLKOUT -- Clockout pin. O CT32B0_MAT2 -- Match output 2 for 32-bit timer 0. I/O PIO0_2 -- General purpose digital input/output pin. O SSEL0 -- Slave Select for SPI0. I CT16B0_CAP0 -- Capture input 0 for 16-bit timer 0. PIO0_3 18[1] I/O PIO0_3 -- General purpose digital input/output pin. PIO0_4/SCL 19[2] I/O PIO0_4 -- General purpose digital input/output pin. I/O SCL -- I2C-bus clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O PIO0_5 -- General purpose digital input/output pin. I/O SDA -- I2C-bus data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O PIO0_6 -- General purpose digital input/output pin. I/O SCK0 -- Serial clock for SPI0. I/O PIO0_7 -- General purpose digital input/output pin (high-current output driver). I CTS -- Clear To Send input for UART. I/O PIO0_8 -- General purpose digital input/output pin. I/O MISO0 -- Master In Slave Out for SPI0. O CT16B0_MAT0 -- Match output 0 for 16-bit timer 0. PIO0_5/SDA 20[2] PIO0_6/SCK0 26[1] PIO0_7/CTS 27[1] PIO0_8/MISO0/ CT16B0_MAT0 31[1] LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 11 of 53 R R R R R D R R A A FT FT FT FT A A R R D D D FT D PIO0_9 -- General purpose digital input/output pin. I/O MOSI0 -- Master Out Slave In for SPI0. O CT16B0_MAT1 -- Match output 1 for 16-bit timer 0. SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 33[1] I SWCLK -- Serial wire clock and test clock TCK for JTAG interface. I/O PIO0_10 -- General purpose digital input/output pin. I/O SCK0 -- Serial clock for SPI0. O CT16B0_MAT2 -- Match output 2 for 16-bit timer 0. I TDI -- Test Data In for JTAG interface. I/O PIO0_11 -- General purpose digital input/output pin. I AD0 -- A/D converter, input 0. O CT32B0_MAT3 -- Match output 3 for 32-bit timer 0. I/O Port 1 -- Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. I TMS -- Test Mode Select for JTAG interface. I/O PIO1_0 -- General purpose digital input/output pin. I AD1 -- A/D converter, input 1. I CT32B1_CAP0 -- Capture input 0 for 32-bit timer 1. O TDO -- Test Data Out for JTAG interface. I/O PIO1_1 -- General purpose digital input/output pin. I AD2 -- A/D converter, input 2. O CT32B1_MAT0 -- Match output 0 for 32-bit timer 1. I TRST -- Test Reset for JTAG interface. I/O PIO1_2 -- General purpose digital input/output pin. I AD3 -- A/D converter, input 3. O CT32B1_MAT1 -- Match output 1 for 32-bit timer 1. F D FT FT A A R R D D D R A FT D R 38[3] 39[3] 41[3] 42[3] PIO1_5/RTS/ CT32B0_CAP0 PIO1_6/RXD/ CT32B0_MAT0 3[1] I/O SWDIO -- Serial wire debug input/output. I/O PIO1_3 -- General purpose digital input/output pin. I AD4 -- A/D converter, input 4. O CT32B1_MAT2 -- Match output 2 for 32-bit timer 1. I/O PIO1_4 -- General purpose digital input/output pin. I AD5 -- A/D converter, input 5. O CT32B1_MAT3 -- Match output 3 for 32-bit timer 1. I WAKEUP -- Deep power-down mode wake-up pin. I/O PIO1_5 -- General purpose digital input/output pin. O RTS -- Request To Send output for UART. I CT32B0_CAP0 -- Capture input 0 for 32-bit timer 0. I/O PIO1_6 -- General purpose digital input/output pin. I RXD -- Receiver input for UART. O CT32B0_MAT0 -- Match output 0 for 32-bit timer 0. LPC1111_12_13_14_0 A 37[3] 2[1] Objective data sheet FT 36[3] PIO1_0 to PIO1_11 PIO1_4/AD5/ CT32B1_MAT3/WAKEUP FT I/O A A A PIO0_9/MOSI0/ CT16B0_MAT1 SWDIO/PIO1_3/AD4/ CT32B1_MAT2 R R R Description TRST/PIO1_2/ AD3/CT32B1_MAT1 R A D D Type 32[1] TDO/PIO1_1/ AD2/CT32B1_MAT0 D R FT FT A A R R D D D Pin TMS/PIO1_0/ AD1/CT32B1_CAP0 FT FT FT FT FT LPC1114 pin description table (PLCC44 package) ...continued Symbol TDI/PIO0_11/ AD0/CT32B0_MAT3 A A A A A Table 4. D D D D D LPC1111/12/13/14 NXP Semiconductors (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 12 of 53 R R R R R A A A A A FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R Pin Type Description PIO1_7/TXD/ CT32B0_MAT1 4[1] I/O PIO1_7 -- General purpose digital input/output pin. O TXD -- Transmitter output for UART. O CT32B0_MAT1 -- Match output 1 for 32-bit timer 0. PIO1_8/CT16B1_CAP0 13[1] I/O PIO1_8 -- General purpose digital input/output pin. I CT16B1_CAP0 -- Capture input 0 for 16-bit timer 1. PIO1_9/CT16B1_MAT0 21[1] I/O PIO1_9 -- General purpose digital input/output pin. O CT16B1_MAT0 -- Match output 0 for 16-bit timer 1. PIO1_10/AD6/ CT16B1_MAT1 34[3] I/O PIO1_10 -- General purpose digital input/output pin. I AD6 -- A/D converter, input 6. O CT16B1_MAT1 -- Match output 1 for 16-bit timer 1. PIO1_11/AD7 44[3] I/O PIO1_11 -- General purpose digital input/output pin. I AD7 -- A/D converter, input 7. I/O Port 2 -- Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. I/O PIO2_0 -- General purpose digital input/output pin. O DTR -- Data Terminal Ready output for UART. O SSEL1 -- Slave Select for SPI1. I/O PIO2_1 -- General purpose digital input/output pin. I DSR -- Data Set Ready input for UART. I/O SCK1 -- Serial clock for SPI1. I/O PIO2_2 -- General purpose digital input/output pin. F FT FT Symbol A A A R R D D D LPC1114 pin description table (PLCC44 package) ...continued FT FT FT FT Table 4. D D D D D LPC1111/12/13/14 NXP Semiconductors D FT FT A A R R D D D R A FT D R PIO2_0/DTR/SSEL1 PIO2_1/DSR/SCK1 PIO2_2/DCD/MISO1 PIO2_3/RI/MOSI1 6[1] 17[1] 30[1] 40[1] I DCD -- Data Carrier Detect input for UART. I/O MISO1 -- Master In Slave Out for SPI1. I/O PIO2_3 -- General purpose digital input/output pin. I RI -- Ring Indicator input for UART. A PIO2_0 to PIO2_11 I/O MOSI1 -- Master Out Slave In for SPI1. PIO2_4 23[1] I/O PIO2_4 -- General purpose digital input/output pin. PIO2_5 24[1] I/O PIO2_5 -- General purpose digital input/output pin. PIO2_6 5[1] I/O PIO2_6 -- General purpose digital input/output pin. PIO2_7 15[1] I/O PIO2_7 -- General purpose digital input/output pin. PIO2_8 16[1] I/O PIO2_8 -- General purpose digital input/output pin. PIO2_9 28[1] I/O PIO2_9 -- General purpose digital input/output pin. PIO2_10 29[1] I/O PIO2_10 -- General purpose digital input/output pin. PIO2_11/SCK0 35[1] I/O PIO2_11 -- General purpose digital input/output pin. I/O SCK0 -- Serial clock for SPI0. I/O Port 3 -- Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins PIO3_0 to PIO3_3 and PIO3_6 to PIO3_11 are not available. PIO3_0 to PIO3_5 PIO3_4 22[1] I/O PIO3_4 -- General purpose digital input/output pin. PIO3_5 25[1] I/O PIO3_5 -- General purpose digital input/output pin. LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 13 of 53 R R R R R A A A A A FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R Pin Type Description VDD(IO) 12[4] I 3.3 V input/output supply voltage. VDD(3V3) 1[4] I 3.3 V supply voltage to the internal regulator and the ADC. Also used as the ADC reference voltage. VSSIO 9 I Ground. XTALIN 10[5] I Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 11[5] O Output from the oscillator amplifier. VSS 43 I Ground. F FT FT Symbol A A A R R D D D LPC1114 pin description table (PLCC44 package) ...continued FT FT FT FT Table 4. D D D D D LPC1111/12/13/14 NXP Semiconductors D FT FT A A R R D D D R FT D I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant. [4] Tie together VDD(3V3) and VDD(IO) externally. If separate supplies are used for VDD(3V3) and VDD(IO), ensure that the voltage difference between both supplies is smaller than or equal to 0.5 V. [5] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 14 of 53 A [2] R 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. LPC1111_12_13_14_0 A [1] D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A Description I/O Port 0 -- Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. I RESET -- External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. I/O PIO0_0 -- General purpose digital input/output pin. I/O PIO0_1 -- General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. O CLKOUT -- Clock out pin. O CT32B0_MAT2 -- Match output 2 for 32-bit timer 0. I/O PIO0_2 -- General purpose digital input/output pin. FT FT A A R R D D Type F FT FT A A R R D D D PIO0_0 to PIO0_11 FT FT FT FT FT Pin A A A A A LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol R R R R R Table 5. D D D D D LPC1111/12/13/14 NXP Semiconductors D D R A O SSEL0 -- Slave select for SPI0. I CT16B0_CAP0 -- Capture input 0 for 16-bit timer 0. A PIO0_2/SSEL0/ CT16B0_CAP0 8[1] R PIO0_1/CLKOUT/ CT32B0_MAT2 3[1] D 2 FT RESET/PIO0_0 PIO0_3 9[1] I/O PIO0_3 -- General purpose digital input/output pin. PIO0_4/SCL 10[2] I/O PIO0_4 -- General purpose digital input/output pin. I/O SCL -- I2C-bus clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O PIO0_5 -- General purpose digital input/output pin. I/O SDA -- I2C-bus data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. I/O PIO0_6 -- General purpose digital input/output pin. I/O SCK0 -- Serial clock for SPI0. I/O PIO0_7 -- General purpose digital input/output pin (high-current output driver). I CTS -- Clear To Send input for UART. I/O PIO0_8 -- General purpose digital input/output pin. I/O MISO0 -- Master In Slave Out for SPI0. O CT16B0_MAT0 -- Match output 0 for 16-bit timer 0. I/O PIO0_9 -- General purpose digital input/output pin. I/O MOSI0 -- Master Out Slave In for SPI0. O CT16B0_MAT1 -- Match output 1 for 16-bit timer 0. PIO0_5/SDA 11[2] PIO0_6/SCK0 15[1] PIO0_7/CTS 16[1] PIO0_8/MISO0/ CT16B0_MAT0 17[1] PIO0_9/MOSI0/ CT16B0_MAT1 18[1] SWCLK/PIO0_10/SCK0/ CT16B0_MAT2 19[1] TDI/PIO0_11/AD0/ CT32B0_MAT3 PIO1_0 to PIO1_11 21[3] I SWCLK -- Serial wire clock and test clock TCK for JTAG interface. I/O PIO0_10 -- General purpose digital input/output pin. I/O SCK0 -- Serial clock for SPI0. O CT16B0_MAT2 -- Match output 2 for 16-bit timer 0. I TDI -- Test Data In for JTAG interface. I/O PIO0_11 -- General purpose digital input/output pin. I AD0 -- A/D converter, input 0. O CT32B0_MAT3 -- Match output 3 for 32-bit timer 0. I/O Port 1 -- Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 15 of 53 R R R R R A A A A A CT32B1_MAT3 -- Match output 3 for 32-bit timer 1. I WAKEUP -- Deep power-down mode wake-up pin. I/O PIO1_5 -- General purpose digital input/output pin. O RTS -- Request To Send output for UART. I CT32B0_CAP0 -- Capture input 0 for 32-bit timer 0. I/O PIO1_6 -- General purpose digital input/output pin. I RXD -- Receiver input for UART. O CT32B0_MAT0 -- Match output 0 for 32-bit timer 0. I/O PIO1_7 -- General purpose digital input/output pin. O TXD -- Transmitter output for UART. R O D AD5 -- A/D converter, input 5. D I F PIO1_4 -- General purpose digital input/output pin. A I/O R CT32B1_MAT2 -- Match output 2 for 32-bit timer 1. D AD4 -- A/D converter, input 4. O FT I FT PIO1_3 -- General purpose digital input/output pin. FT I/O R SWDIO -- Serial wire debug input/output. A I/O A CT32B1_MAT1 -- Match output 1 for 32-bit timer 1. D AD3 -- A/D converter, input 3. O FT I R PIO1_2 -- General purpose digital input/output pin. R I/O D TRST -- Test Reset for JTAG interface. D I FT CT32B1_MAT0 -- Match output 0 for 32-bit timer 1. A AD2 -- A/D converter, input 2. O FT I FT PIO1_1 -- General purpose digital input/output pin. A I/O A TDO -- Test Data Out for JTAG interface. R O R CT32B1_CAP0 -- Capture input 0 for 32-bit timer 1. D AD1 -- A/D converter, input 1. I D I FT PIO1_0 -- General purpose digital input/output pin. A I/O R TMS -- Test Mode Select for JTAG interface. D I R FT FT TMS/PIO1_0/AD1/ CT32B1_CAP0 D A A Description A FT R R Type 22[3] R A D D Pin D R FT FT A A R R D D D LPC1111/12/13/14 pin description table (HVQFN33 package) ...continued Symbol FT FT FT FT Table 5. D D D D D LPC1111/12/13/14 NXP Semiconductors TRST/PIO1_2/AD3/ CT32B1_MAT1 SWDIO/PIO1_3/AD4/ CT32B1_MAT2 PIO1_4/AD5/ CT32B1_MAT3/WAKEUP 24[3] 25[3] 26[3] A TDO/PIO1_1/AD2/ CT32B1_MAT0 23[3] PIO1_5/RTS/ CT32B0_CAP0 30[1] PIO1_6/RXD/ CT32B0_MAT0 31[1] PIO1_7/TXD/ CT32B0_MAT1 32[1] O CT32B0_MAT1 -- Match output 1 for 32-bit timer 0. PIO1_8/CT16B1_CAP0 7[1] I/O PIO1_8 -- General purpose digital input/output pin. I CT16B1_CAP0 -- Capture input 0 for 16-bit timer 1. PIO1_9/CT16B1_MAT0 12[1] I/O PIO1_9 -- General purpose digital input/output pin. O CT16B1_MAT0 -- Match output 0 for 16-bit timer 1. PIO1_10/AD6/ CT16B1_MAT1 20[3] I/O PIO1_10 -- General purpose digital input/output pin. I AD6 -- A/D converter, input 6. O CT16B1_MAT1 -- Match output 1 for 16-bit timer 1. I/O PIO1_11 -- General purpose digital input/output pin. I AD7 -- A/D converter, input 7. I/O Port 2 -- Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. Pins PIO2_1 to PIO2_11 are not available. PIO1_11/AD7 PIO2_0 27[3] LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 16 of 53 R R R R R D R R A A FT FT FT FT A A R R D D D D A FT R PIO2_0/DTR I/O PIO2_0 -- General purpose digital input/output pin. O DTR -- Data Terminal Ready output for UART. I/O Port 3 -- Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins PIO3_0, PIO3_1, PIO3_3 and PIO3_6 to PIO3_11 are not available. D FT FT A A R R D D D PIO3_5 I/O PIO3_5 -- General purpose digital input/output pin. VDD(IO) 6[4] I 3.3 V input/output supply voltage. VDD(3V3) 29[4] I 3.3 V supply voltage to the internal DC-DC converter and the ADC. Also used as the ADC reference voltage. XTALIN 4[5] I Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 5[5] O Output from the oscillator amplifier. VSS 33 - Thermal pad. Connect to ground. [1] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. [2] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled, and the pin is not 5 V tolerant. [4] Tie together VDD(3V3) and VDD(IO) externally. If separate supplies are used for VDD(3V3) and VDD(IO), ensure that the voltage difference between both supplies is smaller than or equal to 0.5 V. [5] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. (c) NXP B.V. 2009. All rights reserved. 17 of 53 A PIO3_4 -- General purpose digital input/output pin. 14[1] R I/O D PIO3_2 -- General purpose digital input/output pin. 13[1] FT I/O PIO3_4 A 28[1] R PIO3_2 Rev. 00.11 -- 13 November 2009 F FT FT Description A A A R R D D D Type 1[1] Objective data sheet R R FT FT A A R R D D D Pin LPC1111_12_13_14_0 FT FT FT FT FT LPC1111/12/13/14 pin description table (HVQFN33 package) ...continued Symbol PIO3_0 to PIO3_5 A A A A A Table 5. D D D D D LPC1111/12/13/14 NXP Semiconductors D D R R R R R D D D A A A A A R A A FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D 7.1 ARM Cortex-M0 processor FT D R FT FT A A R R D D D 7. Functional description FT FT FT FT LPC1111/12/13/14 NXP Semiconductors D D R A FT The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. D R A 7.2 On-chip flash program memory The LPC1111/12/13/14 contain 32 kB (LPC1114), 24 kB (LPC1113), 16 kB (LPC1112), or 8 kB (LPC1111) of on-chip flash memory. 7.3 On-chip SRAM The LPC1111/12/13/14 contain a total of 8 kB, 4 kB, or 2 kB on-chip static RAM memory. 7.4 Memory map The LPC1111/12/13/14 incorporates several distinct memory regions, shown in the following figures. Figure 5 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 1 megabyte in size and is divided to allow for up to 64 peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows simplifying the address decoding for each peripheral. LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 18 of 53 R R R R R A A A A A D R R A A FT FT FT FT A A R R D D D D A FT R A 0x5020 0000 F FT FT A A R R D D D D FT FT A A R R D 0xFFFF FFFF R R FT FT A A R R D D D AHB peripherals LPC1111/12/13/14 FT FT FT FT FT 4 GB D D D D D LPC1111/12/13/14 NXP Semiconductors D D 127- 4 reserved R A reserved 1 GPIO PIO1 0 GPIO PIO0 reserved APB peripherals 0x5003 0000 0x5002 0000 0x5001 0000 0x5000 0000 0x4008 0000 23 - 31 reserved 0x4005 C000 0x4008 0000 1 GB APB peripherals SPI1(1) 22 0x4000 0000 0x4005 8000 21 - 19 reserved 0x4004 C000 reserved 0x2000 0000 0.5 GB 18 system control 17 IOCONFIG 16 15 SPI0 reserved 14 PMU reserved 0x4004 4000 0x4004 0000 0x4003 C000 0x4003 8000 10 - 13 reserved 0x1FFF 4000 16 kB boot ROM 0x4002 8000 9 reserved 8 reserved 0x4002 0000 0x1000 2000 7 ADC 0x4001 C000 0x1000 1000 6 32-bit counter/timer 1 0x4001 8000 0x1000 0800 5 32-bit counter/timer 0 0x4001 4000 4 16-bit counter/timer 1 0x4001 0000 3 16-bit counter/timer 0 0x4000 C000 2 UART 0x4000 8000 1 0 WDT 0x4000 4000 I2C-bus 0x4000 0000 0x1FFF 0000 reserved 8 kB SRAM (LPC1113/14/301) 4 kB SRAM (LPC1111/12/13/14/201) 2 kB SRAM (LPC1111/12/101) 0x1000 0000 reserved 0x0000 8000 32 kB on-chip flash (LPC1114) 24 kB on-chip flash (LPC1113) 16 kB on-chip flash (LPC1112) 0 GB 0x4004 8000 8 kB on-chip flash (LPC1111) 0x0000 6000 0x0000 4000 0x0000 2000 + 512 byte active interrupt vectors 0x4002 4000 0x0000 0200 0x0000 0000 0x0000 0000 002aae699 (1) LQFP48/PLCC44 packages only. Fig 5. LPC1111/12/13/14 memory map 7.5 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.5.1 Features * Controls system exceptions and peripheral interrupts. LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 19 of 53 A 0x5000 0000 GPIO PIO2 R AHB peripherals 2 D 0x5020 0000 GPIO PIO3 FT 0x5004 0000 3 D D R R R R R D D D A A A A A FT FT FT FT FT LPC1111/12/13/14 D R R A A FT FT FT FT A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R F D FT FT A A R R D D D R A FT * 8 programmable interrupt priority levels, with hardware priority level masking * Relocatable vector table. * Software interrupt generation. A FT FT A inputs to the start logic from individual GPIO pins. A R R D D * In the LPC1111/12/13/14, the NVIC supports 32 vectored interrupts including up to 13 D R A 7.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any GPIO pin (total of up to 42 pins) regardless of the selected function, can be programmed to generate an interrupt on a level, or rising edge or falling edge, or both. 7.6 IOCONFIG block The IOCONFIG block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. 7.7 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. LPC1111/12/13/14 use accelerated GPIO functions: * GPIO registers are a dedicated AHB peripheral and are accessed through the AHB so that the fastest possible I/O timing can be achieved. * Entire port value can be written in one instruction. Additionally, any GPIO pin (total of up to 42 pins) providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both. 7.7.1 Features * Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. * Direction control of individual bits. * All I/O default to inputs with pull-ups enabled after reset. * Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG block for each GPIO pin. LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 20 of 53 D D R R R R R D D D A A A A A R A A FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. FT A A R R D The LPC1111/12/13/14 contains one UART. FT D R FT FT A A R R D D D 7.8 UART FT FT FT FT LPC1111/12/13/14 NXP Semiconductors D D R A FT D The UART includes a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. R A 7.8.1 Features * * * * 16 Byte Receive and Transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. * Fractional divider for baud rate control and FIFO control mechanism that enables software flow control implementation. * Support for RS-485/9-bit mode. * Support for modem control. 7.9 SPI serial I/O controller The LPC1111/12/13/14 contain two SPI controllers on the LQFP48/PLCC44 packages and one SPI controller on the HVQFN33 packages (SPI0). Both SPI controllers support SSP features. The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SPI supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.9.1 Features * Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses * * * * Synchronous serial communication Master or slave operation 8-frame FIFOs for both transmit and receive 4-bit to 16-bit frame 7.10 I2C-bus serial I/O controller The LPC1111/12/13/14 contain one I2C-bus controller. The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line (SCL) and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 21 of 53 D D R R R R R D D D A A A A A FT FT FT FT FT LPC1111/12/13/14 D R R A A FT FT FT FT A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. D FT FT A A R R D D D R A 7.10.1 Features FT Easy to configure as master, slave, or master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master). Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. * Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. * Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. * The I2C-bus can be used for test and diagnostic purposes. * The I2C-bus controller supports multiple address recognition and a bus monitor mode. 7.11 10-bit ADC The LPC1111/12/13/14 contains one ADC. It is a single 10-bit successive approximation ADC with eight channels. 7.11.1 Features * * * * * * * * 10-bit successive approximation ADC. Input multiplexing among 8 pins. Power-down mode. Measurement range 0 V to VDD(3V3). 10-bit conversion time 2.44 s. Burst conversion mode for single or multiple inputs. Optional conversion on transition of input pin or Timer Match signal. Individual result registers for each ADC channel to reduce interrupt overhead. 7.12 General purpose external event counters/timers The LPC1111/12/13/14 includes two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 22 of 53 A * * * * * R also supports Fast mode plus with bit rates up to 1 Mbit/s. D * The I2C-interface is a standard I2C compliant bus interface with open-drain pins. I2C0 D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A D FT FT A A R R D * A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. * Counter or timer operation. * One capture channel per timer, that can take a snapshot of the timer value when an F FT FT A A R R D D D 7.12.1 Features FT FT FT FT FT LPC1111/12/13/14 NXP Semiconductors D D R A FT input signal transitions. A capture event may also generate an interrupt. D R * Four match registers per timer that allow: A - Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation. * Up to four external outputs corresponding to match registers, with the following capabilities: - Set LOW on match. - Set HIGH on match. - Toggle on match. - Do nothing on match. 7.13 System tick timer The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a 10 ms interval. 7.14 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to `feed' (or reload) the watchdog within a predetermined amount of time. 7.14.1 Features * Internally resets chip if not periodically reloaded. * Debug mode. * Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. * * * * Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. Flag to indicate watchdog reset. Programmable 32-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK) x 256 x 4) to (Tcy(WDCLK) x 232 x 4) in multiples of Tcy(WDCLK) x 4. * The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator (IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability. LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 23 of 53 D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D A F D FT FT A A R R D 7.15.1 Crystal oscillators R FT FT A A R R D D D 7.15 Clocking and power control FT FT FT FT FT LPC1111/12/13/14 NXP Semiconductors D D The LPC1111/12/13/14 include three independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. R A FT D R See Figure 6 for an overview of the LPC1111/12/13/14 clock generation. SYSTEM CLOCK DIVIDER AHB clock 0 (system) system clock 18 AHB clocks 1 to 18 (memories and peripherals) AHBCLKCTRL[1:18] (AHB clock enable) IRC oscillator MAINCLKSEL (main clock select) IRC oscillator system oscillator SYSPLLCLKSEL (system PLL clock select) SPI0 UART PERIPHERAL CLOCK DIVIDER UART SPI1 PERIPHERAL CLOCK DIVIDER SPI1 SYSTICK TIMER CLOCK DIVIDER SYSTICK timer main clock watchdog oscillator watchdog oscilllator SPI0 PERIPHERAL CLOCK DIVIDER SYSTEM PLL IRC oscillator WDT CLOCK DIVIDER WDT watchdog oscillator WDTUEN (WDT clock update enable) IRC oscillator system oscillator watchdog oscillator CLKOUTUEN (CLKOUT update enable) Fig 6. CLKOUT PIN CLOCK DIVIDER CLKOUT pin 002aae514 LPC1111/12/13/14 clocking generation block diagram LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 24 of 53 A Following reset, the LPC1111/12/13/14 will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. R R R R R A A A A A FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. F FT FT A A R R D D D Internal RC oscillator FT FT FT FT 7.15.1.1 D D D D D LPC1111/12/13/14 NXP Semiconductors D D R A FT D R Upon power-up or any chip reset, the LPC1111/12/13/14 use the IRC as the clock source. Software may later switch to one of the other available clock sources. A 7.15.1.2 System oscillator The system oscillator can be used as the clock source for the CPU, with or without using the PLL. The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. 7.15.2 System PLL (PLL0) The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 s. 7.15.3 Clock output The LPC1111/12/13/14 features a clock output function that routes the IRC oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin. 7.15.4 Wake-up process The LPC1111/12/13/14 begin operation at power-up and when awakened from Deep power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. 7.15.5 Power control The LPC1111/12/13/14 support a variety of power control features. There are three special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 25 of 53 R R R R R A A A A A FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A FT FT A A R R D D When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. F FT FT A A R R D D D Sleep mode FT FT FT FT 7.15.5.1 D D D D D LPC1111/12/13/14 NXP Semiconductors D D In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. R A The timing of the wake-up process from Deep-sleep mode depends on which blocks are selected to be powered down during deep-sleep. For lowest power consumption, the clock source should be switched to IRC before entering Deep-sleep mode, all oscillators and PLLs should be turned off during deep-sleep, and the IRC should be selected as clock source when the chip wakes up from deep-sleep. The IRC can be switched on and off glitch-free and provides a clean clock signal after start-up. If power consumption is not a concern, any of the oscillators and/or PLLs can be left running in Deep-sleep mode to obtain short wake-up times when waking up from deep-sleep. 7.15.5.3 Deep power-down mode In Deep power-down mode, power is shut off to the entire chip with the exception of the WAKEUP pin. The LPC1111/12/13/14 can wake up from Deep power-down mode via the WAKEUP pin. 7.16 System control 7.16.1 Reset Reset has four sources on the LPC1111/12/13/14: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 26 of 53 A The GPIO pins (up to 15 pins total) serve as external wake-up pins to a dedicated start logic to wake up the chip from Deep-sleep mode. R In Deep-sleep mode, the chip is in Sleep mode, and in addition analog blocks are shut down for increased power savings. The user can configure the Deep-sleep mode to a large extend, selecting any of the oscillators, any of the PLLs, BOD, the ADC, and the flash to be shut down or remain powered during Deep-sleep mode. The user can also select which of the oscillators and analog blocks will be powered up after the chip exits from Deep-sleep mode. D Deep-sleep mode FT 7.15.5.2 D D R R R R R D D D A A A A A FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The LPC1111/12/13/14 includes four levels for monitoring the voltage on the VDD(3V3) pin. If this voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. An additional threshold level can be selected to cause a forced reset of the chip. F FT FT A A R R D D D 7.16.2 Brownout detection FT FT FT FT LPC1111/12/13/14 NXP Semiconductors D D R A 2. CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands. 3. Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP. This mode effectively disables ISP override using PIO0_1 pin, too. It is up to the user's application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be disabled. For details see the LPC11xx user manual. 7.16.4 APB interface The APB peripherals are located on one APB bus. 7.16.5 AHBLite The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main static RAM, and the Boot ROM. 7.16.6 External interrupt inputs All GPIO pins can be level or edge sensitive interrupt inputs. LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 27 of 53 A 1. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. R There are three levels of Code Read Protection: D This feature of the LPC1111/12/13/14 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. FT 7.16.3 Code security (Code Read Protection - CRP) D D R R R R R D D D A A A A A FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The Cortex-M0 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register contained in the NVIC. F FT FT A A R R D D D 7.16.7 Memory mapping control FT FT FT FT LPC1111/12/13/14 NXP Semiconductors D D R A FT D R The vector table may be located anywhere within the bottom 1 GB of Cortex-M0 address space. The vector table must be located on a 128 word (512 byte) boundary. A 7.17 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four breakpoints and two watchpoints is supported. LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 28 of 53 D D R R R R R D D D D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R R FT FT A A R VDD(3V3) supply voltage (3.3 V) core and external rail 1.8 3.6 V VDD(IO) input/output supply voltage on pin VDDIO D Unit FT Max A Min R Conditions D Parameter D R A 1.8 3.6 V -0.5 +5.5 V VI input voltage 5 V tolerant I/O pins; only valid when the VDD(IO) supply voltage is present [2] IDD supply current per supply pin [3] - 100 mA ISS ground current per ground pin [3] - 100 mA Ilatch I/O latch-up current -(0.5VDD(IO)) < VI < (1.5VDD(IO)); - 100 mA -65 +150 C - 150 C - 1.5 W -5000 +5000 V Tj < 125 C [4] storage temperature Tj(max) maximum junction temperature Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption Vesd electrostatic discharge voltage human body model; all pins [5] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] Including voltage on outputs in 3-state mode. [3] The peak current is limited to 25 times the corresponding maximum current. [4] Dependent on package type. [5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 F D D Symbol Tstg A FT FT A A R R D D D Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] FT FT FT FT FT 8. Limiting values [1] A A A A A LPC1111/12/13/14 NXP Semiconductors 29 of 53 D D R R R R R D D D D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R F D FT FT A A R R D D D Min Typ[1] Max Unit R 3.6 V 3.3 3.6 V IDD supply current CCLK = 10 MHz - <tbd> - mA CCLK = 50 MHz - <tbd> - mA Sleep mode; VDD(3V3) = 3.3 V; Tamb = 25 C - <tbd> - A Deep-sleep mode; VDD(3V3) = 3.3 V; Tamb = 25 C - <tbd> - A Deep power-down mode; VDD(3V3) = 3.3 V; Tamb = 25 C - <tbd> - A active mode; VDD(3V3) = 3.3 V; Tamb = 25 C; code while(1){} executed from flash; all peripherals enabled Standard port pins, RESET IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - - 3 A IIH HIGH-level input current VI = VDD(IO); on-chip pull-down resistor disabled - - 3 A IOZ OFF-state output current VO = 0 V; VO = VDD(IO); on-chip pull-up/down resistors disabled - - 3 A VI input voltage pin configured to provide a digital function 0 - 5.0 V VO output voltage output active 0 - VDD(IO) V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V [2][3][4] Vhys hysteresis voltage - 0.4 - V VOH HIGH-level output voltage IOH = -4 mA [5] VDD(IO) - 0.4 - - V VOL LOW-level output voltage IOL = 4 mA [5] - - 0.4 V IOH HIGH-level output current VOH = VDD(IO) - 0.4 V [5] -4 - - mA IOL LOW-level output current VOL = 0.4 V [5] 4 - - mA LPC1111_12_13_14_0 (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 30 of 53 A 3.3 1.8 R 1.8 input/output supply voltage D supply voltage (3.3 V) FT VDD(3V3) A Conditions VDD(IO) Objective data sheet A FT FT A A R R D D D Table 7. Static characteristics Tamb = -40 C to +85 C, unless otherwise specified. Parameter FT FT FT FT FT 9. Static characteristics Symbol A A A A A LPC1111/12/13/14 NXP Semiconductors D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R -45 - - 50 mA 10 50 150 A F - A A R R - Unit D Max D Typ[1] HIGH-level short-circuit VOH = 0 V output current IOLS LOW-level short-circuit output current VOL = VDD(IO) [6] Ipd pull-down current VI = 5 V Ipu pull-up current VI = 0 V -15 -50 -85 A VDD(IO) < VI < 5 V 0 0 0 A FT FT mA D D R A FT D R IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - - 3 A IIH HIGH-level input current VI = VDD(IO); on-chip pull-down resistor disabled - - 3 A IOZ OFF-state output current VO = 0 V; VO = VDD(IO); on-chip pull-up/down resistors disabled - - 3 A VI input voltage pin configured to provide a digital function 0 - 5.0 V VO output voltage output active 0 - VDD(IO) V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V Vhys hysteresis voltage 0.4 - - V VOH HIGH-level output voltage IOH = -4 mA [5] VDD(IO) - 0.4 - - V VOL LOW-level output voltage IOL = 4 mA [5] - - 0.4 V IOH HIGH-level output current VOH = VDD(IO) - 0.4 V [5] 20 - - mA IOL LOW-level output current VOL = 0.4 V [5] 4 - - mA IOHS HIGH-level short-circuit VOH = 0 V output current [6] 10 50 150 A IOLS LOW-level short-circuit output current VOL = VDD(IO) [6] -15 -50 -85 A Ipd pull-down current VI = 5 V 0 0 0 A Ipu pull-up current VI = 0 V - - 3 A VDD(IO) < VI < 5 V - - 3 A 0.7VDD(IO) - - V [2][3][4] I2C-bus pins (PIO0_4 and PIO0_5) VIH HIGH-level input voltage VIL LOW-level input voltage - - 0.3VDD(IO) V Vhys hysteresis voltage - 0.5VDD(IO) - V - - 0.4 V IOLS = 20 mA [5] LPC1111_12_13_14_0 (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 31 of 53 A High-drive output pin (PIO0_7) Objective data sheet A FT FT A A R R D D D Min IOHS LOW-level output voltage FT FT FT FT FT Conditions [6] VOL A A A A A Parameter R R R R R Table 7. Static characteristics ...continued Tamb = -40 C to +85 C, unless otherwise specified. Symbol D D D D D LPC1111/12/13/14 NXP Semiconductors R A A FT FT FT D 2 4 - 10 22 A A A R R - Unit D Max D Typ[1] FT FT A D D R A FT D 0 1.8 1.95 V Vo(xtal) crystal output voltage 0 1.8 1.95 V [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] Including voltage on outputs in 3-state mode. [3] VDD(3V3) and VDD(IO) supply voltages must be present. [4] 3-state outputs go into 3-state mode when VDD(IO) is grounded. [5] Accounts for 100 mV voltage drop in all supply lines. [6] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [7] To VSS. Table 8. ADC static characteristics Tamb = -40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz, VDD(3V3) = 2.5 V to 3.6 V. Symbol Parameter VIA analog input voltage Cia analog input capacitance Conditions differential linearity error Min Typ[1] Max Unit 0 - VDD(3V3) V - - 1 pF [2][3][4] - 1 - LSB EL(adj) integral non-linearity [2][5] - 1.5 - LSB EO offset error [2][6] - 2.5 - LSB gain error [2][7] - 0.5 - % absolute error [2][8] - 3 - LSB ET [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] Conditions: VSS = 0 V, VDD(3V3) = 3.3 V. [3] The ADC is monotonic, there are no missing codes. [4] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 7. [5] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 7. [6] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 7. [7] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 7. [8] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 7. LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 32 of 53 A crystal input voltage R Vi(xtal) EG F FT FT Min Oscillator pins ED A A A VI = 5 V R R R VI = VDD(IO) R A D D [7] D R FT FT A A R R D D D Conditions FT D R FT FT A A R R D D D input leakage current FT FT FT FT ILI A A A A A Parameter R R R R R Table 7. Static characteristics ...continued Tamb = -40 C to +85 C, unless otherwise specified. Symbol D D D D D LPC1111/12/13/14 NXP Semiconductors D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT gain error EG FT A A R R D D D D FT FT A A R R D offset error EO FT FT FT FT FT LPC1111/12/13/14 NXP Semiconductors D D R 1023 A FT D R 1022 A 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = VDD(3V3) - VSS 1024 002aae787 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 7. ADC characteristics LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 33 of 53 D D R R R R R D D D A A A A A D R R A A FT A F D FT FT A A R R D Max Unit assertion - 1.69 - V de-assertion - 1.84 - V D Typ R Min D interrupt level 0 FT FT threshold voltage R A A Vth D R R Conditions R A D D Parameter D R FT FT A A R R D D D Table 9. BOD static characteristics[1] Tamb = 25 C. Symbol FT FT FT FT A A R R D D D 9.1 BOD static characteristics FT FT FT FT FT LPC1111/12/13/14 NXP Semiconductors A FT D R A interrupt level 1 assertion - 2.29 - V de-assertion - 2.44 - V assertion - 2.59 - V de-assertion - 2.74 - V assertion - 2.87 - V de-assertion - 2.98 - V assertion - 1.49 - V de-assertion - 1.64 - V interrupt level 2 interrupt level 3 reset level 0 [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC11xx user manual. 9.2 Power consumption 001aac984 X X (X) X X <tbd> X X X X X X X X X (X) Conditions: Tamb = 25 C; active mode entered executing code from flash; core voltage 3.3 V; all peripherals enabled but not configured to run. Fig 8. Supply current at different core frequencies in active mode LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 34 of 53 D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R F D FT FT A A R R D X (X) A FT FT A A R R D D D 001aac984 X FT FT FT FT FT LPC1111/12/13/14 NXP Semiconductors D D X R A FT D R X A <tbd> X X X X X X X X X (X) Conditions: Tamb = 25 C; active mode entered executing code from flash; all peripherals enabled but not configured to run. Fig 9. Supply current at different core voltages in active mode 001aac984 X X (X) X X <tbd> X X X X X X X X X (X) Conditions: active mode entered executing code from flash; core voltage 3.3 V; all peripherals enabled but not configured to run. Fig 10. Supply current at different temperatures in active mode LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 35 of 53 D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D A FT R A F FT FT A A R R D D D D FT FT A A R R D 002aae336 2000 R R FT FT A A R R D D D 9.3 Electrical pin characteristics FT FT FT FT FT LPC1111/12/13/14 NXP Semiconductors D D R A FT VIN (mV) D R A 1000 500 0 0 40 80 120 IIN (mA) Conditions: VDD(IO) = 3.3 V; Tamb = 25 C. Fig 11. I2C-bus current (IIL vs. VIL) 002aae337 4 VOUT (V) 3 2 1 0 0 20 40 60 80 100 IOUT (mA) Conditions: VDD(IO) = 3.3 V; Tamb = 25 C. Fig 12. High drive output (IOH vs. VOH) on pin PIO0_7 LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 36 of 53 D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R F D FT FT A A R R D X (X) A FT FT A A R R D D D 001aac984 X FT FT FT FT FT LPC1111/12/13/14 NXP Semiconductors D D X R A FT D R X A <tbd> X X X X X X X X X (X) Measured on pins Pn.m; VDD(3V3) = x.x V. Fig 13. Typical LOW-level output IOL current versus LOW-level output VOL 001aac984 X X (X) X X <tbd> X X X X X X X X X (X) Measured on pins Pn.m; VDD(3V3) = x.x V. Fig 14. Typical HIGH-level output IOH current versus HIGH-level output voltage VOH LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 37 of 53 D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R F D FT FT A A R R D X (X) A FT FT A A R R D D D 001aac984 X FT FT FT FT FT LPC1111/12/13/14 NXP Semiconductors D D X R A FT D R X A <tbd> X X X X X X X X X (X) Measured on pins Pn.m; VDD(3V3) = x.x V. Fig 15. Typical pull-up current Ipu versus input voltage Vi 001aac984 X X (X) X X <tbd> X X X X X X X X X (X) Measured on pins Pn.m; VDD(3V3) = x.x V. Fig 16. Typical pull-down current Ipd versus input voltage Vi LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 38 of 53 D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R F D FT FT A A R R D 10.1 Flash memory A FT FT A A R R D D D 10. Dynamic characteristics FT FT FT FT FT LPC1111/12/13/14 NXP Semiconductors D D R A Table 10. Flash characteristics Tamb = -40 C to +85 C, unless otherwise specified. FT D endurance tret retention time [1] Conditions Min Typ Max Unit 10000 - - cycles powered 10 - - years unpowered 20 - - years [1] Number of program/erase cycles. 10.2 External clock Table 11. Dynamic characteristic: external clock Tamb = -40 C to +85 C; VDD(3V3) over specified ranges.[1] Min Typ[2] Max Unit oscillator frequency 1 - 25 MHz Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk) x 0.4 - - ns tCLCX clock LOW time Tcy(clk) x 0.4 - - ns tCLCH clock rise time - - 5 ns tCHCL clock fall time - - 5 ns Symbol Parameter fosc Conditions [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. tCHCL tCHCX tCLCH tCLCX Tcy(clk) 002aaa907 Fig 17. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 39 of 53 A Parameter R Symbol Nendu D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D A F FT FT A A R R R D FT FT A A R R D Table 12. Dynamic characteristic: internal oscillators Tamb = -40 C to +85 C; VDD(3V3) over specified ranges.[1] D D D 10.3 Internal oscillators FT FT FT FT FT LPC1111/12/13/14 NXP Semiconductors Conditions Min Typ[2] Max Unit fosc(RC) internal RC oscillator frequency - 11.88 12 12.12 MHz D Parameter D Symbol R A FT D R Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. A [1] 001aac984 X X (X) X X <tbd> X X X X X X X X X (X) conditions: <tbd> Fig 18. Internal RC oscillator frequency vs. temperature 001aac984 X X (X) X X <tbd> X X X X X X X X X (X) conditions: <tbd> Fig 19. Internal RC oscillator frequency vs. core voltage LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 40 of 53 D D R R R R D R R A A FT D A F FT FT A A R R R D FT FT A A R R D Typ Max Unit SCL clock frequency - - 1 MHz fall time - - 45 ns 50 - - ns D Min D R data set-up time R A D D tSU;DAT D R FT FT A A R R D D D tf FT FT FT FT A A R R D D D fSCL Conditions FT FT FT FT FT Table 13. Dynamic characteristic: I2C-bus pins (Fast-mode Plus) Tamb = -40 C to +85 C; VDD(3V3) = VDD(IO) = 3.3 V.[1][2][3] Parameter A A A A A 10.4 I2C-bus Symbol R D D D LPC1111/12/13/14 NXP Semiconductors A FT D R A - [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Main clock frequency 10 MHz; system clock divider AHBCLKDIV = 0x1; I2C-bus interface configured in master mode. [3] Bus capacitance Cb = 550 pF; external pull-up resistance of 103 . SDA tLOW tr tf SCL P S tHIGH tSU;DAT 002aae860 Fig 20. I2C-bus pins clock timing LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 41 of 53 D D R R R R D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R R - - ns in SPI mode [2] 15 - Tcy(clk) ns in SPI mode [2] - - 0 ns D 27.8 D data hold time tDH A data set-up time R SPI master (in SPI mode) tDS tv(Q) data output valid time in SPI mode [2] - - 10 ns th(Q) data output hold time in SPI mode [2] - - 0 ns in SPI mode [3][4] 0 - - ns SPI slave (in SPI mode) data set-up time tDS tDH data hold time in SPI mode [3][4] 3 x Tcy(PCLK) + 4 - - ns tv(Q) data output valid time in SPI mode [3][4] - - 3 x Tcy(PCLK) + 11 ns in SPI mode [3][4] - - 2 x Tcy(PCLK) + 5 ns data output hold time th(Q) [1] Tcy(clk) = (SSPCLKDIV x (1 + SCR) x CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register), and the SPI CPSDVSR parameter (specified in the SPI clock prescale register). [2] Tamb = -40 C to 85 C; VDD(3V3) = 2.0 V to 3.6 V; VDD(IO) = 2.0 V to 3.6 V. [3] Tcy(clk) = 12 x Tcy(PCLK). [4] Tamb = 25 C; VDD(3V3) = 3.3 V; VDD(IO) = 3.3 V. LPC1111_12_13_14_0 Objective data sheet FT ns A - R - D 13.9 [1] clock cycle time FT Unit FT Max A Tcy(clk) Typ A R PCLK cycle time Min F D D Tcy(PCLK) Conditions A FT FT A A R R D D D Parameter FT FT FT FT FT Dynamic characteristics of SPI pins in SPI mode Symbol A A A A A 10.5 SPI interfaces Table 14. R D D D LPC1111/12/13/14 NXP Semiconductors (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 42 of 53 D D R R R R R D D D A A A A A D R R A A R A FT R A F FT FT A A R R D D D tclk(L) D R FT FT A A R R D D D tclk(H) FT FT FT FT A A R R D D D Tcy(clk) FT FT FT FT FT LPC1111/12/13/14 NXP Semiconductors D FT FT A A R R D SCK (CPOL = 0) D D R A FT D SCK (CPOL = 1) R th(Q) DATA VALID MOSI DATA VALID tDS DATA VALID MISO DATA VALID DATA VALID CPHA = 1 th(Q) DATA VALID tDH tDS MISO tDH DATA VALID tv(Q) MOSI A tv(Q) CPHA = 0 DATA VALID 002aae829 Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. Fig 21. SPI master timing in SPI mode LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 43 of 53 D D R R R R R D D D A A A A A D R R A A FT R F FT FT A A A D FT SCK (CPOL = 0) FT A A R R D tDH D R R tDS R A D D tclk(L) D R FT FT A A R R D D D tclk(H) FT FT FT FT A A R R D D D Tcy(clk) FT FT FT FT FT LPC1111/12/13/14 NXP Semiconductors D D R A FT D SCK (CPOL = 1) R DATA VALID DATA VALID tv(Q) MISO th(Q) DATA VALID DATA VALID tDH DATA VALID tv(Q) MISO DATA VALID CPHA = 1 DATA VALID tDS MOSI A MOSI th(Q) CPHA = 0 DATA VALID 002aae830 Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. Fig 22. SPI slave timing in SPI mode LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 44 of 53 D D R R R R R D D D A A A A A R A A FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D 11.1 XTAL input FT D R FT FT A A R R D D D 11. Application information FT FT FT FT LPC1111/12/13/14 NXP Semiconductors D D R The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV(RMS) is needed. A 002aae788 Fig 23. Slave mode operation of the on-chip oscillator 11.2 XTAL Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1,Cx2, and Cx3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout. 11.3 Standard I/O pad configuration Figure 24 shows the possible pin modes for standard I/O pins. The pull-up and pull-down resistors (Rpu and Rpd) can be enabled or disabled. The default value for each standard port pin is input with Rpu enabled. For details on pin modes and hysteresis control, see the LPC11xx user manual. LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 45 of 53 A Cg R Ci 100 pF D XTALIN FT LPC1xxx D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D VDD(IO) FT FT FT FT FT LPC1111/12/13/14 NXP Semiconductors D FT FT A A R R D D D Rpu R A FT D R A enable output PIN input Rpd hysteresis control VSS 002aae828 Fig 24. Standard I/O pad configuration LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 46 of 53 D D R R R R R D D D A A A A A D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 12. Package outline FT FT FT FT FT LPC1111/12/13/14 NXP Semiconductors D FT A A R R D LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm FT SOT313-2 D D R A FT D R A c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M bp pin 1 index Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 7.1 6.9 0.5 9.15 8.85 9.15 8.85 1 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) 0.95 0.55 7o o 0 0.95 0.55 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT313-2 136E05 MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 25. Package outline SOT313-2 (LQFP48) LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 47 of 53 D D R R R R R D D D A A A A A FT FT FT FT FT LPC1111/12/13/14 D R R A A FT FT FT FT A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D PLCC44: plastic leaded chip carrier; 44 leads SOT187-2 D D R A FT D R A eD eE y X 39 A 29 28 40 bp ZE b1 w M 44 1 E HE pin 1 index A A4 A1 e (A 3) 6 18 Lp k 7 detail X 17 e v M A ZD D B HD v M B 0 5 10 mm scale DIMENSIONS (mm dimensions are derived from the original inch dimensions) A4 A1 e UNIT A A3 D(1) E(1) eD eE HD bp b1 max. min. 4.57 4.19 mm inches 0.81 0.66 HE k 16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.27 16.51 16.51 14.99 14.99 17.40 17.40 1.07 0.51 0.25 3.05 0.53 0.33 0.180 0.02 0.165 0.01 0.12 0.021 0.032 0.656 0.656 0.05 0.013 0.026 0.650 0.650 0.63 0.59 0.63 0.59 Lp v w y 1.44 1.02 0.18 0.18 0.1 ZD(1) ZE(1) max. max. 2.16 2.16 45 o 0.695 0.695 0.048 0.057 0.007 0.007 0.004 0.085 0.085 0.685 0.685 0.042 0.040 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT187-2 112E10 MS-018 EDR-7319 EUROPEAN PROJECTION ISSUE DATE 99-12-27 01-11-14 Fig 26. Package outline PLCC44 LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 48 of 53 D D R R R R R D D D A A A A A FT FT FT FT FT LPC1111/12/13/14 D R R A A FT FT FT FT A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm D D R A FT D R A A B D terminal 1 index area E A A1 c detail X e1 e 9 16 C C A B C v w b y y1 C L 8 17 e e2 Eh 33 1 terminal 1 index area 24 32 X 25 Dh 0 2.5 Dimensions Unit mm 5 mm scale A(1) A1 b max 1.00 0.05 0.35 nom 0.85 0.02 0.28 min 0.80 0.00 0.23 c D(1) Dh E(1) 0.2 7.1 7.0 6.9 4.85 4.70 4.55 7.1 7.0 6.9 Eh e e1 e2 L 0.75 4.85 4.70 0.65 4.55 4.55 0.60 0.45 4.55 v 0.1 w y 0.05 0.08 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version References IEC JEDEC JEITA --- hvqfn33_po European projection Issue date 09-03-17 09-03-23 Fig 27. Package outline (HVQFN33) LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 49 of 53 D D R R R R D R R A A FT A Universal Asynchronous Receiver/Transmitter R UART D Transistor-Transistor Logic D Serial Synchronous Interface TTL (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 F SSI FT Serial Peripheral Interface FT SPI A Phase-Locked Loop A PLL R General Purpose Input/Output R Embedded Trace Macrocell GPIO D ETM D BrownOut Detection FT BOD A Advanced Peripheral Bus R APB D Advanced Microcontroller Bus Architecture A FT FT Advanced High-performance Bus AMBA R A A AHB D R R Analog-to-Digital Converter R A D D ADC D R FT FT A A R R D D D Description FT FT FT FT A A R R D D D Acronym FT FT FT FT FT Abbreviations LPC1111_12_13_14_0 Objective data sheet A A A A A 13. Abbreviations Table 15. R D D D LPC1111/12/13/14 NXP Semiconductors 50 of 53 D D R R R R D R R A A FT FT FT FT A A R R D D D FT D A F FT FT A A R R R D FT LPC1111_12_13_14_0.11 <tbd> Objective data sheet - LPC1111_12_13_0.09 R A D R A Parts LPC1111/101, LPC1112/101 added. Flash and SRAM configuration changed (see Table 2). Objective data sheet - LPC1111_13_0.06 - LPC1111_13_0.05 Objective data sheet - LPC1111_13_0.04 Objective data sheet - LPC11xx_0.03 - - Part LPC1112 added. PLCC44 package added. LPC1111_13_0.06 <tbd> Objective data sheet Modifications: SWO removed from pin description LPC1111_13_0.05 <tbd> Modifications: Editorial updates. LPC1111_13_0.04 <tbd> Modifications: SPI1 interface added for LQFP48 packages. LPC11xx_0.03 <tbd> Objective data sheet LPC1111_12_13_14_0 (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 FT Part LPC1114 added. <tbd> * * D Supersedes D Change notice * * * FT A A R R D Data sheet status Objective data sheet R A D D Release date Modifications: D R FT FT A A R R D D D Document ID LPC1111_12_13_0.09 FT FT FT FT FT Revision history Modifications: A A A A A 14. Revision history Table 16. R D D D LPC1111/12/13/14 NXP Semiconductors 51 of 53 D D R R R R R D D D A A A A A FT D R R A A FT FT FT FT A A R R D D D D R R A FT FT FT A A R R D D D R F D FT FT A A R R D 16. Data sheet status A FT FT A A R R D D D 15. Legal information FT FT FT FT LPC1111/12/13/14 NXP Semiconductors D D R A FT Document status[1][2] Product status[3] Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. Definition D R A [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.1 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.2 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC1111_12_13_14_0 Objective data sheet (c) NXP B.V. 2009. All rights reserved. Rev. 00.11 -- 13 November 2009 52 of 53 D D R R R R R D D D D R R A A R A FT R F D FT FT A A R D D 27 27 27 27 27 28 28 29 30 34 34 36 39 39 39 40 41 42 45 45 R D R A A All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 November 2009 Document identifier: LPC1111_12_13_14_0 R Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. D 45 45 47 50 51 52 52 52 52 52 52 53 FT Brownout detection . . . . . . . . . . . . . . . . . . . . Code security (Code Read Protection - CRP) APB interface . . . . . . . . . . . . . . . . . . . . . . . . . AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External interrupt inputs . . . . . . . . . . . . . . . . . Memory mapping control . . . . . . . . . . . . . . . . Emulation and debugging . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . BOD static characteristics . . . . . . . . . . . . . . . Power consumption . . . . . . . . . . . . . . . . . . . Electrical pin characteristics. . . . . . . . . . . . . . Dynamic characteristics. . . . . . . . . . . . . . . . . Flash memory . . . . . . . . . . . . . . . . . . . . . . . . External clock. . . . . . . . . . . . . . . . . . . . . . . . . Internal oscillators . . . . . . . . . . . . . . . . . . . . . I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . . XTAL Printed Circuit Board (PCB) layout guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard I/O pad configuration . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (c) NXP B.V. 2009. A FT FT A A R R D D D 11.3 12 13 14 15 16 16.1 16.2 16.3 17 18 D R FT FT A A R R D D D 7.16.2 7.16.3 7.16.4 7.16.5 7.16.6 7.16.7 7.17 8 9 9.1 9.2 9.3 10 10.1 10.2 10.3 10.4 10.5 11 11.1 11.2 FT FT FT FT A A R R D D D General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional description . . . . . . . . . . . . . . . . . . 18 ARM Cortex-M0 processor . . . . . . . . . . . . . . . 18 On-chip flash program memory . . . . . . . . . . . 18 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 18 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 18 Nested Vectored Interrupt Controller (NVIC) . 19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 20 IOCONFIG block . . . . . . . . . . . . . . . . . . . . . . 20 Fast general purpose parallel I/O . . . . . . . . . . 20 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 I2C-bus serial I/O controller . . . . . . . . . . . . . . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 General purpose external event counters/timers . . . . . . . . . . . . . . . . . . . . . . . . 22 7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.13 System tick timer . . . . . . . . . . . . . . . . . . . . . . 23 7.14 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 23 7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.15 Clocking and power control . . . . . . . . . . . . . . 24 7.15.1 Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 24 7.15.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 25 7.15.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 25 7.15.2 System PLL (PLL0) . . . . . . . . . . . . . . . . . . . . 25 7.15.3 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.15.4 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 25 7.15.5 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.15.5.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.15.5.2 Deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 26 7.15.5.3 Deep power-down mode . . . . . . . . . . . . . . . . 26 7.16 System control . . . . . . . . . . . . . . . . . . . . . . . . 26 7.16.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 FT FT FT FT FT 18. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.5.1 7.5.2 7.6 7.7 7.7.1 7.8 7.8.1 7.9 7.9.1 7.10 7.10.1 7.11 7.11.1 7.12 A A A A A LPC1111/12/13/14 NXP Semiconductors