HEF4020BT,652 - NEXPERIA

HEF4020B

14-stage binary counter

Rev. 10 — 18 October 2018 Product data sheet

1. General description

The HEF4020B is a 14-stage binary counter with a clock input (CP), an overriding asynchronous

master reset input (MR) and twelve fully buffered outputs (Q0, and Q3 to Q13). The counter

advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and

forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle

flip-flop. A feature of the device is its high speed (typ. 35 MHz at VDD = 15 V).

It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS

(usually ground). Unused inputs must be connected to VDD, VSS, or another input.

2. Features and benefits

•High speed operation

•Fully static operation

•5 V, 10 V, and 15 V parametric ratings

•Standardized symmetrical output characteristics

•Specified from -40 °C to +85 °C

•Complies with JEDEC standard JESD 13-B

3. Ordering information

Table 1. Ordering information

PackageType number

Temperature range Name Description Version

HEF4020BT -40 °C to +85 °C SO16 plastic small outline package; 16 leads;

body width 3.9 mm

SOT109-1

Nexperia HEF4020B

14-stage binary counter

4. Functional diagram

001aad722

14-STAGE COUNTER

Q10

Q11

Q12

Q13

Fig. 1. Functional diagram

001aad723

Q0 9

11 MR

10 CP

Q3 7

Q4 5

Q5 4

Q6 6

Q7 13

Q8 12

Q9 14

Q10 15

Q11 1

Q12 2

Q13 3

Fig. 2. Logic symbol

001aad724

0 9

11 CT

CTR14

13 3

Fig. 3. IEC Logic symbol

001aad725

Q10

Q11

Q12

Q13

Fig. 4. Logic diagram

Product data sheet Rev. 10 — 18 October 2018 2 / 11

Nexperia HEF4020B

14-stage binary counter

5. Pinning information

5.1. Pinning

HEF4020B

Q11 VDD

Q12 Q10

Q13 Q9

Q5 Q7

Q4 Q8

Q6 MR

Q3 CP

VSS Q0

001aaj101

Fig. 5. Pin configuration SOT109-1 (SO16)

5.2. Pin description

Table 2. Pin description

Symbol Pin Description

Q3 to Q13 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3 parallel output (Q3 to Q13)

VSS 8 ground supply voltage

Q0 9 parallel output

CP 10 clock input (HIGH-to-LOW edge triggered)

MR 11 master reset input (active HIGH)

VDD 16 supply voltage

6. Functional description

Table 3. Functional table

H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = positive-going transition; ↓ = negative-going transition.

Input Output

CP MR Q0, Q3 to Q13

↑ L no change

↓ L count

X H L

Product data sheet Rev. 10 — 18 October 2018 3 / 11

Nexperia HEF4020B

14-stage binary counter

001aad726

1 2 4 8 16 32 64 128 256 512 1024 2048 4096

CP input

MR input

Q10

Q11

8192 16384

Q12

Q13

Fig. 6. Timing diagram

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage -0.5 +18 V

IIK input clamping current VI < -0.5 V or VI > VDD + 0.5 V - ±10 mA

VIinput voltage -0.5 VDD + 0.5 V

IOK output clamping current VO < -0.5 V or VO > VDD + 0.5 V - ±10 mA

II/O input/output current - ±10 mA

IDD supply current - 50 mA

Tstg storage temperature -65 +150 °C

Tamb ambient temperature -40 +85 °C

Ptot total power dissipation Tamb -40 °C to +85 °C [1] - 500 mW

P power dissipation per output - 100 mW

[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.

8. Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3 - 15 V

VIinput voltage 0 - VDD V

Tamb ambient temperature in free air -40 - +85 °C

VDD = 5 V - - 3.75 μs/V

VDD = 10 V - - 0.5 μs/V

Δt/ΔV input transition rise and fall rate

VDD = 15 V - - 0.08 μs/V

Product data sheet Rev. 10 — 18 October 2018 4 / 11

Nexperia HEF4020B

14-stage binary counter

9. Static characteristics

Table 6. Static characteristics

VSS = 0 V; VI = VSS or VDD; unless otherwise specified.

Tamb = -40 °C Tamb = 25 °C Tamb = 85 °CSymbol Parameter Conditions VDD

Min Max Min Max Min Max

Unit

5 V 3.5 - 3.5 - 3.5 - V

10 V 7.0 - 7.0 - 7.0 - V

VIH HIGH-level input voltage |IO| < 1 μA

15 V 11.0 - 11.0 - 11.0 - V

5 V - 1.5 - 1.5 - 1.5 V

10 V - 3.0 - 3.0 - 3.0 V

VIL LOW-level input voltage |IO| < 1 μA

15 V - 4.0 - 4.0 - 4.0 V

5 V 4.95 - 4.95 - 4.95 - V

10 V 9.95 - 9.95 - 9.95 - V

VOH HIGH-level output voltage |IO| < 1 μA

15 V 14.95 - 14.95 - 14.95 - V

5 V - 0.05 - 0.05 - 0.05 V

10 V - 0.05 - 0.05 - 0.05 V

VOL LOW-level output voltage |IO| < 1 μA

15 V - 0.05 - 0.05 - 0.05 V

VO = 2.5 V 5 V - -1.7 - -1.4 - -1.1 mA

VO = 4.6 V 5 V - -0.52 - -0.44 - -0.36 mA

VO = 9.5 V 10 V - -1.3 - -1.1 - -0.9 mA

IOH HIGH-level output current

VO = 13.5 V 15 V - -3.6 - -3.0 - -2.4 mA

VO = 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA

VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA

IOL LOW-level output current

VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA

IIinput leakage current 15 V - ±0.3 - ±0.3 - ±1.0 μA

5 V - 20 - 20 - 150 μA

10 V - 40 - 40 - 300 μA

IDD supply current IO = 0 A

15 V - 80 - 80 - 600 μA

CIinput capacitance - - - - 7.5 - - pF

Product data sheet Rev. 10 — 18 October 2018 5 / 11

Nexperia HEF4020B

14-stage binary counter

10. Dynamic characteristics

Table 7. Dynamic characteristics

VSS = 0 V; Tamb = 25 °C; for test circuit see Fig. 8.

Symbol Parameter Conditions VDD Extrapolation formula [1] Min Typ Max Unit

5 V 78 ns + (0.55 ns/pF)CL- 105 210 ns

10 V 34 ns + (0.23 ns/pF)CL- 45 90 ns

CP to Q0;

see Fig. 7

15 V 22 ns + (0.16 ns/pF)CL- 30 65 ns

5 V 53 ns + (0.55 ns/pF)CL- 80 160 ns

10 V 19 ns + (0.23 ns/pF)CL- 30 60 ns

Qn to Qn + 1

15 V 12 ns + (0.16 ns/pF)CL- 20 40 ns

5 V 153 ns + (0.55 ns/pF)CL- 180 360 ns

10 V 79 ns + (0.23 ns/pF)CL- 90 180 ns

tPHL HIGH to LOW

propagation delay

MR to Qn;

see Fig. 7

15 V 62 ns + (0.16 ns/pF)CL- 70 140 ns

5 V 78 ns + (0.55 ns/pF)CL- 105 210 ns

10 V 39 ns + (0.23 ns/pF)CL- 50 95 ns

CP to Q0;

see Fig. 7

15 V 27 ns + (0.16 ns/pF)CL- 35 70 ns

5 V 43 ns + (0.55 ns/pF)CL- 70 140 ns

10 V 14 ns + (0.23 ns/pF)CL- 25 50 ns

tPLH LOW to HIGH

propagation delay

Qn to Qn + 1

15 V 12 ns + (0.16 ns/pF)CL- 20 40 ns

5 V 10 ns + (1.00 ns/pF)CL- 60 120 ns

10 V 9 ns + (0.42 ns/pF)CL- 30 60 ns

tttransition time see Fig. 7

15 V 6 ns + (0.28 ns/pF)CL- 20 40 ns

5 V 50 25 - ns

10 V 25 15 - ns

CP = HIGH;

minimum width;

see Fig. 7

15 V 20 10 - ns

5 V 130 65 - ns

10 V 95 50 - ns

tWpulse width

MR = HIGH;

minimum width;

see Fig. 7

15 V 90 45 - ns

5 V 115 60 - ns

10 V 65 35 - ns

trec recovery time MR input;

see Fig. 7

15 V 55 25 - ns

5 V 5 10 - MHz

10 V 13 25 - MHz

fmax maximum frequency see Fig. 7

15 V 18 35 - MHz

[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).

Table 8. Dynamic power dissipation PD

PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.

Symbol Parameter VDD Typical formula for PD (μW) where:

5 V PD = 600 × fi + ∑(fo × CL) × VDD

10 V PD = 2800 × fi + ∑(fo × CL) × VDD

PDdynamic power

dissipation

15 V PD = 8200 × fi + ∑(fo × CL) × VDD

fi = input frequency in MHz,

fo = output frequency in MHz,

CL = output load capacitance in pF,

VDD = supply voltage in V,

∑(fo × CL) = sum of the outputs.

Product data sheet Rev. 10 — 18 October 2018 6 / 11

Nexperia HEF4020B

14-stage binary counter

10.1. Waveforms and test circuit

MR INPUT

Q0 or Qn

OUTPUT

tPHL

trec 1/fmax

001aae591

tPLH

tttt

tPHL

CP INPUT

VOH

VOL

VSS

Measurement points are given in Table 9.

Fig. 7. Propagation delays, minimum pulse widths, transition and recovery times and maximum clock frequency

Table 9. Measurement points

Supply voltage Input Output

VDD VMVM

5 V to 15 V 0.5VDD 0.5VDD

VMVM

10 %

90 %

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

90 %

10 %

001aaj781

a. Input waveforms

VDD

VIVO

001aag182

DUT

b. Test circuit

Test data is given in Table 10.

Definitions for test circuit:

DUT = Device Under Test.

CL = load capacitance including jig and probe capacitance.

RT = termination resistance should be equal to the output impedance Zo of the pulse generator.

Fig. 8. Test circuit for measuring switching times

Table 10. Test data

Supply voltage Input Load

VDD VItr, tfCL

5 V to 15 V VSS or VDD ≤ 20 ns 50 pF

Product data sheet Rev. 10 — 18 October 2018 7 / 11

Nexperia HEF4020B

14-stage binary counter

11. Package outline

w M

detail X

v M A

(A )

pin 1 index

UNIT A

max. A

1 A

2 A

3 b

p c D

(1) E

(1) (1)

e H

E L L

p Q Z y w v θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10

1.45

1.25 0.25 0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8 1.27 6.2

5.8

0.7

0.6

0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004

0.057

0.049 0.01 0.019

0.014

0.0100

0.0075

0.39

0.38

0.16

0.15 0.05

1.05

0.041

0.244

0.228

0.028

0.020

0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Fig. 9. Package outline SOT109-1 (SO16)

Product data sheet Rev. 10 — 18 October 2018 8 / 11

Nexperia HEF4020B

14-stage binary counter

12. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF4020B v.10 20181018 Product data sheet - HEF4020B v.9

Modifications: •The format of this data sheet has been redesigned to comply with the identity guidelines

of Nexperia.

•Legal texts have been adapted to the new company name where appropriate.

HEF4020B v.9 20160321 Product data sheet - HEF4020B v.8

Modifications: •Type number HEF4020BP (SOT38-4) removed.

HEF4020B v.8 20111118 Product data sheet - HEF4020B v.7

Modifications: •Legal pages updated.

•Changes in "General description" and "Features and benefits".

•Section "Applications" removed.

HEF4020B v.7 20111010 Product data sheet - HEF4020B v.6

HEF4020B v.6 20091127 Product data sheet - HEF4020B v.5

HEF4020B v.5 20090707 Product data sheet - HEF4020B v.4

HEF4020B v.4 20081204 Product data sheet - HEF4020B_CNV v.3

HEF4020B_CNV v.3 19950101 Product specification - HEF4020B_CNV v.2

HEF4020B_CNV v.2 19950101 Product specification - -

Product data sheet Rev. 10 — 18 October 2018 9 / 11

Nexperia HEF4020B

14-stage binary counter

13. Legal information

Data sheet status

Document status

[1][2]

Product

status [3]

Definition

Objective [short]

data sheet

Development This document contains data from

the objective specification for

product development.

Preliminary [short]

data sheet

Qualification This document contains data from

the preliminary specification.

Product [short]

data sheet

Production This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

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Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

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given in the Recommended operating conditions section (if present) or the

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Product data sheet Rev. 10 — 18 October 2018 10 / 11

Nexperia HEF4020B

14-stage binary counter

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Functional diagram.......................................................2

5. Pinning information......................................................3

5.1. Pinning.........................................................................3

5.2. Pin description............................................................. 3

6. Functional description................................................. 3

7. Limiting values............................................................. 4

8. Recommended operating conditions..........................4

9. Static characteristics....................................................5

10. Dynamic characteristics............................................ 6

10.1. Waveforms and test circuit........................................ 7

11. Package outline.......................................................... 8

12. Revision history..........................................................9

13. Legal information......................................................10

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 18 October 2018

Product data sheet Rev. 10 — 18 October 2018 11 / 11