XC3000 Logic Cell Array Families Table of Contents Overview .............................................................. 2-104 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families ................................. 2-105 Architecture ...................................................... 2-106 Programmable Interconnect ............................. 2-111 Crystal Oscillator .............................................. 2-117 Programming ................................................... 2-118 Special Configuration Functions ...................... 2-122 Master Serial Mode .......................................... 2-124 Master Serial Mode Programming Switching Characteristics ............................. 2-125 Master Parallel Mode ....................................... 2-126 Master Parallel Mode Programming Switching Characteristics ............................. 2-127 Peripheral Mode ............................................... 2-128 Peripheral Mode Programming Switching Characteristics ............................. 2-129 Slave Serial Mode ............................................ 2-130 Slave Serial Mode Programming Switching Characteristics ............................. 2-131 Program Readback Switching Characteristics ............................................. 2-131 General LCA Switching Characteristics ........... 2-132 Performance .................................................... 2-133 Power ............................................................... 2-134 Pin Descriptions ............................................... 2-136 Pin Functions During Configuration.................. 2-138 XC3000 Families Pin Assignments .................. 2-139 XC3000 Families Pinouts ................................. 2-140 Component Availability ..................................... 2-151 Ordering Information ........................................ 2-152 XC3000A Logic Cell Array Familiy ....................... 2-161 Absolute Maximum Ratings ............................. 2-162 Operating Conditions ....................................... 2-162 DC Characteristics ........................................... 2-163 Switching Characteristic Guidelines CLB .............................................................. 2-164 Buffer ........................................................... 2-164 IOB .............................................................. 2-166 Ordering Information ........................................ 2-168 Component Availability ..................................... 2-168 XC3000L Low Voltage Logic Cell Array Family .... 2-169 Absolute Maximum Ratings ............................. 2-170 Operating Conditions ....................................... 2-170 DC Characteristics ........................................... 2-171 Switching Characteristic Guidelines CLB .............................................................. 2-172 Buffer ........................................................... 2-172 IOB .............................................................. 2-174 Ordering Information ........................................ 2-176 Component Availability ..................................... 2-176 XC3100, XC3100A Logic Cell Array Families ....... 2-177 Absolute Maximum Ratings ............................. 2-178 Operating Conditions ....................................... 2-178 DC Characteristics ........................................... 2-179 Switching Characteristic Guidelines CLB .............................................................. 2-180 Buffer ........................................................... 2-180 IOB .............................................................. 2-182 Ordering Information ........................................ 2-184 Component Availability ..................................... 2-184 XC3000 Logic Cell Array Family ........................... 2-153 Absolute Maximum Ratings ............................. 2-154 Operating Conditions ....................................... 2-154 DC Characteristics ........................................... 2-155 Switching Characteristic Guidelines CLB .............................................................. 2-156 Buffer ........................................................... 2-156 IOB .............................................................. 2-158 Ordering Information ........................................ 2-160 Component Availability ..................................... 2-160 2-103 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Overview other user-friendly enhancements. The ease-of-use of the XC3000A family makes it the obvious choice for all new designs that do not require the speed of the XC3100 or the 3-V operation of the XC3000L. Introduced in 1987/88, XC3000 is the industry's most successful family of FPGAs, with over 10 million devices shipped. In 1992/93, Xilinx introduced three additional families, offering more speed, functionality, and a new supply-voltage option. XC3000L Family The XC3000L is identical in architecture and features to the XC3000A family, but operates at a nominal supply voltage of 3.3 V. The XC3000L is the right solution for battery-operated and low-power applications. There are now five distinct family groupings within the XC3000 class of LCA devices. * * * * * XC3000 Family XC3000A Family (use for new designs) XC3000L Family (use for new designs) XC3100 Family XC3100A Family (use for new designs) XC3100 Family The XC3100 is a performance-optimized relative of the basic XC3000 family. While both families are bitstream and footprint compatible, the XC3100 family extends toggle rates to 270 MHz and in-system performance to 80 MHz. The XC3100 family also offers one additional array size, the XC3195. The XC3100 is best suited for designs that require the highest clock speed or the shortest net delays. All five families share a common architecture, development software, design and programming methodology, and also common package pin-outs. An extensive Product Description covers these common aspects. (Page 2-99). XC3100A Family The XC3100A combines the enhanced feature set of the XC3000A with the performance of the XC3100. It offers the highest functionality, speed and capacity of all XC3000 families. The much shorter individual Product Specifications then provide detailed parametric information for the four individual product families. Here is a simple overview. XC3000 Family The basic XC3000 family forms the cornerstone for the rest of the XC3000 class of devices. The basic XC3000 family offers five different device densities with guaranteed toggle rates from 70 to 125 MHz. The figure below illustrates the relationships between the families. Compared to the original XC3000 family, XC3000A offers additional functionality and , coming soon, increased speed. The XC3000L family offers the same additional functionality, but reduced speed due to its lower supply voltage of 3.3 V. The XC3100 family offers no additional functionality, but substantially higher speed, and higher density with its new member, the XC3195. XC3000A Family The XC3000A is an enhanced version of the basic XC3000 family, featuring additional interconnect resources and nality Functio 0A XC310 0A XC300 0L XC300 0 XC310 Speed C3000 X 95 XC31 Gate city Capa X3447 2-104 IMPORTANT NOTICE All new designs should use XC3000A or XC3100A. Information on XC3000 and XC3100 is presented here as reference for existing designs. XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Product Description Features * Complete XACT Development System - - - - - * Complete line of five related Field Programmable Gate Array product families - XC3000, XC3000A, XC3000L, XC3100, XC3100A * Ideal for a wide range of custom VLSI design tasks * * - Replaces TTL, MSI, and other PLD logic - Integrates complete sub-systems into a single package - Avoids the NRE, time delay, and risk of conventional masked gate arrays High-performance CMOS static memory technology - Guaranteed toggle rates of 70 to 325 MHz, logic delays from 9 to 2.2 ns - System clock speeds over 80 MHz - Low quiescent and active power consumption Flexible FPGA architecture - Compatible arrays ranging from 1,000 to 7,500 gate complexity - Extensive register, combinatorial, and I/O capabilities - High fan-out signal distribution, low-skew clock nets - Internal 3-state bus capabilities - TTL or CMOS input thresholds - On-chip crystal oscillator amplifier Description The CMOS XC3000 Class of Logic Cell Array (LCA) families provide a group of high-performance, high-density, digital integrated circuits. Their regular, extendable, flexible, user-programmable array architecture is composed of a configuration program store plus three types of configurable elements: a perimeter of I/O Blocks (IOBs), a core array of Configurable Logic Bocks (CLBs) and resources for interconnection. The general structure of an LCA device is shown in Figure 1 on the next page. The XACT development system provides schematic capture and auto place-and-route for design entry. Logic and timing simulation, and in-circuit emulation are available as design verification alternatives. The design editor is used for interactive design optimization, and to compile the data pattern that represents the configuration program. The LCA user logic functions and interconnections are determined by the configuration program data stored in internal static memory cells. The program can be loaded in any of several modes to accommodate various system requirements. The program data resides externally in an EEPROM, EPROM or ROM on the application circuit board, or on a floppy disk or hard disk. On-chip initialization logic provides for optional automatic loading of program data at power-up. The companion XC17XX Serial Configuration PROMs provide a very simple serial configuration program storage in a one-time programmable package. * Unlimited reprogrammability * - Easy design iteration - In-system logic changes Extensive Packaging Options - Over 20 different packages - Plastic and ceramic surface-mount and pin-gridarray packages - Thin and Very Thin Quad Flat Pack (TQFP and VQFP) options * Ready for volume production - Standard, off-the-shelf product availability - 100% factory pre-tested devices - Excellent reliability record Device XC3020, 3020A, 3020L, 3120, 3120A XC3030, 3030A, 3030L, 3130, 3130A XC3042, 3042A, 3042L, 3142, 3142A XC3064, 3064A, 3064L, 3164, 3164A XC3090, 3090A, 3090L, 3190, 3190A XC3195, 3195A Schematic capture, automatic place and route Logic and timing simulation Interactive design editor for design optimization Timing calculator Interfaces to popular design environments like Viewlogic, Cadence, Mentor Graphics, and others CLBs Array 64 100 144 224 320 484 8x8 10 x 10 12 x 12 16 x 14 16 x 20 22 x 22 2-105 User I/Os Max 64 80 96 120 144 176 Flip-Flops 256 360 480 688 928 1,320 Horizontal Longlines 16 20 24 32 40 44 Configuration Data Bits 14,779 22,176 30,784 46,064 64,160 94,984 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families configuration. Program data may be either bit serial or byte parallel. The XACT development system generates the configuration program bitstream used to configure the LCA device. The memory loading process is independent of the user logic functions. The XC3000 Logic Cell Array families provide a variety of logic capacities, package styles, temperature ranges and speed grades. Architecture The perimeter of configurable IOBs provides a programmable interface between the internal logic array and the device package pins. The array of CLBs performs user-specified logic functions. The interconnect resources are programmed to form networks, carrying logic signals among blocks, analogous to printed circuit board traces connecting MSI/SSI packages. Configuration Memory The static memory cell used for the configuration memory in the Logic Cell Array has been designed specifically for high reliability and noise immunity. Integrity of the LCA device configuration memory based on this design is assured even under adverse conditions. Compared with other programming alternatives, static memory provides the best combination of high density, high performance, high reliability and comprehensive testability. As shown in Figure 2, the basic memory cell consists of two CMOS inverters plus a pass transistor used for writing and reading cell data. The cell is only written during configuration and only read during readback. During normal operation, the cell provides continuous control and the pass transistor is off and does not affect cell stability. This is quite different from the operation of conventional memory devices, in which the cells are frequently read and rewritten. The block logic functions are implemented by programmed look-up tables. Functional options are implemented by program-controlled multiplexers. Interconnecting networks between blocks are implemented with metal segments joined by program-controlled pass transistors. These LCA functions are established by a configuration program which is loaded into an internal, distributed array of configuration memory cells. The configuration program is loaded into the LCA device at power-up and may be reloaded on command. The Logic Cell Array includes logic and control signals to implement automatic or passive PWR P9 P8 P7 P6 P5 P4 P3 P2 GND DN I/O Blocks P11 3-State Buffers With Access to Horizontal Long Lines Configurable Logic Blocks TCL KIN AA AB AC AD P12 Interconnect Area BA BB U61 Frame Pointer P13 Configuration Memory X3241 Figure 1. Logic Cell Array Structure. It consists of a perimeter of programmable I/O blocks, a core of configurable logic blocks and their interconnect resources. These are all controlled by the distributed array of configuration program memory cells. 2-106 Q Q Read or Write The method of loading the configuration data is selectable. Two methods use serial data, while three use byte-wide data. The internal configuration logic utilizes framing information, embedded in the program data by the XACT development system, to direct memory-cell loading. The serial-data framing and length-count preamble provide programming compatibility for mixes of various LCA device devices in a synchronous, serial, daisy-chain fashion. Configuration Control Data X5382 Figure 2. Static Configuration Memory Cell. It is loaded with one bit of configuration program and controls one program selection in the Logic Cell Array. The memory cell outputs Q and Q use ground and VCC levels and provide continuous, direct control. The additional capacitive load together with the absence of address decoding and sense amplifiers provide high stability to the cell. Due to the structure of the configuration memory cells, they are not affected by extreme power-supply excursions or very high levels of alpha particle radiation. In reliability testing, no soft errors have been observed even in the presence of very high doses of alpha radiation. I/O Block Each user-configurable IOB shown in Figure 3, provides an interface between the external package pin of the device and the internal user logic. Each IOB includes both registered and direct input paths. Each IOB provides a programmable 3-state output buffer, which may be driven by a registered or direct output signal. Configuration options allow each IOB an inversion, a controlled slew rate and a high impedance pull-up. Each input circuit also provides input clamping diodes to provide electrostatic protection, and circuits to inhibit latch-up produced by input currents. Vcc PROGRAM-CONTROLLED MEMORY CELLS OUT INVERT 3- STATE (OUTPUT ENABLE) OUT OUTPUT SELECT 3-STATE INVERT SLEW RATE PASSIVE PULL UP T O D Q OUTPUT BUFFER FLIP FLOP I/O PAD R DIRECT IN REGISTERED IN I Q Q D FLIP FLOP or LATCH TTL or CMOS INPUT THRESHOLD R OK (GLOBAL RESET) IK CK1 CK2 PROGRAM CONTROLLED MULTIPLEXER = PROGRAMMABLE INTERCONNECTION POINT or PIP X3029 Figure 3. Input/Output Block. Each IOB includes input and output storage elements and I/O options selected by configuration memory cells. A choice of two clocks is available on each die edge. The polarity of each clock line (not each flip-flop or latch) is programmable. A clock line that triggers the flip-flop on the rising edge is an active Low Latch Enable (Latch transparent) signal and vice versa. Passive pull-up can only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS thresholds. 2-107 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families The input-buffer portion of each IOB provides threshold detection to translate external signals applied to the package pin to internal logic levels. The global input-buffer threshold of the IOBs can be programmed to be compatible with either TTL or CMOS levels. The buffered input signal drives the data input of a storage element, which may be configured as either a flip-flop or a latch. The clocking polarity (rising/falling edge-triggered flip-flop, High/Low transparent latch) is programmable for each of the two clock lines on each of the four die edges. Note that a clock line driving a rising edge-triggered flip-flop makes any latch driven by the same line on the same edge Lowlevel transparent and vice versa (falling edge, High transparent). All Xilinx primitives in the supported schematic-entry packages, however, are positive edgetriggered flip-flops or High transparent latches. When one clock line must drive flip-flops as well as latches, it is necessary to compensate for the difference in clocking polarities with an additional inverter either in the flip-flop clock input or the latch-enable input. I/O storage elements are reset during configuration or by the active-Low chip RESET input. Both direct input (from IOB pin I) and registered input (from IOB pin Q) signals are available for interconnect. For reliable operation, inputs should have transition times of less than 100 ns and should not be left floating. Floating CMOS input-pin circuits might be at threshold and produce oscillations. This can produce additional power dissipation and system noise. A typical hysteresis of about 300 mV reduces sensitivity to input noise. Each user IOB includes a programmable high-impedance pull-up resistor, which may be selected by the program to provide a constant High for otherwise undriven package pins. Although the Logic Cell Array provides circuitry to provide input protection for electrostatic discharge, normal CMOS handling precautions should be observed. Flip-flop loop delays for the IOB and logic-block flip-flops are about 3 ns. This short delay provides good performance under asynchronous clock and data conditions. Short loop delays minimize the probability of a metastable condition that can result from assertion of the clock during data transitions. Because of the short-loop-delay characteristic in the Logic Cell Array, the IOB flip-flops can be used to synchronize external signals applied to the device. Once synchronized in the IOB, the signals can be used internally without further consideration of their clock relative timing, except as it applies to the internal logic and routing-path delays. (IOB) pin FT can control output activity. An open-drain output may be obtained by using the same signal for driving the output and 3-state signal nets so that the buffer output is enabled only for a Low. Configuration program bits for each IOB control features such as optional output register, logic signal inversion, and 3-state and slew-rate control of the output. The program-controlled memory cells of Figure 3 control the following options. * Logic inversion of the output is controlled by one configuration program bit per IOB. * Logic 3-state control of each IOB output buffer is determined by the states of configuration program bits which turn the buffer on, or off, or select the output buffer 3-state control interconnection (IOB pin T). When this IOB output control signal is High, a logic one, the buffer is disabled and the package pin is high impedance. When this IOB output control signal is Low, a logic zero, the buffer is enabled and the package pin is active. Inversion of the buffer 3-state control-logic sense (output enable) is controlled by an additional configuration program bit. * Direct or registered output is selectable for each IOB. The register uses a positive-edge, clocked flip-flop. The clock source may be supplied (IOB pin OK) by either of two metal lines available along each die edge. Each of these lines is driven by an invertible buffer. * Increased output transition speed can be selected to improve critical timing. Slower transitions reduce capacitive-load peak currents of non-critical outputs and minimize system noise. * An internal high-impedance pull-up resistor (active by default) prevents unconnected inputs from floating. Summary of I/O Options * Inputs - - - - Direct Flip-flop/latch CMOS/TTL threshold (chip inputs) Pull-up resistor/open circuit * Outputs IOB output buffers provide CMOS-compatible 4-mA source-or-sink drive for high fan-out CMOS or TTL- compatible signal levels (8 mA in the XC3100 family). The network driving IOB pin O becomes the registered or direct data source for the output buffer. The 3-state control signal 2-108 - - - - - Direct/registered Inverted/not 3-state/on/off Full speed/slew limited 3-state/output enable (inverse) Configurable Logic Block The array of CLBs provides the functional elements from which the user's logic is constructed. The logic blocks are arranged in a matrix within the perimeter of IOBs. The XC3020 has 64 such blocks arranged in 8 rows and 8 columns. The XACT development system is used to compile the configuration data which is to be loaded into the internal configuration memory to define the operation and interconnection of each block. User definition of CLBs and their interconnecting networks may be done by automatic translation from a schematic-capture logic diagram or optionally by installing library or user macros. Each CLB has a combinatorial logic section, two flip-flops, and an internal control section. See Figure 4. There are: five logic inputs (A, B, C, D and E); a common clock input (K); an asynchronous direct RESET input (RD); and an enable clock (EC). All may be driven from the interconnect resources adjacent to the blocks. Each CLB also has two outputs (X and Y) which may drive interconnect networks. Data input for either flip-flop within a CLB is supplied from the function F or G outputs of the combinatorial logic, or the block input, DI. Both flip-flops in each CLB share the DI DATA IN 0 MUX F D Q 1 DIN G QX RD QX X A F F B LOGIC VARIABLES C D COMBINATORIAL FUNCTION E CLB OUTPUTS G G QY Y QY F DIN G 0 MUX D Q 1 EC ENABLE CLOCK RD 1 (ENABLE) K CLOCK DIRECT RESET RD 0 (INHIBIT) (GLOBAL RESET) X3032 Figure 4. Configurable Logic Block. Each CLB includes a combinatorial logic section, two flip-flops and a program memory controlled multiplexer selection of function. It has. five logic variable inputs A, B, C, D, and E a direct data in DI an enable clock EC a clock (invertible) K an asynchronous direct RESET RD two outputs X and Y 2-109 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families A B Count Enable Parallel Enable Clock QX QY C D Any Function of Up to 4 Variables Terminal Count F Dual Function of 4 Variables E D Q Q0 D0 A B QX QY C D FG Mode Any Function of Up to 4 Variables G E 5a D Q Q1 D1 A B Function of 5 Variables QX F Mode F QY Any Function of 5 Variables G C D E 5b D Q Q2 D2 A B QX Function of 6 Variables QY C FGM Mode Any Function of Up to 4 Variables X5383 D F M U X A B Figure 6. C8BCP Macro. G The C8BCP macro (modulo-8 binary counter with parallel enable and clock enable) uses one combinatorial logic block of each option. QX QY Any Function of Up to 4 Variables C D E 5c FGM Mode X5442 Figure 5 5a. Combinatorial Logic Option FG generates two functions of four variables each. One variable, A, must be common to both functions. The second and third variable can be any choice of of B, C, QX and QY The fourth variable can be any choice of D or E. 5b. Combinatorial Logic Option F generates any function of five variables: A, D, E and and two choices out of B, C, QX, QY. 5c. Combinatorial Logic Option FGM allows variable E to select between two functions of four variables: Both have common inputs A and D and any choice out of B, C, QX and QY for the remaining two variables. Option 3 can then implement some functions of six or seven variables. 2-110 asynchronous RD which, when enabled and High, is dominant over clocked inputs. All flip-flops are reset by the active-Low chip input, RESET, or during the configuration process. The flip-flops share the enable clock (EC) which, when Low, recirculates the flip-flops' present states and inhibits response to the data-in or combinatorial function inputs on a CLB. The user may enable these control inputs and select their sources. The user may also select the clock net input (K), as well as its active sense within each CLB. This programmable inversion eliminates the need to route both phases of a clock signal throughout the device. Flexible routing allows use of common or individual CLB clocking. The combinatorial-logic portion of the CLB uses a 32 by 1 look-up table to implement Boolean functions. Variables selected from the five logic inputs and two internal block flip-flops are used as table address inputs. The combinatorial propagation delay through the network is independent of the logic function generated and is spike free for single input variable changes. This technique can generate two independent logic functions of up to four variables each as shown in Figure 5a, or a single function of five variables as shown in Figure 5b, or some functions of seven variables as shown in Figure 5c. Figure 6 shows a modulo-8 binary counter with parallel enable. It uses one CLB of each type. The partial functions of six or seven variables are implemented using the input variable (E) to dynamically select between two functions of four different variables. For the two functions of four variables each, the independent results (F and G) may be used as data inputs to either flip-flop or either logic block output. For the single function of five variables and merged functions of six or seven variables, the F and G outputs are identical. Symmetry of the F and G functions and the flip-flops allows the interchange of CLB outputs to optimize routing efficiencies of the networks interconnecting the CLBs and IOBs. switch connections to block inputs are unidirectional, as are block outputs, they are usable only for block input connection and not for routing. Figure 8 illustrates routing access to logic block input variables, control inputs and block outputs. Three types of metal resources are provided to accommodate various network interconnect requirements. * General Purpose Interconnect * Direct Connection * Longlines (multiplexed busses and wide AND gates) General Purpose Interconnect General purpose interconnect, as shown in Figure 9, consists of a grid of five horizontal and five vertical metal segments located between the rows and columns of logic and IOBs. Each segment is the height or width of a logic block. Switching matrices join the ends of these segments and allow programmed interconnections between the metal grid segments of adjoining rows and columns. The switches of an unprogrammed device are all nonconducting. The connections through the switch matrix may be established by the automatic routing or by using Editnet to select the desired pairs of matrix pins to be connected or disconnected. The legitimate switching matrix combinations for each pin are indicated in Figure 10 and may be highlighted by the use of the Show-Matrix command in the XACT system. Programmable Interconnect Programmable-interconnection resources in the Logic Cell Array provide routing paths to connect inputs and outputs of the IOBs and CLBs into logic networks. Interconnections between blocks are composed of a two-layer grid of metal segments. Specially designed pass transistors, each controlled by a configuration bit, form programmable interconnect points (PIPs) and switching matrices used to implement the necessary connections between selected metal segments and block pins. Figure 7 is an example of a routed net. The XACT development system provides automatic routing of these interconnections. Interactive routing (Editnet) is also available for design optimization. The inputs of the CLBs or IOBs are multiplexers which can be programmed to select an input network from the adjacent interconnect segments. Since the Figure 7. An XACT view of routing resources used to form a typical interconnection network from CLB GA. 2-111 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families X2662 Figure 8. XACT Development System Locations of interconnect access, CLB control inputs, logic inputs and outputs. The dot pattern represents the available programmable interconnection points (PIPs). Some of the interconnect PIPs are directional. This is indicated on the XACT design editor status line: ND is a nondirectional interconnection. D:H->V is a PIP that drives from a horizontal to a vertical line. D:V->H is a PIP that drives from a vertical to a horizontal line. D:C->T is a "T" PIP that drives from a cross of a T to the tail. D:CW is a corner PIP that drives in the clockwise direction. P0 indicates the PIP is non-conducting , P1 is on. 2-112 Special buffers within the general interconnect areas provide periodic signal isolation and restoration for improved performance of lengthy nets. The interconnect buffers are available to propagate signals in either direction on a given general interconnect segment. These bidirectional (bidi) buffers are found adjacent to the switching matrices, above and to the right and may be highlighted by the use of the Show BIDI command in the XACT system. The other PIPs adjacent to the matrices are accessed to or from Longlines. The development system automatically defines the buffer direction based on the location of the interconnection network source. The delay calculator of the XACT development system automatically calculates and displays the block, interconnect and buffer delays for any paths selected. Generation of the simulation netlist with a worst-case delay model is provided by an XACT option. Figure 9. LCA General-Purpose Interconnect. Composed of a grid of metal segments that may be interconnected through switch matrices to form networks for CLB and X2664 IOB inputs and outputs. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Direct Interconnect Direct interconnect, shown in Figure 11, provides the most efficient implementation of networks between adjacent CLBs or I/O Blocks. Signals routed from block to block using the direct interconnect exhibit minimum interconnect propagation and use no general interconnect resources. For each CLB, the X output may be connected directly to the B input of the CLB immediately to its right and to the C input of the CLB to its left. The Y output can use direct interconnect to drive the D input of the block immediately above and the A input of the block below. Direct intercon- X2663 1105 13 Figure 10. Switch Matrix Interconnection Options for Each Pin. Switch matrices on the edges are different. Use Show Matrix menu option in the XACT system Figure 11. CLB X and Y Outputs. The X and Y outputs of each CLB have single contact, direct access to inputs of adjacent CLBs 2-113 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families X2660 Figure 12. XC3020 Die-Edge IOBs. The XC3020 die-edge IOBs are provided with direct access to adjacent CLBs. 2-114 nect should be used to maximize the speed of highperformance portions of logic. Where logic blocks are adjacent to IOBs, direct connect is provided alternately to the IOB inputs (I) and outputs (O) on all four edges of the die. The right edge provides additional direct connects from CLB outputs to adjacent IOBs. Direct interconnections of IOBs with CLBs are shown in Figure 12. Longlines The Longlines bypass the switch matrices and are intended primarily for signals that must travel a long distance, or must have minimum skew among multiple destinations. Longlines, shown in Figure 13, run vertically and horizontally the height or width of the interconnect area. Each interconnection column has three vertical Longlines, and each interconnection row has two horizontal Longlines. Two additional Longlines are located adjacent to the outer sets of switching matrices. In devices larger than the XC3020, two vertical Longlines in each column are connectable half-length lines. On the XC3020, only the outer Longlines are connectable half-length lines. Longlines can be driven by a logic block or IOB output on a column-by-column basis. This capability provides a common low skew control or clock line within each column of logic blocks. Interconnections of these Longlines are shown in Figure 14. Isolation buffers are provided at each input to a Longline and are enabled automatically by the development system when a connection is made. A buffer in the upper left corner of the LCA chip drives a global net which is available to all K inputs of logic blocks. Using the global buffer for a clock signal provides a skewfree, high fan-out, synchronized clock for use at any or all of the IOBs and CLBs. Configuration bits for the K input to each logic block can select this global line or another routing resource as the clock source for its flip-flops. This net may also be programmed to drive the die edge clock lines for IOB use. An enhanced speed, CMOS threshold, direct access to this buffer is available at the second pad from the top of the left die edge. A buffer in the lower right corner of the array drives a horizontal Longline that can drive programmed connections to a vertical Longline in each interconnection column. This alternate buffer also has low skew and high fan-out. The network formed by this alternate buffer's Longlines can be selected to drive the K inputs of the CLBs. CMOS threshold, high speed access to this buffer is available from the third pad from the bottom of the right die edge. Internal Busses A pair of 3-state buffers, located adjacent to each CLB, permits logic to drive the horizontal Longlines. Logic operation of the 3-state buffer controls allows them to implement wide multiplexing functions. Any 3-state buffer input can be selected as drive for the horizontal long-line bus by applying a Low logic level on its 3-state control line. See Figure 15a. The user is required to avoid contention which can result from multiple drivers with opposing logic levels. X1243 Figure 13. Horizontal and Vertical Longlines. These Longlines provide high fan-out, low-skew signal distribution in each row and column. The global buffer in the upper left die corner drives a common line throughout the LCA device. 2-115 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Control of the 3-state input by the same signal that drives the buffer input, creates an open-drain wired-AND function. A logic High on both buffer inputs creates a high impedance, which represents no contention. A logic Low enables the buffer to drive the Longline Low. See Figure 15b. Pull-up resistors are available at each end of the Longline to provide a High output when all connected buffers are non-conducting. This forms fast, wide gating functions. When data drives the inputs, and separate signals drive the 3-state control lines, these buffers form multiplexers (3-state busses). In this case, care must be used to prevent contention through multiple active buffers X1244 Figure 14. Programmable Interconnection of Longlines. This is provided at the edges of the routing area. Three-state buffers allow the use of horizontal Longlines to form on-chip wired AND and multiplexed buses. The left two non-clock vertical Longlines per column (except XC3020) and the outer perimeter Longlines may be programmed as connectible half-length lines. VCC VCC Z = DA * DB * DC * ... * DN (LOW) DA DB DC DN Figure 15a. 3-State Buffers Implement a Wired-AND Function. When all the buffer 3-state lines are High, (high impedance), the pull-up resistor(s) provide the High output. The buffer inputs are driven by the control signals or a Low. X3036 T OE Z = DA * A + DB * B + DC * C + ... + DN * N WEAK KEEPER CIRCUIT DA DB DC DN A B C N Figure 15b. 3-State Buffers Implement a Multiplexer. The selection is accomplished by the buffer 3-state signal. 2-116 X1741 of conflicting levels on a common line. Each horizontal Longline is also driven by a weak keeper circuit that prevents undefined floating levels by maintaining the previous logic level when the line is not driven by an active buffer or a pull-up resistor. Figure 16 shows 3-state buffers, Longlines and pull-up resistors. Crystal Oscillator Figure 16 also shows the location of an internal high speed inverting amplifier which may be used to implement an onchip crystal oscillator. It is associated with the auxiliary buffer in the lower right corner of the die. When the oscillator is configured by MakeBits and connected as a signal source, two special user IOBs are also configured to connect the oscillator amplifier with external crystal oscillator components as shown in Figure 17. A divide by two option is available to assure symmetry. The oscillator circuit becomes active early in the configuration process to allow the oscillator to stabilize. Actual internal connection is delayed until completion of configuration. In Figure 17 the feedback resistor R1, between the output and input, biases the amplifier at threshold. The inversion of the amplifier, together with the R-C networks and an AT-cut series resonant crystal, produce the 360-degree phase shift of the Pierce oscillator. A series resistor R2 may be included to add to the amplifier output impedance when needed for phase-shift control, crystal resistance matching, or to limit the amplifier input swing to control clipping at large amplitudes. Excess feedback voltage may be corrected by the ratio of C2/C1. The amplifier is designed to be used from 1 MHz to about one-half the specified CLB toggle frequency. Use at frequencies below 1 MHz may require individual characterization with respect to a series X1245 Figure 16. XACT Development System. An extra large view of possible interconnections in the lower right corner of the XC3020. 2-117 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families D Q Internal Alternate Clock Buffer External XTAL1 XTAL2 (IN) R1 Suggested Component Values R1 0.5 - 1 M R2 0 - 1 k (may be required for low frequency, phase)t (shift and/or compensation level for crystal Q) C1, C2 10 - 40 pF Y1 1 - 20 MHz AT-cut parallel resonant XTAL 1 (OUT) XTAL 2 (IN) 44 PIN PLCC 30 26 68 PIN PLCC 47 43 84 PIN PGA PLCC J11 57 L11 53 R2 Y1 C1 100 PIN CQFP PQFP 67 82 61 76 C2 132 PIN PGA P13 M13 160 PIN PQFP 82 76 164 PIN CQFP 105 99 175 PIN 208 PIN PGA PQFP T14 110 P15 100 X5302 Figure 17. Crystal Oscillator Inverter. When activated in the MakeBits program and by selecting an output network for its buffer, the crystal oscillator inverter uses two unconfigured package pins and external components to implement an oscillator. An optional divide-by-two mode is available to assure symmetry. resistance. Crystal oscillators above 20 MHz generally require a crystal which operates in a third overtone mode, where the fundamental frequency must be suppressed by an inductor across C2, turning this parallel resonant circuit to double the fundamental crystal frequency, i.e., 2/3 of the desired third harmonic frequency network. When the oscillator inverter is not used, these IOBs and their package pins are available for general user I/O. Programming Table 1 M0 M1 M2 CCLK 0 0 0 0 0 0 1 1 0 1 0 1 output output -- output 1 1 1 1 0 0 1 1 0 1 0 1 -- output -- input Mode Master Master reserved Master Data Bit Serial Byte Wide Addr. = 0000 up -- Byte Wide Addr. = FFFF down reserved -- Peripheral Byte Wide reserved -- Slave Bit Serial Initialization Phase An internal power-on-reset circuit is triggered when power is applied. When Vcc reaches the voltage at which portions of the LCA device begin to operate (nominally 2.5 to 3 V), the programmable I/O output buffers are 3-stated and a high-impedance pull-up resistor is provided for the user I/O pins. A time-out delay is initiated to allow the power supply voltage to stabilize. During this time the powerdown mode is inhibited. The Initialization state time-out (about 11 to 33 ms) is determined by a 14-bit counter driven by a self-generated internal timer. This nominal 1MHz timer is subject to variations with process, temperature and power supply. As shown in Table 1, five configuration mode choices are available as determined by the input levels of three mode pins; M0, M1 and M2. In Master configuration modes, the LCA device becomes the source of the Configuration Clock (CCLK). The beginning of configuration of devices using Peripheral or Slave modes must be delayed long enough for their initialization to be completed. An LCA device with mode lines selecting a Master configuration mode extends its initialization state using four times the delay (43 to 130 ms) to assure that all daisy-chained slave devices, which it may be driving, will 2-118 be ready even if the master is very fast, and the slave(s) very slow. Figure 18 shows the state sequences. At the end of Initialization, the LCA device enters the Clear state where it clears the configuration memory. The active Low, open-drain initialization signal INIT indicates when the Initialization and Clear states are complete. The LCA device tests for the absence of an external active Low RESET before it makes a final sample of the mode lines and enters the Configuration state. An external wired-AND of one or more INIT pins can be used to control configuration by the assertion of the active-Low RESET of a master mode device or to signal a processor that the LCA devices are not yet initialized. If a configuration has begun, a re-assertion of RESET for a minimum of three internal timer cycles will be recognized and the LCA device will initiate an abort, returning to the Clear state to clear the partially loaded configuration memory words. The LCA device will then resample RESET and the mode lines before re-entering the Configuration state. A re-program is initiated.when a configured XC3000 family device senses a High-to-Low transition and subsequent >6 s Low level on the Done/PROG package pin, or, if this pin is externally held permanently Low, a High-to-Low transition and subsequent >6 s Low time on the RESET package pin. The LCA device returns to the Clear state where the configuration memory is cleared and mode lines resampled, as for an aborted configuration. The complete configuration program is cleared and loaded during each configuration program cycle. Length count control allows a system of multiple Logic Cell Arrays, of assorted sizes, to begin operation in a synchronized fashion. The configuration program generated by the MakePROM program of the XACT development system begins with a preamble of 111111110010 followed by a 24-bit length count representing the total number of configuration clocks needed to complete loading of the configuration program(s). The data framing is shown in Figure 19. All LCA devices connected in series read and shift preamble and length count in on positive and out on negative configuration clock edges. An LCA device which has received the preamble and length count then presents a High Data Out until it has intercepted the appropriate number of data frames. When the configuration program memory of an LCA device is full and the length count does not yet compare, the LCA device shifts any additional data through, as it did for preamble and length count. When the LCA device configuration memory is full and the length count compares, the LCA device will execute a synchronous start-up sequence and become operational. See Figure 20. Two CCLK cycles after the completion of loading configuration data, the user I/O pins are enabled as configured. As selected in MakeBits, the internal userlogic RESET is released either one clock cycle before or after the I/O pins become active. A similar timing selection is programmable for the DONE/PROG output signal. DONE/PROG may also be programmed to be an open drain or include a pull-up resistor to accommodate wired ANDing. The High During Configuration (HDC) and Low During Configuration (LDC) are two user I/O pins which are driven active while an LCA device is in its Initialization, All User I/O Pins 3-Stated with High Impedance Pull-Up, HDC=High, LDC=Low INIT Output = Low Power Down No HDC, LDC or Pull-Up PWRDWN Inactive Initialization Power-On Time Delay PWRDWN Active Active RESET Clear Configuration Memory RESET Active No Test Mode Pins Configuration Program Mode Start-Up Operational Mode Active RESET Operates on User Logic Low on DONE/PROGRAM and RESET Clear Is ~ 200 Cycles for the XC3020--130 to 400 s ~ 250 Cycles for the XC3030--165 to 500 s ~ 290 Cycles for the XC3042--195 to 580 s ~ 330 Cycles for the XC3064--220 to 660 s ~ 375 Cycles for the XC3090--250 to 750 s Power-On Delay is 214 Cycles for Non-Master Mode--11 to 33 ms 216 Cycles for Master Mode--43 to 130 ms Figure 18. A State Diagram of the Configuration Process for Power-up and Reprogram. 2-119 X3399 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Clear or Configure states. They and DONE/PROG provide signals for control of external logic signals such as RESET, bus enable or PROM enable during configuration. For parallel Master configuration modes, these signals provide PROM enable control and allow the data pins to be shared with user logic signals. User I/O inputs can be programmed to be either TTL or CMOS compatible thresholds. At power-up, all inputs have TTL thresholds and can change to CMOS thresholds 11111111 0010 < 24-Bit Length Count > 1111 at the completion of configuration if the user has selected CMOS thresholds. The threshold of PWRDWN and the direct clock inputs are fixed at a CMOS level. If the crystal oscillator is used, it will begin operation before configuration is complete to allow time for stabilization before it is connected to the internal circuitry. Configuration Data Configuration data to define the function and interconnection within a Logic Cell Array is loaded from an external --Dummy Bits* --Preamble Code --Configuration Program Length --Dummy Bits (4 Bits Minimum) 0 <Data Frame # 001 > 111 0 <Data Frame # 002 > 111 0 <Data Frame # 003 > 111 . . . . . . . . . . . . 0 <Data Frame # 196 > 111 0 <Data Frame # 197 > 111 Header For XC3120 197 Configuration Data Frames (Each Frame Consists of: A Start Bit (0) A 71-Bit Data Field Three Stop Bits 1111 Program Data Repeated for Each Logic Cell Array in a Daisy Chain Postamble Code (4 Bits Minimum) *The LCA Device Require Four Dummy Bits Min; XACT Software Generates Eight Dummy Bits X5300 XC3020 XC3020A XC3020L XC3120 XC3120A XC3030 XC3030A XC3030L XC3130 XC3130A XC3042 XC3042A XC3042L XC3142 XC3142A XC3064 XC3064A XC3064L XC3164 XC3164A XC3090 XC3090A XC3090L XC3190 XC3190A XC3195 XC3195A Gates 1,000 to 1,500 1,500 to 2,000 2,000 to 3,000 3,500 to 4,500 5,000 to 6,000 6,500 to 7,500 CLBs Row x Col 64 (8 x 8) 100 (10 x 10) 144 (12 x 12) 224 (16 x 14) 320 (20 x 16) 484 (22 x 22) IOBs 64 80 96 120 144 176 Flip-flops 256 Device 360 480 688 928 1,320 Horizontal Longlines 16 20 24 32 40 44 TBUFs/Horizontal LL 9 11 13 15 17 23 Bits per Frame 75 (including1 start and 3 stop bits) 92 108 140 172 188 Frames 241 285 329 373 505 Program Data = 14,779 Bits x Frames + 4 bits (excludes header) 22,176 30,784 46,064 64,160 94,944 PROM size (bits) = Program Data + 40-bit Header 22,216 30,824 46,104 64,200 94,984 197 14,819 Figure 19. Internal Configuration Data Structure for an LCA Device. This shows the preamble, length count and data frames generated by the XACT Development System. The Length Count produced by the MakeBits program = [(40-bit preamble + sum of program data + 1 per daisy chain device) rounded up to multiple of 8] - (2 K 4) where K is a function of DONE and RESET timing selected. An additional 8 is added if roundup increment is less than K. K additional clocks are needed to complete start-up after length count is reached. 2-120 Postamble Last Frame Data Frame 12 24 4 3 3 4 STOP DIN Stop Preamble Length Count Data Start Bit Length Count* Start Bit The configuration data consists of a composite * 40-bit preamble/length count, followed by one or more concatenated LCA programs, separated by 4-bit postambles. An additional final postamble bit is added for each slave device and the result rounded up to a byte boundary. The length count is two less than the number of resulting bits. Weak Pull-Up PROGRAM Timing of the assertion of DONE and termination of the INTERNAL RESET may each be programmed to occur one cycle before or after the I/O outputs become active. I/O Active DONE Internal Reset Heavy lines indicate the default condition X5303 Figure 20. Configuration and Start-up of One or More LCA Devices. storage at power-up and after a re-program signal. Several methods of automatic and controlled loading of the required data are available. Logic levels applied to mode selection pins at the start of configuration time determine the method to be used. See Table 1. The data may be either bit-serial or byte-parallel, depending on the configuration mode. The different LCA devices have different sizes and numbers of data frames. To maintain compatibility between various device types, the Xilinx product families use compatible configuration formats. For the XC3020, configuration requires 14779 bits for each device, arranged in 197 data frames. An additional 40 bits are used in the header. See Figure 20. The specific data format for each device is produced by the MakeBits command of the development system and one or more of these files can then be combined and appended to a length count preamble and be transformed into a PROM format file by the MakePROM command of the XACT development system. A compatibility exception precludes the use of an XC2000-series device as the master for XC3000series devices if their DONE or RESET are programmed to occur after their outputs become active. The Tie Option of the MakeBits program defines output levels of unused blocks of a design and connects these to unused routing resources. This prevents indeterminate levels that might produce parasitic supply currents. If unused blocks are not sufficient to complete the tie, the Flagnet command of EDITLCA can be used to indicate nets which must not be used to drive the remaining unused routing, as that might affect timing of user nets. Norestore will retain the results of tie for timing analysis with Querynet before Restore returns the design to the untied condition. Tie can be omitted for quick breadboard iterations where a few additional milliamps of ICC are acceptable. The configuration bitstream begins with eight High preamble bits, a 4-bit preamble code and a 24-bit length count. When configuration is initiated, a counter in the LCA device is set to zero and begins to count the total number of configuration clock cycles applied to the device. As each configuration data frame is supplied to the LCA device, it is internally assembled into a data word, which is then loaded in parallel into one word of the internal configuration memory array. The configuration loading process is complete when the current length count equals the loaded length count and the required configuration program data frames have been written. Internal user flip-flops are held Reset during configuration. Two user-programmable pins are defined in the unconfigured Logic Cell array. High During Configuration (HDC) and Low During Configuration (LDC) as well as DONE/PROG may be used as external control signals during configuration. In Master mode configurations it is convenient to use LDC as an active-Low EPROM Chip 2-121 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Enable. After the last configuration data bit is loaded and the length count compares, the user I/O pins become active. Options in the MakeBits program allow timing choices of one clock earlier or later for the timing of the end of the internal logic RESET and the assertion of the DONE signal. The open-drain DONE/PROG output can be ANDtied with multiple LCA devices and used as an active-High READY, an active-Low PROM enable or a RESET to other portions of the system. The state diagram of Figure 18 illustrates the configuration process. Master Mode In Master mode, the LCA device automatically loads configuration data from an external memory device. There are three Master modes that use the internal timing source to supply the configuration clock (CCLK) to time the incoming data. Master Serial mode uses serial configuration data supplied to Data-in (DIN) from a synchronous serial source such as the Xilinx Serial Configuration PROM shown in Figure 21. Master Parallel Low and High modes automatically use parallel data supplied to the D0-D7 pins in response to the 16-bit address generated by the LCA device. Figure 22 shows an example of the parallel Master mode connections required. The LCA HEX starting address is 0000 and increments for Master Low mode and it is FFFF and decrements for Master High mode. These two modes provide address compatibility with microprocessors which begin execution from opposite ends of memory. Peripheral Mode Peripheral mode provides a simplified interface through which the device may be loaded byte-wide, as a processor peripheral. Figure 23 shows the peripheral mode connections. Processor write cycles are decoded from the common assertion of the active low Write Strobe (WS), and two active low and one active high Chip Selects (CS0, CS1, CS2). The LCA device generates a configuration clock from the internal timing generator and serializes the parallel input data for internal framing or for succeeding slaves on Data Out (DOUT). A output High on READY/BUSY pin indicates the completion of loading for each byte when the input register is ready for a new byte. As with Master modes, Peripheral mode may also be used as a lead device for a daisy-chain of slave devices. Slave Serial Mode Slave Serial mode provides a simple interface for loading the Logic Cell Array configuration as shown in Figure 24. Serial data is supplied in conjunction with a synchronizing input clock. Most Slave mode applications are in daisychain configurations in which the data input is driven from the previous Logic Cell Array's data out, while the clock is supplied by a lead device in Master or Peripheral mode. Data may also be supplied by a processor or other special circuits. Daisy Chain The XACT development system is used to create a composite configuration for selected LCA devices including: a preamble, a length count for the total bitstream, multiple concatenated data programs and a postamble plus an additional fill bit per device in the serial chain. After loading and passing-on the preamble and length count to a possible daisy-chain, a lead device will load its configuration data frames while providing a High DOUT to possible down-stream devices as shown in Figure 22. Loading continues while the lead device has received its configuration program and the current length count has not reached the full value. The additional data is passed through the lead device and appears on the Data Out (DOUT) pin in serial form. The lead device also generates the Configuration Clock (CCLK) to synchronize the serial output data and data in of down-stream LCA devices. Data is read in on DIN of slave devices by the positive edge of CCLK and shifted out the DOUT on the negative edge of CCLK. A parallel Master mode device uses its internal timing generator to produce an internal CCLK of 8 times its EPROM address rate, while a Peripheral mode device produces a burst of 8 CCLKs for each chip select and writestrobe cycle. The internal timing generator continues to operate for general timing and synchronization of inputs in all modes. Special Configuration Functions The configuration data includes control over several special functions in addition to the normal user logic functions and interconnect. * * * * * * Input thresholds Readback disable DONE pull-up resistor DONE timing RESET timing Oscillator frequency divided by two Each of these functions is controlled by configuration data bits which are selected as part of the normal XACT development system bitstream generation process. Input Thresholds Prior to the completion of configuration all LCA device input thresholds are TTL compatible. Upon completion of configuration, the input thresholds become either TTL or CMOS compatible as programmed. The use of the TTL threshold option requires some additional supply current for threshold shifting. The exception is the threshold of the PWRDWN input and direct clocks which always have a CMOS input. Prior to the completion of configuration the user I/O pins each have a high impedance pull-up. The 2-122 configuration program can be used to enable the IOB pullup resistors in the Operational mode to act either as an input load or to avoid a floating input on an otherwise unused pin. Readback The contents of a Logic Cell Array may be read back if it has been programmed with a bitstream in which the Readback option has been enabled. Readback may be used for verification of configuration and as a method of determining the state of internal logic nodes during debugging. There are three options in generating the configuration bitstream. * "Never" inhibits the Readback capability. * "One-time," inhibits Readback after one Readback has been executed to verify the configuration. * "On-command" allows unrestricted use of Readback. Readback is accomplished without the use of any of the user I/O pins; only M0, M1 and CCLK are used. The initiation of Readback is produced by a Low to High transition of the M0/RTRIG (Read Trigger) pin. The CCLK input must then be driven by external logic to read back the configuration data. The first three Low-to-High CCLK transitions clock out dummy data. The subsequent Lowto-High CCLK transitions shift the data frame information out on the M1/RDATA (Read Data) pin. Note that the logic polarity is always inverted, a zero in configuration becomes a one in Readback, and vice versa. Note also that each Readback frame has one Start bit (read back as a one) but, unlike in configuration, each Readback frame has only one Stop bit (read back as a zero). The third leading dummy bit mentioned above can be considered the Start bit of the first frame. All data frames must be read back to complete the process and return the Mode Select and CCLK pins to their normal functions. Readback data includes the current state of each CLB flip-flop, each input flip-flop or latch, and each device pad. These data are imbedded into unused configuration bit positions during Readback. This state information is used by the XACT development system In-Circuit Verifier to provide visibility into the internal operation of the logic while the system is operating. To readback a uniform timesample of all storage elements, it may be necessary to inhibit the system clock. Reprogram To initiate a re-programming cycle, the dual-function pin DONE/PROG must be given a High-to-Low transition. To reduce sensitivity to noise, the input signal is filtered for two cycles of the LCA device internal timing generator. When reprogram begins, the user-programmable I/O output buffers are disabled and high-impedance pull-ups are provided for the package pins. The device returns to the Clear state and clears the configuration memory before it indicates `initialized'. Since this Clear operation uses chipindividual internal timing, the master might complete the Clear operation and then start configuration before the slave has completed the Clear operation. To avoid this problem, the slave INIT pins must be AND-wired and used to force a RESET on the master (see Figure 22). Reprogram control is often implemented using an external opencollector driver which pulls DONE/PROG Low. Once a stable request is recognized, the DONE/PROG pin is held Low until the new configuration has been completed. Even if the re-program request is externally held Low beyond the configuration period, the LCA device will begin operation upon completion of configuration. DONE Pull-up DONE/PROG is an open-drain I/O pin that indicates the LCA device is in the operational state. An optional internal pull-up resistor can be enabled by the user of the XACT development system when MAKEBITS is executed. The DONE/PROG pins of multiple LCA devices in a daisychain may be connected together to indicate all are DONE or to direct them all to reprogram. DONE Timing The timing of the DONE status signal can be controlled by a selection in the MakeBits program to occur either a CCLK cycle before, or after, the outputs going active. See Figure 20. This facilitates control of external functions such as a PROM enable or holding a system in a wait state. RESET Timing As with DONE timing, the timing of the release of the internal reset can be controlled by a selection in the MakeBits program to occur either a CCLK cycle before, or after, the outputs going active. See Figure 20. This reset keeps all user programmable flip-flops and latches in a zero state during configuration. Crystal Oscillator Division A selection in the MakeBits program allows the user to incorporate a dedicated divide-by-two flip-flop between the crystal oscillator and the alternate clock line. This guarantees a symmetrical clock signal. Although the frequency stability of a crystal oscillator is very good, the symmetry of its waveform can be affected by bias or feedback drive. The following seven pages describe the different configuration modes in detail 2-123 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Master Serial Mode * IF READBACK IS ACTIVATED, A 5-k RESISTOR IS REQUIRED IN SERIES WITH M1 +5 V * M0 DURING CONFIGURATION THE 5 k M2 PULL-DOWN RESISTOR OVERCOMES THE INTERNAL PULL-UP, BUT IT ALLOWS M2 TO BE USER I/O. M1 PWRDWN TO DIN OF OPTIONAL DAISY-CHAINED LCAs WITH DIFFERENT CONFIGURATIONS DOUT M2 TO CCLK OF OPTIONAL DAISY-CHAINED LCAs WITH DIFFERENT CONFIGURATIONS HDC LDC GENERALPURPOSE USER I/O PINS INIT OTHER I/O PINS TO CCLK OF OPTIONAL SLAVE LCAs WITH IDENTICAL CONFIGURATIONS * * * * * XC3000 LCA DEVICE TO DIN OF OPTIONAL SLAVE LCAs WITH IDENTICAL CONFIGURATIONS +5 V RESET RESET VCC DIN VPP DATA DATA CCLK CLK CLK SCP D/P CE INIT OE/RESET CEO CE CASCADED SERIAL MEMORY OE/RESET XC17xx (LOW RESETS THE XC17xx ADDRESS POINTER) X6092 Figure 21. Master Serial Mode In Master Serial mode, the CCLK output of the lead LCA device drives a Xilinx Serial PROM that feeds the LCA DIN input. Each rising edge of the CCLK output increments the Serial PROM internal address counter. This puts the next data bit on the SPROM data output, connected to the LCA DIN pin. The lead LCA device accepts this data on the subsequent rising CCLK edge. The lead LCA device then presents the preamble data (and all data that overflows the lead device) on its DOUT pin. There is an internal delay of 1.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next LCA device in the daisy-chain accepts data on the subsequent rising CCLK edge. The SPROM CE input can be driven from either LDC or DONE . Using LDC avoids potential contention on the DIN pin, if this pin is configured as user-I/O, but LDC is then restricted to be a permanently High user output. Using DONE also avoids contention on DIN, provided the early DONE option is invoked. 2-124 Master Serial Mode Programming Switching Characteristics CCLK (Output) 2 TCKDS 1 Serial Data In Serial DOUT (Output) TDSCK n n-3 n+1 n-2 n+2 n-1 n X3223 Speed Grade Description CCLK Data In setup Data In hold Min Max Units Symbol 1 TDSCK 2 CKDS 60 0 Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a non-monotonically rising VCC may require >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P after VCC has reached 4.0 V (2.5 V for the XC3000L). 2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is High. 3. Master-serial-mode timing is based on slave-mode testing. 2-125 ns ns XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Master Parallel Mode * +5 V * If Readback is Activated, a 5-k Resistor is Required in Series With M1 5 k +5 V * +5 V M0 M1PWRDWN M0 M1PWRDWN CCLK CCLK DOUT DIN HDC RCLK 5 k A14 LDC A13 A13 A12 A12 A11 A11 A10 A10 A9 A9 D7 A8 A8 D6 A7 A7 D7 D5 A6 A6 D6 D4 A5 A5 D5 D3 A4 A4 D4 D2 A3 A3 D3 D1 A2 A2 D2 A1 A1 D1 A0 A0 D0 D/P OE ..... LCA Master D0 RESET INIT N.C. EPROM GeneralPurpose User I/O Pins LDC Other I/O Pins INIT GeneralPurpose User I/O Pins INIT D/P D/P RESET Reset Note: XC2000 Devices Do Not Have INIT to Hold Off a Master Device. Reset of a Master Device Should be Asserted by an External Timing Circuit to Allow for LCA CCLK Variations in Clear State Time. CE +5 V 8 Reprogram Other I/O Pins M2 ... A14 Other I/O Pins LCA Slave #n HDC ... HDC DOUT DIN ... A15 5 k CCLK M2 A15 GeneralPurpose User I/O Pins M0 M1PWRDWN DOUT LCA Slave #1 M2 * +5 V 5 k Each Open Collector System Reset X3159 Figure 22. Master Parallel Mode In Master Parallel mode, the lead LCA device directly addresses an industry-standard byte-wide EPROM and accepts eight data bits right before incrementing (or decrementing) the address outputs. The eight data bits are serialized in the lead LCA device, which then presents the preamble data (and all data that overflows the lead device) on the DOUT pin. There is an internal delay of 1.5 CCLK periods, after the rising CCLK edge that accepts a byte of data, and also changes the EPROM address, until the falling CCLK edge that makes the LSB (D0) of this byte appear at DOUT. This means that DOUT changes on the falling CCLK edge, and the next LCA device in the daisy chain accepts data on the subsequent rising CCLK edge. 2-126 Master Parallel Mode Programming Switching Characteristics A0-A15 (output) Address for Byte n Address for Byte n + 1 1 TRAC D0-D7 Byte 3 TRCD 2 TDRC RCLK (output) 7 CCLKs CCLK CCLK (output) DOUT (output) D6 D7 Byte n - 1 Description RCLK To address valid To data setup To data hold RCLK High RCLK Low Symbol 1 2 3 TRAC TDRC TRCD TRCH TRCL X5380 Min Max Units 0 60 0 600 4.0 200 ns ns ns ns s Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a non-monotonically rising VCC may require a >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P after VCC has reached 4.0 V (2.5 V for the XC3000L). 2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is High. This timing diagram shows that the EPROM requirements are extremely relaxed: EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements. 2-127 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Peripheral Mode +5 V CONTROL SIGNALS ADDRESS BUS DATA BUS * 8 M0 D0-7 5 k M1 PWR DWN D0-7 CCLK OPTIONAL DAISY-CHAINED LCAs WITH DIFFERENT CONFIGURATIONS DOUT ... ADDRESS DECODE LOGIC * IF READBACK IS ACTIVATED, A 5-k RESISTOR IS REQUIRED IN SERIES WITH M1 M2 CS0 HDC +5 V LCA GENERALPURPOSE USER I/O PINS LDC CS1 CS2 ... OTHER I/O PINS RDY/BUSY WS INIT REPROGRAM OC D/P RESET Figure 23. Peripheral Mode. X3031 Peripheral mode uses the trailing edge of the logic AND condition of the CS0, CS1, CS2, and WS inputs to accept byte-wide data from a microprocessor bus. In the lead LCA device, this data is loaded into a double-buffered UARTlike parallel-to-serial converter and is serially shifted into the internal logic. The lead LCA device presents the preamble data (and all data that overflows the lead device) on the DOUT pin. again when the byte-wide input buffer has transferred its information into the shift register, and the buffer is ready to receive new data. The length of the BUSY signal depends on the activity in the UART. If the shift register had been empty when the new byte was received, the BUSY signal lasts for only two CCLK periods. If the shift register was still full when the new byte was received, the BUSY signal can be as long as nine CCLK periods. The Ready/Busy output from the lead LCA device acts as a handshake signal to the microprocessor. RDY/BUSY goes Low when a byte has been received, and goes High Note that after the last byte has been entered, only seven of its bits are shifted out. CCLK remains High with DOUT equal to bit 6 (the next-to-last bit) of the last byte entered. 2-128 Peripheral Mode Programming Switching Characteristics WRITE TO LCA WS, CS0, CS1 CS2 1 TCA 2 TDC D0-D7 TCD 3 Valid CCLK 4 TWTRB TBUSY 6 RDY/BUSY DOUT D6 D7 D0 D1 Previous Byte D2 New Byte X3249 Description Write RDY Symbol Min Max Units Effective Write time required (Assertion of CS0, CS1, CS2, WS) 1 TCA 100 ns DIN Setup time required DIN Hold time required 2 3 TDC TCD 60 0 ns ns RDY/BUSY delay after end of WS 4 TWTRB Earliest next WS after end of BUSY 5 TRBWT 0 BUSY Low time generated 6 TBUSY 2.5 60 ns ns 9 CCLK Periods Notes: 1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a non-monotonically rising VCC may require a >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P after VCC has reached 4.0 V (2.5 V for the XC3000L). 2. Configuration must be delayed until the INIT of all LCAs is High. 3. Time from end of WS to CCLK cycle for the new byte of data depends on completion of previous byte processing and the phase of the internal timing generator for CCLK. 4. CCLK and DOUT timing is tested in slave mode. 5. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest TBUSY occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is loaded into the input register before the second-level buffer has started shifting out data. This timing diagram shows very relaxed requirements: Data need not be held beyond the rising edge of WS. BUSY will go active within 60 ns after the end of WS. BUSY will stay active for several microseconds. WS may be asserted immediately after the end of BUSY. 2-129 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Slave Serial Mode +5 V * If Readback is Activated, a 5-k Resistor is Required in Series with M1 * M0 M1 PWRDWN Micro Computer 5 k STRB CCLK D0 I/O Port DIN DOUT D1 HDC D2 LDC D3 Optional Daisy-Chained LCAs with Different Configurations M2 GeneralPurpose User I/O Pins +5 V LCA D4 D6 ... Other I/O Pins D5 D/P D7 INIT RESET RESET X3157 Figure 24. Slave Serial Mode. In Slave Serial mode, an external signal drives the CCLK input(s) of the LCA device(s). The serial configuration bitstream must be available at the DIN input of the lead LCA device a short set-up time before each rising CCLK edge. The lead LCA device then presents the preamble data (and all data that overflows the lead device) on its DOUT pin. There is an internal delay of 0.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next LCA device in the daisy-chain accepts data on the subsequent rising CCLK edge. 2-130 Slave Serial Mode Programming Switching Characteristics DIN Bit n 1 TDCC Bit n + 1 2 TCCD 5 TCCL CCLK 4 TCCH DOUT (Output) 3 TCCO Bit n - 1 Bit n X5379 Description CCLK Symbol To DOUT 3 TCCO DIN setup DIN hold High time Low time (Note 1) Frequency 1 2 4 5 TDCC TCCD TCCH TCCL FCC Min 60 0 0.05 0.05 Max Units 100 ns 5.0 10 ns ns s s MHz Notes: 1. The max limit of CCLK Low time is caused by dynamic circuitry inside the LCA device. 2. Configuration must be delayed until the INIT of all LCA devices is High. 3. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a non-monotonically rising VCC may require a >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P after VCC has reached 4.0 V (2.5 V for the XC3000L). Program Readback Switching Characteristics DONE/PROG (OUTPUT) 1 TRTH RTRIG (M0) 2 TRTCC 4 TCCL 4 TCCL CCLK(1) 5 3 TCCRD M1 Input/ RDATA Output H1-Z VALID READBACK OUTPUT VALID READBACK OUTPUT X6116 RTRIG CCLK Notes: 1. 2. 3. 4. Description RTRIG High Symbol 1 TRTH Min 250 RTRIG setup RDATA delay High time Low time 2 3 5 4 200 TRTCC TCCRD TCCHR TCCLR Max 100 0.5 0.5 During Readback, CCLK frequency may not exceed 1 MHz. RETRIG (M0 positive transition) shall not be done until after one clock following active I/O pins. Readback should not be initiated until configuration is complete. TCCLR is 5 s min to 15 s max for XC3000L. 2-131 5 Units ns ns ns s s XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families General LCA Switching Characteristics 4 TMRW RESET 2 TMR 3 TRM M0/M1/M2 5 TPGW DONE/PROG 6 TPGI INIT (Output) User State Clear State Configuration State PWRDWN Note 3 VCC (Valid) VCCPD X5387 Description Symbol Min RESET (2) M0, M1, M2 setup time required M0, M1, M2 hold time required RESET Width (Low) req. for Abort 2 3 4 TMR TRM TMRW 1 3 6 DONE/PROG Width (Low) required for Re-config. 5 INIT response after D/P is pulled Low 6 TPGW TPGI 6 Power Down VCC VCCPD 2.3 PWRDWN (3) Max Units s s s 7 s s V Notes: 1. At power-up, Vcc must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vcc has reached 4.0 V (2.5 V for XC3000L). A very long Vcc rise time of >100 ms, or a non-monotonically rising Vcc may require a >1-s High level on RESET, followed by a >6-s Low level on RESET and D/P after Vcc has reached 4.0 V (2.5 V for XC3000L). 2. RESET timing relative to valid mode lines (M0, M1, M2) is relevant when RESET is used to delay configuration. The specified hold time is caused by a shift-register filter slowing down the response to RESET during configuration. 3. PWRDWN transitions must occur while Vcc >4.0 V(2.5 V for XC3000L). 2-132 Performance Device Performance The XC3000 families of FPGAs can achieve very high performance. This is the result of * A sub-micron manufacturing process, developed and continuously being enhanced for the production of state-of-the-art CMOS SRAMs. * Careful optimization of transistor geometries, circuit design, and lay-out, based on years of experience with the XC3000 family. * A look-up table based, coarse-grained architecture that can collapse multiple-layer combinatorial logic into a single function generator. One CLB can implement up to four layers of conventional logic in as little as 2.7 ns. Actual system performance is determined by the timing of critical paths, including the delay through the combinatorial and sequential logic elements within CLBs and IOBs, plus the delay in the interconnect routing. The ac-timing specifications state the worst-case timing parameters for the various logic resources available in the XC3000families architecture. Figure 25 shows a variety of elements involved in determining system performance. Logic block performance is expressed as the propagation time from the interconnect point at the input to the block to the output of the block in the interconnect area. Since combinatorial logic is implemented with a memory lookup table within a CLB, the combinatorial delay through the CLB, called TILO, is always the same, regardless of the function being implemented. For the combinatorial logic function driving the data input of the storage element, the critical timing is data set-up relative to the clock edge provided to the flip-flop element. The delay from the clock source to the output of the logic block is critical in the timing signals produced by storage elements. Loading of a logic- block output is limited only by the resulting propagation delay of the larger interconnect network. Speed performance of the logic block is a function of supply voltage and temperature. See Figure 26. Interconnect performance depends on the routing resources used to implement the signal path. Direct interconnects to the neighboring CLB provide an extremely fast path. Local interconnects go through switch matrices (magic boxes) and suffer an RC delay, equal to the resistance of the pass transistor multiplied by the capacitance of the driven metal line. Longlines carry the signal across the length or breadth of the chip with only one access delay. Generous on-chip signal buffering makes performance relatively insensitive to signal fan-out; increasing fan-out from 1 to 8 changes the CLB delay by only 10%. Clocks can be distributed with two low-skew clock distribution networks. The tools in the XACT Development System used to place and route a design in an XC3000 FPGA (the Automatic Place and Route [APR] program and the XACT Design Editor)automatically calculate the actual maximum worstcase delays along each signal path. This timing information can be back-annotated to the design's netlist for use in timing simulation or examined with X-DELAY, a static timing analyzer. Actual system performance is applications dependent. The maximum clock rate that can be used in a system is determined by the critical path delays within that system. These delays are combinations of incremental logic and routing delays, and vary from design to design. In a synchronous system, the maximum clock rate depends on the number of combinatorial logic layers between resynchronizing flip-flops. Figure 27 shows the achievable clock rate as a function of the number of CLB layers. Clock to Output Combinatorial Setup TCKO TILO TICK CLB TOP CLB Logic CLB IOB Logic PAD (K) (K) CLOCK TCKO IOB PAD TOKPO T PID X3178 Figure 25. Primary Block Speed Factors. Actual timing is a function of various block factors combined with routing factors. Overall performance can be evaluated with the XACT timing calculator or by an optional simulation. 2-133 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families SPECIFIED WORST-CASE VALUES 1.00 AL RCI 5 V) (4.7 ME MAX COM ) .5 V Y (4 TAR ILI AX M M NORMALIZED DELAY 0.80 TYPICAL COMMERCIAL (+ 5.0 V, 25C) 0.60 TYPICAL MILITARY 0.40 .75 V) ERCIAL (4 MIN COMM .25 V) (5 L ERCIA MIN COMM ARY (4.5 MIN MILIT V) Y (5.5 V) MIN MILITAR 0.20 - 55 - 40 - 20 0 25 40 70 80 100 125 TEMPERATURE (C) Figure 26. Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations Power 300 System Clock (MHz) 250 200 150 100 X6094 XC3100-3 50 XC3000-125 0 CLB Levels: 4 CLBs Gate Levels: (4-16) 3 CLBs (3-12) 2 CLBs (2-8) 1 CLB (1-4) Toggle Rate X3250 Figure 27. Clock Rate as a Function of Logic Complexity (Number of Combinational Levels between Flip-Flops) Power Distribution Power for the LCA device is distributed through a grid to achieve high noise immunity and isolation between logic and I/O. Inside the LCA device, a dedicated VCC and ground ring surrounding the logic array provides power to the I/O drivers. An independent matrix of VCC and groundlines supplies the interior logic of the device. This power distribution grid provides a stable supply and ground for all internal logic, providing the external package power pins are all connected and appropriately decoupled. Typically a 0.1-F capacitor connected near the VCC and ground pins will provide adequate decoupling. Output buffers capable of driving the specified 4- or 8-mA loads under worst-case conditions may be capable of driving as much as 25 to 30 times that current in a best case. Noise can be reduced by minimizing external load capacitance and reducing simultaneous output transitions in the same direction. It may also be beneficial to locate heavily loaded output buffers near the ground pads. The I/O Block output buffers have a slew-limited mode which should be used where output rise and fall times are not speed critical. Slew-limited outputs maintain their dc drive capability, but generate less external reflections and internal noise. 2-134 Dynamic Power Consumption XC3042 XC3042A XC3042L XC3142A One CLB driving three local interconnects 0.25 0.17 0.07 0.25 mW per MHz One global clock buffer and clock line 2.25 1.40 0.50 1.70 mW per MHz One device output with a 50 pF load 1.25 1.25 0.55 1.25 mW per MHz Power Consumption The Logic Cell Array exhibits the low power consumption characteristic of CMOS ICs. For any design, the configuration option of TTL chip input threshold requires power for the threshold reference. The power required by the static memory cells that hold the configuration data is very low and may be maintained in a power-down mode. Typically, most of power dissipation is produced by external capacitive loads on the output buffers. This load and frequency dependent power is 25 W/pF/MHz per output. Another component of I/O power is the external dc loading on all output pins. Internal power dissipation is a function of the number and size of the nodes, and the frequency at which they change. In an LCA device, the fraction of nodes changing on a given clock is typically low (10-20%). For example, in a long binary counter, the total activity of all counter flip-flops is equivalent to that of only two CLB outputs toggling at the clock frequency. Typical global clock-buffer power is between 2.0 mW/MHz for the XC3020 and 3.5 mW/MHz for the XC3090. The internal capacitive load is more a function of interconnect than fan-out. With a typical load of three general interconnect segments, each CLB output requires about 0.25 mW per MHz of its output frequency. Because the control storage of the Logic Cell Array is CMOS static memory, its cells require a very low standby current for data retention. In some systems, this low data retention current characteristic can be used as a method of preserving configurations in the event of a primary power loss. The Logic Cell Array has built in Powerdown logic which, when activated, will disable normal operation of the device and retain only the configuration data. All internal operation is suspended and output buffers are placed in their high-impedance state with no pull-ups. Different from the XC3000 family which can be powered down to a current consumption of a few microamps, the XC3100 draws 5 mA, even in power-down. This makes power-down operation less meaningful. In contrast, ICCPD for the XC3000L is only 10 A. To force the Logic Cell Array into the Powerdown state, the user must pull the PWRDWN pin Low and continue to supply a retention voltage to the VCC pins. When normal power is restored, VCC is elevated to its normal operating voltage and PWRDWN is returned to a High. The Logic Cell Array resumes operation with the same internal sequence that occurs at the conclusion of configuration. Internal-I/O and logic-block storage elements will be reset, the outputs will become enabled and the DONE/PROG pin will be released. When VCC is shut down or disconnected, some power might unintentionally be supplied from an incoming signal driving an I/O pin. The conventional electrostatic input protection is implemented with diodes to the supply and ground. A positive voltage applied to an input (or output) will cause the positive protection diode to conduct and drive the VCC connection. This condition can produce invalid power conditions and should be avoided. A large series resistor might be used to limit the current or a bipolar buffer may be used to isolate the input signal. 2-135 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Pin Descriptions Permanently Dedicated Pins. VCC Two to eight (depending on package type) connections to the positive V supply voltage. All must be connected. GND Two to eight (depending on package type) connections to ground. All must be connected. PWRDWN A Low on this CMOS-compatible input stops all internal activity, but retains configuration. All flip-flops and latches are reset, all outputs are 3-stated, and all inputs are interpreted as High, independent of their actual level. When PWDWN returns High, the LCA device becomes operational with DONE Low for two cycles of the internal 1-MHz clock.Before and during configuration, PWRDWN must be High. If not used, PWRDWN must be tied to VCC. RESET This is an active Low input which has three functions. Prior to the start of configuration, a Low input will delay the start of the configuration process. An internal circuit senses the application of power and begins a minimal time-out cycle. When the time-out and RESET are complete, the levels of the M lines are sampled and configuration begins. If RESET is asserted during a configuration, the LCA device is re-initialized and restarts the configuration at the termination of RESET. DONE/PROG (D/P) DONE is an open-drain output, configurable with or without an internal pull-up resistor of 2 to 8 k . At the completion of configuration, the LCA device circuitry becomes active in a synchronous order; DONE is programmed to go active High one cycle either before or after the outputs go active. Once configuration is done, a High-to-Low transition of this pin will cause an initialization of the LCA device and start a reconfiguration. M0/RTRIG As Mode 0, this input is sampled on power-on to determine the power-on delay (214 cycles if M0 is High, 216 cycles if M0 is Low). Before the start of configuration, this input is again sampled together with M1, M2 to determine the configuration mode to be used . A Low-to-High input transition, after configuration is complete, acts as a Read Trigger and initiates a Readback of configuration and storage-element data clocked by CCLK. By selecting the appropriate Readback option when generating the bitstream, this operation may be limited to a single Readback, or be inhibited altogether. M1/RDATA As Mode 1, this input and M0, M2 are sampled before the start of configuration to establish the configuration mode to be used. If Readback is never used, M1 can be tied directly to ground or VCC. If Readback is ever used, M1 must use a 5-k resistor to ground or VCC, to accommodate the RDATA output. As an active-Low Read Data, after configuration is complete, this pin is the output of the Readback data. If RESET is asserted after configuration is complete, it provides a global asynchronous RESET of all IOB and CLB storage elements of the LCA device. CCLK During configuration, Configuration Clock is an output of an LCA device in Master mode or Peripheral mode, but an input in Slave mode. During Readback, CCLK is a clock input for shifting configuration data out of the LCA device CCLK drives dynamic circuitry inside the LCA device. The Low time may, therefore, not exceed a few microseconds. When used as an input, CCLK must be "parked High". An internal pull-up resistor maintains High when the pin is not being driven. 2-136 User I/O Pins that can have special functions. M2 During configuration, this input has a weak pull-up resistor. Together with M0 and M1, it is sampled before the start of configuration to establish the configuration mode to be used. After configuration, this pin is a user-programmable I/O pin. HDC During configuration, this output is held at a High level to indicate that configuration is not yet complete. After configuration, this pin is a user-programmable I/O pin. LDC During Configuration, this output is held at a Low level to indicate that the configuration is not yet complete. After configuration, this pin is a user-programmable I/O pin. LDC is particularly useful in Master mode as a Low enable for an EPROM, but it must then be programmed as a High after configuration. INIT This is an active Low open-drain output with a weak pullup and is held Low during the power stabilization and internal clearing of the configuration memory. It can be used to indicate status to a configuring microprocessor or, as a wired AND of several slave mode devices, a hold-off signal for a master mode device. After configuration this pin becomes a user-programmable I/O pin. BCLKIN This is a direct CMOS level input to the alternate clock buffer (Auxiliary Buffer) in the lower right corner. XTL1 This user I/O pin can be used to operate as the output of an amplifier driving an external crystal and bias circuitry. XTL2 This user I/O pin can be used as the input of an amplifier connected to an external crystal and bias circuitry. The I/ O Block is left unconfigured. The oscillator configuration is activated by routing a net from the oscillator buffer symbol output and by the MakeBits program. CS0, CS1, CS2, WS These four inputs represent a set of signals, three active Low and one active High, that are used to control configuration-data entry in the Peripheral mode. Simultaneous assertion of all four inputs generates a Write to the internal data buffer. The removal of any assertion clocks in the D0D7 data. In Master-Parallel mode, WS and CS2 are the A0 and A1 outputs. After configuration, these pins are userprogrammable I/O pins. RDY/BUSY During Peripheral Parallel mode configuration this pin indicates when the chip is ready for another byte of data to be written to it. After configuration is complete, this pin becomes a user-programmed I/O pin. RCLK During Master Parallel mode configuration, each change on the A0-15 outputs is preceded by a rising edge on RCLK, a redundant output signal. After configuration is complete, this pin becomes a user-programmed I/O pin. D0-D7 This set of eight pins represents the parallel configuration byte for the parallel Master and Peripheral modes. After configuration is complete, they are user-programmed I/O pins. A0-A15 During Master Parallel mode, these 16 pins present an address output for a configuration EPROM. After configuration, they are user-programmable I/O pins. DIN During Slave or Master Serial configuration, this pin is used as a serial-data input. In the Master or Peripheral configuration, this is the Data 0 input. After configuration is complete, this pin becomes a user-programmed I/O pin. DOUT During configuration this pin is used to output serialconfiguration data to the DIN pin of a daisy-chained slave. After configuration is complete, this pin becomes a userprogrammed I/O pin. TCLKIN This is a direct CMOS-level input to the global clock buffer. This pin can also be configured as a user programmable I/O pin. However, since TCLKIN is the preferred input to the global clock net, and the global clock net should be used as the primary clock source, this pin is usually the clock input to the chip. Unrestricted User I/O Pins. I/O An I/O pin may be programmed by the user to be an Input or an Output pin following configuration. All unrestricted I/ O pins, plus the special pins mentioned on the following page, have a weak pull-up resistor of 50 k to 100 k that becomes active as soon as the device powers up, and stays active until the end of configuration. Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a 50 k to 100 k pull-up resistor. 2-137 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families Pin Functions During Configuration Configuration Mode <M2:M1:M0> SLAVE <1:1:1> MASTER-SER <0:0:0> PERIPHERAL <1:0:1> MASTER-HIGH <1:1:0> MASTER-LOW <1:0:0> PWRDWN (I) VCC M1 (HIGH) (I) M0 (HIGH) (I) M2 (HIGH) (I) HDC (HIGH) LDC (LOW) INIT* GND PWRDWN (I) VCC M1 (LOW) (I) M0 (LOW) (I) M2 (LOW) (I) HDC (HIGH) LDC (LOW) INIT* GND PWRDWN (I) VCC M1 (LOW) (I) M0 (HIGH) (I) M2 (HIGH) (I) HDC (HIGH) LDC (LOW) INIT* GND PWRDWN (I) VCC M1 (HIGH) (I) M0 (LOW) (I) M2 (HIGH) (I) HDC (HIGH) LDC (LOW) INIT* GND PWRDWN (I) VCC M1 (LOW) (I) M0 (LOW) (I) M2 (HIGH) (I) HDC (HIGH) LDC (LOW) INIT* GND RESET (I) DONE RESET (I) DONE RESET (I) DONE DATA 7 (I) RESET (I) DONE DATA 7 (I) RESET (I) DONE DATA 7 (I) DATA 6 (I) DATA 5 (I) CS0 (I) DATA 4 (I) VCC DATA 3 (I) CS1 (I) DATA 2 (I) DATA 1 (I) RDY/BUSY DATA 0 (I) DOUT CCLK(O) WS (I) CS2 (I) DATA 6 (I) DATA 5 (I) DATA 6 (I) DATA 5 (I) DATA 4 (I) VCC DATA 3 (I) DATA 4 (I) VCC DATA 3 (I) DATA 2 (I) DATA 1 (I) RCLK DATA 0 (I) DOUT CCLK(O) A0 A1 A2 A3 A15 A4 A14 A5 GND A13 A6 A12 A7 A11 A8 A10 A9 DATA 2 (I) DATA 1 (I) RCLK DATA 0 (I) DOUT CCLK(O) A0 A1 A2 A3 A15 A4 A14 A5 GND A13 A6 A12 A7 A11 A8 A10 A9 **** *** 208 68 84 84 100 100 132 160 175 44 PLCC PLCC PLCC PGA PQFP TQFP PGA PQFP PGA PQFP 7 12 16 17 18 19 20 22 23 26 27 28 30 VCC VCC DIN (I) DOUT CCLK (I) DIN (I) DOUT CCLK(O) GND GND GND 34 38 39 40 1 X 10 18 25 26 27 28 30 34 35 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 12 22 31 32 33 34 36 42 43 53 54 55 56 57 58 60 61 62 64 65 66 67 70 71 72 73 74 75 76 77 78 81 82 83 84 1 2 3 4 5 8 9 10 11 B2 F3 J2 L1 K2 K3 L3 K6 J6 L11 K10 J10 K11 J11 H10 F10 G10 G11 F9 F11 E11 E10 D10 C11 B11 C10 A11 B10 B9 A10 A9 B6 B7 A7 C7 C6 A6 A5 B5 C5 A3 A2 B3 A1 29 41 52 54 56 57 59 65 66 76 78 80 81 82 83 87 88 89 91 92 93 94 98 99 100 1 2 5 6 8 9 12 13 14 15 16 17 18 19 20 23 24 25 26 26 38 49 51 53 54 56 62 63 73 75 77 78 79 80 84 85 86 88 89 90 91 95 96 97 98 99 2 3 5 6 9 10 11 12 13 14 15 16 17 20 21 22 26 X X X X X X** X** X** X X X X X X X X A1 C8 B13 A14 C13 B14 D14 G14 H12 M13 P14 N13 M12 P13 N11 M9 N9 N8 M8 N7 P6 M6 M5 N4 N2 M3 P1 M2 N1 L2 L1 K1 J2 H1 H2 H3 G2 G1 F2 E1 D1 D2 B1 C2 159 20 40 42 44 45 49 59 19 76 78 80 81 82 86 92 93 98 100 102 103 108 114 115 119 120 121 124 125 128 129 132 133 136 137 139 141 142 147 148 151 152 155 156 B2 D9 B14 B15 C15 E14 D16 H15 J14 P15 R15 R14 N13 T14 P12 T11 R10 R9 N9 P8 R8 R7 R5 P5 R3 N4 R2 P2 M3 P1 N1 M1 L2 K2 K1 J3 H2 H1 F2 E1 D1 C1 E3 C2 3 26 48 50 56 57 61 77 79 100 102 107 109 110 115 122 123 128 130 132 133 138 145 146 151 152 153 161 162 165 166 172 173 178 179 182 184 185 192 193 199 200 203 204 X X X X X X X X User Operation PWRDWN (I) VCC RDATA RTRIG (I) I/O I/O I/O I/O GND XTL2 OR I/O RESET (I) PROGRAM (I) I/O XTL1 OR I/O I/O I/O I/O I/O Vcc I/O I/O I/O I/O I/O I/O I/O CCLK (I) I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O All Others XC3020 etc. XC3030 etc. XC3042 etc. XC3064 etc. XC3090 etc. XC3195 X5266 * (I) ** *** **** Represents a 50-k to 100-k pull-up before and during configuration INIT is an open drain output during configuration Represents an input Pin assignmnent for the XC3064/XC3090 and XC3195 differ from those shown. See page 2-138. Peripheral mode and master parallel mode are not supported in the PC44 package. See page 2-135. Pin assignments for the XC3195 PQ208 differ from those shown. See page 2-146. Pin assignments of PGA Footprint PLCC sockets and PGA packages are not electrically identical. Generic I/O pins are not shown. The information on this page is provided as a convenient summary. For detailed pin descriptions, see the preceding two pages. For a detailed description of the configuration modes, see pages 2-190 through 2-200. For pinout details, see pages 2-136 through 2-146. Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a 50 k to 100 k pull-up resistor. 2-138 XC3000 Families Pin Assignments Note that there is no perfect match between the number of bonding pads on the chip and the number of pins on a package. In some cases, the chip has more pads than there are pins on the package, as indicated by the information ("unused" pads) below the line in the following table. The IOBs of the unconnected pads can still be used as storage elements if the specified propagation delays and set-up times are acceptable. Xilinx offers the six different array sizes in the XC3000 families in a variety of surface-mount and through-hole package types, with pin counts from 44 to 223. Each chip is offered in several package types to accommodate the available PC board space and manufacturing technology. Most package types are also offered with different chips to accommodate design changes without the need for PC board changes. In other cases, the chip has fewer pads than there are pins on the package; therefore, some package pins are not connected (n.c.), as shown above the line in the following table. Number of Unbounded or Unconnected Pins Number of Package Pins Device Pads 44 64 68 132 144 160 175 176 208 223 10 n.c. 26 n.c. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 84 100 3020 74 -- -- 6u 3030 98 54 u 34 u 30 u 14 u 2 n.c. 3042 118 -- -- -- 34 u 18 u 3064 142 -- -- -- 50 u -- 10 u 2u 18 n.c. -- 3090 166 -- -- -- 82 u -- -- -- 6u 9 n.c -- 9 n.c. 32 u 3195 198 -- -- -- 114 u 14 n.c. 26 n.c. -- -- -- 10 n.c. 42 n.c. n.c. = Unconnected package pin u = Unbonded device pad -- -- 10 n.c. 25 n.c. X6095 Number of Available I/O Pins Number of Package Pins Max I/O XC3020/XC3120 XC3030/XC3130 XC3042/XC3142 XC3064/XC3164 XC3090/XC3190 XC3195 64 80 96 120 144 176 44 64 68 84 100 120 132 144 156 160 164 175 176 191 196 208 223 240 34 54 58 58 64 74 74 70 70 70 64 80 82 96 110 120 138 142 144 144 144 138 144 176 176 X3478 2-139 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families XC3000 Family 44-Pin PLCC Pinouts XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 XC3030 Pin No. 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 GND I/O I/O I/O I/O I/O PWRDWN TCLKIN-I/O I/O I/O I/O VCC I/O I/O I/O M1-RDATA M0-RTRIG M2-I/O HDC-I/O LDC-I/O I/O INIT-I/O XC3030 GND I/O I/O XTL2(IN)-I/O RESET DONE-PGM I/O XTL1(OUT)-BCLK-I/O I/O I/O I/O VCC I/O I/O I/O DIN-I/O DOUT-I/O CCLK I/O I/O I/O I/O Peripheral mode and Master Parallel mode are not supported in the PC44 package XC3030 Family 64-Pin Plastic VQFP Pinouts XC3000, XC3000A, XC3000L and XC3100 families have identical pinouts Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 XC3030 Pin No. XC3030 A0-WS-I/O A1-CS2-I/O A2-I/O A3-I/O A4-I/O A14-I/O A5-I/O GND A13-I/O A6-I/O A12-I/O A7-I/O A11-I/O A8-I/O A10-I/O A9-I/O PWRDN TCLKIN-I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O M1-RDATA M0-RTRIG 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 M2-I/O HDC-I/O I/O LDC-I/O I/O I/O I/O INIT-I/O GND I/O I/O I/O I/O I/O XTAL2(IN)-I/O RESET DONE-PG D7-I/O XTAL1(OUT)-BCLKIN-I/O D6-I/O D5-I/O CS0-I/O D4-I/O VCC D3-I/O CS1-I/O D2-I/O D1-I/O RDY/BUSY-RCLK-I/O D0-DIN-I/O DOUT-I/O CCLK 2-140 XC3000 Families 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts 68 PLCC 84 PGA 68 PLCC XC3030 XC3020 XC3020 XC3030, XC3042 XC3030 XC3020 XC3020 XC3030, XC3042 84 PLCC 84 PGA 10 10 PWRDN 12 B2 44 RESET 54 K10 11 11 TCLKIN-I/O 13 C2 45 DONE-PG 55 J10 12 -- I/O* 14 B1 46 D7-I/O 56 K11 13 12 I/O 15 C1 47 XTL1(OUT)-BCLKIN-I/O 57 J11 14 13 I/O 16 D2 48 D6-I/O 58 H10 H11 84 PLCC -- -- I/O 17 D1 -- I/O 59 15 14 I/O 18 E3 49 D5-I/O 60 F10 16 15 I/O 19 E2 50 CS0-I/O 61 G10 -- 16 I/O 20 E1 51 D4-I/O 62 G11 17 17 I/O 21 F2 -- I/O 63 G9 18 18 VCC 22 F3 52 VCC 64 F9 19 19 I/O 23 G3 53 D3-I/O 65 F11 -- -- I/O 24 G1 54 CS1-I/O 66 E11 20 20 I/O 25 G2 55 D2-I/O 67 E10 -- 21 I/O 26 F1 -- I/O 68 E9 21 22 I/O 27 H1 -- I/O* 69 D11 22 -- I/O 28 H2 56 D1-I/O 70 D10 23 23 I/O 29 J1 57 RDY/BUSY-RCLK-I/O 71 C11 24 24 I/O 30 K1 58 D0-DIN-I/O 72 B11 25 25 M1-RDATA 31 J2 59 DOUT-I/O 73 C10 26 26 M0-RTRIG 32 L1 60 CCLK 74 A11 27 27 M2-I/O 33 K2 61 A0-WS-I/O 75 B10 28 28 HDC-I/O 34 K3 62 A1-CS2-I/O 76 B9 29 29 I/O 35 L2 63 A2-I/O 77 A10 30 30 LDC-I/O 36 L3 64 A3-I/O 78 A9 -- 31 I/O 37 K4 -- I/O* 79 B8 I/O* 38 L4 -- I/O* 80 A8 31 32 I/O 39 J5 65 A15-I/O 81 B6 32 33 I/O 40 K5 66 A4-I/O 82 B7 33 -- I/O* 41 L5 67 A14-I/O 83 A7 -- 34 34 INIT-I/O 42 K6 68 A5-I/O 84 C7 35 35 GND 43 J6 1 GND 1 C6 36 36 I/O 44 J7 2 A13-I/O 2 A6 37 37 I/O 45 L7 3 A6-I/O 3 A5 38 38 I/O 46 K7 4 A12-I/O 4 B5 39 39 I/O 47 L6 5 A7-I/O 5 C5 -- 40 I/O 48 L8 -- I/O* 6 A4 -- 41 I/O 49 K8 -- I/O* 7 B4 40 I/O* 50 L9 6 A11-I/O 8 A3 41 I/O* 51 L10 7 A8-I/O 9 A2 42 42 I/O 52 K9 8 A10-I/O 10 B3 43 43 XTL2(IN)-I/O 53 L11 9 A9-I/O 11 A1 Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. This table describes the pinouts of three different chips in three different packages. The pin-description column lists 84 of the 118 pads on the XC3042 (and 84 of the 98 pads on the XC3030) that are connected to the 84 package pins. Ten pads, indicated by an asterisk, do not exist on the XC3020, which has 74 pads; therefore the corresponding pins on the 84-pin packages have no connections to an XC3020. Six pads on the XC3020 and 16 pads on the XC3030, indicated by a dash (--) in the 68 PLCC column, have no connection to the 68 PLCC, but are connected to the 84-pin packages. 2-141 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families XC3064/XC3090/XC3195 84-Pin PLCC Pinouts XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts PLCC Pin Number XC3064, XC3090, XC3195 PLCC Pin Number 12 PWRDN 54 RESET 13 TCLKIN-I/O 55 DONE-PG 14 I/O 56 D7-I/O 15 I/O 57 XTL1(OUT)-BCLKIN-I/O 16 I/O 58 D6-I/O 17 I/O 59 I/O 18 I/O 19 D5-I/O CS0-I/O D4-I/O XC3064, XC3090, XC3195 I/O 60 61 20 I/O 62 21 GND 63 I/O 22 VCC 64 VCC 23 I/O 65 GND 24 I/O 25 I/O 66 67 D3-I/O CS1-I/O 26 I/O 68 D2-I/O 27 I/O 69 I/O 28 I/O 29 I/O 70 71 D1-I/O RDY/BUSY-RCLK-I/O 30 31 I/O M1-RDATA 72 D0-DIN-I/O 73 DOUT-I/O 32 M0-RTRIG 33 M2-I/O 74 75 CCLK A0-WS-I/O 34 HDC-I/O 76 A1-CS2-I/O 35 36 I/O LDC-I/O 77 A2-I/O 78 A3-I/O 37 I/O 79 I/O 38 I/O 80 I/O 39 I/O 81 A15-I/O 40 I/O 82 A4-I/O 41 INIT/I/O 83 A14-I/O 42 VCC 84 A5-I/O 43 GND 1 GND 44 I/O 2 VCC 45 I/O 3 A13-I/O 46 I/O 4 A6-I/O 47 I/O 5 A12-I/O 48 I/O 6 A7-I/O 49 I/O 7 I/O 50 I/O 8 A11-I/O 51 I/O 9 A8-I/O 52 I/O 10 A10-I/O 53 XTL2(IN)-I/O 11 A9-I/O Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed ouptuts are default slew-rate limited. In the PC84 package, XC3064, XC3090 and XC3195 have additional V CC and GND pins and thus a different pin definition than XC3020/XC3030/XC3042. 2-142 XC3000 Families 100-Pin QFP Pinouts XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts Pin No. CQFP PQFP TQFP VQFP XC3020 XC3030 XC3042 Pin No. CQFP PQFP TQFP VQFP XC3020 XC3030 XC3042 Pin No. XC3020 XC3030 XC3042 CQFP PQFP TQFP VQFP 1 16 13 GND 35 50 47 I/O* 2 17 14 A13-I/O 36 51 48 I/O* 69 70 84 85 81 82 I/O* I/O* 3 18 15 A6-I/O 37 52 49 M1-RD 71 86 83 I/O 4 19 16 A12-I/O 38 53 50 GND* 72 87 84 D5-I/O 5 20 17 A7-I/O 39 54 51 MO-RT 73 88 85 CS0-I/O 6 21 18 I/O* 40 55 52 VCC* 74 89 86 D4-I/O 7 22 19 I/O* 41 56 53 M2-I/O 75 90 87 I/O 8 23 20 A11-I/O 42 57 54 HDC-I/O 76 91 88 VCC 9 24 21 A8-I/O 43 58 55 I/O 77 92 89 D3-I/O 10 25 22 A10-I/O 44 59 56 LDC-I/O 78 93 90 CS1-I/O 11 26 23 A9-I/O 45 60 57 I/O* 79 94 91 D2-I/O 12 27 24 VCC* 46 61 58 I/O* 80 95 92 I/O 13 28 25 GND* 47 62 59 I/O 81 96 93 I/O* 14 29 26 PWRDN 48 63 60 I/O 82 97 94 I/O* 15 30 27 TCLKIN-I/O 49 64 61 I/O 83 98 95 D1-I/O 16 31 28 I/O** 50 65 62 INIT-I/O 84 99 96 RDY/BUSY-RCLK-I/O 17 32 29 I/O* 51 66 63 GND 85 100 97 DO-DIN-I/O 18 33 30 I/O* 52 67 64 I/O 86 1 98 DOUT-I/O 19 34 31 I/O 53 68 65 I/O 87 2 99 CCLK 20 35 32 I/O 54 69 66 I/O 88 3 100 VCC* 21 36 33 I/O 55 70 67 I/O 89 4 1 GND* 22 37 34 I/O 56 71 68 I/O 90 5 2 AO-WS-I/O 23 38 35 I/O 57 72 69 I/O 91 6 3 A1-CS2-I/O 24 39 36 I/O 58 73 70 I/O 92 7 4 I/O** 25 40 37 I/O 59 74 71 I/O* 93 8 5 A2-I/O 26 41 38 VCC 60 75 72 I/O* 94 9 6 A3-I/O 27 42 39 I/O 61 76 73 XTL2-I/O 95 10 7 I/O* 28 43 40 I/O 62 77 74 GND* 96 11 8 I/O* 29 44 41 I/O 63 78 75 RESET 97 12 9 A15-I/O 30 45 42 I/O 64 79 76 VCC* 98 13 10 A4-I/O 31 46 43 I/O 65 80 77 DONE-PG 99 14 11 A14-I/O 32 47 44 I/O 66 81 78 D7-I/O 100 15 12 A5-I/O 33 48 45 I/O 67 82 79 BCLKIN-XTL1-I/O 34 49 46 I/O 68 83 80 D6-I/O Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. * This table describes the pinouts of three different chips in three different packges. The pin-description column lists 100 of the 118 pads on the XC3042 that are connected to the 100 package pins. Two pads, indicated by double asterisks, do not exist on the XC3030, which has 98 pads; therefore the corresponding pins have no connections. Twenty-six pads, indicated by single or double asterisks, do not exist on the XC3020, which has 74 pads; therefore, the corresponding pins have no connections. (See table on page 2-139.) 2-143 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families XC3000 Families 132-Pin Ceramic and Plastic PGA Pinouts XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts XC3042 XC3064 PGA Pin Number XC3042 XC3064 PGA Pin Number XC3042 XC3064 PGA Pin Number XC3042 XC3064 C4 GND M3 DOUT-I/O GND P14 M11 RESET PWRDN B13 C11 M1-RD A1 VCC P1 CCLK C3 I/O-TCLKIN A14 M0-RT N13 DONE-PG M4 B2 I/O D12 VCC M12 D7-I/O L3 VCC GND B3 I/O C13 M2-I/O P13 XTL1-I/O-BCLKIN M2 A0-WS-I/O A2 I/O* B14 HDC-I/O N12 I/O N1 A1-CS2-I/O PGA Pin Number B4 I/O C14 I/O P12 I/O M1 I/O C5 I/O E12 I/O N11 D6-I/O K3 I/O A3 I/O* D13 I/O M10 I/O L2 A2-I/O A4 I/O D14 LDC-I/O A3-I/O I/O E13 I/O* I/O* I/O L1 B5 P11 N10 K2 I/O C6 I/O F12 I/O P10 I/O J3 I/O A5 I/O E14 I/O M9 D5-I/O K1 A15-I/O B6 I/O F13 I/O N9 CS0-I/O J2 A4-I/O A6 I/O F14 I/O P9 I/O* B7 I/O G13 I/O I/O* A14-I/O C7 GND VCC A7 H2 H3 G3 A5-I/O C8 I/O* D4-I/O I/O J1 H1 G14 INIT-I/O I/O G12 H12 VCC GND P8 N8 P7 M8 B8 I/O H14 I/O M7 VCC GND G2 A13-I/O A8 I/O H13 I/O N7 D3-I/O G1 A6-I/O A9 I/O J14 I/O P6 CS1-I/O F1 I/O* B9 I/O J13 I/O N6 I/O* F2 A12-I/O GND VCC C9 I/O K14 I/O P5 I/O* E1 A7-I/O A10 I/O J12 I/O M6 D2-I/O F3 I/O B10 I/O K13 I/O N5 I/O E2 I/O A11 I/O* L14 I/O* P4 I/O D1 A11-I/O C10 I/O L13 I/O P3 I/O D2 A8-I/O B11 I/O K12 I/O M5 D1-I/O A12 I/O* M14 N14 I/O I/O N4 RDY/BUSY-RCLK-I/O E3 C1 I/O I/O P2 I/O B1 A10-I/O M13 L12 XTL2(IN)-I/O N3 I/O C2 A9-I/O GND N2 D0-DIN-I/O D3 VCC B12 I/O A13 I/O* C12 I/O Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. * Indicates unconnected package pins (14) for the XC3042. 2-144 XC3000 Families 144-Pin Plastic TQFP Pinouts XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts XC3042 XC3064 Pin Number XC3042 XC3064 49 I/O 97 I/O 50 I/O* 98 I/O I/O* 51 I/O 99 I/O* 4 I/O 52 I/O 100 I/O 5 I/O 53 INIT-I/O 101 I/O* 6 I/O* 54 VCC 102 D1-I/O 7 I/O 55 GND 103 RDY/BUSY-RCLK-I/O 8 I/O 56 I/O 104 I/O 9 I/O* 57 I/O 105 I/O 10 I/O 58 I/O 106 D0-DIN-I/O 11 I/O 59 I/O 107 DOUT-I/O 12 I/O 60 I/O 108 CCLK 13 I/O 61 I/O 109 VCC 14 I/O 62 I/O 110 GND 15 I/O* 63 I/O* 111 A0-WSI/O 16 I/O 64 I/O* 112 A1-CS2-I/O 17 I/O 65 I/O 113 I/O 18 GND 66 I/O 114 I/O 19 VCC 67 I/O 115 A2-I/O 20 I/O 68 I/O 116 A3-I/O 21 I/O 69 XTL2(IN)-I/O 117 I/O 22 I/O 70 GND 118 I/O 23 I/O 71 RESET 119 A15-I/O 24 I/O 72 VCC 120 A4-I/O 25 I/O 73 DONE-PG 121 I/O* 26 I/O 74 D7-I/O 122 I/O* 27 I/O 75 XTL1(OUT)-BCLKIN-I/O 123 A14-I/O 28 I/O* 76 I/O 124 A5-I/O 29 I/O 77 I/O 125 - 30 I/O 78 D6-I/O 126 GND 31 I/O* 79 I/O 127 VCC 32 I/O* 80 I/O* 128 A13-I/O 33 I/O 81 I/O 129 A6-I/O 34 I/O* 82 I/O 130 I/O* 35 I/O 83 I/O* 131 - 36 M1-RD 84 D5-I/O 132 I/O* 37 GND 85 CS0-I/O 133 A12-I/O 38 MO-RT 86 I/O* 134 A7-I/O 39 VCC 87 I/O* 135 I/O 40 M2-I/O 88 D4-I/O 136 I/O 41 HDC-I/O 89 I/O 137 A11-I/O 42 I/O 90 VCC 138 A8-I/O 43 I/O 91 GND 139 I/O 44 I/O 92 D3-I/O 140 I/O 45 LDC-I/O 93 CS1-I/O 141 A10-I/O 46 I/O* 94 I/O* 142 A9-I/O 47 I/O 95 I/O* 143 VCC 48 I/O 96 D2-I/O 144 GND XC3042 XC3064 Pin Number 1 PWRDN 2 I/O-TCLKIN 3 Pin Number Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. * Indicates unconnected package pins (24) for the XC3042. 2-145 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families XC3000 Families160-Pin PQFP Pinouts XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts PQFP Pin Number XC3064, XC3090, XC3195 PQFP Pin Number XC3064, XC3090, XC3195 PQFP Pin Number 1 I/O* 2 I/O* 41 GND 42 M0-RTRIG 3 I/O * 43 4 I/O 5 I/O 6 7 8 XC3064, XC3090, XC3195 PQFP Pin Number XC3064, XC3090, XC3195 81 D7-I/O 121 CCLK 82 XTL1-I/O-BCLKIN 122 VCC VCC 83 I/O * 123 GND 44 M2-I/O 84 I/O 124 A0-WS-I/O 45 HDC-I/O 85 I/O 125 A1-CS2-I/O I/O 46 I/O 86 D6-I/O 126 I/O I/O 47 I/O 87 I/O 127 I/O I/O 48 I/O 88 I/O 128 A2-I/O 9 I/O 49 LDC-I/O 89 I/O 129 A3-I/O 10 I/O 50 I/O* 90 I/O 130 I/O 11 I/O 51 I/O * 91 I/O 131 I/O 12 I/O 52 I/O 92 D5-I/O 132 A15-I/O 13 I/O 53 I/O 93 CS0-I/O 133 A4-I/O 14 I/O 54 I/O 94 I/O * 134 I/O 15 I/O 55 I/O 95 I/O * 135 I/O 16 I/O 56 I/O 96 I/O 136 A14-I/O 17 I/O 57 I/O 97 I/O 137 A5-I/O 18 I/O 58 I/O 98 D4-I/O 138 I/O * 19 GND 59 INIT-I/O 99 I/O 139 GND 20 VCC 60 VCC 100 VCC 140 VCC 21 I/O * 61 GND 101 GND 141 A13-I/O 22 I/O 62 I/O 102 D3-I/O 142 A6-I/O 23 I/O 63 I/O 103 CS1-I/O 143 I/O * 24 I/O 64 I/O 104 I/O 144 I/O * 25 I/O 65 I/O 105 I/O 145 I/O 26 I/O 66 I/O 106 I/O * 146 I/O 27 I/O 67 I/O 107 I/O * 147 A12-I/O 28 I/O 68 I/O 108 D2-I/O 148 A7-I/O 29 I/O 69 I/O 109 I/O 149 I/O 30 I/O 70 I/O 110 I/O 150 I/O 31 I/O 71 I/O 111 I/O 151 A11-I/O 32 I/O 72 I/O 112 I/O 152 A8-I/O 33 I/O 73 I/O 113 I/O 153 I/O 34 I/O 74 I/O 114 D1-I/O 154 I/O 35 I/O 75 I/O * 115 RDY/BUSY-RCLK-I/O 155 A10-I/O 36 I/O 76 XTL2-I/O 116 I/O 156 A9-I/O 37 I/O 77 GND 117 I/O 157 VCC 38 I/O * 78 RESET 118 I/O * 158 GND 39 I/O * 79 VCC 119 D0-DIN-I/O 159 PWRDWN 40 M1-RDATA 80 DONE/PG 120 DOUT-I/O 160 TCLKIN-I/O Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed IOBs are default slew-rate limited. *Indicates unconnected package pins (18) for the XC3064. 2-146 XC3000 Families 175-Pin Ceramic and Plastic PGA Pinouts XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts PGA Pin Number XC3090, XC3195 PGA Pin Number XC3090, XC3195 PGA Pin Number XC3090, XC3195 PGA Pin Number XC3090, XC3195 B2 PWRDN D13 I/O R14 DONE-PG R3 D0-DIN-I/O D4 TCLKIN-I/O M1-RDATA N13 D7-I/O N4 DOUT-I/O B3 I/O B14 C14 GND T14 XTL1(OUT)-BCLKIN-I/O CCLK C4 I/O B15 M0-RTRIG P13 I/O R2 P3 B4 I/O D14 VCC R13 I/O N3 VCC GND A4 I/O C15 M2-I/O T13 I/O P2 A0-WS-I/O D5 I/O E14 HDC-I/O N12 I/O M3 A1-CS2-I/O C5 I/O B16 I/O P12 D6-I/O R1 I/O B5 I/O D15 I/O R12 I/O N2 I/O A5 I/O C16 I/O T12 I/O P1 A2-I/O C6 I/O LDC-I/O I/O I/O N1 A3-I/O I/O D16 F14 P11 D6 N11 I/O L3 I/O B6 I/O E15 I/O R11 I/O M2 I/O A6 I/O E16 I/O T11 D5-I/O M1 A15-I/O B7 I/O F15 I/O R10 CS0-I/O L2 A4-I/O C7 I/O F16 I/O P10 I/O L1 I/O D7 I/O G14 I/O N10 I/O K3 I/O A7 I/O G15 I/O T10 I/O K2 A14-I/O A8 I/O G16 I/O T9 I/O K1 A5-I/O B8 I/O H16 I/O R9 D4-I/O J1 I/O C8 D8 I/O H15 INIT-I/O P9 I/O J2 I/O H14 J14 VCC GND N9 N8 VCC GND J3 D9 GND VCC H3 GND VCC C9 I/O J15 I/O P8 D3-I/O H2 A13-I/O B9 I/O J16 I/O R8 CS1-I/O H1 A6-I/O A9 I/O K16 I/O T8 I/O G1 I/O A10 I/O K15 I/O T7 I/O G2 I/O D10 I/O K14 I/O N7 I/O G3 I/O C10 I/O L16 I/O P7 I/O F1 I/O B10 I/O L15 I/O R7 D2-I/O F2 A12-I/O A11 I/O M16 I/O T6 I/O E1 A7-I/O B11 I/O M15 I/O R6 I/O E2 I/O D11 I/O L14 I/O N6 I/O F3 I/O C11 I/O N16 I/O P6 I/O D1 A11-I/O A12 I/O P16 I/O T5 I/O C1 A8-I/O B12 I/O N15 I/O R5 D1-I/O D2 I/O C12 I/O R16 I/O P5 RDY/BUSY-RCLK-I/O B1 I/O D12 I/O M14 I/O N5 I/O E3 A10-I/O A13 I/O P15 XTL2(IN)-I/O T4 I/O C2 A9-I/O B13 I/O N14 GND R4 I/O C13 I/O R15 RESET P4 I/O D3 C3 VCC GND A14 I/O P14 VCC Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. Pins A2, A3, A15, A16, T1, T2, T3, T15 and T16 are not connected. Pin A1 does not exist. 2-147 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families XC3090 176-Pin TQFP Pinouts XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts Pin Number XC3090 1 2 PWRDWN TCLKIN-I/O 3 I/O 4 I/O 5 I/O 6 Pin Number Pin Number XC3090 M1-RDATA 89 DONE-PG Pin Number 133 46 GND 90 D7-I/O 134 GND 47 M0-RTRIG 91 XTAL1(OUT)-BCLKIN-I/O 135 A0-WS-I/O 48 VCC 92 I/O 136 A1-CS2-I/O 49 M2-I/O 93 I/O 137 - I/O 50 HDC-I/O 94 I/O 138 I/O 7 I/O 51 I/O 95 I/O 139 I/O 8 I/O 52 I/O 96 D6-I/O 140 A2-I/O 45 XC3090 XC3090 VCC 9 I/O 53 I/O 97 I/O 141 A3-I/O 10 I/O 54 LDC-I/O 98 I/O 142 - 11 I/O 55 - 99 I/O 143 - 12 I/O 56 I/O 100 I/O 144 I/O 13 I/O 57 I/O 101 I/O 145 I/O 14 I/O 58 I/O 102 D5-I/O 146 A15-I/O 15 I/O 59 I/O 103 CS0-I/O 147 A4-I/O 16 I/O 60 I/O 104 I/O 148 I/O 17 I/O 61 I/O 105 I/O 149 I/O 18 I/O 62 I/O 106 I/O 150 A14-I/O 19 I/O 63 I/O 107 I/O 151 A5-I/O 20 I/O 64 I/O 108 D4-I/O 152 I/O 21 I/O 65 INIT-I/O 109 I/O 153 I/O 22 GND 66 VCC 110 VCC 154 GND 23 VCC 67 GND 111 GND 155 VCC 24 I/O 68 I/O 112 D3-I/O 156 A13-I/O 25 I/O 69 I/O 113 CS1-I/O 157 A6-I/O 26 I/O 70 I/O 114 I/O 158 I/O 27 I/O 71 I/O 115 I/O 159 I/O 28 I/O 72 I/O 116 I/O 160 - 29 I/O 73 I/O 117 I/O 161 - 30 I/O 74 I/O 118 D2-I/O 162 I/O 31 I/O 75 I/O 119 I/O 163 I/O 32 I/O 76 I/O 120 I/O 164 A12-I/O 33 I/O 77 I/O 121 I/O 165 A7-I/O 34 I/O 78 I/O 122 I/O 166 I/O 35 I/O 79 I/O 123 I/O 167 I/O 36 I/O 80 I/O 124 D1-I/O 168 - 37 I/O 81 I/O 125 RDY/BUSY-RCLK-I/O 169 A11-I/O 38 I/O 82 - 126 I/O 170 A8-I/O 39 I/O 83 - 127 I/O 171 I/O 40 I/O 84 I/O 128 I/O 172 I/O 41 I/O 85 XTAL2(IN)-I/O 129 I/O 173 A10-I/O 42 I/O 86 GND 130 D0-DIN-I/O 174 A9-I/O 43 I/O 87 RESET 131 DOUT-I/O 175 VCC 44 - 88 VCC 132 CCLK 176 GND Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. 2-148 XC3090 208-Pin PQFP Pinouts XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts Pin Number XC3090 1 2 Pin Number XC3090 Pin Number XC3090 - GND 53 - 105 54 - 3 PWRDWN 55 VCC 4 TCLKIN-I/O 56 5 I/O 6 I/O 7 8 - Pin Number 157 XC3090 - 106 VCC 158 - 107 D/P 159 - M2-I/O 108 - 160 GND 57 HDC-I/O 109 D7-I/O 161 WS-A0-I/O 58 I/O 110 XTL1-BCLKIN-I/O 162 CS2-A1-I/O I/O 59 I/O 111 I/O 163 I/O I/O 60 I/O 112 I/O 164 I/O 9 I/O 61 LDC-I/O 113 I/O 165 A2-I/O 10 I/O 62 I/O 114 I/O 166 A3-I/O 11 I/O 63 I/O 115 D6-I/O 167 I/O 12 I/O 64 - 116 I/O 168 I/O 13 I/O 65 - 117 I/O 169 - 14 I/O 66 - 118 I/O 170 - 15 - 67 - 119 - 171 - 16 I/O 68 I/O 120 I/O 172 A15-I/O 17 I/O 69 I/O 121 I/O 173 A4-I/O 18 I/O 70 I/O 122 D5-I/O 174 I/O 19 I/O 71 I/O 123 CS0-I/O 175 I/O 20 I/O 72 - 124 I/O 176 - 21 I/O 73 - 125 I/O 177 - 22 I/O 74 I/O 126 I/O 178 A14-I/O 23 I/O 75 I/O 127 I/O 179 A5-I/O 24 I/O 76 I/O 128 D4-I/O 180 I/O 25 GND 77 INIT-I/O 129 I/O 181 I/O 26 VCC 78 VCC 130 VCC 182 GND 27 I/O 79 GND 131 GND 183 VCC 28 I/O 80 I/O 132 D3-I/O 184 A13-I/O 29 I/O 81 I/O 133 CS1-I/O 185 A6-I/O 30 I/O 82 I/O 134 I/O 186 I/O 31 I/O 83 - 135 I/O 187 I/O 32 I/O 84 - 136 I/O 188 - 33 I/O 85 I/O 137 I/O 189 - 34 I/O 86 I/O 138 D2-I/O 190 I/O 35 I/O 87 I/O 139 I/O 191 I/O 36 I/O 88 I/O 140 I/O 192 A12-I/O 37 - 89 I/O 141 I/O 193 A7-I/O 38 I/O 90 - 142 - 194 - 39 I/O 91 - 143 I/O 195 - 40 I/O 92 - 144 I/O 196 - 41 I/O 93 I/O 145 D1-I/O 197 I/O 42 I/O 94 I/O 146 RDY/BUSY-RCLK-I/O 198 I/O 43 I/O 95 I/O 147 I/O 199 A11-I/O 44 I/O 96 I/O 148 I/O 200 A8-I/O 45 I/O 97 I/O 149 I/O 201 I/O 46 I/O 98 I/O 150 I/O 202 I/O 47 I/O 99 I/O 151 DIN-D0-I/O 203 A10-I/O 48 M1-RDATA 100 XTL2-I/O 152 DOUT-I/O 204 A9-I/O 49 GND 101 GND 153 CCLK 205 VCC 50 M0-RTRIG 102 RESET 154 VCC 206 - 51 - 103 - 155 - 207 - 52 - 104 - 156 - 208 - Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. *In PQ208, XC3090 and XC3195 have different pinouts. 2-149 XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families XC3195 PQ208 and PG223 Pinouts Pin Description PG223 PQ208 Pin Description PG223 PQ208 Pin Description PG223 PQ208 A9-I/O B1 206 I/O U18 102 I/O B16 A10-I/O E3 205 I/O P15 101 I/O A16 49 48 I/O E4 204 I/O T17 100 I/O D14 47 I/O C2 203 I/O T18 99 I/O C15 46 I/O C1 202 I/O P16 98 I/O B15 45 I/O D2 201 I/O R17 97 I/O A15 44 A8-I/O E2 200 I/O N15 96 I/O C14 43 42 A11-I/O F4 199 I/O R18 95 I/O D13 I/O F3 198 I/O P17 94 I/O B14 41 I/O D1 197 I/O N17 93 I/O C13 40 39 I/O F2 196 I/O N16 92 I/O B13 I/O G2 194 I/O M15 89 I/O B12 38 A7-I/O G4 193 I/O M18 88 I/O D12 37 A12-I/O G1 192 I/O M17 87 I/O A12 36 I/O H2 191 I/O L18 86 I/O B11 35 I/O H3 190 I/O L17 85 I/O C11 34 I/O H1 189 I/O L15 84 I/O A11 33 I/O H4 188 I/O L16 83 I/O D11 32 I/O J3 187 I/O K18 82 I/O A10 31 I/O J2 186 I/O K17 81 I/O B10 30 A6-I/O J1 185 I/O K16 80 I/O C10 29 A13-I/O K3 184 GND K15 79 I/O C9 28 VCC J4 183 VCC J15 78 VCC D10 27 GND K4 182 INIT J16 77 GND D9 26 I/O K2 181 I/O J17 76 I/O B9 25 I/O K1 180 I/O J18 75 I/O A9 24 A5-I/O L2 179 I/O H16 74 I/O C8 23 A14-I/O L4 178 I/O H15 73 I/O D8 22 I/O L3 177 I/O H17 72 I/O B8 21 I/O L1 176 I/O H18 71 I/O A8 20 I/O M1 175 I/O G17 70 I/O B7 19 I/O M2 174 I/O G18 69 I/O A7 18 A4-I/O M4 173 I/O G15 68 I/O D7 17 A15-I/O N2 172 I/O F16 67 I/O B6 14 I/O N3 171 I/O F17 66 I/O C6 13 12 I/O P2 169 I/O E17 63 I/O B5 I/O R1 168 I/O C18 62 I/O A4 11 I/O N4 167 I/O F15 61 I/O D6 10 A3-I/O T1 166 I/O D17 60 I/O C5 9 A2-I/O R2 165 LDC-I/O E16 59 I/O B4 8 I/O P3 164 I/O C17 58 I/O B3 7 I/O T2 163 I/O B18 57 I/O C4 6 I/O P4 162 I/O E15 56 I/O D5 5 I/O U1 161 HDC-I/O A18 55 I/O C3 4 A1-CS2-I/O V1 160 M2-I/O A17 54 I/O A3 3 A0-WS-I/O T3 159 VCC D16 53 TCLKIN-I/O A2 2 GND R3 158 M0-RTIG B17 52 PWRDN B2 1 VCC R4 157 GND D15 51 GND D4 208 CCLK U2 156 M1/RDATA C16 50 VCC D3 207 DOUT-I/O V2 155 Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-rate limited. In the PQ208 package, pins 15, 16, 64, 65, 90, 91, 142, 143, 170 and 195 are not connected. *In PQ208, XC3090 and XC3195 have different pinouts. 2-150 XC3000 Component Availability 44 PINS TYPE CODE XC3020 XC3030 XC3042 XC3064 XC3090 XC3020A XC3030A XC3042A XC3064A XC3090A -50 -70 -100 -125 -50 -70 -100 -125 -50 -70 -100 -125 -50 -70 -100 -125 -50 -70 -100 -125 -7 -6 -7 -6 -7 -6 -7 -6 -7 -6 64 68 XC3142A XC3164A XC3190A XC3195A CERAM PLAST. 144 PLAST. PLAST. PLAST. VQFP PLCC PLCC PC44 VQ64 PC68 PC84 CI CI CIMB CI CMB CI CI CIMB CI CMB C C C C CI CI CI CIM CI CI CI CI CIM CI C C C C C C C CI CIMB CI C CMB C CIMB CI CIMB CI C CMB C CIMB C C C C PGA PQFP PLAST. 132 TOPPLAST. BRAZED PLAST. CERAM. PLAST. PLCC TQFP VQFP CQFP PGA PGA TQFP 160 164 175 176 TOPPLAST. BRAZED PLAST. CERAM. PLAST. PQFP CQFP PGA PGA TQFP 208 223 PLAST. CERAM. PQFP PGA PG84 PQ100 TQ100 VQ100 CB100 PP132 PG132 TQ144 PQ160 CB164 PP175 PG175 TQ176 PQ208 PG223 M B M B M C MB MB MB C C M CI CI CIM CI CI CI CIM CI C C C C M B CI M B CI CI CIMB CI CIMB CI CI CI CIMB CI CIMB CI C C C C C CI CI CI C C C C CI CI CI CI CI CI C C C C C C C CI CI CI CI CI CI C C C C C C C CI CI CI CI C C C C CI CI CI C CI CI CI CI CI CI C C C C C C C C XC3030L XC3042L XC3064L XC3090L XC3130A 100 PLAST. XC3020L XC3120A 84 C C C C C C C C -5 -4 -3 -2 -1 -5 -4 -3 -2 -1 -5 -4 -3 -2 -1 -5 -4 -3 -2 -1 -5 -4 -3 -2 -1 -5 -4 -3 -2 -1 C CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI C C CI CI CI CI CI CI CI CI CI CI CI CI CI CI C C C C C C C CI CIMB CI C C CIMB CI CI CI CI C C CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI C C C C C C C CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI CI C CI CI CI CI C CI CI CI CI C C C C C CI CI CI CI C CI CI CI CI C MB C = Commercial = 0 to +85 C I = Industrial = -40 to +100 C Parentheses indicate future product plans 2-151 M B M B M = Mil Temp = -55 to +125 C CI CI CI CI C CI CI CI CI C CIMB CI CI CI C CIMB CI CI CI C CI CI CI CI C CI CI CI CI C CI CI CI CI C B = MIL-STD-883C Class B CI CI CI CI C XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families For a detailed description of the device architecture, see pages 2-105 through 2-123. For a detailed description of the configuration modes and their timing, see pages 2-124 through 2-132. For detailed lists of package pin-outs, see pages 2-140 through 2-150. For package physical dimensions and thermal data, see Section 4. Ordering Information Example: XC3130A- 3 PC44C Device Type Temperature Range Block Delay Number of Pins Package Type XC3000, XC3000A, XC3000L, XC3100, XC3100A The features of the original XC3000 family are described on the preceding pages. XC3100A is functionally identical with XC3000, but offers substantially faster performance. There is also an additional high-end family member, the XC3195A. XC3000L uses a 3.3 V supply voltage and has lower power-down current. The XC3000A, XC3000L and XC3100A families all offer identical enhanced functionality. They are thus supersets of the XC3000 familiy. Additional routing resources provide improved performance and higher density. There is now a direct connection from each CLB output to the data input of its nearest TBUF. This speeds up the path and preserves general routing resources that can be used for other purposes. The CLB clock enable and the TBUF output enable are now driven by two different vertical Longlines. In the XC3000/3100 devices, the CLB clock enable signal and the adjacent TBUF output enable signal can both be driven only from the same vertical Longline. That makes these two functions mutually exclusive, and thus creates placement constraints. Using separate Longlines for these two functions leads to improved density and performance, especially in bus-oriented applications. Bitstream error checking protects against erroneous configuration. Each Xilinx FPGA bitstream consists of a 40-bit preamble, followed by a device-specific number of data frames. The number of bits per frame is also device-specific; however, each frame ends with three stop bits (111) followed by a start bit for the next frame (0). All devices in all XC3000 families start reading in a new frame when they find the first 0 after the end of the previous frame. XC3000/XC3100 devices do not check for the correct stop bits, but XC3000A/XC3100A and XC3000L devices check that the last three bits of any frame are actually 111. Under normal circumstances, all these FPGAs behave the same way; however, if the bitstream is corrupted, an XC3000/XC3100 device will always start a new frame as soon as it finds the first 0 after the end of the previous frame, even if the data is completely wrong or out-of-sync. Given sufficient zeros in the data stream, the device will also go Done, but with incorrect configuration and the possibility of internal contention. An XC3000A/XC3100A/XC3000L device starts any new frame only if the three preceding bits are all ones. If this check fails, it pulls INIT Low and stops the internal configuration, although the Master CCLK keeps running. The user must then start a new configuration by applying a >6 s Low level on RESET. This simple check does not protect against random bit errors, but it offers almost 100 percent protection against erroneous configuration files, defective configuration data sources, synchronization errors between configuration source and FPGA, or PC-board level defects, such as broken lines or solder-bridges. A separate modification slows down the RESET input before configuration by using a two-stage shift register driven from the internal clock. It tolerates submicrosecond High spikes on RESET before configuration. The XC3000 master can be connected like an XC4000 master, but with its RESET input used instead of INIT. (On XC3000, INIT is output only). Soft start-up. After configuration, the outputs of all LCA device in a daisy-chain become active simultaneously, as a result of the same CCLK edge. In the original XC3000/ 3100 devices, each output becomes active in either fast or slew-rate limited mode, depending on the way it is configured. This can lead to large ground-bounce signals. In the new XC3000A/XC3000L/XC31000A devices, all outputs become active first in slew-rate limited mode, reducing the ground bounce. After this soft start-up, each individual output slew rate is again controlled by the respective configuration bit. The XC3000, XC3000L, ZC3100A are fully supported by the XACT Version 5.0, or later, development system. XACT 5.0 provides many advanced features not available with the XC3000 software such as timing-driven place and route (XACT-Performance)and the X-BLOX module generator. 2-152