0.50
0.55
0.60
0.65
0.70
0.75
0.80
1.25 1.50 1.75 2.00 2.25 2.50 2.75
POWER SUPPLY (Vs)
SUPPLY CURRENT (mA)
10 1000 100000
0.0
20.0
40.0
80.0
140.0
160.0
VOLTAGE NOISE (nV/ Hz)
FREQUENCY (Hz)
100 10000
120.0
100.0
60.0
LME49726
www.ti.com
SNAS432C –NOVEMBER 2008–REVISED APRIL 2013
LME49726 High Current, Low Distortion, Rail-to-Rail Output
Audio Operational Amplifier
Check for Samples: LME49726
1FEATURES APPLICATIONS
2• Rail-to-Rail Output • Portable Audio Amplification
• Easily Drives 2kΩLoads to within 4mV of Each • Preamplifiers and Multimedia
Power Supply Voltage Rail • Equalization and Crossover Networks
• Optimized for Superior Audio Signal Fidelity • Line Drivers and Receivers
• Output Short Circuit Protection • Active Filters
• High Output Drive (>300mA) • DAC I–V Converter Gain Stage
• Available in VSSOP Exposed-DAP Package • ADC Front-End Signal Conditioning
KEY SPECIFICATIONS DESCRIPTION
The LME49726 is a low distortion, low noise rail-to-
• Power Supply Voltage Range: 2.5 to 5.5 V rail output audio operational amplifier optimized and
• Quiescent Current per Amplifier at 5V: 0.7 fully specified for high performance, high fidelity
mA (Typ) applications. The LME49726 delivers superior audio
• THD+N, AV= 1, fIN = 1kHz, RL= 10kΩ:signal amplification for outstanding audio
performance. The LME49726 has a very low THD+N
– (VOUT = 3.5VP-P, VDD = 5.0V): 0.00008 % (Typ) to easily satisfy demanding audio applications. To
– (VOUT = 1.5VP-P, VDD = 2.5V): 0.00002 % (Typ) ensure that the most challenging loads are driven
• Equivalent Input Noise (f = 10k): 8.3 nV/√Hz without compromise, the LME49726 provides output
(Typ) current greater than 300mA at 5V. Further, dynamic
range is maximized by an output that drives 2kΩ
• Slew Rate: ±3.7 V/μs (Typ) loads to within 4mV of either power supply voltage.
• Gain Bandwidth Product: 6.25 MHz (Typ) The LME49726 has a supply range of 2.5V to 5.5V.
• Open Loop Gain (RL= 10kΩ): 120 dB (Typ) Over this supply range the LME49726’s input circuitry
• Input Bias Current: 0.2 pA (Typ) maintains excellent common-mode and power supply
• Input Offset Voltage: 0.5 mV (Typ) rejection, as well as maintaining its low input bias
current. The LME49726 is unity gain stable.
• PSRR (DC): 104 dB (Typ)
Figure 1. Input Voltage Noise vs Frequency Figure 2. Supply Current vs Supply Voltage
VDD = 3V per Amplifier, RL= No Load, AV= –1
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
1
2
3
45
6
7
8
OUTPUTA
NON-INVERTING INPUT A
INVERTING INPUT A
INVERTING INPUT B
OUTPUTB
NON-INVERTING INPUT B
+
-
+
-
VDD
VSS
VDD
-
+
VOUT
VIN
VEE
R1R2
VDD
-
+
VOUT
VIN R1R2
VDD/2 RL
VDD/2
LME49726
SNAS432C –NOVEMBER 2008–REVISED APRIL 2013
www.ti.com
Typical Connections
Figure 3. Inverting Configuration Split Supplies Figure 4. Inverting Configuration Single Supplies
Connection Diagram
Figure 5. See Package Number DGN0008A
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LME49726
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)(3)
Power Supply Voltage VS= VSS-VDD 6V
Storage Temperature −65°C to 150°C
Input Voltage (VSS) – 0.7V to (VDD) + 0.7V
Output Short Circuit(4) Continuous
Power Dissipation Internally Limited
ESD Rating(5) 2000V
ESD Rating(6) 200V
Junction Temperature 150°C
Thermal Resistance θJA (DGN0008A) 72°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
(2) The Electrical Characteristics tables list specifications under the listed Recommended Operating Conditions except as otherwise
modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not
ensured.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(4) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower.
(5) Human body model, applicable std. JESD22-A114C.
(6) Machine model, applicable std. JESD22-A115-A.
OPERATING RATINGS(1)
Temperature Range TMIN ≤TA ≤TMAX −40°C ≤TA≤125°C
Supply Voltage Range 2.5V ≤VS≤5.5V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
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LME49726
SNAS432C –NOVEMBER 2008–REVISED APRIL 2013
www.ti.com
ELECTRICAL CHARACTERISTICS (VDD = 5.0V and VDD = 2.5V)
The following specifications apply for the circuit shown in Figure 1. VDD = 5.0V and VDD = 2.5V, VSS = 0.0V, VCM = VDD/2, RL=
10kΩ, CLOAD = 20pF, fIN = 1kHz, BW = 20–20kHz, and TA= 25°C, unless otherwise specified. LME49726 Units
Symbol Parameter Conditions (Limits)
Typical(1) Limit(2)
AV= –1, VOUT = 3.5Vp-p, VDD = 5V
RL= 600Ω0.0008 %
RL= 2kΩ0.0002 %
RL= 10kΩ0.00008 %
THD+N Total Harmonic Distortion + Noise AV= –1, VOUT = 1.5Vp-p, VDD = 2.5V
RL= 600Ω0.001 %
RL= 2kΩ0.0008 %
RL= 10kΩ0.0002 %
GBWP Gain Bandwidth Product 6.25 5.0 MHz (min)
SR Slew Rate AV= +1, RL= 10kΩ3.7 2.5 V/μs (min)
AV= 1V step
tsSettling time 0.1% error range 800 ns
0.001% error range 1.2 μs
μVRMS
eNEquivalent Input Noise Voltage fBW = 20Hz to 20kHz (A-weighted) 0.7 1.25 (max)
f = 10kHz 8.3 nV/√Hz
eNEquivalent Input Noise Density f = 1kHz 10 nV/√Hz
f = 100Hz 24 nV/√Hz
INCurrent Noise Density f = 1kHz 0.75 pA/√Hz
VOS Input Offset Voltage VIN = VDD/2, VO= VDD/2, AV= 1 0.5 2.25 mV (max)
Average Input Offset Voltage Drift vs
ΔVOS/ΔTemp 40°C ≤TA≤85°C 1.2 μV/°C
Temperature
PSRR Power Supply Rejection Ratio 2.5 to 5.5V, VCM = 0, VDD/2 104 85 dB (min)
ISOCH-CH Channel-to-Channel Isolation fIN = 1kHz 94 dB
IBInput Bias Current VCM = VDD/2 ±0.2 pA
Input Bias Current Drift vs
ΔIOS/ΔTemp –40°C ≤TA≤85°C 35 nA/°C
Temperature
IOS Input Offset Current VCM = VDD/2 ±0.2 pA
VDD–1.6
VIN-CM Common-Mode Input Voltage Range V (min)
VSS+0.1
CMRR Common Mode Rejection Ratio 0.1V < VDD – 1.6V 95 80 dB (min)
1/f 1/f Corner Frequency 2 kHz
AVOL Open-Loop Voltage Gain VOUT = VDD/2 120 100 dB (min)
VDD–0.004 V (min)
RL= 2kΩto VDD/2 VSS +0.004 V (max)
VOUTSWING Maximum Output Voltage Swing VDD –0.33 V (min)
RL= 16Ωto VDD/2 VSS+0.33 V (max)
VOUT = 5V, VDD = 5V 350 mA
IOUT Output Current VOUT = 2.5V, VDD = 2.5V 160 mA
IOUT = 0mA, VDD = 5V 0.7 1.1 mA (max)
ISQuiescent Current per Amplifier IOUT = 0mA, VDD = 2.5V 0.64 1.0 mA (max)
(1) Typical values represent most likely parametric norms at TA= +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
(2) Datasheet min/max specification limits are specified by test or statistical analysis.
4Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LME49726
0.0001
0.001
0.01
0.1
0.01 0.1 1 10
OUTPUT VOLTAGE (V)
THD+N (%)
0.0001
0.001
0.01
0.1
100 1k 10k 100k
FREQUENCY (Hz)
THD+N (%)
10
0.0001
0.001
0.01
0.1
0.01 0.1 1 10
OUTPUT VOLTAGE (V)
THD+N (%)
0.0001
0.001
0.01
0.1
100 1k 10k 100k
FREQUENCY (Hz)
THD+N (%)
10
0.0001
0.001
0.01
0.1
0.01 0.1 1 10
OUTPUT VOLTAGE (V)
THD+N (%)
0.0001
0.001
0.01
0.1
100 1k 10k 100k
FREQUENCY (Hz)
THD+N (%)
10
LME49726
www.ti.com
SNAS432C –NOVEMBER 2008–REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS
THD+N vs Output Voltage THD+N vs Frequency
VDD = 1.25V, VSS = –1.25V, RL= 600ΩVDD = 1.25V, VSS = –1.25V, RL= 600Ω
AV= –1, f = 1kHz, BW = 22–22kHz VO= 1.5VP-P, BW = 22–80kHz
Figure 6. Figure 7.
THD+N vs Output Voltage THD+N vs Frequency
VDD = 1.25V, VSS = –1.25V, RL= 10kΩVDD = 1.25V, VSS = –1.25V, RL= 10kΩ
AV= –1, f = 1kHz, BW = 22–22kHz VO= 1VP-P, BW = 22–80kHz
Figure 8. Figure 9.
THD+N vs Output Voltage THD+N vs Frequency
VDD = 2.50V, VSS = –2.50V, RL= 600ΩVDD = 2.50V, VSS = –2.50V, RL= 600Ω
AV= –1, f = 1kHz, BW = 22–22kHz VO= 3.5VP-P, BW = 22–80kHz
Figure 10. Figure 11.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LME49726
OUTPUT VOLTAGE (V)
THD+N (%)
0.00001
0.0001
0.001
0.01
0.1
0.01 0.1 110
0.0001
0.001
0.01
0.1
100 1k 10k 100k
FREQUENCY (Hz)
THD+N (%)
10
0.0001
0.001
0.01
0.1
100 1k 10k 100k
FREQUENCY (Hz)
THD+N (%)
10
0.0001
0.001
0.01
0.1
0.01 0.1 1 10
OUTPUT VOLTAGE (V)
THD+N (%)
OUTPUT VOLTAGE (V)
THD+N (%)
0.00001
0.0001
0.001
0.01
0.1
0.01 0.1 110
0.0001
0.001
0.01
0.1
100 1k 10k 100k
FREQUENCY (Hz)
THD+N (%)
10
LME49726
SNAS432C –NOVEMBER 2008–REVISED APRIL 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Output Voltage THD+N vs Frequency
VDD = 2.50V, VSS = –2.50V, RL= 10kΩVDD = 2.50V, VSS = –2.50V, RL= 10kΩ
AV= –1, f = 1kHz, BW = 22–22kHz VO= 1VP-P, BW = 22–80kHz
Figure 12. Figure 13.
THD+N vs Output Voltage THD+N vs Frequency
VDD = 2.75V, VSS = –2.75V, RL= 600ΩVDD = 2.75V, VSS = –2.75V, RL= 600Ω
AV= –1, f = 1kHz, BW = 22–22kHz VO= 3.5VP-P, BW = 22–80kHz
Figure 14. Figure 15.
THD+N vs Output Voltage THD+N vs Frequency
VDD = 2.75V, VSS = –2.75V, RL= 10kΩVDD = 2.75V, VSS = –2.75V, RL= 10kΩ
AV= –1, f = 1kHz, BW = 22–22kHz VO= 3.5VP-P, BW = 22–80kHz
Figure 16. Figure 17.
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Product Folder Links: LME49726
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
PSRR (dB)
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
PSRR (dB)
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
PSRR (dB)
FREQUENCY (Hz)
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10 100 1k 10k 100k 1M
PSRR (dB)
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
PSRR (dB)
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
PSRR (dB)
LME49726
www.ti.com
SNAS432C –NOVEMBER 2008–REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
PSRR+ vs Frequency PSRR– vs Frequency
VDD = 1.25V, VSS = –1.25V, VRIPPLE = 200mVP-P VDD = 1.25V, VSS = –1.25V, VRIPPLE = 200mVP-P
Input terminated, BW = 22–80kHz Input terminated, BW = 22–80kHz
Figure 18. Figure 19.
PSRR+ vs Frequency PSRR– vs Frequency
VDD = 2.50V, VEE = –2.50V, VRIPPLE = 200mVP-P VDD = 2.50V, VSS = –2.50V, VRIPPLE = 200mVP-P
Input terminated, BW = 22–80kHz Input terminated, BW = 22–80kHz
Figure 20. Figure 21.
PSRR+ vs Frequency PSRR– vs Frequency
VDD = 2.75V, VSS = –2.75V, VRIPPLE = 200mVP-P VDD = 2.75V, VSS = –2.75V, VRIPPLE = 200mVP-P
Input terminated, BW = 22–80kHz Input terminated, BW = 22–80kHz
Figure 22. Figure 23.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: LME49726
10 1000 100000
0.0
20.0
40.0
80.0
140.0
160.0
VOLTAGE NOISE (nV/ Hz)
FREQUENCY (Hz)
100 10000
120.0
100.0
60.0
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
CROSSTALK (dB)
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
CMRR (dB)
0.0
1.0
1.5
2.0
2.5
2.5 3.0 3.5 4.0 4.5 5.0 5.5
POWER SUPPLY (Vs)
OUTPUT VOLTAGE
0.5
0.0
1.0
1.5
2.0
2.5
2.5 3.0 3.5 4.0 4.5 5.0 5.5
POWER SUPPLY (Vs)
OUTPUT VOLTAGE
0.5
LME49726
SNAS432C –NOVEMBER 2008–REVISED APRIL 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Output Voltage vs Supply Voltage Output Voltage vs Supply Voltage
RL= 600Ω, AV= –1 RL= 10kΩ, AV= –1
f = 1kHz, THD+N = 1%, BW = 22–80kHz f = 1kHz, THD+N = 1%, BW = 22–80kHz
Figure 24. Figure 25.
Crosstalk vs Frequency
VDD = 2.50V, VSS = –2.50V, RL= 10kΩCMRR vs Frequency
AV= –1, f = 1kHz, BW = 80kHz VDD = 2.5V, VSS = –2.5V, VRIPPLE = 200mVP-P
Figure 26. Figure 27.
Input Voltage Noise vs Frequency
VDD = 5V
Figure 28.
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Product Folder Links: LME49726
-
+Distortion Signal Gain = 1 + (R2/R3)
R1R2
Audio Precision
System Two
Cascade
LME49726
Generator Output Analyzer Input
1 k 1 k
R3
10
LME49726
www.ti.com
SNAS432C –NOVEMBER 2008–REVISED APRIL 2013
APPLICATION INFORMATION
DISTORTION MEASUREMENTS
The vanishingly low residual distortion produced by LME49726 is below the capabilities of all commercially
available equipment. This makes distortion measurements just slightly more difficult than simply connecting a
distortion meter to the amplifier's inputs and outputs. The solution. however, is quite simple: an additional
resistor. Adding this resistor extends the resolution of the distortion measurement equipment.
The LME49726's low residual is an input referred internal error. As shown in Figure 29, adding the 10Ωresistor
connected between athe amplifier's inverting and non-inverting inputs changes the amplifier's noise gain. The
result is that the error signal (distortion) is amplified by a factor of 101. Although the amplifier's closed-loop gain
is unaltered, the feedback available to correct distortion errors is reduced by 101. To ensure minimum effects on
distortion measurements, keep the value of R1 low as shown in Figure 29.
This technique is verified by duplicating the measurements with high closed loop gain and/or making the
measurements at high frequencies. Doing so, produces distortion components that are within measurement
equipment capabilities. This datasheet's THD+N and IMD values were generated using the above described
circuit connected to an Audio Precision System Two Cascade.
Figure 29. THD+N and IMD Distortion Test Circuit
OPERATING RATINGS AND BASIC DESIGN GUIDELINES
The LME49726 has a supply voltage range from +2.5V to +5.5V single supply or ±1.25 to ±2.75V dual supply.
Bypassed capacitors for the supplies should be placed as close to the amplifier as possible. This will help
minimize any inductance between the power supply and the supply pins. In addition to a 10μF capacitor, a 0.1μF
capacitor is also recommended in CMOS amplifiers.
The amplifier's inputs lead lengths should also be as short as possible. If the op amp does not have a bypass
capacitor, it may oscillate.
BASIC AMPLIFIER CONFIGURATIONS
The LME49726 may be operated with either a single supply or dual supplies. Figure 2 shows the typical
connection for a single supply inverting amplifier. The output voltage for a single supply amplifier will be centered
around the common-mode voltage, VCM. Note, the voltage applied to the VCM insures the output stays above
ground. Typically, the VCM should be equal to VDD/2. This is done by putting a resistor divider circuit at this node,
see Figure 30.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: LME49726
+
-
VIN
VDD
VOUT
+
-
R1R2
VOUT
VIN
VDD
VSS
+
-
VDD
R1R2
VOUT
VCM
R3
R4
VDD
LME49726
SNAS432C –NOVEMBER 2008–REVISED APRIL 2013
www.ti.com
Figure 30. Single Supply Inverting Op Amp
Figure 31 shows the typical connection for a dual supply inverting amplifier. The output voltage is centered on
zero.
Figure 31. Dual Supply Inverting Configuration
Figure 32 shows the typical connection for the Buffer Amplifier or also called a Voltage Follower. The Buffer is a
unity gain stable amplifier.
Figure 32. Unity-Gain Buffer Configuration
10 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LME49726
-
+
R
1/2 LME49726 V0
V2
V1
R
R
R
LME49726
www.ti.com
SNAS432C –NOVEMBER 2008–REVISED APRIL 2013
Typical Applications
AV= 34.5
F = 1 kHz
En= 0.38 μV
A Weighted
Figure 33. NAB Preamp
AV= 34.5
F = 1 kHz
En= 0.38 μV
A Weighted
Figure 34. NAB Preamp Voltage Gain vs Frequency
VO= V1–V2
Figure 35. Balanced to Single Ended Converter
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Product Folder Links: LME49726
-
+
1/2 LME49726 V0
V1
R1
11k
R2
22k
C1
0.01 PFC2
0.01 PF
-
+
R
1/2 LME49726 V0
V2
V1 R
R
R
R
R
V4
V3
LME49726
SNAS432C –NOVEMBER 2008–REVISED APRIL 2013
www.ti.com
VO= V1 + V2 −V3 −V4
Figure 36. Adder/Subtracter
Figure 37. Sine Wave Oscillator
Illustration is f0= 1 kHz
Figure 38. Second Order High Pass Filter
(Butterworth)
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Product Folder Links: LME49726
-
+
1/2 LME49726
-
+
1/2 LME49726
R6
15k
V0 = VIN
C1
10 PF
VIN
R2
20k R3
10k R4
20k
R5
20k
R1
20k
R7
6.2k
D2
1S1588
D1
1S1588
-
+
1/2 LME49726
R1
R2
10k
C1
0.01 PF
10k -
+
-
+
1/2 LME49726 1/2 LME49726
R2
0.01 PF
R1
16k 16k
C1
R0
556
R2
10k
VHP VLP
VIN
VBP
RG
10k
-
+
1/2 LME49726 V0
R2
10k
V1
C1
0.022 PF
R1
10k
C2
0.011 PF
LME49726
www.ti.com
SNAS432C –NOVEMBER 2008–REVISED APRIL 2013
Illustration is f0= 1 kHz
Figure 39. Second Order Low Pass Filter
(Butterworth)
Illustration is f0= 1 kHz, Q = 10, ABP = 1
Figure 40. State Variable Filter
Figure 41. AC/DC Converter
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Product Folder Links: LME49726
R2
-VEE
Q2
-
+
1/2 LME49726
VCC
R1
V1
Q1
V0
R6
10k
R9
10k
R3
10k
R5
10k
BIAS
R8
33
R7
33
-
+
1/2 LME49726 V01
+
-
1/2 LME49726 V02
R1
15k R1
15k 3.41R1
51k
R1
15k R1
15k
3.41R1
51k
VI0.707R1
10k
LME49726
SNAS432C –NOVEMBER 2008–REVISED APRIL 2013
www.ti.com
Figure 42. 2 Channel Panning Circuit (Pan Pot)
Figure 43. Line Driver
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Product Folder Links: LME49726
-
+
1/2 LME49726
V1
V0
R4
500k
BOOST-TREBLE-CUT
BOOST-BASS-CUT
R5
3.6k
C2
0.005 PF
C1
0.05 PFC1
0.05 PF
R2
100k R1
11k
R1
11k
R3
11k
R5
3.6k
LME49726
www.ti.com
SNAS432C –NOVEMBER 2008–REVISED APRIL 2013
Illustration is:
fL= 32 Hz, fLB = 320 Hz
fH=11 kHz, fHB = 1.1 kHz
Figure 44. Tone Control
Figure 45.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LME49726
-
+
R7
1/2 LME49726
+
-
R6
10k
+
-
1/2 LME49726
V2
R2
R5
10k
10k
R1
200
1/2 LME49726
R
R
V1 R3 R4
10k 10k
V0
10k
LME49726
SNAS432C –NOVEMBER 2008–REVISED APRIL 2013
www.ti.com
Av= 35 dB
En= 0.33 μV
S/N = 90 dB
f = 1 kHz
A Weighted
A Weighted, VIN = 10 mV
@f = 1 kHz
Figure 46.
Illustration is:
V0 = 101(V2 −V1)
Figure 47. Balanced Input Mic Amp
16 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LME49726
LME49726
www.ti.com
SNAS432C –NOVEMBER 2008–REVISED APRIL 2013
Figure 48.
fo (Hz) C1C2R1R2
32 0.12μF 4.7μF 75kΩ500Ω
64 0.056μF 3.3μF 68kΩ510Ω
125 0.033μF 1.5μF 62kΩ510Ω
250 0.015μF 0.82μF 68kΩ470Ω
500 8200pF 0.39μF 62kΩ470Ω
1k 3900pF 0.22μF 68kΩ470Ω
2k 2000pF 0.1μF 68kΩ470Ω
4k 1100pF 0.056μF 62kΩ470Ω
8k 510pF 0.022μF 68kΩ510Ω
16k 330pF 0.012μF 51kΩ510Ω
At volume of change = ±12 dB Q = 1.
LME49726 Bill of Materials
Description Designator Part Number Manufacturer Quantity/Brd
Ceramic Capacitor 0.1uF, 10%, AVX
C1, C2, C5–C8 08055C104KAT2A 2
50V 0805 SMD
Tantalum Capacitor 2.2uF,10%, Kemet
C9, C11 T491A225K020AT Not Stuff
20V, A-size
Tantalum Capacitor 10uF,10%, Kemet
C3, C4 T491B106K020AT 2
20V, B-size R1, R4, R6, R9, R13, Vishay
Resistor 0Ω, 1/8W 1% 0805 SMD CRCW08050000Z0EA 6
R14
Header, 2-Pin JP1, JP2, JP3, JP4 HDR1X2 Header 2 4
Header, 3-Pin JP5 HDR1X3 Header 3 1
Resistor 10kΩ, 1/8W 1% 0805 SMD R2, R3, R7, R8 CRCW080510K0FKEA Vishay 4
Texas
Dual Rail-to-Rail Op Amp U1 LME49726 1
Instruments
Resistor 100meg/open R5, R10, R11, R12 OPEN N/A N/A 0
1/8W 0805 SMD
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LME49726
LME49726
www.ti.com
SNAS432C –NOVEMBER 2008–REVISED APRIL 2013
REVISION HISTORY
Rev Date Description
1.0 11/05/08 Initial release.
1.01 05/25/10 Increased Operating Temperature Range.
1.02 07/14/11 Added curves 30038602 and 03 and input text edits.
Re-released the D/S to the WEB after adding curves 30038602 and
1.03 07/19/11 03 .
C 04/04/13 Changed layout of National Data Sheet to TI format.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LME49726
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LME49726MY/NOPB ACTIVE HVSSOP DGN 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 ZA3
LME49726MYX/NOPB ACTIVE HVSSOP DGN 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 ZA3
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LME49726MY/NOPB HVSSOP DGN 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LME49726MYX/NOPB HVSSOP DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Sep-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LME49726MY/NOPB HVSSOP DGN 8 1000 210.0 185.0 35.0
LME49726MYX/NOPB HVSSOP DGN 8 3500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Sep-2019
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
6X 0.65
2X
1.95
8X 0.38
0.25
5.05
4.75 TYP
SEATING
PLANE
0.15
0.05
0.25
GAGE PLANE
0 -8
1.1 MAX
0.23
0.13
1.88
1.58
2.0
1.7
B3.1
2.9
NOTE 4
A
3.1
2.9
NOTE 3
0.7
0.4
PowerPAD VSSOP - 1.1 mm max heightDGN0008A
SMALL OUTLINE PACKAGE
4218836/A 11/2019
1
4
5
8
0.13 C A B
PIN 1 INDEX AREA
SEE DETAIL A
0.1 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
PowerPAD is a trademark of Texas Instruments.
TM
A 20
DETAIL A
TYPICAL
SCALE 4.000
EXPOSED THERMAL PAD
1
45
8
9
www.ti.com
EXAMPLE BOARD LAYOUT
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
8X (1.4)
8X (0.45)
6X (0.65)
(4.4)
(R0.05) TYP
(2)
NOTE 9
(3)
NOTE 9
(1.22)
(0.55)
( 0.2) TYP
VIA
(1.88)
(2)
PowerPAD VSSOP - 1.1 mm max heightDGN0008A
SMALL OUTLINE PACKAGE
4218836/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
TM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SYMM
SYMM
1
45
8
SOLDER MASK
DEFINED PAD
METAL COVERED
BY SOLDER MASK
SEE DETAILS
9
15.000
METAL
SOLDER MASK
OPENING METAL UNDER
SOLDER MASK SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK DETAILS
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
8X (1.4)
8X (0.45)
6X (0.65)
(4.4)
(R0.05) TYP
(1.88)
BASED ON
0.125 THICK
STENCIL
(2)
BASED ON
0.125 THICK
STENCIL
PowerPAD VSSOP - 1.1 mm max heightDGN0008A
SMALL OUTLINE PACKAGE
4218836/A 11/2019
1.59 X 1.690.175 1.72 X 1.830.15 1.88 X 2.00 (SHOWN)0.125 2.10 X 2.240.1
SOLDER STENCIL
OPENING
STENCIL
THICKNESS
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
TM
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
SYMM
SYMM
1
45
8
METAL COVERED
BY SOLDER MASK SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
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