Document Number: 91058 www.vishay.com
S11-1049-Rev. C, 30-May-11 1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
Power MOSFET
IRF820AS, SiHF820AS, IRF820AL, SiHF820AL
Vishay Siliconix
FEATURES
•Halogen-free According to IEC 61249-2-21
Definition
• Low Gate Charge Qg Results in Simple Drive
Requirement
• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
• Fully Characterized Capacitance and Avalanche
Voltage and Current
• Effective Coss specified
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
• Switch Mode Power Supply (SMPS)
• Uninterruptible Power Supply
• High Speed Power Switching
TYPICAL SMPS TOPOLOGIES
• Two Transistor Forward
• Half Bridge and Full Bridge
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 45 mH, Rg = 25 , IAS = 2.5 A (see fig. 12).
c. ISD 2.5 A, dI/dt 270 A/μs, VDD VDS, TJ 150 °C.
d. 1.6 mm from case.
e. Uses IRF820A, SiHF820A data and test conditions.
PRODUCT SUMMARY
VDS (V) 500
RDS(on) (Max.) ()V
GS = 10 V 3.0
Qg (Max.) (nC) 17
Qgs (nC) 4.3
Qgd (nC) 8.5
Configuration Single
N-Channel MOSFET
G
D
S
D
2
PAK (TO-263)
GD
S
I
2
PAK (TO-262)
GDS
ORDERING INFORMATION
Package D2PAK (TO-263) I2PAK (TO-262)
Lead (Pb)-free and Halogen-free SiHF820AS-GE3 SiHF820AL-GE3
Lead (Pb)-free IRF820ASPbF IRF820ALPbF
SiHF820AS-E3 SiHF820AL-E3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS 500 V
Gate-Source Voltage VGS ± 30
Continuous Drain Current VGS at 10 V TC = 25 °C ID
2.5
ATC = 100 °C 1.6
Pulsed Drain Currenta, e IDM 10
Linear Derating Factor 0.4 W/°C
Single Pulse Avalanche Energyb, e EAS 140 mJ
Avalanche CurrentaIAR 2.5 A
Repetiitive Avalanche EnergyaEAR 5.0 mJ
Maximum Power Dissipation TC = 25 °C PD50 W
Peak Diode Recovery dV/dtc, e dV/dt 3.4 V/ns
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150 °C
Soldering Recommendations (Peak Temperature) for 10 s 300d
Mounting Torque 6-32 or M3 screw 10 lbf · in
1.1 N · m
* Pb containing terminations are not RoHS compliant, exemptions may apply
www.vishay.com Document Number: 91058
2S11-1049-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRF820AS, SiHF820AS, IRF820AL, SiHF820AL
Vishay Siliconix
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width 300 μs; duty cycle 2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS.
d. Uses IRF820A/SiHF820A data and test conditions.
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient (PCB
Mounted, steady-state)aRthJA -62
°C/W
Maximum Junction-to-Case (Drain) RthJC -2.5
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0, ID = 250 μA 500 - - V
VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mAd-0.60-V/°C
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.5 V
Gate-Source Leakage IGSS V
GS = ± 30 V - - ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = 500 V, VGS = 0 V - - 25 μA
VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250
Drain-Source On-State Resistance RDS(on) V
GS = 10 V ID = 1.5 Ab--3.0
Forward Transconductance gfs VDS = 50 V, ID = 1.5 Ad1.4 - - S
Dynamic
Input Capacitance Ciss VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5d
- 340 -
pFOutput Capacitance Coss -53-
Reverse Transfer Capacitance Crss -2.7-
Output Capacitance Coss VGS = 0 V
VDS = 1.0 V, f = 1.0 MHz - 490 -
VDS = 400 V, f = 1.0 MHz - 15 -
Effective Output Capacitance Coss eff. VDS = 0 V to 400 Vc, d -28-
Total Gate Charge Qg
VGS = 10 V ID = 2.5 A, VDS = 400 V,
see fig. 6 and 13b, d
--17
nC Gate-Source Charge Qgs --4.3
Gate-Drain Charge Qgd --8.5
Turn-On Delay Time td(on)
VDD = 250 V, ID = 2.5 A,
Rg = 21 , RD = 97 , see fig. 10b, d
-8.1-
ns
Rise Time tr -12-
Turn-Off Delay Time td(off) -16-
Fall Time tf -13-
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current ISMOSFET symbol
showing the
integral reverse
p - n junction diode
--2.5
A
Pulsed Diode Forward CurrentaISM --10
Body Diode Voltage VSD TJ = 25 °C, IS = 2.5 A, VGS = 0 Vb--1.6V
Body Diode Reverse Recovery Time trr TJ = 25 °C, IF = 2.5 A, dI/dt = 100 A/μsb, d - 330 500 ns
Body Diode Reverse Recovery Charge Qrr - 760 1140 nC
Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
S
D
G
Document Number: 91058 www.vishay.com
S11-1049-Rev. C, 30-May-11 3
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRF820AS, SiHF820AS, IRF820AL, SiHF820AL
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics
Fig. 2 - Typical Output Characteristics
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
91058_01
Bottom
To p
V
GS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
4.5 V
20 µs Pulse Width
TJ = 25 °C
4.5 V
VDS, Drain-to-Source Voltage (V)
ID, Drain-to-Source Current (A)
10 102
10
0.1
10-2
1
0.1 1
102
V
DS,
Drain-to-Source Voltage (V)
I
D
, Drain-to-Source Current (A)
Bottom
To p
VGS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
4.5 V
20 µs Pulse Width
TJ = 150 °C
91058_02
4.5 V
10
0.1
1
101
20 µs Pulse Width
VDS = 50 V
10
1
10-2
ID, Drain-to-Source Current (A)
VGS, Gate-to-Source Voltage (V)
5.0 6.0 7.0 8.0 9.0
4.0
91058_03
TJ = 25 °C
TJ = 150 °C
0.1
I
D
= 2.5 A
V
GS
= 10 V
3.0
0.0
0.5
1.0
1.5
2.0
2.5
TJ, Junction Temperature (°C)
RDS(on), Drain-to-Source On Resistance
(Normalized)
91058_04
- 60 - 40 - 20 0 20 40 60 80 100 120 140 160
www.vishay.com Document Number: 91058
4S11-1049-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRF820AS, SiHF820AS, IRF820AL, SiHF820AL
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
102
104
1
C, Capacitance (pF)
V
DS,
Drain-to-Source Voltage (V)
Ciss
Crss
Coss
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
91058_05
103
102
10
110 10
3
Q
G
, Total Gate Charge (nC)
V
GS
, Gate-to-Source Voltage (V)
20
15
10
5
0
04 16128
V
DS
= 100 V
V
DS
= 250 V
For test circuit
see figure 13
V
DS
= 400 V
91058_06
I
D
= 2.5 A
10
1
V
SD
, Source-to-Drain Voltage (V)
I
SD
, Reverse Drain Current (A)
0.4 1.2
1.00.80.6
V
GS
= 0 V
91058_07
TJ = 25 °C
TJ = 150 °C
0.1
10 µs
100 µs
1 ms
10 ms
Operation in this area limited
by RDS(on)
VDS, Drain-to-Source Voltage (V)
ID, Drain Current (A)
TC = 25 °C
TJ = 150 °C
Single Pulse
102
0.1
1
10
10 102103104
91058_08
Document Number: 91058 www.vishay.com
S11-1049-Rev. C, 30-May-11 5
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRF820AS, SiHF820AS, IRF820AL, SiHF820AL
Vishay Siliconix
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10a - Switching Time Test Circuit
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
RD
VGS
Rg
D.U.T.
10 V
+
-
VDS
VDD
VDS
90 %
10 %
VGS
td(on) trtd(off) tf
10
1
0.1
10-2
10-5 10-4 10-3 10-2 0.1 1
PDM
t1
t2
t1, Rectangular Pulse Duration (s)
Thermal Response (ZthJC)
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
Single Pulse
(Thermal Response)
D = 0.50
0.20
0.05
0.02
0.01
91058_11
0.10
A
Rg
IAS
0.01 Ω
tp
D.U.T
L
VDS
+
-VDD
Driver
15 V
20 V
IAS
VDS
tp
www.vishay.com Document Number: 91058
6S11-1049-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRF820AS, SiHF820AS, IRF820AL, SiHF820AL
Vishay Siliconix
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Fig. 13a - Maximum Avalanche Energy vs. Drain Current
Fig. 12d - Basic Gate Charge Waveform
Fig. 13b - Gate Charge Test Circuit
QGS QGD
QG
V
G
Charge
10 V
650
550
600
0.0 2.5
2.0
1.51.0
0.5
IAV, Avalanche Current (A)
VDSav, Avalanche Voltage (V)
700
91058_12d
D.U.T.
3 mA
VGS
VDS
IGID
0.3 µF
0.2 µF
50 kΩ
12 V
Current regulator
Current sampling resistors
Same type as D.U.T.
+
-
Document Number: 91058 www.vishay.com
S11-1049-Rev. C, 30-May-11 7
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRF820AS, SiHF820AS, IRF820AL, SiHF820AL
Vishay Siliconix
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91058.
P.W. Period
dI/dt
Diode recovery
dV/dt
Ripple ≤ 5 %
Body diode forward drop
Re-applied
voltage
Reverse
recovery
current
Body diode forward
current
VGS = 10 Va
ISD
Driver gate drive
D.U.T. lSD waveform
D.U.T. VDS waveform
Inductor current
D = P.W.
Period
+
-
+
+
+
-
-
-
Peak Diode Recovery dV/dt Test Circuit
VDD
• dV/dt controlled by Rg
• Driver same type as D.U.T.
• ISD controlled by duty factor “D”
• D.U.T. - device under test
D.U.T. Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
Rg
Note
a. VGS = 5 V for logic level devices
VDD
Document Number: 91364 www.vishay.com
Revision: 15-Sep-08 1
Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
5
4
13
L1
L2
D
BB
E
H
B
A
Detail A
A
A
c
c2
A
2 x e
2 x b2
2 x b
0.010 A B
MM ± 0.004 B
M
Base
metal
Plating b1, b3
(b, b2)
c1
(c)
Section B - B and C - C
Scale: none
Lead tip
4
34
(Datum A)
2CC
BB
5
5
View A - A
E1
D1
E
4
4
B
H
Seating plane
Gauge
plane
0° to 8°
Detail “A”
Rotated 90° CW
scale 8:1
L3 A1
L4
L
MILLIMETERS INCHES MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.
A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 -
A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420
b 0.51 0.99 0.020 0.039 E1 6.22 - 0.245 -
b1 0.51 0.89 0.020 0.035 e 2.54 BSC 0.100 BSC
b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625
b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110
c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066
c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070
c2 1.14 1.65 0.045 0.065 L3 0.25 BSC 0.010 BSC
D 8.38 9.65 0.330 0.380 L4 4.78 5.28 0.188 0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
AN826
Vishay Siliconix
Document Number: 73397
11-Apr-05
www.vishay.com
1
RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead
0.635
(16.129)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.420
(10.668)
0.355
(9.017)
0.145
(3.683)
0.135
(3.429)
0.200
(5.080)
0.050
(1.257)
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Revision: 12-Mar-12 1Document Number: 91000
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