0 XC9572 In-System Programmable CPLD R DS065 (v4.3) April 3, 2006 0 5 Product Specification Features Description * * 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz * * * 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3V or 5V I/O capability Advanced CMOS 5V FastFLASHTM technology Supports parallel programming of more than one XC9500 concurrently Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP, and 100-pin TQFP packages The XC9572 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview. * * * * * * * * * * Power dissipation can be reduced in the XC9572 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC9572 device. 200 e manc Typical ICC (mA) * * Power Management erfor High P (160) (125) 100 ower Low P (100) (65) 0 50 100 Clock Frequency (MHz) DS065_01_110501 Figure 1: Typical ICC vs. Frequency for XC9572 (c) 1996-2006 Xilinx, Inc. All rights reserved. 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DS065 (v4.3) April 3, 2006 Product Specification www.xilinx.com 1 R XC9572 In-System Programmable CPLD 3 JTAG Port 1 JTAG Controller In-System Programming Controller 36 Function Block 1 18 I/O Macrocells 1 to 18 I/O Fast CONNECT II Switch Matrix I/O I/O I/O Blocks I/O I/O I/O 36 Function Block 2 18 Macrocells 1 to 18 36 Function Block 3 18 Macrocells 1 to 18 I/O 3 I/O/GCK 36 1 Function Block 4 18 I/O/GSR 2 Macrocells 1 to 18 I/O/GTS DS065_02_110101 Figure 2: XC9572 Architecture Function block outputs (indicated by the bold line) drive the I/O blocks directly. 2 www.xilinx.com DS065 (v4.3) April 3, 2006 Product Specification R XC9572 In-System Programmable CPLD Absolute Maximum Ratings Symbol Description Value Units -0.5 to 7.0 V VCC Supply voltage relative to GND VIN Input voltage relative to GND -0.5 to VCC + 0.5 V VTS Voltage applied to 3-state output -0.5 to VCC + 0.5 V TSTG Storage temperature (ambient) -65 to +150 oC +150 oC TJ Junction temperature Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operation Conditions Symbol VCCINT VCCIO Parameter Supply voltage for internal logic and input buffers Supply voltage for output drivers for 5V operation Commercial TA = 0oC to 70oC Industrial TA = -40oC to +85oC Commercial TA = 0oC to 70oC Industrial TA = -40oC to +85oC Supply voltage for output drivers for 3.3V operation Min Max Units 4.75 5.25 V 4.5 5.5 4.75 5.25 4.5 5.5 3.0 3.6 V VIL Low-level input voltage 0 0.80 V VIH High-level input voltage 2.0 VCCINT + 0.5 V VO Output voltage 0 VCCIO V Quality and Reliability Characteristics Symbol Parameter TDR Data Retention NPE Program/Erase Cycles (Endurance) Min Max Units 20 - Years 10,000 - Cycles DC Characteristic Over Recommended Operating Conditions Symbol Min Max Units IOH = -4.0 mA, VCC = Min 2.4 - V Output high voltage for 3.3V outputs IOH = -3.2 mA, VCC = Min 2.4 - V Output low voltage for 5V outputs IOL = 24 mA, VCC = Min - 0.5 V Output low voltage for 3.3V outputs IOL = 10 mA, VCC = Min - 0.4 V IIL Input leakage current VCC = Max VIN = GND or VCC - 10 A IIH I/O high-Z leakage current VCC = Max VIN = GND or VCC - 10 A CIN I/O capacitance VIN = GND f = 1.0 MHz - 10 pF ICC Operating supply current (low power mode, active) VI = GND, No load f = 1.0 MHz 65 (Typical) VOH VOL Parameter Output high voltage for 5V outputs DS065 (v4.3) April 3, 2006 Product Specification Test Conditions www.xilinx.com mA 3 R XC9572 In-System Programmable CPLD AC Characteristics XC9572-7 Symbol Parameter XC9572-10 XC9572-15 Min Max Min Max Min Max Units - 7.5 - 10.0 - 15.0 ns 4.5 - 6.0 - 8.0 - ns TPD I/O to output valid TSU I/O setup time before GCK TH I/O hold time after GCK 0 - 0 - 0 - ns GCK to output valid - 4.5 - 6.0 - 8.0 ns 16-bit counter frequency 125.0 - 111.1 - 95.2 - MHz Multiple FB internal operating frequency 83.3 - 66.7 - 55.6 - MHz TPSU I/O setup time before p-term clock input 0.5 - 2.0 - 4.0 - ns TPH I/O hold time after p-term clock input 4.0 - 4.0 - 4.0 - ns P-term clock output valid - 8.5 - 10.0 - 12.0 ns TOE GTS to output valid - 5.5 - 6.0 - 11.0 ns TOD GTS to output disable - 5.5 - 6.0 - 11.0 ns TPOE Product term OE to output enabled - 9.5 - 10.0 - 14.0 ns TPOD Product term OE to output disabled - 9.5 - 10.0 - 14.0 ns TWLH GCK pulse width (High or Low) 4.0 - 4.5 - 5.5 - ns Asynchronous preset/reset pulse width (High or Low) 7.0 - 7.5 - 8.0 - ns TCO fCNT (1) fSYSTEM (2) TPCO TAPRPW Notes: 1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable. fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG. 2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs. VTEST R1 Output Type VCCIO VTEST R1 R2 CL 5.0V 5.0V 160 120 35 pF 3.3V 3.3V 260 360 35 pF Device Output R2 CL DS067_03_110101 Figure 3: AC Load Circuit 4 www.xilinx.com DS065 (v4.3) April 3, 2006 Product Specification R XC9572 In-System Programmable CPLD Internal Timing Parameters XC9572-7 Symbol Parameter XC9572-10 XC9572-15 Min Max Min Max Min Max Units Buffer Delays TIN Input buffer delay - 2.5 - 3.5 - 4.5 ns TGCK GCK buffer delay - 1.5 - 2.5 - 3.0 ns TGSR GSR buffer delay - 4.5 - 6.0 - 7.5 ns TGTS GTS buffer delay - 5.5 - 6.0 - 11.0 ns TOUT Output buffer delay - 2.5 - 3.0 - 4.5 ns TEN Output buffer enable/disable delay - 0 - 0 - 0 ns Product Term Control Delays TPTCK Product term clock delay - 3.0 - 3.0 - 2.5 ns TPTSR Product term set/reset delay - 2.0 - 2.5 - 3.0 ns TPTTS Product term 3-state delay - 4.5 - 3.5 - 5.0 ns - 0.5 - 1.0 - 3.0 ns Internal Register and Combinatorial Delays TPDI Combinatorial logic propagation delay TSUI Register setup time 1.5 - 2.5 - 3.5 - ns THI Register hold time 3.0 - 3.5 - 4.5 - ns TCOI Register clock to output valid time - 0.5 - 0.5 - 0.5 ns TAOI Register async. S/R to output delay - 6.5 - 7.0 - 8.0 ns TRAI Register async. S/R recover before clock 7.5 - 10.0 - 10.0 - ns TLOGI Internal logic delay - 2.0 - 2.5 - 3.0 ns TLOGILP Internal low power logic delay - 10.0 - 11.0 - 11.5 ns Feedback Delays TF FastCONNECT feedback delay - 8.0 - 9.5 - 11.0 ns TLF Function block local feedback delay - 4.0 - 3.5 - 3.5 ns TPTA(1) Incremental product term allocator delay - 1.0 - 1.0 - 1.0 ns TSLEW - 4.0 - 4.5 - 5.0 ns Time Adders Slew-rate limited delay Notes: 1. TPTA is multiplied by the span of the function as defined in the XC9500 family data sheet. DS065 (v4.3) April 3, 2006 Product Specification www.xilinx.com 5 R XC9572 In-System Programmable CPLD XC9572 I/O Pins BScan Order Function Block Macrocell 16 213 3 1 - 25 43 41 105 15 13 210 3 2 11 17 34 32 102 20 18 207 3 3 - 31 51 49 99 7 22 20 204 3 4 - 32 52 50 96 2 16 14 201 3 5 12 19 37 35 93 3 3 17 15 198 3 6 - 34 55 53 90 - 11 27 25 195 3 7 - 35 56 54 87 8 4 5 19 17 192 3 8 13 21 39 37 84 1 9 5[1] 9[1] 24[1] 22[1] 189 3 9 14 26 44 42 81 1 10 - 13 30 28 186 3 10 - 40 62 60 78 1 11 6[1] 10[1] 25[1] 23[1] 183 3 11 18 33 54 52 75 1 12 - 18 35 33 180 3 12 - 41 63 61 72 1 13 - 20 38 36 177 3 13 - 43 65 63 69 1 14 7[1] 12[1] 29[1] 27[1] 174 3 14 19 36 57 55 66 1 15 8 14 31 29 171 3 15 20 37 58 56 63 1 16 - 23 41 39 168 3 16 - 45 67 65 60 1 17 9 15 32 30 165 3 17 22 39 60 58 57 Function Block Macrocell PC44 1 1 - 4 18 1 2 1 1 1 3 - 6 1 4 - 1 5 2 1 6 1 7 1 PC84 PQ100 TQ100 PC44 PC84 PQ100 TQ100 BScan Order 1 18 - 24 42 40 162 3 18 - - 61 59 54 2 1 - 63 89 87 159 4 1 - 46 68 66 51 2 2 35 69 96 94 156 4 2 24 44 66 64 48 2 3 - 67 93 91 153 4 3 - 51 73 71 45 2 4 - 68 95 93 150 4 4 - 52 74 72 42 2 5 36 70 97 95 147 4 5 25 47 69 67 39 2 6 37 71 98 96 144 4 6 - 54 78 76 36 - 76[2] 5[2] 3[2] 141 4 7 - 55 79 77 33 2 7 2 8 38 72 99 97 138 4 8 26 48 70 68 30 2 9 39[1] 74[1] 1[1] 99[1] 135 4 9 27 50 72 70 27 2 10 - 75 3 1 132 4 10 - 57 83 81 24 2 11 40[1] 77[1] 6[1] 4[1] 129 4 11 28 53 76 74 21 2 12 - 79 8 6 126 4 12 - 58 84 82 18 2 13 - 80 10 8 123 4 13 - 61 87 85 15 2 14 42[3] 81[3] 11[3] 9[3] 120 4 14 29 56 80 78 12 2 15 43 83 13 11 117 4 15 33 65 91 89 9 2 16 - 82 12 10 114 4 16 - 62 88 86 6 2 17 44 84 14 12 111 4 17 34 66 92 90 3 2 18 - - 94 92 108 4 18 - - 81 79 0 Notes: 1. Global control piN. 2. Global control pin GTS1 for PC84, PQ100, and TQ100. 3. Global control pin GTS1 for PC44. 6 www.xilinx.com DS065 (v4.3) April 3, 2006 Product Specification R XC9572 In-System Programmable CPLD XC9572 Global, JTAG and Power Pins Pin Type PC44 PC84 PQ100 TQ100 I/O/GCK1 5 9 24 22 I/O/GCK2 6 10 25 23 I/O/GCK3 7 12 29 27 I/O/GTS1 42 76 5 3 I/O/GTS2 40 77 6 4 I/O/GSR 39 74 1 99 TCK 17 30 50 48 TDI 15 28 47 45 TDO 30 59 85 83 TMS 16 29 49 47 VCCINT 5V 21,41 38,73,78 7,59,100 5,57,98 VCCIO 3.3V/5V 32 22,64 28,40,53,90 26,38,51,88 GND 10,23,31 8,16,27,42, 2,23,33,46,64,71, 100,21,31,44,62,69, 49,60 77,86 75, 84 - 4,9,21,26,36,45,48, 2,7,19,24,34,43,46, 75, 82 73, 80 No Connects DS065 (v4.3) April 3, 2006 Product Specification - www.xilinx.com 7 R XC9572 In-System Programmable CPLD Device Part Marking and Ordering Combination Information R XC95xxx TQ144 Device Type Package This line not related to device part number 7C Speed Operating Range 1 Sample package with part marking. Device Ordering and Part Marking Number XC9572-7PC44C XC9572-7PCG44C XC9572-7PC84C XC9572-7PCG84C XC9572-7PQ100C XC9572-7PQG100C XC9572-7TQ100C XC9572-7TQG100C XC9572-10PC44C XC9572-10PCG44C XC9572-10PC84C XC9572-10PCG84C XC9572-10PQ100C XC9572-10PQG100C XC9572-10TQ100C XC9572-10TQG100C XC9572-10PC44I XC9572-10PCG44I XC9572-10PC84I XC9572-10PCG84I XC9572-10PQ100I XC9572-10PQG100I XC9572-10TQ100I XC9572-10TQG100I XC9572-15PC44C XC9572-15PCG44C XC9572-15PC84C XC9572-15PCG84C XC9572-15PQ100C XC9572-15PQG100C XC9572-15TQ100C XC9572-15TQG100C XC9572-15PC44I 8 Speed (pin-to-pin delay) 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns Pkg. Symbol PC44 PCG44 PC84 PCG84 PQ100 PQG100 TQ100 TQG100 PC44 PCG44 PC84 PCG84 PQ100 PQG100 TQ100 TQG100 PC44 PCG44 PC84 PCG84 PQ100 PQG100 TQ100 TQG100 PC44 PCG44 PC84 PCG84 PQ100 PQG100 TQ100 TQG100 PC44 No. of Pins 44-pin 44-pin 84-pin 84-pin 100-pin 100-pin 100-pin 100-pin 44-pin 44-pin 84-pin 84-pin 100-pin 100-pin 100-pin 100-pin 44-pin 44-pin 84-pin 84-pin 100-pin 100-pin 100-pin 100-pin 44-pin 44-pin 84-pin 84-pin 100-pin 100-pin 100-pin 100-pin 44-pin Package Type Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC); Pb-Free Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC); Pb-Free Plastic Quad Flat Pack (PQFP) Plastic Quad Flat Pack (PQFP); Pb-Free Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP); Pb-Free Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC); Pb-Free Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC); Pb-Free Plastic Quad Flat Pack (PQFP) Plastic Quad Flat Pack (PQFP); Pb-Free Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP); Pb-Free Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC); Pb-Free Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC); Pb-Free Plastic Quad Flat Pack (PQFP) Plastic Quad Flat Pack (PQFP); Pb-Free Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP); Pb-Free Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC); Pb-Free Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC); Pb-Free Plastic Quad Flat Pack (PQFP) Plastic Quad Flat Pack (PQFP); Pb-Free Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP); Pb-Free Plastic Lead Chip Carrier (PLCC) www.xilinx.com Operating Range(1) C C C C C C C C C C C C C C C C I I I I I I I I C C C C C C C C I DS065 (v4.3) April 3, 2006 Product Specification R XC9572 In-System Programmable CPLD Device Ordering and Part Marking Number XC9572-15PCG44I XC9572-15PC84I XC9572-15PCG84I XC9572-15PQ100I XC9572-15PQG100I XC9572-15TQ100I XC9572-15TQG100I Speed (pin-to-pin Pkg. No. of delay) Symbol Pins 15 ns PCG44 44-pin 15 ns PC84 84-pin 15 ns PCG84 84-pin 15 ns PQ100 100-pin 15 ns PQG100 100-pin 15 ns TQ100 100-pin 15 ns TQG100 100-pin Package Type Plastic Lead Chip Carrier (PLCC); Pb-Free Plastic Lead Chip Carrier (PLCC) Plastic Lead Chip Carrier (PLCC); Pb-Free Plastic Quad Flat Pack (PQFP) Plastic Quad Flat Pack (PQFP); Pb-Free Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP); Pb-Free Operating Range(1) I I I I I I I Notes: 1. C = Commercial: TA = 0 to +70C; I = Industrial: TA = -40 to +85C Warranty Disclaimer THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS. Revision History The following table shows the revision history for this document. Date Version 12/04/98 3.0 Update AC characteristics and internal parameters. 06/18/03 4.0 Updated format. 08/21/03 4.1 Updated Package Device Marking Pin 1 orientation. 04/15/05 4.2 Added asynchronous preset/reset pulse width specification (TAPRPW) 04/03/06 4.3 Added Warranty Disclaimer. Added Pb-Free package information. DS065 (v4.3) April 3, 2006 Product Specification Revision www.xilinx.com 9