DS065 (v4.3) April 3, 2006 www.xilinx.com 1
Product Specification
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All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
• 7.5 ns pin-to-pin logic delays on all pins
•f
CNT to 125 MHz
• 72 macrocells with 1,600 usable gates
• Up to 72 user I/O pins
• 5V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables,
set and reset signals
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
• Programmable power reduction mode in each
macrocell
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design
protection
• High-drive 24 mA outputs
• 3.3V or 5V I/O capability
• Advanced CMOS 5V FastFLASH™ technology
• Supports parallel programming of more than one
XC9500 concurrently
• Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP,
and 100-pin TQFP packages
Description
The XC9572 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC9572 by config-
uring macrocells to standard or low-power modes of opera-
tion. Unused macrocells are turned off to minimize power
dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC9572 device.
0
XC9572 In-System
Programmable CPLD
DS065 (v4.3) April 3, 2006 05Product Specification
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Figure 1:
Typical ICC vs. Frequency for XC9572
Clock Frequency (MHz)
Typical ICC (mA)
050
100
(65)
(125)
(160)
(100)
200
100
High Performance
Low Power
DS065_01_110501
XC9572 In-System Programmable CPLD
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Product Specification
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Figure 2:
XC9572 Architecture
Function block outputs (indicated by the bold line) drive the I/O blocks directly.
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port
3
36
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
2
1
I/O
I/O
I/O
I/O
3
DS065_02_110101
1
Function
Block 2
36
18
18
Function
Block 3
Macrocells
1 to 18
36
18
Function
Block 4
Macrocells
1 to 18
36
18
Fast CONNECT II Switch Matrix
XC9572 In-System Programmable CPLD
DS065 (v4.3) April 3, 2006 www.xilinx.com 3
Product Specification
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Absolute Maximum Ratings
Recommended Operation Conditions
Quality and Reliability Characteristics
DC Characteristic Over Recommended Operating Conditions
Symbol Description Value Units
VCC Supply voltage relative to GND –0.5 to 7.0 V
VIN Input voltage relative to GND –0.5 to VCC + 0.5 V
VTS Voltage applied to 3-state output –0.5 to VCC + 0.5 V
TSTG Storage temperature (ambient) –65 to +150 oC
TJJunction temperature +150 oC
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Symbol Parameter Min Max Units
VCCINT Supply voltage for internal logic
and input buffers
Commercial TA = 0oC to 70oC 4.75 5.25 V
Industrial TA = –40oC to +85oC4.5 5.5
VCCIO Supply voltage for output drivers
for 5V operation
Commercial TA = 0oC to 70oC 4.75 5.25 V
Industrial TA = –40oC to +85oC4.5 5.5
Supply voltage for output drivers for 3.3V operation 3.0 3.6
VIL Low-level input voltage 0 0.80 V
VIH High-level input voltage 2.0 VCCINT + 0.5 V
VOOutput voltage 0 VCCIO V
Symbol Parameter Min Max Units
TDR Data Retention 20 - Years
NPE Program/Erase Cycles (Endurance) 10,000 - Cycles
Symbol Parameter Test Conditions Min Max Units
VOH Output high voltage for 5V outputs IOH = –4.0 mA, VCC = Min 2.4 - V
Output high voltage for 3.3V outputs IOH = –3.2 mA, VCC = Min 2.4 - V
VOL Output low voltage for 5V outputs IOL = 24 mA, VCC = Min - 0.5 V
Output low voltage for 3.3V outputs IOL = 10 mA, VCC = Min - 0.4 V
IIL Input leakage current VCC = Max
VIN = GND or VCC
-±10μA
IIH I/O high-Z leakage current VCC = Max
VIN = GND or VCC
-±10μA
CIN I/O capacitance VIN = GND
f = 1.0 MHz
-10pF
ICC Operating supply current
(low power mode, active)
VI = GND, No load
f = 1.0 MHz
65 (Typical) mA
XC9572 In-System Programmable CPLD
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Product Specification
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AC Characteristics
Symbol Parameter
XC9572-7 XC9572-10 XC9572-15
UnitsMin Max Min Max Min Max
TPD I/O to output valid - 7.5 - 10.0 - 15.0 ns
TSU I/O setup time before GCK 4.5 - 6.0 - 8.0 - ns
THI/O hold time after GCK 0 - 0 - 0 - ns
TCO GCK to output valid - 4.5 - 6.0 - 8.0 ns
fCNT(1) 16-bit counter frequency 125.0 - 111.1 - 95.2 - MHz
fSYSTEM(2) Multiple FB internal operating frequency 83.3 - 66.7 - 55.6 - MHz
TPSU I/O setup time before p-term clock input 0.5 - 2.0 - 4.0 - ns
TPH I/O hold time after p-term clock input 4.0 - 4.0 - 4.0 - ns
TPCO P-term clock output valid - 8.5 - 10.0 - 12.0 ns
TOE GTS to output valid - 5.5 - 6.0 - 11.0 ns
TOD GTS to output disable - 5.5 - 6.0 - 11.0 ns
TPOE Product term OE to output enabled - 9.5 - 10.0 - 14.0 ns
TPOD Product term OE to output disabled - 9.5 - 10.0 - 14.0 ns
TWLH GCK pulse width (High or Low) 4.0 - 4.5 - 5.5 - ns
TAPRPW Asynchronous preset/reset pulse width (High
or Low)
7.0 - 7.5 - 8.0 - ns
Notes:
1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable.
fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG.
2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.
Figure 3:
AC Load Circuit
Device Output
Output Type VTEST
5.0V
3.3V
VTEST
R1
160Ω
260Ω
R1
R2CL
R2
120Ω
360Ω
CL
35 pF
35 pF
DS067_03_110101
VCCIO
5.0V
3.3V
XC9572 In-System Programmable CPLD
DS065 (v4.3) April 3, 2006 www.xilinx.com 5
Product Specification
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Internal Timing Parameters
Symbol Parameter
XC9572-7 XC9572-10 XC9572-15
UnitsMinMaxMinMaxMinMax
Buffer Delays
TIN Input buffer delay - 2.5 - 3.5 - 4.5 ns
TGCK GCK buffer delay - 1.5 - 2.5 - 3.0 ns
TGSR GSR buffer delay - 4.5 - 6.0 - 7.5 ns
TGTS GTS buffer delay - 5.5 - 6.0 - 11.0 ns
TOUT Output buffer delay - 2.5 - 3.0 - 4.5 ns
TEN Output buffer enable/disable delay - 0 - 0 - 0 ns
Product Term Control Delays
TPTCK Product term clock delay - 3.0 - 3.0 - 2.5 ns
TPTSR Product term set/reset delay - 2.0 - 2.5 - 3.0 ns
TPTTS Product term 3-state delay - 4.5 - 3.5 - 5.0 ns
Internal Register and Combinatorial Delays
TPDI Combinatorial logic propagation delay - 0.5 - 1.0 - 3.0 ns
TSUI Register setup time 1.5 - 2.5 - 3.5 - ns
THI Register hold time 3.0 - 3.5 - 4.5 - ns
TCOI Register clock to output valid time - 0.5 - 0.5 - 0.5 ns
TAOI Register async. S/R to output delay - 6.5 - 7.0 - 8.0 ns
TRAI Register async. S/R recover before clock 7.5 - 10.0 - 10.0 - ns
TLOGI Internal logic delay - 2.0 - 2.5 - 3.0 ns
TLOGILP Internal low power logic delay - 10.0 - 11.0 - 11.5 ns
Feedback Delays
TFFastCONNECT feedback delay - 8.0 - 9.5 - 11.0 ns
TLF Function block local feedback delay - 4.0 - 3.5 - 3.5 ns
Time Adders
TPTA(1) Incremental product term allocator delay - 1.0 - 1.0 - 1.0 ns
TSLEW Slew-rate limited delay - 4.0 - 4.5 - 5.0 ns
Notes:
1. TPTA is multiplied by the span of the function as defined in the XC9500 family data sheet.
XC9572 In-System Programmable CPLD
6www.xilinx.com DS065 (v4.3) April 3, 2006
Product Specification
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XC9572 I/O Pins
Function
Block
Macro-
cell PC44 PC84 PQ100 TQ100
BScan
Order
Function
Block
Macro-
cell PC44 PC84 PQ100 TQ100
BScan
Order
1 1 – 4 18 16 213 3 1 – 25 43 41 105
1 2 1 1 15 13 210 3 2 11 17 34 32 102
1 3 – 6 20 18 207 3 3 – 31 51 49 99
1 4 – 7 22 20 204 3 4 – 32 52 50 96
1 5 2 2 16 14 201 3 5 12 19 37 35 93
1 6 3 3 17 15 198 3 6 – 34 55 53 90
1 7 – 11 27 25 195 3 7 – 35 56 54 87
1 8 4 5 19 17 192 3 8 13 21 39 37 84
1 9 5[1] 9[1] 24[1] 22[1] 189 3 9 14 26 44 42 81
110 –13 30 28 186 310 –40 62 60 78
111 6[1] 10[1] 25[1] 23[1] 183 311 18 33 54 52 75
112 –18 35 33 180 312 –41 63 61 72
113 –20 38 36 177 313 –43 65 63 69
114 7[1] 12[1] 29[1] 27[1] 174 314 19 36 57 55 66
115 814 31 29 171 315 20 37 58 56 63
116 –23 41 39 168 316 –45 67 65 60
117 915 32 30 165 317 22 39 60 58 57
1 18 – 24 42 40 162 318––615954
2 1 – 63 89 87 159 4 1 – 46 68 66 51
2 2 35 69 96 94 156 4 2 24 44 66 64 48
2 3 – 67 93 91 153 4 3 – 51 73 71 45
2 4 – 68 95 93 150 4 4 – 52 74 72 42
2 5 36 70 97 95 147 4 5 25 47 69 67 39
2 6 37 71 98 96 144 4 6 – 54 78 76 36
2 7 – 76[2] 5[2] 3[2] 141 4 7 – 55 79 77 33
2 8 38 72 99 97 138 4 8 26 48 70 68 30
2 9 39[1] 74[1] 1[1] 99[1] 135 4 9 27 50 72 70 27
210 –75 31 132 410 –57 83 81 24
211 40[1] 77[1] 6[1] 4[1] 129 411 28 53 76 74 21
212 –79 86 126 412 –58 84 82 18
213 –80 10 8 123 413 –61 87 85 15
214 42[3] 81[3] 11[3] 9[3] 120 414 29 56 80 78 12
215 43 83 13 11 117 415 33 65 91 89 9
216 –82 12 10 114 416 –62 88 86 6
217 44 84 14 12 111 417 34 66 92 90 3
2 18 – – 94 92 108 418––81790
Notes:
1. Global control piN.
2. Global control pin GTS1 for PC84, PQ100, and TQ100.
3. Global control pin GTS1 for PC44.
XC9572 In-System Programmable CPLD
DS065 (v4.3) April 3, 2006 www.xilinx.com 7
Product Specification
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XC9572 Global, JTAG and Power Pins
Pin Type PC44 PC84 PQ100 TQ100
I/O/GCK1 5 9 24 22
I/O/GCK2 6 10 25 23
I/O/GCK3 7 12 29 27
I/O/GTS1 42 76 5 3
I/O/GTS2 40 77 6 4
I/O/GSR 39 74 1 99
TCK 17 30 50 48
TDI 15 28 47 45
TDO 30 59 85 83
TMS 16 29 49 47
VCCINT 5V 21,41 38,73,78 7,59,100 5,57,98
VCCIO 3.3V/5V 32 22,64 28,40,53,90 26,38,51,88
GND 10,23,31 8,16,27,42,
49,60
2,23,33,46,64,71,
77,86
100,21,31,44,62,69,
75, 84
No Connects - - 4,9,21,26,36,45,48,
75, 82
2,7,19,24,34,43,46,
73, 80
XC9572 In-System Programmable CPLD
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Product Specification
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Device Part Marking and Ordering Combination Information
Device Ordering and
Part Marking Number
Speed
(pin-to-pin
delay)
Pkg.
Symbol
No. of
Pins Package Type
Operating
Range(1)
XC9572-7PC44C 7.5 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) C
XC9572-7PCG44C 7.5 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-Free C
XC9572-7PC84C 7.5 ns PC84 84-pin Plastic Lead Chip Carrier (PLCC) C
XC9572-7PCG84C 7.5 ns PCG84 84-pin Plastic Lead Chip Carrier (PLCC); Pb-Free C
XC9572-7PQ100C 7.5 ns PQ100 100-pin Plastic Quad Flat Pack (PQFP) C
XC9572-7PQG100C 7.5 ns PQG100 100-pin Plastic Quad Flat Pack (PQFP); Pb-Free C
XC9572-7TQ100C 7.5 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) C
XC9572-7TQG100C 7.5 ns TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-Free C
XC9572-10PC44C 10 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) C
XC9572-10PCG44C 10 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-Free C
XC9572-10PC84C 10 ns PC84 84-pin Plastic Lead Chip Carrier (PLCC) C
XC9572-10PCG84C 10 ns PCG84 84-pin Plastic Lead Chip Carrier (PLCC); Pb-Free C
XC9572-10PQ100C 10 ns PQ100 100-pin Plastic Quad Flat Pack (PQFP) C
XC9572-10PQG100C 10 ns PQG100 100-pin Plastic Quad Flat Pack (PQFP); Pb-Free C
XC9572-10TQ100C 10 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) C
XC9572-10TQG100C 10 ns TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-Free C
XC9572-10PC44I 10 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) I
XC9572-10PCG44I 10 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-Free I
XC9572-10PC84I 10 ns PC84 84-pin Plastic Lead Chip Carrier (PLCC) I
XC9572-10PCG84I 10 ns PCG84 84-pin Plastic Lead Chip Carrier (PLCC); Pb-Free I
XC9572-10PQ100I 10 ns PQ100 100-pin Plastic Quad Flat Pack (PQFP) I
XC9572-10PQG100I 10 ns PQG100 100-pin Plastic Quad Flat Pack (PQFP); Pb-Free I
XC9572-10TQ100I 10 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) I
XC9572-10TQG100I 10 ns TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-Free I
XC9572-15PC44C 15 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) C
XC9572-15PCG44C 15 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-Free C
XC9572-15PC84C 15 ns PC84 84-pin Plastic Lead Chip Carrier (PLCC) C
XC9572-15PCG84C 15 ns PCG84 84-pin Plastic Lead Chip Carrier (PLCC); Pb-Free C
XC9572-15PQ100C 15 ns PQ100 100-pin Plastic Quad Flat Pack (PQFP) C
XC9572-15PQG100C 15 ns PQG100 100-pin Plastic Quad Flat Pack (PQFP); Pb-Free C
XC9572-15TQ100C 15 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) C
XC9572-15TQG100C 15 ns TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-Free C
XC9572-15PC44I 15 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) I
XC95xxx
TQ144
7C
De vice Type
Package
Speed
Operating Range
This line not
related to device
part number
Sample package with part marking.
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1
XC9572 In-System Programmable CPLD
DS065 (v4.3) April 3, 2006 www.xilinx.com 9
Product Specification
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Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Revision History
The following table shows the revision history for this document.
XC9572-15PCG44I 15 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-Free I
XC9572-15PC84I 15 ns PC84 84-pin Plastic Lead Chip Carrier (PLCC) I
XC9572-15PCG84I 15 ns PCG84 84-pin Plastic Lead Chip Carrier (PLCC); Pb-Free I
XC9572-15PQ100I 15 ns PQ100 100-pin Plastic Quad Flat Pack (PQFP) I
XC9572-15PQG100I 15 ns PQG100 100-pin Plastic Quad Flat Pack (PQFP); Pb-Free I
XC9572-15TQ100I 15 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) I
XC9572-15TQG100I 15 ns TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-Free I
Notes:
1. C = Commercial: TA = 0° to +70°C; I = Industrial: TA = –40° to +85°C
Date Version Revision
12/04/98 3.0 Update AC characteristics and internal parameters.
06/18/03 4.0 Updated format.
08/21/03 4.1 Updated Package Device Marking Pin 1 orientation.
04/15/05 4.2 Added asynchronous preset/reset pulse width specification (TAPRPW)
04/03/06 4.3 Added Warranty Disclaimer. Added Pb-Free package information.
Device Ordering and
Part Marking Number
Speed
(pin-to-pin
delay)
Pkg.
Symbol
No. of
Pins Package Type
Operating
Range(1)
