FPGA Configuration Memory - Atmel Corporation

Features

•EE Reprogrammable 4,194,304 x 1 bit Serial Memories Designed to Store Configuration

Programs for Field Programmable Gate Arrays (FPGAs)

•In-System Programmable via 2-wire Bus

•Simple Interface to SRAM FPGAs

•Compatible with Atmel AT6000, AT40K FPGAs, Altera FLEX® Devices,

ORCA® FPGAs, Xilinx XC3000, XC4000, XC5200, Spartan®, Virtex® FPGAs

•Cascadable Read Back to Support Additional Configurations or

Future Higher-density Arrays

•Low-power CMOS EEPROM Process

•Programmable Reset Polarity

•Available in PLCC Package (Pin Compatible Across Product Family)

•Emulation of Atmel’s AT24CXXX Serial EEPROMs

•Available in 3.3V ± 10% LV and 5V ± 5% C Versions

•System-friendly READY Pin

•Low-power Standby Mode

Description

The AT17C040 and AT17LV040 (high-density AT17 Series) FPGA Configuration

EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration

memory for Field Programmable Gate Arrays (FPGA). The AT17 Series is packaged in

the popular 44-pin TQFP and 44-pin PLCC. The AT17 Series family uses a simple

serial-access procedure to configure one or more FPGA devices. The AT17 Series

organization supplies enough memory to configure one or multiple smaller FPGAs.

The user can select the polarity of the reset function by programming internal

EEPROM bytes. These devices also support a system-friendly READY pin, which

signifies a “good” power level to the FPGA and can be used to ensure reliable system

power-up.

The AT17 Series Configurators can be programmed with industry-standard program-

mers or Atmel’s ATDH2200E programming system.

4-megabit

FPGA

Configuration

EEPROM

Memory

AT17C040

AT17LV040

Advance

Information

Rev. 2282C–06/01

Pin Configurations

44 PLCC

WP1

RESET/OE

WP2

GND

CEO/A2

READY

CLK

GND

DATA

VCC

SERER

44 TQFP

WP1

RESET/OE

WP2

GND

CEO/A2

READY

CLK

GND

DATA

VCC

SER_EN

2AT17C/LV040

Block Diagram

FPGA Master Serial

Mode Summary

The I/O and logic functions of the FPGA and their associated interconnections are

established by a configuration program. The program is loaded either automatically

upon power-up, or on command, depending on the state of the FPGA mode pins. In

master mode, the FPGA automatically loads the configuration program from an external

memory. The AT17 Series Configuration EEPROM has been designed for compatibility

with the master serial mode.

This document discusses the AT40K FPGA interface. For more details or for AT6K

FPGA applications, please reference the “AT40K Series Configuration” or the “AT6000

Series Configuration” application notes.

Controlling the High-

density AT17 Series

Serial EEPROMs

During Configuration

Most connections between the FPGA device and the AT17 Series Configuration

EEPROM are simple and self-explanatory:

•The DATA output of the AT17 Series Configurator drives DIN of the FPGA devices.

•The master FPGA CCLK output drives the CLK input of the AT17 Series

Configurator.

•The CEO output of any AT17C/LV040 drives the CE input of the next AT17C/LV040

in a cascade chain of EEPROMs.

•SER_EN must be connected to VCC, (except during ISP).

The READY pin is available as an open-collector indicator of the device’s RESET

status; it is driven Low while the device is in its POWER-ON RESET cycle and released

(tri-stated) when the cycle is complete.

CEO (A2)

WP1

WP2

SER_EN

AT17C/LV040

There are two different ways to use the inputs CE and OE.

Condition 1 The simplest connection is to have the FPGA CON pin drive both CE and RESET/OE(1)

in parallel. Due to its simplicity, however, this method will fail if the FPGA receives an

external reset condition during the configuration cycle. If a system reset is applied to the

FPGA, it will abort the original configuration and then reset itself for a new configuration.

The AT17 Series Configurator does not see the external reset signal and will not reset

its internal address counters and, consequently, will remain out of sync with the FPGA

for the remainder of the configuration cycle.

Note: 1. For this condition, the reset polarity of the EEPROM must be set active High.

Figure 1. Condition 2 Connection

Notes: 1. Use of the READY pin is optional.

2. Reset polarity must be set to active Low.

Condition 2 The FPGA CON pin drives only the CE input of the AT17 Series Configurator, while the

OE input is driven by the FPGA INIT pin (Figure 1). This connection works under all nor-

mal circumstances, even when the user aborts a configuration before CON has gone

High. A Low level on the RESET/OE(1) input – during FPGA reset – clears the configura-

tor’s internal address pointer, so that the reconfiguration starts at the beginning.

Note: 1. For this condition, the reset polarity of the EEPROM must be set active Low.

The AT17 Series Configurator does not require an inverter for either condition since the

RESET polarity is programmable.

Cascading Serial

Configuration

EEPROMs

For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger

configuration memories, cascaded configurators provide additional memory.

As the last bit from the first Configurator is read, the clock signal to the configurator

asserts its CEO output Low and disables its DATA line driver. The second configurator

recognizes the Low level on its CE input and enables its DATA output.

After configuration is complete, the address counters of all cascaded configurators are

reset if the RESET/OE on each configurator is driven to its active (default High) level.

If the address counters are not to be reset upon completion, then the RESET/OE inputs

can be tied to its inactive (default Low) level. For more details on programming the

EEPROM’s reset polarity, please reference “Programming Specification for Atmel’s

FPGA Configuration EEPROMs”.

RESET

D<0>

CCLK

CON

INIT

RESET

AT40K

DATA

CLK

RESET/OE

SER_EN

READY

AT17C/LV040 VCC

GND

4AT17C/LV040

AT17 Series Reset

Polarity

The AT17 Series Configurator allows the user to program the reset polarity as either

RESET/OE or RESET/OE. This feature is supported by industry standard programmer

algorithms. For more details on programming the EEPROM’s reset polarity, please

reference the “Programming Specification for Atmel’s FPGA Configuration EEPROMs”

application note.

Programming Mode The programming mode is entered by bringing SER_EN Low. In this mode the chip can

be programmed by the 2-wire serial bus. The programming is done at VCC supply only.

Programming super voltages are generated inside the chip. See the “Programming

Specification for Atmel's FPGA Configuration EEPROMs” application note for further

information. The AT17C parts are read/write at 5V nominal. The AT17LV parts are

read/write at 3.3V nominal.

Standby Mode The AT17C/LV040 enters a low-power standby mode whenever CE is asserted High. In

this mode, the Configurator consumes less than 0.5 mA of current at 5.0 volts with

CMOS level inputs. The output remains in a high impedance state regardless of the

state of the OE input.

AT17C/LV040

Pin Configurations

TQFP

PLCC

Pin Name I/O Description

40 2 DATA I/O Three-state DATA output for configuration. Open-collector bi-directional pin for

programming.

43 5 CLK I Clock input. Used to increment the internal address and bit counter for reading and

programming.

12 18 WP1 I WRITE PROTECT (1). Used to protect portions of memory during programming.

Disables by default due to internal pull-down resistor. This input pin is not used during

FPGA loading operations. See the “Programming Specification for Atmel's FPGA

Configuration EEPROMs” application note for more details.

13 19 RESET/OE I RESET/Output Enable input (when SER_EN is High). A Low level on both the CE and

RESET/OE inputs enables the data output driver. A High level on RESET/OE resets

both the address and bit counters. The logic polarity of this input is programmable as

either RESET/OE or RESET/OE. This document describes the pin as RESET/OE.

14 20 WP2 I WRITE PROTECT (2). Used to protect portions of memory during programming.

Disables by default due to internal pull-down resistor. This input pin is not used during

FPGA loading operations. See the Programming Specification for Atmel's FPGA

Configuration EEPROMs” application note for more details.

15 21 CE I Chip Enable input. Used for device selection. A Low level on both CE and OE enables

the data output driver. A High level on CE disables both the address and bit counters

and forces the device into a low power standby mode. Note that this pin will not

enable/disable the device in the 2-wire Serial Programming Mode (i.e., when

SER_EN is Low).

18 &

3 & 24 GND Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended.

21 27

CEO O Chip Enable Output. This signal is asserted Low on the clock cycle following the last

bit read from the memory. It will stay Low as long as CE and OE are both Low. It will

then follow CE until OE goes High. Thereafter, CEO will stay High until the entire

EEPROM is read again.

A2 I Device selection input, A2. This is used to enable (or select) the device during

programming (i.e., when SER_EN is Low; see the “Programming Specification for

Atmel's FPGA Configuration EEPROMs” application note for more details).

22 28 READY O Open collector reset state indicator. Driven Low during power-up reset, released

when power-up is complete. (Recommend a 4.7 KΩ pull-up on this pin if used).

35 41 SER_EN I Serial enable must be held High during FPGA loading operations. Bringing SER_EN

Low enables the 2-wire Serial Programming Mode.

38 44 VCC +3.3V/+5V power supply pin.

6AT17C/LV040

Absolute Maximum Ratings*

Operating Temperature.................................. -55°C to +125°C*NOTICE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent dam-

age to the device. These are stress ratings only,

and functional operation of the device at these or

any other conditions beyond those listed under

Operating Conditions is not implied. Exposure to

Absolute Maximum Ratings conditions for

extended periods of time may affect device reli-

ability.

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin

with Respect to Ground .............................-0.1V to VCC + 0.5V

Supply Voltage (VCC) .........................................-0.5V to +7.0V

Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260°C

Operating Conditions

Symbol Description

AT17C040 AT17LV040

UnitsMin Max Min Max

VCC

Commercial Supply voltage relative to GND,

-0°C to +70°C

4.75 5.25 3.0 3.6 V

Industrial Supply voltage relative to GND,

-40°C to +85°C

4.5 5.5 3.0 3.6 V

Military Supply voltage relative to GND,

-55°C to +125°C

4.5 5.5 3.0 3.6 V

AT17C/LV040

DC Characteristics for AT17C040

VCC = 5V ± 5% Commercial, 5V ± 10% Industrial/Military

Symbol Description Min Max Units

VIH High-level Input Voltage 2.0 VCC V

VIL Low-level Input Voltage 0 0.8 V

VOH High-level Output Voltage (IOH = -4 mA) Commercial 3.86 V

VOL Low-level Output Voltage (IOL = +4 mA) 0.32 V

VOH High-level Output Voltage (IOH = -4 mA) Industrial 3.76 V

VOL Low-level Output Voltage (IOL = +4 mA) 0.37 V

VOH High-level Output Voltage (IOH = -4 mA) Military 3.7 V

VOL Low-level Output Voltage (IOL = +4 mA) 0.4 V

ICCA Supply Current, Active Mode 10 mA

ILInput or Output Leakage Current(VIN = VCC or GND) -10 10 µA

ICCS1 Supply Current, Standby Mode, CMOS Commercial 0.5 mA

Industrial/Military 0.5 mA

ICCS2 Supply Current, Standby Mode, TTL Comm./Industrial 1.0 mA

DC Characteristics for AT17LV040

VCC = 3.3V ± 10%

Symbol Description Min Max Units

VIH High-level Input Voltage 2.0 VCC V

VIL Low-level Input Voltage 0 0.8 V

VOH High-level Output Voltage (IOH = -2.5 mA) Commercial 2.4 V

VOL Low-level Output Voltage (IOL = +3 mA) 0.4 V

VOH High-level Output Voltage (IOH = -2 mA) Industrial 2.4 V

VOL Low-level Output Voltage (IOL = +3 mA) 0.4 V

VOH High-level Output Voltage (IOH = -2 mA) Military 2.4 V

VOL Low-level Output Voltage (IOL = +2.5 mA) 0.4 V

ICCA Supply Current, Active Mode 5 mA

ILInput or Output Leakage Current(VIN = VCC or GND) -10 10 µA

ICCS Supply Current, Standby Mode Commercial 100 µA

Industrial/Military 100 µA

8AT17C/LV040

AC Characteristics

AC Characteristics When Cascading

RESET/OE

CLK

DATA

TSCE

TLC THC

TCAC

TOE

TCE

TOH

THOE

TSCE THCE

TDF

TOH

RESET/OE

CLK

DATA

CEO

LAST BIT

TCDF

TOCK TOCE

TOCE

TOOE

FIRST BIT

AT17C/LV040

Notes: 1. Preliminary specifications for military operating range only.

2. AC test load = 50 pF.

3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.

Notes: 1. Preliminary specifications for military operating range only.

2. AC test load = 50 pF.

3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.

AC Characteristics for AT17C040

VCC = 5V ± 5% Commercial, VCC = 5V ± 10% Industrial/Military

Symbol Description

Commercial Industrial/Military(1)

UnitsMin Max Min Max

TOE(2) OE to Data Delay 30 35 ns

TCE(2) CE to Data Delay 45 45 ns

TCAC(2) CLK to Data Delay 50 50 ns

TOH Data Hold From CE, OE, or CLK 0 0 ns

TDF(3) CE or OE to Data Float Delay 50 50 ns

TLC CLK Low Time 20 20 ns

THC CLK High Time 20 20 ns

TSCE CE Setup Time to CLK (to guarantee proper counting) 20 25 ns

THCE CE Hold Time from CLK (to guarantee proper counting) 0 0 ns

THOE OE High Time (guarantees counter is reset) 20 20 ns

FMAX MAX Input Clock Frequency 15 15 MHz

AC Characteristics for AT17C040 When Cascading

VCC = 5V± 5% Commercial/VCC = 5V ± 10% Industrial/Military

Symbol Description

Commercial Industrial/Military(1)

UnitsMin Max Min Max

TCDF (3) CLK to Data Float Delay 50 50 ns

TOCK(2) CLK to CEO Delay 35 40 ns

TOCE(2) CE to CEO Delay 35 35 ns

TOOE(2) RESET/OE to CEO Delay 30 30 ns

FMAX MAX Input Clock Frequency 12.5 12.5 MHz

10 AT17C/LV040

Notes: 1. Preliminary specifications for military operating range only.

2. AC test load = 50 pF.

3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.

Notes: 1. Preliminary specifications for military operating range only.

2. AC test load = 50 pF.

3. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.

AC Characteristics for AT17LV040

VCC = 3.3V ± 10%

Symbol Description

Commercial Industrial/Military(1)

UnitsMin Max Min Max

TOE(2) OE to Data Delay 50 55 ns

TCE(2) CE to Data Delay 55 60 ns

TCAC(2) CLK to Data Delay 55 60 ns

TOH Data Hold From CE, OE, or CLK 0 0 ns

TDF(3) CE or OE to Data Float Delay 50 50 ns

TLC CLK Low Time 25 25 ns

THC CLK High Time 25 25 ns

TSCE CE Setup Time to CLK (to guarantee proper counting) 30 35 ns

THCE CE Hold Time from CLK (to guarantee proper counting) 0 0 ns

THOE OE High Time (guarantees counter is reset) 25 25 ns

FMAX MAX Input Clock Frequency 15 10 MHz

AC Characteristics for AT17LV040 When Cascading

VCC = 3.3V ± 10%

Symbol Description

Commercial Industrial/Military(1)

UnitsMin Max Min Max

TCDF(3) CLK to Data Float Delay 50 50 ns

TOCK(2) CLK to CEO Delay 50 55 ns

TOCE(2) CE to CEO Delay 35 40 ns

TOOE(2) RESET/OE to CEO Delay 35 35 ns

FMAX MAX Input Clock Frequency 12.5 10 MHz

AT17C/LV040

Ordering Information – 5V Devices

Memory Size Ordering Code Package Operation Range

4 M AT17C040-10TQC 44A Commercial

(0°C to 70°C)

AT17C040-10TQI 44A Industrial

(-40°C to 85°C)

AT17C040-10BJC 44J Commercial

(0°C to 70°C)

AT17C040-10BJI 44J Industrial

(-40°C to 85°C)

Ordering Information – 3.3V Devices

Memory Size Ordering Code Package Operation Range

4 M AT17LV040-10TQC 44A Commercial

(0°C to 70°C)

AT17LV040-10TQI 44A Industrial

(-40°C to 85°C)

AT17LV040-10BJC 44J Commercial

(0°C to 70°C)

AT17LV040-10BJI 44J Industrial

(-40°C to 85°C)

Package Type

44A 44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP)

44J 44-lead, Plastic J-leaded Chip Carrier (PLCC)

Packaging Information

AT17C/LV040

.045(1.14) X 45°PIN NO. 1

IDENTIFY

.045(1.14) X 30° - 45°.012(.305)

.008(.203)

.021(.533)

.013(.330)

.630(16.0)

.590(15.0)

.043(1.09)

.020(.508)

.120(3.05)

.090(2.29)

.180(4.57)

.165(4.19)

.500(12.7) REF SQ

.032(.813)

.026(.660)

.050(1.27) TYP

.022(.559) X 45° MAX (3X)

.656(16.7)

.650(16.5)

.695(17.7)

.685(17.4)SQ

*Controlling dimensions in millimeters

44A, 44-lead, Thin (1.0 mm) Plastic Quad Flat

Package (TQFP)

Dimensions in Millimeters and (Inches)*

JEDEC STANDARD MS-026 ACB

44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)

Dimensions in inches and (Millimeters)*

JEDEC STANDARD MS-018 AC

1.20(0.047) MAX

10.10(0.394)

9.90(0.386) SQ

12.21(0.478)

11.75(0.458) SQ

0.75(0.030)

0.45(0.018)

0.15(0.006)

0.05(0.002)

0.20(.008)

0.09(.003)

0.80(0.031) BSC

PIN 1 ID

0.45(0.018)

0.30(0.012)

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2282C–06/01/xM

FLEX is a registered trademark of Altera Corporation.

ORCA is a registered trademark of Lucent Technologies, Inc.

Spartan and Virtex are registered trademarks of Xilinx, Inc.

Terms and product names in this document may be trademarks of others.