LTC3554EUD-1#PBF - Linear Technology Corporation

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

TYPICAL APPLICATION

DESCRIPTION

Micropower USB Power

Manager with Li-Ion Charger

and Two Step-Down Regulators

The LTC

3554 family* are micropower, highly integrated

power management and battery charger ICs for single-cell

Li-Ion/Polymer battery applications. They include a

PowerPath™ manager with automatic load prioritization,

a battery charger, an ideal diode and numerous internal

protection features. Designed specifically for USB applica-

tions, the LTC3554 power managers automatically limit

input current to a maximum of either 100mA or 500mA.

Battery charge current is automatically reduced such that

the sum of the load current and the charge current does

not exceed the selected input current limit.

The LTC3554 also includes two synchronous step-down

switching regulators as well as a pushbutton controller.

With all supplies enabled in standby mode, the quiescent

current drawn from the battery is only 10μA. The LTC3554

family are available in a 3mm × 3mm × 0.75mm 20-lead

QFN package.

Battery Drain Current

vs Temperature

FEATURES

APPLICATIONS

n 10μA Standby Mode Quiescent Current (All Outputs On)

n Seamless Transition Between Input Power Sources:

Li-Ion/Polymer Battery and USB

n 240mΩ Internal Ideal Diode

n Dual High Efficiency Step-Down Switching Regulators

(200mA IOUT) with Adjustable Output Voltages

n Pushbutton On/Off Control with System Reset

n Reset Time: 5 sec (LTC3554/LTC3554-1),

14 sec (LTC3554-2/LTC3554-3)

n Full Featured Li-Ion/Polymer Battery Charger

n Programmable Charge Current with Thermal Limiting

n Instant-On Operation with Discharged Battery

n Battery Float Voltage: 4.2V (LTC3554/LTC3554-2/

LTC3554-3), 4.1V (LTC3554-1)

n 3mm × 3mm × 0.75mm 20-Lead QFN Package

n USB-Based Handheld Products

n Portable Li-Ion/Polymer Based Electronic Devices

n Fitness Computers

n Low Power Medical Devices

VBUS

NTC

PROG

HPWR

SUSP

PWR_ON1

FSEL

STBY

PGOOD

PWR_ON2

PBSTAT

VOUT

CHRG

BAT

BVIN

SW1

FB1

SW2

FB2

ON/OFF

Li-Ion

BATTERY

100k

100k T

1.87k

10pF 10µF

2.2µF

2.05M

649k

3.3V

200mA

4.7µH

10pF 10µF332k

649k

1.2V

200mA

3554 TA01a

10µH

SYSTEM

LOAD

4.35V TO 5.5V

USB INPUT

LTC3554

10µF10µF

TEMPERATURE (°C)

–75 –50 –25 25 50 75 100 1250

BATTERY DRAIN CURRENT (µA)

3554 TA01b

BOTH REGULATORS DISABLED

ONE REGULATOR ENABLED

HARD RESET

BOTH REGULATORS

ENABLED

VBAT = 3.8V

STBY = 3.8V

REGULATORS LOAD = 0mA

L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks

and PowerPath, Hot Swap and Bat-Track are trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Protected by U.S. Patents,

including 6522118, 6700364, 5481178, 6304066, 6570372, 6580258, 7511390.

*See table on page 2 for available options.

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

VBUS, VOUT, BVIN

t < 1ms and Duty Cycle < 1% ................... –0.3V to 7V

Steady State ............................................ –0.3V to 6V

BAT, NTC, CHRG, SUSP, PBSTAT,

ON, PGOOD, FB1, FB2 .................................. –0.3V to 6V

PWR_ON1, PWR_ON2, STBY

HPWR, FSEL (Note 4) ......................–0.3V to VCC + 0.3V

IBAT .............................................................................1A

ISW1, ISW2 (Continuous) ...................................... 300mA

ICHRG, IPGOOD, IPBSTAT ............................................75mA

Operating Junction Temperature Range ...–40°C to 85°C

Junction Temperature ............................................110°C

Storage Temperature Range .................. –65°C to 125°C

(Notes 1, 2, 3)

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3554EUD#PBF LTC3554EUD#TRPBF LDYS 20-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C

LTC3554EUD-1#PBF LTC3554EUD-1#TRPBF LGFG 20-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C

LTC3554EUD-2#PBF LTC3554EUD-2#TRPBF LFZX 20-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C

LTC3554EUD-3#PBF LTC3554EUD-3#TRPBF LGHK 20-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C

LTC3554EPD#PBF LTC3554EPD#TRPBF FDPT 20-Lead (3mm × 3mm) Plastic UTQFN –40°C to 85°C (OBSOLETE)

Consult LTC Marketing for parts specified with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

20 19 18 17 16

7 8

TOP VIEW

GND

UD PACKAGE

20-LEAD (3mm × 3mm) PLASTIC QFN

910

HPWR

FSEL

PBSTAT

PGOOD

NTC

CHRG

SW1

BVIN

SW2

VBUS

SUSP

VOUT

BAT

PROG

FB1

FB2

PWR_ON2

PWR_ON1

STBY

TJMAX = 110°C, θJA = 70°C/W

EXPOSED PAD (PIN 21) IS GND, AND MUST BE SOLDERED TO PCB GND

LTC3554 Options

PART NUMBER

FLOAT

VOLTAGE

HARD

RESET TIME SEQUENCING

LTC3554 4.2V 5 seconds Yes (Buck1 → Buck2)

LTC3554-1 4.1V 5 seconds Yes (Buck1 → Buck2)

LTC3554-2 4.2V 14 seconds Yes (Buck1 → Buck2)

LTC3554-3 4.2V 14 seconds No (Buck1 and Buck2

Together)

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

POWER MANAGER ELECTRICAL CHARACTERISTICS

The l denotes specifications that

apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VBUS = 5V, VBAT = 3.8V,

HPWR = SUSP = PWR_ON1 = PWR_ON2 = 0V, RPROG = 1.87k, STBY = High, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

No-Load Quiescent Currents

IBATQ Battery Drain Current IOUT = 0 (Note 5)

VBUS = 0V (Hard Reset)

VBUS = 0V

VBUS = 0V, PWR_ON1 = PWR_ON2 = 3.8V

0.2

6.5

µA

IBATQC Battery Drain Current, VBUS Available VBAT = VFLOAT, Timer Timed Out 5 8 µA

IBUSQ VBUS Input Current 100mA, 500mA Modes

SUSP = 5V (Suspend Mode)

300

500

µA

IBVINQ BVIN Input Current

Shutdown Input Current

One Buck Enabled, Standby Mode

Both Bucks Enabled, Standby Mode

One Buck Enabled

Both Bucks Enabled

VBVIN = 3.8V, VBUS = 0V (Note 8)

PWR_ON1 = STBY = 3.8V

PWR_ON1 = PWR_ON2 = STBY = 3.8V

PWR_ON1 = 3.8V, STBY = 0V

PWR_ON1 = PWR_ON2 = 3.8V, STBY = 0V

0.01

1.5

µA

Input Power Supply

VBUS Input Supply Voltage 4.35 5.5 V

IBUS(LIM) Total Input Current HPWR = 0V (100mA)

HPWR = 5V (500mA)

400

450

100

500

VUVLO VBUS Undervoltage Lockout Rising Threshold

Falling Threshold

3.5

3.8

3.6

3.9 V

VDUVLO VBUS to BAT Differential Undervoltage

Lockout

Rising Threshold

Falling Threshold

200

300 mV

RON_ILIM Input Current Limit Power FET

On-Resistance (Between VBUS and VOUT)

350 mΩ

Battery Charger

VFLOAT VBAT Regulated Output Voltage LTC3554/LTC3554-2/LTC3554-3

LTC3554/LTC3554-2/LTC3554-3, 0°C < TA < 85°C

LTC3554-1

LTC3554-1, 0°C < TA < 85°C

4.179

4.165

4.079

4.065

4.2

4.1

4.221

4.235

4.121

4.135

ICHG Constant-Current Mode Charge Current RPROG = 1.87k, 0 ≤ TA ≤ 85°C 380 400 420 mA

VPROG

VPROG,TRKL

PROG Pin Servo Voltage

PROG Pin Servo Voltage in Trickle Charge

VBAT < VTRKL

0.1

hPROG Ratio of IBAT to PROG Pin Current 750 mA/mA

ITRKL Trickle Charge Current VBAT < VTRKL 30 40 50 mA

VTRKL Trickle Charge Threshold Voltage VBAT Rising

VBAT Falling

2.6

2.9

2.75

3 V

ΔVRECHRG Recharge Battery Threshold Voltage Threshold Voltage Relative to VFLOAT –75 –100 –115 mV

tTERM Safety Timer Termination Period Timer Starts when VBAT = VFLOAT – 50mV 3.2 4 5 Hour

tBADBAT Bad Battery Termination Time VBAT < VTRKL 0.4 0.5 0.63 Hour

hC/10 End-of-Charge Indication Current Ratio (Note 6) 0.085 0.1 0.115 mA/mA

RON_CHG Battery Charger Power FET

On-Resistance (Between VOUT and BAT)

IBAT = 200mA 220 mΩ

TLIM Junction Temperature in Constant

Temperature Mode

110 °C

NTC

VCOLD Cold Temperature Fault Threshold Voltage Rising NTC Voltage

Hysteresis

75 76

1.3

77 %VBUS

%VBUS

VHOT Hot Temperature Fault Threshold Voltage Falling NTC Voltage

Hysteresis

34 35

1.3

36 %VBUS

%VBUS

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

POWER MANAGER ELECTRICAL CHARACTERISTICS

The l denotes specifications that

apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VBUS = 5V, VBAT = 3.8V,

HPWR = SUSP = PWR_ON1 = PWR_ON2 = 0V, RPROG = 1.87k, STBY = High, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VDIS NTC Disable Threshold Voltage Falling NTC Voltage

Hysteresis

l1.2 1.7

2.2 %VBUS

INTC NTC Leakage Current VNTC = VBUS = 5V –50 50 nA

Ideal Diode

VFWD Forward Voltage Detection (Note 12) 15 mV

RDROPOUT Diode On-Resistance, Dropout IOUT = 200mA, VBUS = 0V 240 mΩ

IMAX Diode Current Limit (Note 7) 1 A

Logic Inputs (HPWR, SUSP)

VIL Input Low Voltage 0.4 V

VIH Input High Voltage 1.2 V

RPD Internal Pull-Down Resistance 4 MΩ

Logic Output (CHRG)

VOL Output Low Voltage ICHRG = 5mA 65 250 mV

ICHRG Output Hi-Z Leakage Current VBAT = 4.5V, VCHRG = 5V 0 1 µA

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

BVIN Input Supply Voltage (Note 9) l2.7 5.5 V

VOUT UVLO VOUT Falling

VOUT Rising

BVIN Connected to VOUT Through Low

Impedance. VOUT UVLO Disables the Switching

Regulators.

2.5 2.6

2.8

2.9

fOSC Oscillator Frequency FSEL High

FSEL Low

1.91

0.955

2.25

1.125

2.59

1.295

MHz

IFB1

IFB2

FB1 Input Current (Note 8)

FB2 Input Current (Note 8)

–0.05

0.05

µA

RSW1_PD

RSW2_PD

SW1 Pull-Down in Shutdown

SW2 Pull-Down in Shutdown

PWR_ON1 = 0V

PWR_ON2 = 0V

kΩ

Logic Input Pins (FSEL, STBY)

Input High Voltage 1.2 V

Input Low Voltage 0.4 V

Input Current –1 1 µA

Switching Regulator 1 in Normal Operation (STBY Low)

ILIM1 Peak PMOS Current Limit PWR_ON1 = 3.8V (Note 7) 300 450 600 mA

VFB1 Regulated Feedback Voltage PWR_ON1 = 3.8V l780 800 820 mV

D1 Max Duty Cycle 100 %

RP1 RDS(ON) of PMOS ISW1 = 100mA 1.1 Ω

RN1 RDS(ON) of NMOS ISW1 = –100mA 0.7 Ω

Switching Regulator 1 in Standby Mode (STBY High)

VFB1_LOW Feedback Voltage Threshold PWR_ON1 = 3.8V, VFB1 Falling l770 800 820 mV

ISHORT1_SB Short-Circuit Current 10 21 50 mA

VDROP1_SB Standby Mode Dropout Voltage PWR_ON1 = 2.9V, ISW1 = 5mA, VFB1 = 0.77V,

VOUT = 2.9V, BVIN = 2.9V

25 60 mV

SWITCHING REGULATOR ELECTRICAL CHARACTERISTICS

The l denotes

specifications that apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2).

VOUT = BVIN = 3.8V, PWR_ON1 = PWR_ON2 = 0V, unless otherwise noted.

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

SWITCHING REGULATOR ELECTRICAL CHARACTERISTICS

PUSHBUTTON INTERFACE ELECTRICAL CHARACTERISTICS

The l denotes

specifications that apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2).

VOUT = BVIN = 3.8V, PWR_ON1 = PWR_ON2 = 0V, unless otherwise noted.

The l denotes

specifications that apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2).

VBAT = 3.8V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Switching Regulator 2 in Normal Operation (STBY Low)

ILIM2 Peak PMOS Current Limit PWR_ON2 = 3.8V (Note 7) 300 450 600 mA

VFB2 Regulated Feedback Voltage PWR_ON2 = 3.8V l780 800 820 mV

D2 Max Duty Cycle 100 %

RP2 RDS(ON) of PMOS ISW2 = 100mA 1.1 Ω

RN2 RDS(ON) of NMOS ISW2 = –100mA 0.7 Ω

Switching Regulator 2 in Standby Mode (STBY High)

VFB2_LOW Feedback Voltage Threshold PWR_ON2 = 3.8V, VFB2 Falling l770 800 820 mV

ISHORT2_SB Short-Circuit Current 10 21 50 mA

VDROP2_SB Standby Mode Dropout Voltage PWR_ON2 = 2.9V, ISW2 = 5mA, VFB2 = 0.77V, VOUT

= 2.9V, BVIN = 2.9V

25 60 mV

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Pushbutton Pin (ON)

VCC_PB Pushbutton Operating Supply Range (Notes 4 , 9) l2.7 5.5 V

VON_TH ON Threshold Rising

ON Threshold Falling

0.4

1.2 V

ION ON Input Current VON = VCC (Note 4) –1 1 µA

RPB_PU Pushbutton Pull-Up Resistance Pull-Up to VCC (Note 4) 200 400 650 kΩ

Logic Input Pins (PWR_ON1, PWR_ON2)

VPWR_ONx PWR_ONx Threshold Rising

PWR_ONx Threshold Falling

0.4

1.2 V

IPWR_ONx PWR_ONx Input Current –1 1 µA

Status Output Pins (PBSTAT, PGOOD)

IPBSTAT PBSTAT Output High Leakage Current VPBSTAT = 3V –1 1 µA

VPBSTAT PBSTAT Output Low Voltage IPBSTAT = 3mA 0.1 0.4 V

IPGOOD PGOOD Output High Leakage Current VPGOOD = 3V –1 1 µA

VPGOOD PGOOD Output Low Voltage IPGOOD = 3mA 0.1 0.4 V

VTHPGOOD PGOOD Threshold Voltage (Note 10) –8 %

Pushbutton Timing Parameters (Note 11)

tON_PBSTATL Minimum ON Low Time to Cause PBSTAT

Low

ON Brought Low During Power-On (PON) or

Power-Up (PUP1, PUP2) States

50 ms

tON_

PBSTATH

Delay from ON High to PBSTAT High Power-On (PON) State, After PBSTAT Has Been

Low for at Least tPBSTAT_PW

900 µs

tON_PUP Minimum ON Low Time to Enter

Power-Up (PUP1 or PUP2) State

Starting in the Hard Reset (HR) or Power-Off

(POFF) States

400 ms

tON_HR Minimum ON Low Time to Hard Reset ON Brought Low During the Power-On (PON)or

Power-Up (PUP1, PUP2) States

LTC3554/LTC3554-1

LTC3554-2/LTC3554-3

tPBSTAT_PW PBSTAT Minimum Pulse Width Power-On (PON) or Power-Up (PUP1, PUP2)

States

40 50 ms

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

Note 1. Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC3554 is tested under pulsed load conditions such that

TJ ≈ TA. The LTC3554 are guaranteed to meet specifications from

0°C to 85°C junction temperature. Specifications over the –40°C to

85°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. Note that

the maximum ambient temperature consistent with these specifications

is determined by specific operating conditions in conjunction with board

layout, the rated package thermal impedance and other environmental

factors.

The junction temperature (TJ, in °C) is calculated from the ambient

temperature (TA, in °C) and power dissipation (PD, in Watts) according to

the formula:

TJ = TA + (PD • θJA)

where θJA (in °C/W) is the package thermal impedance.

Note 3. This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperatures will exceed 110°C when overtemperature protection is

active. Continuous operation above the specified maximum operating

junction temperature may result in device degradation or failure.

Note 4. VCC is the greater of VBUS or BAT.

Note 5. Total Battery Drain Current is the sum of IBATQ and IOUT. For

example, in applications where the buck input (BVIN pin) is connected to

the PowerPath output (VOUT pin) such that IOUT = IBVIN, total battery drain

current = IBATQ + IBVIN.

Note 6. hC/10 is expressed as a fraction of programmed full charge

current with specified PROG resistor.

Note 7. The current limit features of this part are intended to protect the

IC from short term or intermittent fault conditions. Continuous operation

above the absolute maximum specified pin current rating may result in

device degradation or failure.

Note 8. FB High, Not Switching

Note 9. VOUT not in UVLO.

Note 10. PGOOD threshold is expressed as a percentage difference from

the buck regulation voltage. The threshold is measured with the buck

feedback pin voltage rising.

Note 11. See the Operation section of this data sheet for detailed

explanation of the pushbutton state machine and the effects of each state

on switching regulator and power manager operation.

Note 12. If VBUS < VUVLO then VFWD = 0 and the forward voltage across

the ideal diode is equal to its current times RDROPOUT.

PUSHBUTTON INTERFACE ELECTRICAL CHARACTERISTICS

The l denotes

specifications that apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2).

VBAT = 3.8V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

tEXTPWR Power-Up from USB Present to Power-Up

(PUP1 or PUP2) State

Starting in the Hard Reset (HR) or Power-Off

(POFF) States

100 ms

tPON_UP Any PWR_ONx High to Power-On State Starting with Both PWR_ONx Low in the Power-

Off (POFF) State

900 µs

tPON_DIS PWR_ONx Low to Buckx Disabled 1 µs

tPUP Power-Up (PUP1 or PUP2) State Duration 5 s

tPDN Power-Down (PDN1 or PDN2) State

Duration

1 s

tPGOODH Bucks in Regulation to PGOOD High All Enabled Bucks within PGOOD Threshold

Voltage

230 ms

tPGOODL Bucks Disabled to PGOOD Low All Bucks Disabled 100 µs

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

VBUS Supply Current

vs Temperature

VBUS Supply Current

vs Temperature (Suspend Mode)

Battery Drain Current

vs Temperature

VBUS Current Limit

vs Temperature

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, unless otherwise specified.

TEMPERATURE (°C)

–75

200

IBUS (µA)

300

350

400

–25 25 50 150

3554 G01

250

–50 0 75 100 125

VBUS = 5V

HPWR = L

TEMPERATURE (°C)

–75

IBUS (µA)

–25 25 50 150

3554 G02

–50 0 75 100 125

VBUS = 5V

TEMPERATURE (°C)

–75 –50 –25 25 50 75 100 1250

BATTERY DRAIN CURRENT (µA)

3554 G03

BOTH REGULATORS DISABLED

ONE REGULATOR ENABLED

HARD RESET

BOTH REGULATORS

ENABLED

VBAT = 3.8V

STBY = 3.8V

REGULATORS LOAD = 0mA

TEMPERATURE (°C)

–75

IBAT (µA)

–25 25 50 150

3554 G03b

–50 0 75 100 125

VBUS = 5V

VBAT = 3.8V

TEMPERATURE (°C)

–75

IVBUS (mA)

200

300

500

400

–25 25 50

3554 G04

100

–50 0 75 100 125

VBUS = 5V

HPWR = H

HPWR = L

Battery Drain Current

vs Temperature (Suspend Mode)

LOAD CURRENT (mA)

0 100 300 500400200

–100

CURRENT (mA)

100

200

400

600

500

300

3554 G05

RPROG = 1.87k

IVBUS

ILOAD

IBAT

(CHARGING)

IBAT

(DISCHARGING)

VBUS and Battery Current

vs Load Current

Battery Charge Current and

Voltage vs Time

(LTC3554/LTC3554-2/LTC3554-3)

RON from VBUS to VOUT

vs Temperature

Charge Current vs Temperature

(Thermal Regulation)

TEMPERATURE (°C)

–75 –50 –25 25 50 75 100 1501250

0.20

RON (Ω)

0.30

0.35

0.45

0.50

0.40

3554 G05a

0.25

IOUT = 200mA

TEMPERATURE (°C)

–75

IBAT (mA)

160

240

480

400

320

–25 25 50 150

3554 G06

–50 0 75 100 125

VBUS = 5V

HPWR = H

RPROG = 1.87k

TIME (hour)

BATTERY CURRENT (mA)

VOLTAGE (V)

200

300

600

500

400

245

3554 G07

100

1 3 678

920mAhr CELL

VBUS = 5V

RPROG = 1.87k

CHRG

VBAT

SAFETY TIMER

TERMINATION

C/10

IBAT

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, unless otherwise specified.

Forward Voltage

vs Ideal Diode Current VBUS Connect Waveform VBUS Disconnect Waveform

IBAT (mA)

0 400200

VFWD (mV)

100

150

250

300

200

1000 1200

3554 G11

800600

VBUS = 5V

VBUS = 0V

VBAT = 3.75V

IOUT = 100mA

RPROG = 2k

1ms/DIV

VBUS

VOUT

IBUS

0.5A/DIV

IBAT

0.5A/DIV

3554 G12

VBAT = 3.75V

IOUT = 100mA

RPROG = 2k

3554 G13

50µs/DIV

VBUS

VOUT

IBUS

0.5A/DIV

IBAT

0.5A/DIV

Oscillator Frequency

vs Temperature

Switching from Suspend Mode to

500mA Mode

VBAT = 3.75V

IOUT = 50mA

RPROG = 2k

3554 G15

1ms/DIV

SUSP

VOUT

IBUS

0.5A/DIV

IBAT

0.5A/DIV

Switching from 100mA Mode to

500mA Mode

VBAT = 3.75V

IOUT = 50mA

RPROG = 2k

3554 G14

1ms/DIV

HPWR 0

IBUS

0.5A/DIV

IBAT

0.5A/DIV

TEMPERATURE (°C)

–75 –50 –25 25 50 75 100 1501250

1.9

OSCILLATOR FREQUENCY (MHz)

2.1

2.2

2.4

2.6

2.5

2.3

3554 G16

2.0

2.7V

3.8V

5.5V

IBAT vs VB AT

(LTC3554/LTC3554-2/LTC3554-3)VFLOAT Load Regulation

Battery Regulation (Float)

Voltage vs Temperature

VBAT (V)

2 2.4 3.6 43.22.8

IBAT (mA)

200

300

500

400

3554 G10

100

4.4

VBUS = 5V

HPWR = H

RPROG = 1.87k

IBAT (mA)

0 50

4.08

FLOAT

(V)

4.12

4.14

4.22

4.20

4.18

4.16

200150 250 350 450

400

3554 G08

4.10

100 300

VBUS = 5V

HPWR = H

LTC3554/LTC3554-2/LTC3554-3

LTC3554-1

TEMPERATURE (°C)

–75 –25–50

4.08

VFLOAT (V)

4.16

4.18

4.22

4.20

50 100 125

3554 G09

4.14

4.12

4.10

250 75

VBUS = 5V

IBAT = 2mA

LTC3554/LTC3554-2/LTC3554-3

LTC3554-1

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

TYPICAL PERFORMANCE CHARACTERISTICS

Burst Mode

BVIN Supply Current

Per Enabled Step-Down Switching

Regulator

Standby Mode BVIN Supply

Current Per Enabled Step-Down

Switching Regulator

Step-Down Switching Regulator 1

3.3V Output Efficiency vs IOUT1

Step-Down Switching Regulator 2

1.8V Output Efficiency vs IOUT2

TA = 25°C, unless otherwise specified.

Step-Down Switching Regulator 1

2.5V Output Efficiency vs IOUT1

Step-Down Switching Regulator 2

1.2V Output Efficiency vs IOUT2

IOUT1 (mA)

0.01 0.1

EFFICIENCY (%)

100

1 10 100 1000

3554 G24a

FSEL = L

STBY = L

3.8V

IOUT2 (mA)

0.01 0.1

EFFICIENCY (%)

100

1 10 100 1000

3554 G25

FSEL = L

STBY = L

3.8V

BVIN SUPPLY VOLTAGE (V)

2.5 3 4 4.5 5.553.5

BVIN SUPPLY CURRENT (µA)

3554 G17

NO LOAD

STBY = L

–45°C

25°C

90°C

BVIN SUPPLY VOLTAGE (V)

2.5 3 4 4.5 5.553.5

BVIN SUPPLY CURRENT (µA)

1.0

1.5

2.5

3.0

2.0

3554 G18

0.5

NO LOAD

STBY = H

–45°C

25°C

90°C

IOUT1 (mA)

EFFICIENCY (%)

3554 G31

0.01 0.1 100 1000101

100

FSEL = L

STBY = L

3.8V

IOUT2 (mA)

EFFICIENCY (%)

3554 G32

0.01 0.1 100 1000101

100

FSEL = L

STBY = L

3.8V

Step-Down Switching Regulator

Output Transient

Step-Down Switching Regulator

Short-Circuit Current

vs Temperature

TEMPERATURE (°C)

–75 –50 –25 25 50 75 100 1501250

400

SHORT CIRCUIT CURRENT (mA)

440

460

500

480

3554 G19

420

STBY = L

VOUT2 = 1.2V

STBY = H

VOUT2

20mV/DIV

(AC)

5mA

10µA

IOUT2

3554 G26

50µs/DIV

Step-Down Switching Regulator

Output Transient

VOUT1 = 3.3V

STBY = L

VOUT1

100mV/DIV

(AC)

150mA

5mA

IOUT1

3554 G27

200µs/DIV

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, unless otherwise specified.

Step-Down Switching Regulator

Start-Up Waveform

VOUT2 = 1.2V

IOUT2 = 50mA

ROUT1 = 22Ω

STBY = L

VOUT2

50mV/DIV

(AC)

VOUT1

1V/DIV

IL1

100mA/DIV

PWR_ON1

0mA

3554 G28

100µs/DIV

Step-Down Switching

Regulator Output Transient (STBY

High to Low)

Step-Down Switching

Regulator Output Transient

(FSEL Low to High)

VOUT1 = 3.3V

IOUT1 = 100mA

VOUT2 = 1.2V

IOUT2 = 50mA

STBY = L

VOUT2

20mV/DIV

(AC)

VOUT1

50mV/DIV

(AC)

FSEL

3554 G29

50µs/DIV

VOUT1 = 3.3V

IOUT1 = 5mA

VOUT2 = 1.2V

IOUT2 = 5mA

VOUT2

20mV/DIV

(AC)

VOUT1

20mV/DIV

(AC)

STBY

3554 G30

50µs/DIV

Step-Down Switching Regulator

Dropout Voltage in Standby Mode

vs Load Current

LOAD CURRENT (mA)

0 2 6 14121084

DROPOUT VOLTAGE (mV)

100

200

160

180

140

120

3554 G23

VBVIN = 2.9V

VFBx = 780mV

STBY = H

–45°C

25°C

90°C

Step-Down Switching

Regulator Switch Impedance

vs Temperature

TEMPERATURE (°C)

–75 –50 –25 25 50 75 100 1501250

SWITCH IMPEDANCE (Ω)

0.4

0.6

1.6

0.8

1.0

1.2

1.4

3554 G20

0.2

PMOS

NMOS

BVIN = 3.2V

STBY = L

Step-Down Switching

Regulator Feedback Voltage

vs Output Current

OUTPUT CURRENT (mA)

FEEDBACK VOLTAGE (V)

3554 G21

0.1 1 100 100010

0.780

0.790

0.795

0.820

0.800

0.805

0.810

0.815

0.785

3.8V

STBY = L

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

HPWR (Pin 1): High Power Logic Input. When this pin is

low the input current limit is set to 100mA and when this

pin is driven high it is set to 500mA. The SUSP pin needs

to be low for the input current limit circuit to be enabled.

This pin has a conditional internal pull-down resistor when

power is applied to the VBUS pin.

FSEL (Pin 2): Buck Frequency Select. When this pin is

low the buck switching frequency is set to 1.125MHz and

when this pin is driven high it is set to 2.25MHz.

PBSTAT (Pin 3): Pushbutton Status. This open-drain output

is a debounced and buffered version of the ON pushbut-

ton input. It may be used to interrupt a microprocessor.

PGOOD (Pin 4): Power Good. This open-drain output

indicates that all enabled buck regulators have been in

regulation for at least 230ms.

ON (Pin 5): Pushbutton Input. Weak internal pull-up

forces a high state if ON is left floating. A normally open

pushbutton is connected from ON to ground to force a

low state on this pin.

FB1 (Pin 6): Feedback Input for Step-Down Switching

Regulator 1. This pin servos to a fixed voltage of 0.8V

when the control loop is complete.

FB2 (Pin 7): Feedback Input for Step-Down Switching

Regulator 2. This pin servos to a fixed voltage of 0.8V

when the control loop is complete.

PWR_ON2 (Pin 8): Logic Input Enables Step-Down Switch-

ing Regulator 2.

PWR_ON1 (Pin 9): Logic Input Enables Step-Down Switch-

ing Regulator 1.

STBY (Pin 10): Standby Mode. When this pin is driven

high the part enters a very low quiescent current mode.

The buck regulators are each limited to 5mA maximum

load current in this mode.

SW2 (Pin 11): Power Transmission (Switch) Pin for Step-

Down Switching Regulator 2.

BVIN (Pin 12): Power Input for Step-Down Switching

Regulators 1 and 2. It is recommended that this pin be

connected to the VOUT pin. It should be bypassed with a

low impedance multilayer ceramic capacitor.

SW1 (Pin 13): Power Transmission (Switch) Pin for Step-

Down Switching Regulator 1.

CHRG (Pin 14): Open-Drain Charge Status Output. This pin

indicates the status of the battery charger. It is internally

pulled low while charging. Once the battery charge cur-

rent reduces to less than one-tenth of the programmed

charge current, this pin goes into a high impedance state.

An external pull-up resistor and/or LED is required to

provide indication.

NTC (Pin 15): The NTC pin connects to a battery’s therm-

istor to determine if the battery is too hot or too cold to

charge. If the battery’s temperature is out of range, charging

is paused until it drops back into range. A low drift bias

resistor is required from VBUS to NTC and a thermistor is

required from NTC to ground. If the NTC function is not

desired, the NTC pin should be grounded.

PROG (Pin 16): Charge Current Program and Charge

Current Monitor Pin. Connecting a resistor from PROG to

ground programs the charge current as given by:

ICHG (A)=750V

RPROG

If sufficient input power is available in constant-current

mode, this pin servos to 1V. The voltage on this pin always

represents the actual charge current.

BAT (Pin 17): Single-Cell Li-Ion Battery Pin. Depending

on available power and load, a Li-Ion battery on BAT will

either deliver system power to VOUT through the ideal

diode or be charged from the battery charger.

VOUT (Pin 18): Output Voltage of the PowerPath Control-

ler and Input Voltage of the Battery Charger. The majority

of the portable products should be powered from VOUT.

PIN FUNCTIONS

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

PIN FUNCTIONS

The LTC3554 will partition the available power between

the external load on VOUT and the internal battery charger.

Priority is given to the external load and any extra power

is used to charge the battery. An ideal diode from BAT to

VOUT ensures that VOUT is powered even if the load exceeds

the allotted input current from VBUS or if the VBUS power

source is removed. VOUT should be bypassed with a low

impedance multilayer ceramic capacitor.

SUSP (Pin 19): Suspend Mode Logic Input. If this pin

is driven high the input current limit path is disabled.

In this state the circuit draws negligible power from the

VBUS pin. Any load at the VOUT pin is provided by the

battery through the internal ideal diode. When this input

is grounded, the input current limit will be set to desired

value as determined by the state of the HPWR pin. This

pin has a conditional internal pull-down resistor when

power is applied to the VBUS pin.

VBUS (Pin 20): USB Input Voltage. VBUS will usually be

connected to the USB port of a computer or a DC output

wall adapter. VBUS should be bypassed with a low imped-

ance multilayer ceramic capacitor.

GND (Exposed Pad Pin 21): Ground. The exposed pack-

age pad is ground and must be soldered to the PC board

for proper functionality and for maximum heat transfer.

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

BLOCK DIAGRAM

0.8V

OSC

200mA STEP-DOWN DC/DC

STBY

INPUT

CURRENT

LIMIT

CC/CV

CHARGER

BATTERY

TEMP

MONITOR

POWER GOOD

COMPARATORS

PUSH BUTTON

INTERFACE

2.25MHz/

1.125MHz

OSCILLATOR

CHARGE

STATUS

0.8V

OSC

VBUS VOUT

BAT

PROG

SW1

FB1

BVIN

SW2

FB2

PGOOD

HPWR

SUSP

NTC

FSEL

EXTPWR UVLO

STBY

GND

3554 BD1

PWR_ON1

PWR_ON2

PBSTAT

CHRG

200mA STEP-DOWN DC/DC

STBY

20 18

4096

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

Introduction

The LTC3554 is a highly integrated power management

IC that includes the following features:

PowerPath controller

Battery charger

Ideal diode

Pushbutton controller

Two step-down switching regulators

Designed specifically for USB applications, the PowerPath

controller incorporates a precision input current limit

which communicates with the battery charger to ensure

that input current never violates the USB specifications.

The ideal diode from BAT to VOUT guarantees that ample

power is always available to VOUT even if there is insufficient

or absent power at VBUS. The LTC3554 also includes a

pushbutton input to control the two synchronous step-

down switching regulators and system reset. The two

constant-frequency current mode step-down switching

regulators provide 200mA each and support 100% duty

cycle operation as well as operating in Burst Mode operation

for high efficiency at light load. No external compensation

components are required for the switching regulators.

Either regulator can be programmed for a minimum out-

put voltage of 0.8V and can be used to power a micro-

controller core, microcontroller I/O, memory or other

logic circuitry. The buck regulators can be operated at

1.125MHz or 2.25MHz. They also include a low power

standby mode which can be used to power essential

keep-alive circuitry while draining ultralow current from

the battery for extended battery life.

USB PowerPath Controller

The input current limit and charger control circuits of

the LTC3554 are designed to limit input current as well

as control battery charge current as a function of IVOUT.

VOUT drives the combination of the external load, the two

step-down switching regulators and the battery charger.

If the combined load does not exceed the programmed

input current limit, VOUT will be connected to VBUS through

an internal 350mΩ P-channel MOSFET. If the combined

load at VOUT exceeds the programmed input current limit,

the battery charger will reduce its charge current by the

amount necessary to enable the external load to be satisfied

while maintaining the programmed input current. Even if

the battery charge current is set to exceed the allowable

USB current, the average input current USB specification

will not be violated. Furthermore, load current at VOUT will

always be prioritized and only excess available current will

be used to charge the battery.

The input current limit is programmed by the HPWR and

SUSP pins. If SUSP pin set high, the input current limit

is disabled. If SUSP pin is low, the input current limit is

enabled. HPWR pin selects between 100mA input current

limit when it is low and 500mA input current limit when

it is high.

OPERATION

Simplified PowerPath Block Diagram

100mA/500mA

INPUT CURRENT

LIMIT

CC/CV

CHARGER 15mV

IDEAL

3554 F01

–

VOUT

VBUS 20

BAT

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

Ideal Diode From BAT to VOUT

The LTC3554 has an internal ideal diode from BAT to VOUT

designed to respond quickly whenever VOUT drops below

BAT. If the load increases beyond the input current limit,

additional current will be pulled from the battery via the ideal

diode. Furthermore, if power to VBUS (USB) is removed,

then all of the application power will be provided by the

battery via the ideal diode. The ideal diode is fast enough

to keep VOUT from dropping significantly with just the

recommended output capacitor. The ideal diode consists

of a precision amplifier that enables an on-chip P-channel

MOSFET whenever the voltage at VOUT is approximately

15mV (VFWD) below the voltage at BAT. The resistance of

the internal ideal diode is approximately 240mΩ.

Suspend Mode

When the SUSP pin is pulled high the LTC3554 enters

suspend mode to comply with the USB specification. In

this mode, the power path between VBUS and VOUT is put

in a high impedance state to reduce the VBUS input current

to 15μA. The system load connected to VOUT is supplied

through the ideal diode connected to BAT.

VBUS Undervoltage Lockout (UVLO) and Undervoltage

Current Limit (UVCL)

An internal undervoltage lockout circuit monitors VBUS

and keeps the input current limit circuitry off until VBUS

rises above the rising UVLO threshold (3.8V) and at least

200mV above VBAT. Hysteresis on the UVLO turns off the

input current limit circuitry if VBUS drops below 3.6V or

within 50mV of VBAT. When this happens, system power at

VOUT will be drawn from the battery via the ideal diode. To

minimize the possibility of oscillation in and out of UVLO

when using resistive input supplies, the input current limit

is reduced as VBUS falls below 4.45V typical.

Battery Charger

The LTC3554 includes a constant-current/constant-volt-

age battery charger with automatic recharge, automatic

termination by safety timer, low voltage trickle charging,

bad cell detection and thermistor sensor input for out of

temperature charge pausing. When a battery charge cycle

begins, the battery charger first determines if the battery

is deeply discharged. If the battery voltage is below VTRKL,

typically 2.9V, an automatic trickle charge feature sets the

battery charge current to 10% of the programmed value. If

the low voltage persists for more than 1/2 hour, the battery

charger automatically terminates. Once the battery voltage

is above 2.9V, the battery charger begins charging in full

power constant current mode. The current delivered to

the battery will try to reach 750V/RPROG. Depending on

available input power and external load conditions, the

battery charger may or may not be able to charge at the

full programmed current. The external load will always be

prioritized over the battery charge current. The USB cur-

rent limit programming will always be observed and only

additional current will be available to charge the battery.

When system loads are light, battery charge current will

be maximized.

Charge Termination

The battery charger has a built-in safety timer. When the

battery voltage approaches the float voltage (4.2V for

LTC3554/LTC3554-2/LTC3554-3 or 4.1V for LTC3554-1),

the charge current begins to decrease as the LTC3554

enters constant-voltage mode. Once the battery charger

detects that it has entered constant-voltage mode, the four

hour safety timer is started. After the safety timer expires,

charging of the battery will terminate and no more current

will be delivered to the battery.

OPERATION

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

Automatic Recharge

After the battery charger terminates, it will remain off

drawing only microamperes of current from the battery.

If the portable product remains in this state long enough,

the battery will eventually self discharge. To ensure that the

battery is always topped off, a charge cycle will automati-

cally begin when the battery voltage falls below VRECHRG

(typically 4.1V for LTC3554/LTC3554-2/LTC3554-3 or 4V

for LTC3554-1). In the event that the safety timer is running

when the battery voltage falls below VRECHRG, the timer

will reset back to zero. To prevent brief excursions below

VRECHRG from resetting the safety timer, the battery volt-

age must be below VRECHRG for approximately 2ms. The

charge cycle and safety timer will also restart if the VBUS

UVLO cycles low and then high (e.g., VBUS, is removed

and then replaced).

Charge Current

The charge current is programmed using a single resistor

from PROG to ground. 1/750th of the battery charge cur-

rent is delivered to PROG which will attempt to servo to

1.000V. Thus, the battery charge current will try to reach

750 times the current in the PROG pin. The program

resistor and the charge current are calculated using the

following equations:

RPROG =750V

ICHG

,ICHG =750V

RPROG

In either the constant-current or constant-voltage charg-

ing modes, the PROG pin voltage will be proportional to

the actual charge current delivered to the battery. There-

fore, the actual charge current can be determined at any

time by monitoring the PROG pin voltage and using the

following equation:

IBAT =VPROG

RPROG

•750

In many cases, the actual battery charge current, IBAT, will

be lower than ICHG due to limited input current available

and prioritization with the system load drawn from VOUT.

Thermal Regulation

To prevent thermal damage to the IC or surrounding

components, an internal thermal feedback loop will

automatically decrease the programmed charge current

if the die temperature rises to approximately 110°C.

Thermal regulation protects the LTC3554 from excessive

temperature due to high power operation or high ambient

thermal conditions and allows the user to push the limits

of the power handling capability with a given circuit board

design without risk of damaging the LTC3554 or external

components. The benefit of the LTC3554 thermal regula-

tion loop is that charge current can be set according to the

desired charge rate rather than worst-case conditions with

the assurance that the battery charger will automatically

reduce the current in worst-case conditions.

Charge Status Indication

The CHRG pin indicates the status of the battery charger. An

open-drain output, the CHRG pin can drive an indicator LED

through a current limiting resistor for human interfacing or

simply a pull-up resistor for microprocessor interfacing.

When charging begins, CHRG is pulled low and remains

low for the duration of a normal charge cycle. When charg-

ing is complete, i.e., the charger enters constant-voltage

mode and the charge current has dropped to one-tenth

of the programmed value, the CHRG pin is released (high

impedance). The CHRG pin does not respond to the C/10

threshold if the LTC3554 reduces the charge current due

to excess load on the VOUT pin. This prevents false end

of charge indications due to insufficient power available

to the battery charger. Even though charging is stopped

during an NTC fault the CHRG pin will stay low indicating

that charging is not complete.

OPERATION

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

Battery Charger Stability Considerations

The LTC3554’s battery charger contains both a constant-

voltage and a constant-current control loop. The constant-

voltage loop is stable without any compensation when a

battery is connected with low impedance leads. Excessive

lead length, however, may add enough series inductance

to require a bypass capacitor of at least 1μF from BAT to

GND. Furthermore, a 100μF 1210 ceramic capacitor in

series with a 0.3Ω resistor from BAT to GND is required

to keep ripple voltage low if operation with the battery

disconnected is allowed.

High value, low ESR multilayer ceramic chip capacitors

reduce the constant-voltage loop phase margin, possibly

resulting in instability. Ceramic capacitors up to 22μF

may be used in parallel with a battery, but larger ceramics

should be decoupled with 0.2Ω to 1Ω of series resistance.

In constant-current mode, the PROG pin is in the feed-

back loop rather than the battery voltage. Because of the

additional pole created by any PROG pin capacitance,

capacitance on this pin must be kept to a minimum. With

no additional capacitance on the PROG pin, the battery

charger is stable with program resistor values as high

as 25k. However, additional capacitance on this node

reduces the maximum allowed program resistor. The pole

frequency at the PROG pin should be kept above 100kHz.

Therefore, if the PROG pin has a parasitic capacitance,

CPROG, the following equation should be used to calculate

the maximum resistance value for RPROG:

RPROG ≤1

2π•100kHz •CPROG

NTC Thermistor

The battery temperature is measured by placing a nega-

tive temperature coefficient (NTC) thermistor close to the

battery pack. To use this feature connect the NTC therm-

istor, RNTC, between the NTC pin and ground and a bias

resistor, RNOM, from VBUS to NTC, as shown in Figure 1.

RNOM should be a 1% resistor with a value equal to the

value of the chosen NTC thermistor at 25°C (R25). The

LTC3554 will pause charging when the resistance of the

NTC thermistor drops to 0.54 times the value of R25

or approximately 54k (for a Vishay curve 1 thermistor,

this corresponds to approximately 40°C). If the battery

charger is in constant-voltage mode, the safety timer also

pauses until the thermistor indicates a return to a valid

temperature. As the temperature drops, the resistance of

the NTC thermistor rises. The LTC3554 is also designed

to pause charging when the value of the NTC thermistor

increases to 3.17 times the value of R25. For a Vishay

curve 1 thermistor this resistance, 317k, corresponds to

approximately 0°C. The hot and cold comparators each

have approximately 3°C of hysteresis to prevent oscillation

about the trip point.

Alternate NTC Thermistors and Biasing

The LTC3554 provides temperature qualified charging if

a grounded thermistor and a bias resistor are connected

to NTC. By using a bias resistor whose value is equal to

the room temperature resistance of the thermistor (R25)

the upper and lower temperatures are preprogrammed

to approximately 40°C and 0°C, respectively (assuming

a Vishay curve 1 thermistor).

The upper and lower temperature thresholds can be

adjusted by either a modification of the bias resistor value

or by adding a second adjustment resistor to the circuit.

If only the bias resistor is adjusted, then either the upper

or the lower threshold can be modified but not both. The

other trip point will be determined by the characteristics

of the thermistor. Using the bias resistor in addition to an

adjustment resistor, both the upper and the lower tem-

perature trip points can be independently programmed

with the constraint that the difference between the upper

and lower temperature thresholds cannot decrease.

Examples of each technique are given below.

OPERATION

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

NTC thermistors have temperature characteristics which

are indicated on resistance-temperature conversion tables.

The Vishay-Dale thermistor NTHS0603N011-N1003F, used

in the following examples, has a nominal value of 100k

and follows the Vishay curve 1 resistance-temperature

characteristic.

In the explanation below, the following notation is used.

R25 = Value of the thermistor at 25°C

RNTC|COLD = Value of thermistor at the cold trip point

RNTC|HOT = Value of the thermistor at the hot trip point

rCOLD = Ratio of RNTC|COLD to R25

rHOT = Ratio of RNTC|HOT to R25

RNOM = Primary thermistor bias resistor (see Figure 2)

R1 = Optional temperature range adjustment resistor (see

Figure 2)

The trip points for the LTC3554’s temperature qualifica-

tion are internally programmed at 0.35 • VBUS for the hot

threshold and 0.76 • VBUS for the cold threshold.

OPERATION

Figure 1. Typical NTC Thermistor Circuit

Figure 2. NTC Thermistor Circuit with Additional Bias Resistor

–

RNOM

100k

RNTC

100k

NTC

VBUS

NTC_ENABLE

3554 F01

NTC BLOCK

TOO_COLD

TOO_HOT

0.76 • VBUS

(NTC RISING)

0.35 • VBUS

(NTC FALLING)

0.017 • VBUS

(NTC FALLING)

–

15 –

–

RNOM

105k

RNTC

100k

12.7k

NTC

VBUS

NTC_ENABLE

3554 F02

TOO_COLD

TOO_HOT

0.76 • VBUS

(NTC RISING)

0.35 • VBUS

(NTC FALLING)

0.017 • VBUS

(NTC FALLING)

–

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

OPERATION

Therefore, the hot trip point is set when:

RNTC|HOT

RNOM +RNTC|HOT

•VBUS =0.35 •VBUS

and the cold trip point is set when:

RNTC|COLD

RNOM +RNTC|COLD

•VBUS =0.76 •VBUS

Solving these equations for RNTC|COLD and RNTC|HOT

results in the following:

RNTC|HOT = 0.538 • RNOM

and

RNTC|COLD = 3.17 • RNOM

By setting RNOM equal to R25, the above equations result

in rHOT = 0.538 and rCOLD = 3.17. Referencing these ratios

to the Vishay Resistance-Temperature Curve 1 chart gives

a hot trip point of about 40°C and a cold trip point of about

0°C. The difference between the hot and cold trip points

is approximately 40°C.

By using a bias resistor, RNOM, different in value from

R25, the hot and cold trip points can be moved in either

direction. The temperature span will change somewhat due

to the nonlinear behavior of the thermistor. The following

equations can be used to easily calculate a new value for

the bias resistor:

RNOM =rHOT

0.538

•R25

RNOM =rCOLD

3.17

•R25

where rHOT and rCOLD are the resistance ratios at the de-

sired hot and cold trip points. Note that these equations

are linked. Therefore, only one of the two trip points can

be independently set, the other is determined by the de-

fault ratios designed in the IC.

Consider an example where a 60°C hot trip point is desired.

From the Vishay curve 1 R-T characteristics, rHOT is 0.2488

at 60°C. Using the above equation, RNOM should be set to

46.4k. With this value of RNOM, the cold trip point is about

16°C. Notice that the span is now 44°C rather than the

previous 40°C. This is due to the decrease in temperature

gain of the thermistor as absolute temperature increases.

The upper and lower temperature trip points can be in-

dependently programmed by using an additional bias

resistor as shown in Figure 2. The following formulas can

be used to compute the values of RNOM and R1:

RNOM =rCOLD – r HOT

2.714 •R25

R1=0.536 •RNOM – r HOT •R25

For example, to set the trip points to 0°C and 45°C with

a Vishay curve 1 thermistor choose:

RNOM =

3.266 – 0.4368

2.714

•100k =104.2k

the nearest 1% value is 105k

R1 = 0.536 • 105k – 0.4368 • 100k = 12.6k

The nearest 1% value is 12.7k. The final solution is shown

in Figure 2 and results in an upper trip point of 45°C and

a lower trip point of 0°C.

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

STEP-DOWN SWITCHING REGULATOR

Introduction

The LTC3554 includes two constant-frequency current-

mode 200mA step-down switching regulators, also

known as buck regulators. At light loads, each regulator

automatically enters Burst Mode operation to maintain

high efficiency.

Applications with a near-zero-current sleep or memory

keep-alive mode can command the LTC3554 switching

regulators into a standby mode that maintains output

regulation while drawing only 1.5µA quiescent current

per active regulator. Load capability drops to 5mA per

regulator in this mode.

Switching frequency and switch slew rate are pin-select-

able, allowing the application circuit to dynamically trade

off efficiency and EMI performance.

The regulators are enabled, disabled and sequenced (ex-

cept LTC3554-3) through the pushbutton interface (see

the Pushbutton Interface section for more information). It

is recommended that the step-down switching regulator

input supply (BVIN) be connected to the system supply pin

(VOUT). This is recommended because the undervoltage

lockout circuit on the VOUT pin (VOUT UVLO) disables the

step-down switching regulators when the VOUT voltage

drops below the VOUT UVLO threshold. If driving the step-

down switching regulator input supplies from a voltage

other than VOUT, the regulators should not be operated

outside their specified operating voltage range as opera-

tion is not guaranteed beyond this range.

Output Voltage Programming

Figure 3 shows the step-down switching regulator

application circuit. The output voltage for each step-down

switching regulator is programmed using a resistor divider

from the step-down switching regulator output connected

to the feedback pins (FB1 and FB2) such that:

VOUTx =0.8V •R1

R2 +1











Typical values for R1 can be as high as 2.2MΩ.

(R1 + R2) can be as high as 3MΩ. The capacitor CFB

cancels the pole created by feedback resistors and

the input capacitance of the FB pin and also helps to

improve transient response for output voltages much

greater than 0.8V. A variety of capacitor sizes can be used

for CFB but a value of 10pF is recommended for most

applications. Experimentation with capacitor sizes between

2pF and 22pF may yield improved transient response.

OPERATION

Figure 3. Step-down Switching Regulator Ap-

plication Circuit

3554 F03

0.8V

VIN

CFB COUT

VOUTx

GND

FBx

SWx L

PWM

CONTROL

FSEL

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

PGOOD Operation

The PGOOD pin is an open-drain output which indicates that

all enabled step-down switching regulators have reached

their final regulation voltage. It goes high-impedance

230ms after all enabled switching regulators reach 92%

of their regulation value. The delay allows ample time

for an external processor to reset itself. PGOOD may be

used as a power-on reset to a microprocessor powered

by the step-down switching regulators. Since PGOOD is

an open-drain output, a pull-up resistor to an appropriate

power source is needed. A suggested approach is to con-

nect the pull-up resistor to one of the step-down switching

regulator output voltages so that power is not dissipated

while the regulators are disabled.

In hard reset, the PGOOD pin is placed in high impedance

state to minimize current draw from the battery in this ul-

tralow power state. This will cause the PGOOD pin to signal

the wrong state (high level) if it is pulled up to a supply

that is not shut down in hard reset (e.g. BAT). If PGOOD

is pulled up to one of the step-down switching regulator

outputs then the PGOOD pin will indicate the correct state

(low level) in hard reset because the switching regulator

output will be low.

Normal Operating Mode (STBY Pin Low)

In normal mode (STBY pin low), the regulators perform

as traditional constant-frequency current mode switching

regulators. Switching frequency is determined by an inter-

nal oscillator whose frequency is selectable via the FSEL

pin. An internal latch is set at the start of every oscillator

cycle, turning on the main P-channel MOSFET switch.

During each cycle, a current comparator compares the

inductor current to the output of an error amplifier. The

output of the current comparator resets the internal latch,

which causes the main P-channel MOSFET switch to turn

off and the N-channel MOSFET synchronous rectifier to turn

on. The N-channel MOSFET synchronous rectifier turns off

at the end of the clock cycle, or when the current through

the N-channel MOSFET synchronous rectifier drops to

zero, whichever happens first. Via this mechanism, the

error amplifier adjusts the peak inductor current to deliver

the required output power. All necessary compensation

is internal to the step-down switching regulator requiring

only a single ceramic output capacitor for stability.

At light load and no-load conditions, the buck automatically

switches to a power-saving hysteretic control algorithm that

operates the switches intermittently to minimize switching

losses. Known as Burst Mode operation, the buck cycles

the power switches enough times to charge the output

capacitor to a voltage slightly higher than the regulation

point. The buck then goes into a reduced quiescent current

sleep mode. In this state, power loss is minimized while the

load current is supplied by the output capacitor. Whenever

the output voltage drops below a predetermined value, the

buck wakes from sleep and cycles the switches again until

the output capacitor voltage is once again slightly above

the regulation point. Sleep time thus depends on load

current, since the load current determines the discharge

rate of the output capacitor.

Standby Mode (STBY Pin High)

There are situations where even the low quiescent current

of Burst Mode operation is not low enough. For instance,

in a static memory keep alive situation, load current may

fall well below 1µA. In this case, the 25µA typical BVIN

quiescent current per active regulator in Burst Mode opera-

tion becomes the main factor determining battery run time.

Standby mode cuts BVIN quiescent current down to just

1.5µA per active regulator, greatly extending battery run

time in this essentially no-load region of operation. The

application circuit commands the LTC3554 into and out

of standby mode via the STBY pin logic input. Bringing

the STBY pin high places both regulators into standby

mode, while bringing it low returns them to Burst Mode

operation. In standby mode, load capability drops to 5mA

per regulator.

OPERATION

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

In standby mode, each regulator operates hysteretically.

When the FB pin voltage falls below the internal 0.8V

reference, a current source from BVIN to SW turns on,

delivering current through the inductor to the switching

regulator output capacitor and load. When the FB pin

voltage rises above the reference plus a small hysteresis

voltage, that current is shut off. In this way, output regula-

tion is maintained.

Since the power transfer from BVIN to SW is through a

high impedance current source rather than through a low

impedance MOSFET switch, power loss scales with load

current as in a linear low dropout (LDO) regulator, rather

than as in a switching regulator. For near-zero load condi-

tions where regulator quiescent current is the dominant

power loss, standby mode is ideal. But at any appreciable

load current, Burst Mode operation yields the best overall

conversion efficiency.

Shutdown

Each step-down switching regulator is shut down and

enabled via the pushbutton interface. In shutdown, each

switching regulator draws only a few nanoamps of leak-

age current from the BVIN pin. Each disabled regulator

also pulls down on its output with a 10k resistor from its

switch pin to ground.

Dropout Operation

It is possible for a step-down switching regulator’s input

voltage to fall near or below its programmed output volt-

age (e.g., a battery voltage of 3.4V with a programmed

output voltage of 3.3V). When this happens, the PMOS

switch duty cycle increases to 100%, keeping the switch on

OPERATION

continuously. Known as dropout operation, the respective

output voltage equals the regulator’s input voltage minus

the voltage drops across the internal P-channel MOSFET

and the inductor.

Soft-Start Operation

In normal operating mode, soft-start works by gradually

increasing the peak inductor current for each step-down

switching regulator over a 500μs period. This allows each

output to rise slowly, helping minimize the inrush current

needed to charge up the output capacitor. A soft-start cycle

occurs whenever a given switching regulator is enabled.

Soft-start occurs only in normal operation, but not in

standby mode. Standby mode operation is already inher-

ently current-limited, since the regulator works by inter-

mittently turning on a current source from BVIN to SW.

Changing the state of the STBY pin while the regulators

are operating doesn’t trigger a new soft-start cycle, to

avoid glitching the outputs.

Frequency/Slew Rate Select

The FSEL pin allows an application to dynamically trade off

between highest efficiency and reduced electromagnetic

interference (EMI) emission.

When FSEL is high, the switching regulator frequency is

set to 2.25MHz to stay out of the AM radio band. Also,

new patented circuitry is enabled which limits the slew rate

of the switch nodes (SW1 and SW2). This new circuitry

is designed to transition the switch node over a period of

a few nanoseconds, significantly reducing radiated EMI

and conducted supply noise.

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

OPERATION

When FSEL is low, the frequency of the switching regulators

is reduced to 1.125Mhz. The slower switching frequency

reduces switching losses and raises efficiency as shown

in Figures 4 and 5. Switch node slew rate is also increased

to minimize transition losses. As the programmed output

voltage decreases, the difference in efficiency is more

appreciable.

Low Supply Operation

An undervoltage lockout circuit on the VOUT pin (VOUT

UVLO) shuts down the step-down switching regulators

when VOUT drops below about 2.6V. It is thus recom-

mended that the step-down switching regulator input

supply (BVIN) be connected directly to the power path

output (VOUT). The UVLO prevents the step-down

switching regulators from operating at low supply voltages

where loss of regulation or other undesirable operation

may occur. If driving the step-down switching regulator

input supply from a voltage other than the VOUT pin, the

regulators should not be operated outside the specified

operating range as operation is not guaranteed beyond

this range.

Inductor Selection

Many different sizes and shapes of inductors are avail-

able from numerous manufacturers. Choosing the right

inductor from such a large selection of devices can be

overwhelming, but following a few basic guidelines will

make the selection process much simpler.

Figure 4. 1.2V Output Efficiency and Power Loss vs

Load Current

Figure 5. 3.3V Output Efficiency and Power Loss

vs Load Current

LOAD CURRENT (mA)

0.01 0.1

EFFICIENCY (%)

POWER LOSS (mW)

100

1 10 100 1000

3554 F04

1000

0.1

100

90 BAT = 3.8V

FSEL = L

FSEL = H

EFFICIENCY

POWER LOSS

LOAD CURRENT (mA)

0.01 0.1

EFFICIENCY (%)

POWER LOSS (mW)

100

1 10 100 1000

3554 F05

1000

0.1

100

90 BAT = 3.8V

FSEL = L

FSEL = H

EFFICIENCY

POWER LOSS

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

OPERATION

Inductor value should be chosen based on the desired

output voltage. See Table 2. Table 3 shows several inductors

that work well with the step-down switching regulators.

These inductors offer a good compromise in current rat-

ing, DCR and physical size. Consult each manufacturer for

detailed information on their entire selection of inductors.

Larger value inductors reduce ripple current, which im-

proves output ripple voltage. Lower value inductors result in

higher ripple current and improved transient response time,

but will reduce the available output current. To maximize

efficiency, choose an inductor with a low DC resistance.

Choose an inductor with a DC current rating at least 1.5

times larger than the maximum load current to ensure that

the inductor does not saturate during normal operation.

If output short circuit is a possible condition, the induc-

tor should be rated to handle the maximum peak current

specified for the step-down converters.

Different core materials and shapes will change the size/

current and price/current relationship of an inductor. Toroid

or shielded pot cores in ferrite or permalloy materials are

small and do not radiate much energy, but generally cost

more than powdered iron core inductors with similar

Table 3. Recommended Inductors for Step-Down Switching Regulators

INDUCTOR PART NO. L (µH) MAX IDC (A) MAX DCR (Ω) SIZE (L × W × H) (mm) MANUFACTURER

1117AS-4R7M

1117AS-6R8M

1117AS-100M

4.7

6.8

0.64

0.54

0.45

0.18*

0.250*

0.380*

3.0 × 2.8 × 1.0 Toko

www.toko.com

CDRH2D11BNP-4R7N

CDRH2D11BNP-6R8N

CDRH2D11BNP-100N

4.7

6.8

0.7

0.6

0.48

0.248

0.284

0.428

3.0 × 3.0 × 1.2 Sumida

www.sumida.com

SD3112-4R7-R

SD3112-6R8-R

SD3112-100-R

4.7

6.8

0.8

0.68

0.55

0.246*

0.291*

0.446*

3.1 × 3.1 × 1.2 Cooper

www.cooperet.com

EPL2014-472ML_

EPL2014-682ML_

EPL2014-103ML_

4.7

6.8

0.88

0.8

0.6

0.254

0.316

0.416

2.0 × 1.8 × 1.4 Coilcraft

www.coilcraft.com

* = Typical DCR

Table 1. Ceramic Capacitor Manufacturers

AVX www.avxcorp.com

Murata www.murata.com

Taiyo Yuden www.t-yuden.com

Vishay Siliconix www.vishay.com

TDK www.tdk.com

Table 2. Choosing the Inductor Value

DESIRED OUTPUT VOLTAGE RECOMMENDED INDUCTOR VALUE

1.8V or Less 10µH

1.8V to 2.5V 6.8µH

2.5V to 3.3V 4.7µH

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

electrical characteristics. Inductors that are very thin or

have a very small volume typically have much higher core

and DCR losses, and will not give the best efficiency. The

choice of which style inductor to use often depends more

on the price versus size, performance and any radiated

EMI requirements than on what the step-down switching

regulators requires to operate.

The inductor value also has an effect on Burst Mode

operation. Lower inductor values will cause Burst Mode

switching frequency to increase.

Input/Output Capacitor Selection

Low ESR (equivalent series resistance) ceramic capacitors

should be used at both step-down switching regulator

outputs as well as at the step-down switching regulator

input supply. Only X5R or X7R ceramic capacitors should

be used because they retain their capacitance over wider

voltage and temperature ranges than other ceramic types.

For good transient response and stability the output capaci-

tor for each step-down switching regulator should retain

at least 4μF of capacitance over operating temperature and

bias voltage. Generally, a good starting point is to use a

10μF output capacitor.

The switching regulator input supply should be bypassed

with a 2.2μF capacitor. Consult with capacitor manufac-

turers for detailed information on their selection and

specifications of ceramic capacitors. Many manufacturers

now offer very thin (<1mm tall) ceramic capacitors ideal

for use in height-restricted designs. Table 1 shows a list

of several ceramic capacitor manufacturers.

PUSHBUTTON INTERFACE

State Diagram/Operation

Figure 6 shows the LTC3554 pushbutton state diagram.

Figure 6. Pushbutton State Diagram

3554 F06

PUP2

PDN1

PDN2 HRST

HRST

POR

PWR_ONx

AND UVLO

PWR_ONx

EXTPWR OR

PB400MS

1SEC

5SEC

1SEC

PON

POFF

PUP1

PWR_ONx

OR UVLO

EXTPWR OR

PB400MS

The pushbutton state machine has a clock with a 1.82ms

period.

Upon first application of power, VBUS or BAT, an internal

power on reset (POR) signal places the pushbutton cir-

cuitry into the power-down (PDN1) state. One second

after entering the PDN1 state the pushbutton circuitry will

transition into the hard reset (HR) state.

OPERATION

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

In the HR state, all supplies are disabled. The PowerPath

circuitry is placed in an ultralow quiescent state to minimize

battery drain. If no external charging supply is present

(VBUS) then the ideal diode is shut down, disconnecting

VOUT from BAT to further minimize battery drain. The ultra-

low power consumption in the HR state makes it ideal for

shipping or long term storage, minimizing battery drain.

The following events cause the state machine to transition

out of HR into the power-up (PUP1) state:

ON input low for 400ms (PB400MS)

Application of external power (EXTPWR)

Upon entering the PUP1 state, the pushbutton circuitry

will sequence up the two step-down switching regula-

tors, buck1 followed by buck2 (except LTC3554-3). In the

LTC3554-3, buck1 and buck2 are simultaneously enabled.

The PWR_ON1 and PWR_ON2 inputs are ignored in the

PUP1 state. The state machine remains in the PUP1 state

for five seconds. During the five seconds, the application’s

microprocessor, powered by the switching regulators, has

time to boot and assert PWR_ON1 and/or PWR_ON2.

Five seconds after entering the PUP1 state, the pushbut-

ton circuitry automatically transitions into the power-on

(PON) state.

In the PON state, the switching regulators can be enabled

and shut down at any time by the PWR_ON1 and PWR_ON2

pins. A high on PWR_ON1 is needed to keep buck1 en-

abled, and a high on PWR_ON2 is needed to keep buck2

enabled. To remain in the PON state, the application circuit

must keep at least one of the PWR_ON inputs high, else

the state machine enters the power-down (PDN2) state.

When PWR_ON1 and PWR_ON2 are both low, or when

VOUT drops to its undervoltage lockout (VOUT UVLO)

threshold, the state machine will leave the PON state and

OPERATION

enter the power-down (PDN2) state. In the power-down

state (PDN2), both switching regulators are kept disabled

regardless of the states of the PWR_ON pins. The state

machine remains in the power-down state for one second,

before automatically entering the power-off (POFF) state.

This one second delay allows all LTC3554 generated sup-

plies time to power down completely before they can be

re-enabled.

The same events used to exit the hard reset (HR) state

are also used to exit the POFF state and enter the PUP2

state. The PUP2 state operates in the same manner as the

PUP1 state previously described.

Both bucks remain powered up during the five second

power-up (PUP1 or PUP2) period, regardless of the state

of the PWR_ON inputs.

In either the HR or POFF states, if any PWR_ON pin is

driven high, the pushbutton circuitry directly enters the

PON state, without passing through the power-up (PUP1

or PUP2) states. This is because by asserting logic high

on the PWR_ON1 or PWR_ON2 pins, the application has

already told the LTC3554 exactly which buck(s) to turn

on, so there is no need for an intermediate PUP state in

which both bucks are enabled for five seconds.

Starting from the HR state, bringing any PWR_ON pin high

enables the PowerPath, if it wasn’t already enabled due

to VBUS power being available. This powers up the VOUT

pin from VBUS or BAT. When the VOUT voltage rises above

the VOUT UVLO threshold, the state machine transitions

from the HR state into the PON state, allowing the selected

buck(s) to turn on.

The hard reset (HRST) event is generated by pressing

and holding the pushbutton (ON input low) for 5 seconds

for LTC3554/LTC3554-1 (14 seconds for LTC3554-2/

LTC3554-3). For a valid HRST event to occur the button

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

BAT

*BUCK1 AND BUCK2 FOR THE LTC3554-3

VBUS

ON (PB)

PBSTAT

BUCK1*

BUCK2

PGOOD

PWR_ON1

PWR_ON2

STATE POFF/HR PONPUP2/PUP1

3554 TD01

230ms

400ms

Figure 7. Power-Up Via Pushbutton Press

OPERATION

press must start in the PUP1, PUP2 or PON state, but

can end in any state. If a valid HRST event is present in

PON, PDN2 or POFF, then the state machine will transition

to the PDN1 state and subsequently transition to the HR

state one second later.

Debounced Pushbutton Output (PBSTAT)

In the PON, PUP1, and PUP2 states, the PBSTAT open-drain

output pin outputs a debounced version of the ON push-

button signal. ON must be held low for at least 50ms for

the pushbutton interface to recognize it and cause PBSTAT

to go low. PBSTAT goes high impedance when ON goes

high, except the logic enforces a minimum pulse width on

PBSTAT. Once it goes low, it stays low for at least 50ms.

In the HR, POFF, PDN1, and PDN2 states, PBSTAT remains

high impedance regardless of the state of ON.

Power-Up Via Pushbutton Press

Figure 7 shows the LTC3554 powering up through ap-

plication of the external pushbutton. For this example the

pushbutton circuitry starts in the POFF or HR state with a

battery connected and both bucks disabled. Pushbutton

application (ON low) for 400ms transitions the pushbutton

circuitry into the PUP state and powers up buck1 followed

by buck2 (except LTC3554-3). In the LTC3554-3, buck1

and buck2 power up at the same time. If either PWR_ON

is low or goes low after the 5 second period the corre-

sponding buck(s) will be shut down. In the above example

PWR_ON2 is low at the end of the 5 second period and

therefore buck2 is disabled at the end of the 5 second

period. PGOOD is asserted once all enabled bucks are

within 8% of their regulation voltage for 230ms.

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

The PWR_ON inputs can be driven via a μP/μC or by one

of the buck outputs through a high impedance (100kΩ

typical) to keep the bucks enabled as described above.

PBSTAT does not go low on initial pushbutton applica-

tion for power-up, but will go low with subsequent ON

pushbutton applications in the PUP1, PUP2 or PON states.

Power-Up Via Applying External Power

Figure 8 shows the LTC3554 powering up through ap-

plication of external power (VBUS). For this example the

pushbutton circuitry starts in the POFF or HR state with

a battery connected and both bucks disabled. 100ms

after VBUS application the pushbutton circuitry transi-

tions into the PUP state and powers up buck1 followed

by buck2 (except LTC3554-3). In the LTC3554-3, buck1

and buck2 power up at the same time. The 100ms delay

time allows the applied supply to settle. The bucks will

stay powered as long as their respective PWR_ON inputs

are driven high before the 5 second PUP period is over.

If either PWR_ON is low or goes low after the 5 second

OPERATION

period the corresponding buck(s) will be shut down. In

the above example both PWR_ONs are high at the end of

the 5 second period and therefore both bucks continue

to stay on at the end of the 5 second period. PGOOD is

asserted once all enabled bucks are within 8% of their

regulation voltage for 230ms.

The PWR_ON inputs can be driven via a μP/μC or one of

the buck outputs through a high impedance (100kΩ typ)

to keep the bucks enabled as described above.

Without a battery present, initial power application causes

a power-on reset which puts the pushbutton circuitry in

the PDN1 state and subsequently the HR state one second

later. At this time, if a valid supply voltage is detected at the

BUS pin (i.e., VBUS > VUVLO and VBUS – VBAT > VDUVLO),

the pushbutton circuity immediately enters the PUP1 state.

For this to work reliably, the BAT pin voltage must be kept

well-behaved when no battery is connected. Ensure this

by bypassing the BAT pin to GND with an RC network con-

sisting of a 100µF ceramic capacitor in series with 0.3Ω.

BAT

VBUS

ON (PB)

PBSTAT

BUCK1

BUCK2*

PGOOD

PWR_ON1

PWR_ON2

STATE POFF/HR

*BUCK1 AND BUCK2 FOR THE LTC3554-3

PONPUP2/PUP1

3554 TD02

230ms

100ms

Figure 8. Power-Up Via Applying External Power

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

BAT

VBUS

ON (PB)

PBSTAT

BUCK1

BUCK2

PGOOD

PWR_ON1

PWR_ON2

STATE PON POFFPDN2

3554 TD04

µC/µP CONTROL

50ms

µC/µP CONTROL

Figure 10. Power-Down Via PWR_ON De-Assertion

OPERATION

Power-Up Via Asserting PWR_ON Pins

Figure 9 shows the LTC3554 powering up by driving

PWR_ON1 high. For this example the pushbutton circuitry

starts in the POFF or HR state with a battery connected

and all bucks disabled. Once PWR_ON1 goes high, the

pushbutton circuitry enters the PON state and buck1

powers up. Once buck1’s output is within 8% of its regu-

lation voltage for 230ms, PGOOD is asserted. Similarly,

if PWR_ON2 is brought high at a later time, buck2 will

power up. The pushbutton circuitry remains in the PON

state. During the time that buck2 powers up, PGOOD will

be held low. PGOOD will be asserted again once buck2 is

within 8% of its regulation for 230ms.

Powering up via PWR_ON is useful for applications

containing an always-on μC that’s not powered by the

LTC3554 regulators. That μC can power the application

up and down for housekeeping and other activities not

needing the user’s control.

Power-Down Via PWR_ON De-Assertion

Figure 10 shows the LTC3554 powering down by μC/μP

control. For this example the pushbutton circuitry starts

in the PON state with a battery connected and all bucks

enabled. The user presses the pushbutton (ON low) for at

least 50ms, which generates a debounced, low impedance

pulse on the PBSTAT output. After receiving the PBSTAT

signal, the μC/μP software decides to drive the PWR_ON

inputs low in order to power down. After the last PWR_ON

pin goes low, the pushbutton circuitry will enter the PDN2

state. In the PDN2 state a one second wait time is initi-

ated after which the pushbutton circuitry enters the POFF

state. During this one second time, the ON and PWR_ON

inputs as well as external power application are ignored

to allow all LTC3554 generated supplies to go low. Though

the above assumes a battery present, the same operation

would take place with a valid external supply (VBUS) with

or without a battery present.

BAT

VBUS

ON (PB)

PBSTAT

BUCK1

BUCK2

PGOOD

PWR_ON1

PWR_ON2

STATE POFF/HR PON

3554 TD03

230ms 230ms

Figure 9. Power-Up Via Asserting PWR_ON Pins

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

Holding ON low through the one second power-down

period will not cause a power-up event at end of the one

second period. The ON pin must be brought high following

the power-down event and then go low again to establish

a valid power-up event.

UVLO Minimum Off-Time Timing (Low Battery)

Figure 11 assumes the battery is either missing or at a

voltage below the VOUT UVLO threshold, and the applica-

tion is running via external power (VBUS). A glitch on the

external supply causes VOUT to drop below the VOUT UVLO

threshold temporarily. This VOUT UVLO condition causes

the pushbutton circuitry to transition from the PON state

to the PDN2 state. Upon entering the PDN2 state PGOOD

will go low and the bucks power down together.

In the typical case where the PWR_ON1 and PWR_ON2 pins

are driven by logic powered by the bucks, the PWR_ON1

and PWR_ON2 pins would also go low, as depicted in

Figure 11. If the external supply recovers after entering the

PDN2 state such that VOUT is no longer in UVLO, then the

LTC3554 will transition back into the PUP2 state once the

PDN2 one second delay is complete. Following the state

diagram, the transition from PDN2 to PUP2 in this case

actually occurs via a brief visit to the POFF state, during

which the state machine immediately recognizes that valid

external power is available and transitions into the PUP2

state. Entering the PUP2 state will cause the bucks to

power up as described previously in the power-up sections.

Not depicted here, but in the case where the PWR_ON

pins are driven by a supply other than the bucks, and are

able to remain high while both bucks are off in the PDN2

state, then as per the state diagram in Figure 6, once the

one second PDN2 delay is over, the pushbutton circuitry

enters the POFF state. Provided at least one PWR_ON pin

is high, and VOUT is no longer in UVLO, the pushbutton

circuitry will transition directly into the PON state, enabling

the buck(s) corresponding to the asserted PWR_ON pin(s).

Note: If VOUT drops too low (below about 1.9V ) the

LTC3554 will see this as a POR condition and will enter

the PDN1 rather than the PDN2 state. One second later the

part will transition to the HR state. Under these conditions

an explicit power up event (such as a pushbutton press)

may be required to bring the LTC3554 out of hard reset.

Hard Reset Timing

HARD RESET provides an ultralow power-down state for

shipping or long term storage as well as a way to power

down the application in case of a software lockup. In the

case of software lockup, the user can hold the pushbut-

ton (ON low) for 5 seconds for LTC3554/LTC3554-1

(14 seconds for LTC3554-2/LTC3554-3) and a hard reset

event (HRST) will occur, placing the pushbutton circuitry

in the power-down (PDN1) state. At this point the bucks

will be shut down and PGOOD will go low. Following a one

second power-down period the pushbutton circuitry will

enter the hard reset state (HR).

OPERATION

BAT

VBUS

ON (PB)

PBSTAT

BUCK1

BUCK2

PGOOD

PWR_ON1

PWR_ON2

STATE PON PONPUP2PDN2

3554 TD05

1s, BUCK1 POWERS UP

BUCK2 POWERS UP

230ms

Figure 11. UVLO Minimum Off-Time Timing

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

Holding ON low through the one second power-down

period will not cause a power-up event at end of the one

second period. ON must be brought high following the

power-down event and then go low again for 400ms to

establish a valid power-up event, as shown in Figure 12.

The regulators in Figure 13 are slewing up with nominal

output capacitors and no-load. Adding a load or increasing

output capacitance on any of the outputs will reduce the

slew rate and lengthen the time it takes the regulator to

get into regulation. In the LTC3554-3, buck1 and buck2

power up at the same time without sequencing.

OPERATION

BAT

VBUS

ON (PB)

PBSTAT

BUCK1

BUCK2

PGOOD

PWR_ON1

PWR_ON2

STATE PON PUP1HRPDN1

3554 TD06

400ms

50ms

tON_HR

VOUT2

0.5V/DIV

VOUT1

1V/DIV

3554 F13

100µs/DIV

Figure 13. Power-Up Sequencing

Figure 12. Hard Reset Via Holding ON Low

LAYOUT AND THERMAL CONSIDERATIONS

Printed Circuit Board Power Dissipation

In order to be able to deliver maximum charge current

under all conditions, it is critical that the Exposed Pad

on the backside of the LTC3554 package is soldered to

a ground plane on the board. Correctly soldered to a

2500mm2 ground plane on a double-sided 1oz copper

board, the LTC3554 has a thermal resistance (θJA) of ap-

proximately 70°C/W. Failure to make good thermal contact

between the Exposed Pad on the backside of the package

and an adequately sized ground plane will result in thermal

resistances far greater than 70°C/W.

The conditions that cause the LTC3554 to reduce charge

current due to the thermal protection feedback can be

approximated by considering the power dissipated in the

part. For high charge currents the LTC3554 power dis-

sipation is approximately:

PD = (VBUS–BAT) • IBAT + PD(REGS)

where PD is the total power dissipated, VBUS is the supply

voltage, BAT is the battery voltage, and IBAT is the battery

charge current. PD(REGS) is the sum of power dissipated

on chip by the step-down switching regulators.

Power-Up Sequencing (Except LTC3554-3)

Figure 13 shows the actual power-up sequencing of the

LTC3554. Buck1 and buck2 are both initially disabled (0V).

Once the pushbutton has been applied (ON low) for 400ms

buck1 is enabled. Buck1 slews up and enters regulation.

The actual slew rate is controlled by the soft start function

of buck1 in conjunction with output capacitance and load

(see the Step-Down Switching Regulator Operation sec-

tion for more information). When buck1 is within about

8% of final regulation, buck2 is enabled and slews up

into regulation. 230ms after buck2 is within 8% of final

regulation, the PGOOD output will go high impedance.

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

OPERATION

The power dissipated by a step-down switching regulator

can be estimated as follows:

PD(SWx) = (BOUTx • IOUT) • (100 - Eff)/100

Where BOUTx is the programmed output voltage, IOUT

is the load current and Eff is the % efficiency which can

be measured or looked up on an efficiency table for the

programmed output voltage.

Thus the power dissipated by all regulators is:

PD(REGS) = PD(SW1) + PD(SW2)

It is not necessary to perform any worst-case power dis-

sipation scenarios because the LTC3554 will automatically

reduce the charge current to maintain the die temperature

at approximately 110°C. However, the approximate ambi-

ent temperature at which the thermal feedback begins to

protect the IC is:

TA = 110°C – PD • θJA

Example: Consider the LTC3554 operating from a wall

adapter with 5V (VBUS) providing 400mA (IBAT) to charge a

Li-Ion battery at 3.3V (BAT). Also assume PD(REGS) = 0.3W,

so the total power dissipation is:

PD = (5V – 3.3V) • 400mA + 0.3W = 0.98W

The ambient temperature above which the LTC3554 will be-

gin to reduce the 400mA charge current, is approximately:

TA = 110°C – 0.98W • 70°C/W = 41.4°C

The LTC3554 can be used above 41.4°C, but the charge

current will be reduced below 400mA. The charge current

at a given ambient temperature can be approximated by:

PD = (110°C – TA) / θJA = (VBUS – BAT) • IBAT + PD(REGS)

Thus:

IBAT = [(110°C – TA) / θJA - PD(REGS)]

(VBUS – BAT)

Consider the above example with an ambient tem-

perature of 60°C. The charge current will be reduced to

approximately:

IBAT = [(110°C - 60°C) / 70°C/W - 0.3W]/(5V – 3.3V)

IBAT = (0.71W - 0.3W) / 1.7V = 241mA

Printed Circuit Board Layout

When laying out the printed circuit board, the following

list should be followed to ensure proper operation of the

LTC3554:

1. The Exposed Pad of the package (Pin 21) should connect

directly to a large ground plane to minimize thermal

and electrical impedance.

2. The trace to the step-down switching regulator input

supply pin (BVIN) and its decoupling capacitor should be

kept as short as possible. The GND side of this capacitor

should connect directly to the ground plane of the part.

This capacitor provides the AC current to the internal

power MOSFETs and their drivers. It is important to

minimize inductance from this capacitor to the pin of

the LTC3554. Connect BVIN to VOUT through a short

low impedance trace.

3. The switching power traces connecting SW1 and SW2

to their respective inductors should be minimized to

reduce radiated EMI and parasitic coupling. Due to the

large voltage swing of the switching nodes, sensitive

nodes such as the feedback nodes (FB1 and FB2) should

be kept far away or shielded from the switching nodes

or poor performance could result.

4. Connections between the step-down switching regu-

lator inductors and their respective output capacitors

should be kept as short as possible. The GND side of

the output capacitors should connect directly to the

thermal ground plane of the part.

5. Keep the buck feedback pin traces (FB1 and FB2) as

short as possible. Minimize any parasitic capacitance

between the feedback traces and any switching node

(i.e., SW1, SW2 and logic signals). If necessary, shield

the feedback nodes with a GND trace.

6. Connections between the LTC3554 PowerPath pins

(VBUS and VOUT) and their respective decoupling ca-

pacitors should be kept as short as possible. The GND

side of these capacitors should connect directly to the

ground plane of the part.

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

TYPICAL APPLICATION

VBUS

NTC

PROG

HPWR

SUSP

PWR_ON1

FSEL

STBY

PGOOD

PWR_ON2

PBSTAT

VOUT

CHRG

BAT

BVIN

SW1

FB1

SW2

FB2

GND

3 CELL

ALKALINE

OR LITHIUM

10µF

PB1

1415

RPROG

1.87k

10pF

10µF

2.2µF

RUP1

RUP2

590k

RLO1

464k

2.5V

L1 10µH

10pF

100k

10µF

RLO2

464k

1.8V

10µH

SYSTEM LOAD

4.35V TO 5.5V

USB INPUT

LTC3554

I/O

CORE

PBSTAT

PGOOD

STBY

FSEL

SUSP

HPWR

3554 F14

µC

Figure 14. 3-Cell Alkaline/Lithium with PowerPath (Charger Disabled)

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

PACKAGE DESCRIPTION

3.00 ± 0.10

(4 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

1.65 ± 0.05

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 ± 0.10

BOTTOM VIEW—EXPOSED PAD

1.65 ± 0.10

(4-SIDES)

0.75 ± 0.05 R = 0.115

TYP

R = 0.05

TYP

0.20 ± 0.05

PIN 1 NOTCH

R = 0.20 TYP

OR 0.25 × 45°

CHAMFER

19 20

0.40 BSC

0.200 REF

2.10 ± 0.05

3.50 ± 0.05

(4 SIDES)

0.70 ±0.05

0.00 – 0.05

(UD20) QFN 0306 REV A

0.20 ±0.05

0.40 BSC

PACKAGE

OUTLINE

UD Package

20-Lead Plastic QFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1720 Rev A)

UD Package

20-Lead Plastic QFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1720 Rev A)

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 7/10 PD package information removed and UD package information added to data sheet

Update to Typical Application

LTC3554EUD added and LTC3554EPD designated Obsolete in Order Information section

Note 2 updated

Pin 21 description updated

Updated Related Parts

1 to 16

B 01/11 LTC3554-2 Option Added. Reflected throughout the data sheet 1 to 36

C 10/11 LTC3554-1 Option Added. Reflected throughout the data sheet 1 to 36

D 01/12 Corrected title on axis of graph G23

Updated Block Diagram

Added text to State Diagram/Operation section

E 08/12 Added new part number LTC3554-3

Added Options table

Throughout

LTC3554/LTC3554-1/

LTC3554-2/LTC3554-3

3554123fd

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2009

LT 0812 REV E • PRINTED IN USA

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LTC3456 2-Cell, Multioutput DC/DC Converter with

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LTC3557 USB Power Manager with Li-Ion Charger,

Triple Step-Down DC/DC Regulators

Triple Step-Down Switching Regulators (600mA, 400mA); 4mm × 4mm QFN Package

LTC3559 USB Charger with Dual Buck Regulators Adjustable, Synchronous Buck Converters, 3mm × 3mm QFN-16 Package

LTC4080 500mA Standalone Charger with 300mA

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LTC3553 µPower PMIC/Charger/Buck/LDO 3mm × 3mm × 0.75mm QFN-20 Package

TYPICAL APPLICATION

BUS

NTC

PROG

HPWR

SUSP

PWR_ON1

FSEL

STBY

PGOOD

PWR_ON2

PBSTAT

OUT

CHRG

BAT

BVIN

SW1

FB1

SW2

FB2

GND

Li-Ion

BATTERY

10µF

100k

PB1

1415

PROG

1.87k

10pF

10µF

2.2µF

UP1

UP2

2.05M

LO1

649k

3.3V

LDO

1.8V

L1 4.7µH

10pF

10µF

332k

LO2

649k

1.2V

10µH

SYSTEM LOAD

4.35V TO 5.5V

USB INPUT

LTC3554

I/O

CORE

PBSTAT

PWR_ON2

PGOOD

STBY

FSEL

PWR_ON1

SUSP

HPWR

3554 F15

µC

MEMORY

100k

10µF

Figure 15. USB PowerPath with LI-Ion Battery (NTC Qualified Charging)