CLC021 www.ti.com SNLS068H - MAY 2000 - REVISED APRIL 2013 CLC021 SMPTE 259M Digital Video Serializer with EDH Generation and Insertion Check for Samples: CLC021 FEATURES APPLICATIONS * * 1 2 * * * * * * * * * * * * * (1) SMPTE 259M Serial Digital Video Standard Compliant Supports All NTSC and PAL Standard Component and Composite Serial Video Data Rates No External Serial Data Rate Setting or VCO Filtering Components Required (1) Fast VCO Lock Time: <75 s at 270 Mbps Built-In Self-Test (BIST) and Video Test Pattern Generator (TPG) with 16 Internal Patterns (1) Automatic EDH Character and Flag Generation and Insertion per SMPTE RP 165 Non-SMPTE Mode Operation as Parallel-toSerial Converter NRZ-to-NRZI Conversion Control HCMOS/LSTTL-Compatible Data and Control Inputs and Outputs for CLC021AVGZ-5.0, LVCMOS for CLC021AVGZ-3.3 75 ECL-Compatible, Differential, Serial CableDriver Outputs Single Power Supply Operation: 5V (CLC021AVGZ-5.0) or 3.3V (CLC021AVGZ-3.3) in TTL or ECL Systems Low Power: Typically 235 mW JEDEC 44-Lead Metric PQFP Package Commercial Temperature Range 0C to +70C * * SMPTE 259M Parallel-to-Serial Digital Video Interfaces for: - Video Cameras - VTRs - Telecines - Video Test Pattern Generators and Digital Video Test Equipment - Video Signal Generators Non-SMPTE Video Applications Other High Data Rate Parallel/Serial Video and Data Applications DESCRIPTION The CLC021 SMPTE 259M Digital Video Serializer with EDH Generation and Insertion is a monolithic integrated circuit that encodes, serializes and transmits bit-parallel digital data conforming to SMPTE 125M and 267M component video and SMPTE 244M composite video standards. The CLC021 can also serialize other 8- or 10-bit parallel data. The CLC021 operates at data rates from below 100 Mbps to over 400 Mbps. The serial data clock frequency is internally generated and requires no external frequency setting, trimming or filtering components*. Patents Applications Made or Pending. TYPICAL APPLICATION 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000-2013, Texas Instruments Incorporated CLC021 SNLS068H - MAY 2000 - REVISED APRIL 2013 www.ti.com DESCRIPTION (CONTINUED) Functions performed by the CLC021 include: parallel-to-serial data conversion, ITU-R BT.601-4 input data clipping, data encoding using the SMPTE polynomial (X9+X4+1), data format conversion from NRZ to NRZI, parallel data clock frequency multiplication and encoding with the serial data, and differential, serial output data driving. The CLC021 has circuitry for automatic EDH character and flag generation and insertion per SMPTE RP165. The CLC021 has an exclusive built-in self-test (BIST) and video test pattern generator (TPG) with 16 component video test patterns: reference black, PLL and EQ pathologicals and modified colour bars in 4:3 and 16:9 raster formats for NTSC and PAL formats*. The CLC021 has inputs for enabling sync detection, non-SMPTE mode operation, enabling the EDH function, NRZ/NRZI mode control and an external reset control. Outputs are provided for H, V and F bits, new TRS sync character position indication, ancilliary data header detection, NTSC/PAL raster indication and PLL lock detect. Separate power pins for the output driver, VCO and the serializer improve power supply rejection, output jitter and noise performance. The CLC021AVGZ-5.0V is powered by a single +5V supply. The CLC021AVGZ-3.3V is powered by a single +3.3V supply. Power dissipation is typically 235 mW including two 75 back-matched output loads. The device is packaged in a JEDEC metric 44-lead PQFP. BLOCK DIAGRAM 2 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: CLC021 CLC021 www.ti.com SNLS068H - MAY 2000 - REVISED APRIL 2013 CONNECTION DIAGRAM Figure 1. 44-Pin Metric PQFP See Package Number PGB0044A Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: CLC021 3 CLC021 SNLS068H - MAY 2000 - REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) Supply Voltage (VDD-VSS) CLC021AVGZ-5.0V CMOS/TTL Input Voltage (VI) CMOS/TTL Output Voltage (VO) CMOS/TTL Input Current (single input) 4.0V CLC021AVGZ-5.0V -0.5V to VDD+0.5V CLC021AVGZ-3.3V -0.3V to VDD+0.3V CLC021AVGZ-5.0V -0.5V to VDD+0.5V CLC021AVGZ-3.3V -0.3V to VDD+0.3V VI = VSS -0.5V: -5 mA VI = VDD +0.5V: +5 mA Input Current, Other Inputs 1 mA CMOS/TTL Output Source/Sink Current 16 mA SDO Output Source Current Package Thermal Resistance 6.0V CLC021AVGZ-3.3V 22 mA JA 44-lead Metric PQFP (@ 0 LFM airflow) 60C/W (@ 500 LFM airflow) 43C/W JC 44-lead Metric PQFP 17C/W Storage Temp. Range -65C to +150C Junction Temperature +150C Lead Temperature Soldering 4 Sec +260C ESD Rating (HBM) 2 kV ESD Rating (MM) 150V Transistor Count (1) (2) 33,400 Absolute Maximum Ratings are those parameter values beyond which the life and operation of the device cannot be ensured. The stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of Electrical Characteristics specifies acceptable device operating conditions. It is anticipated that this device will not be offered in a military qualified version. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for availability and specifications. RECOMMENDED OPERATING CONDITIONS Supply Voltage (VDD-VSS) CLC021AVGZ-5.0 5.0V 10% CLC021AVGZ-3.3 3.3V 10% CMOS/TTL Input Voltage Maximum DC Bias on SDO pins VSS to VDD CLC021AVGZ-5.0 CLC021AVGZ-3.3 PCLK Frequency Range 1.3V 10% 10 to 40MHz PCLK Duty Cycle 45 to 55% DN and PCLK Rise/Fall Time 1.0 to 3.0 ns Operating Free Air Temperature (TA) 4 3.0V 10% 0C to +70C Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: CLC021 CLC021 www.ti.com SNLS068H - MAY 2000 - REVISED APRIL 2013 DC ELECTRICAL CHARACTERISTICS--CLC021AVGZ-5.0 Over Supply Voltage and Operating Temperature ranges, unless otherwise specified Symbol Parameter Conditions Reference (1) (2) . Min Typ Max Units V VIH Input Voltage High Level 2.0 VDD VIL Input Voltage Low Level VSS 0.8 V IIH Input Current High Level VIH = VDD +40 +60 A IIL Input Current Low Level VIL = VSS -1 -20 A VOH CMOS Output Voltage High Level IOH = -10 mA 2.4 4.7 VDD V VOL CMOS Output Voltage Low Level IOL = +10 mA 0.0 0.3 VSS + 0.5V V VSDO Serial Driver Output Voltage RL = 75 1%, RREF = 1.69 k 1%, See Figure 3 700 800 900 mVP-P 47 60 mA IDD (1) (2) Power Supply Current, Total All CMOS Inputs All CMOS Outputs SDO, SDO RL = 75 1%, RREF = 1.69 k 1%, PCLK = 27 MHz, NTSC Colour Bar Pattern, See Figure 3 Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated referenced to VSS = 0V. Typical values are stated for VDD = +5.0V (CLC021AVGZ-5.0) or +3.3V (CLC021AVGZ-3.3) and TA = +25C. DC ELECTRICAL CHARACTERISTICS--CLC021AVGZ-3.3 Over Supply Voltage and Operating Temperature ranges, unless otherwise specified Symbol Parameter Conditions VIH Input Voltage High Level VIL Input Voltage Low Level IIH Input Current High Level VIH = VDD IIL Input Current Low Level VIL = VSS VOH CMOS Output Voltage High Level IOH = -8 mA VOL CMOS Output Voltage Low Level IOL = +8 mA VSDO Serial Driver Output Voltage RL = 75 1%, RREF = 1.69 k 1%, See Figure 3 IDD (1) (2) Power Supply Current, Total Reference (1) (2) . Min Typ 2.0 All CMOS Inputs VSS Max Units VDD V 0.6 V +22 +60 A -1 -20 A 2.4 3.0 VDD V 0.0 0.3 VSS + 0.5V V 720 800 880 mVP-P 33 55 mA All CMOS Outputs SDO, SDO RL = 75 1%, RREF = 1.69 k 1%, PCLK = 27 MHz, NTSC Colour Bar Pattern, See Figure 3 Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated referenced to VSS = 0V. Typical values are stated for VDD = +5.0V (CLC021AVGZ-5.0) or +3.3V (CLC021AVGZ-3.3) and TA = +25C. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: CLC021 5 CLC021 SNLS068H - MAY 2000 - REVISED APRIL 2013 www.ti.com AC ELECTRICAL CHARACTERISTICS--CLC021AVGZ-5.0 Over Supply Voltage and Operating Temperature ranges, unless otherwise specified Symbol Parameter Conditions See (2) (1) . Reference Min Typ Max Units BRSDO Serial Data Rate SDO, SDO 100 400 Mbps FPCLK Reference Clock Input Frequency PCLK 10 40 MHz Reference Clock Duty Cycle PCLK 45 50 55 % DN, PCLK 1.0 1.5 3.0 tr, tf Rise Time, Fall Time tj Serial Output Jitter 270 Mbps tjit Serial Output Jitter See tr, tf Rise Time, Fall Time 20%-80% Output Overshoot See (4) tLOCK Lock Time See (2) (5) tSU Setup Time See (4) and Figure 4 DN to PCLK tHLD Hold Time See (4) and Figure 4 DN from PCLK LGEN Output Inductance See (4) RGEN Output Resistance See (4) (1) (2) (3) (4) (5) (3) , See Figure 3 220 (2) (4) (2) (4) SDO, SDO 500 ns psP-P 100 200 psP-P 800 1500 ps 1 % 75 s 3 2 ns 3 2 ns 6 nH 25k SDO, SDO Typical values are stated for VDD = +5.0V (CLC021AVGZ-5.0) or +3.3V (CLC021AVGZ-3.3) and TA = +25C. RL = 75, AC-coupled @ 270 Mbps, RREF = 1.69 k 1%, See TEST LOADS and Figure 3. CLC021 mounted in the SD021EVK board, configured in BIST mode (NTSC colour bars) with PCLK = 27 MHz derived from Tektronix TG2000 black-burst reference. Timing jitter measured with Tektronix VM700T using jitter measurement FFT mode, frame rate, 1 kHz filter bandwidth, Hanning window. Specification is ensured by design. Measured from rising-edge of first PCLK cycle until Lock Detect output goes high (true). AC ELECTRICAL CHARACTERISTICS--CLC021AVGZ-3.3 Over Supply Voltage and Operating Temperature ranges, unless otherwise specified Symbol Parameter Max Units 100 400 Mbps Reference Clock Input Frequency PCLK 10 40 MHz Reference Clock Duty Cycle PCLK 45 50 55 % DN, PCLK 1.0 1.5 3.0 Serial Data Rate FPCLK See (2) tr, tf Rise Time, Fall Time tj Serial Output Jitter 270 Mbps tjit Serial Output Jitter See tr, tf Reference , See Figure 3 (2) (4) (2) (4) SDO, SDO 20%-80% See (4) tLOCK Lock Time See (2) (5) tSU Setup Time See (4) and Figure 4 DN to PCLK and Figure 4 DN from PCLK tHLD Hold Time See (4) LGEN Output Inductance See (4) RGEN Output Resistance See (4) 6 Typ 220 Output Overshoot (4) (5) Min (3) Rise Time, Fall Time (1) (2) (3) . SDO, SDO BRSDO Conditions (1) SDO, SDO 500 ns psP-P 100 200 psP-P 800 1500 ps 1 % 75 s 4 2 ns 4 2 ns 6 nH 25k Typical values are stated for VDD = +5.0V (CLC021AVGZ-5.0) or +3.3V (CLC021AVGZ-3.3) and TA = +25C. RL = 75, AC-coupled @ 270 Mbps, RREF = 1.69 k 1%, See TEST LOADS and Figure 3. CLC021 mounted in the SD021EVK board, configured in BIST mode (NTSC colour bars) with PCLK = 27 MHz derived from Tektronix TG2000 black-burst reference. Timing jitter measured with Tektronix VM700T using jitter measurement FFT mode, frame rate, 1 kHz filter bandwidth, Hanning window. Specification is ensured by design. Measured from rising-edge of first PCLK cycle until Lock Detect output goes high (true). Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: CLC021 CLC021 www.ti.com SNLS068H - MAY 2000 - REVISED APRIL 2013 TEST LOADS Figure 2. Test Loads Figure 3. Test Circuit Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: CLC021 7 CLC021 SNLS068H - MAY 2000 - REVISED APRIL 2013 www.ti.com TIMING DIAGRAM Figure 4. Setup and Hold Timing 8 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: CLC021 CLC021 www.ti.com SNLS068H - MAY 2000 - REVISED APRIL 2013 DEVICE OPERATION The CLC021 SMPTE 259M Serial Digital Video Serializer is used in digital video signal origination equipment: cameras, video tape recorders, telecines and video test and other equipment. It converts parallel component or composite digital video signals into serial format. Logic levels within this equipment are normally TTL-compatible as produced by CMOS or bipolar logic devices. The encoder produces ECL-compatible serial digital video (SDV) signals conforming to SMPTE 259M-1997. The CLC021 operates at all standard SMPTE and ITU-R parallel data rates. In addition, the CLC021 can serialize other 8- and 10-bit data. VIDEO DATA PROCESSING CIRCUITS The input data register accepts 8- or 10-bit parallel data and clock signals having HCMOS/LSTTL-compatible signal levels. Parallel data may conform to any of several standards: SMPTE 125M, SMPTE 267M, SMPTE 244M or ITU-R BT.601. If the data is 8-bit, it is converted to a 10-bit representation according to the type of data being input: component 4:2:2 per SMPTE 259M paragraph 7.1.1, composite NTSC per paragraph 8.1.1 or composite PAL per paragraph 9.1.1. Eight-bit video data corresponds to the upper 8 bits of the 10-bit video data word and is MSB-aligned. Output from this register feeds the TRS (sync) character detector, SMPTE polynomial generator/serializer and the EDH polynomial generators/serializers and control system. All parallel data and clock inputs have internal pull-down devices. The sync detector or TRS character detector receives data from the input register. The detection function is controlled by Sync Detect Enable, a low-true, TTL-compatible, external signal. Synchronization words, the timing reference signals (TRS), start-of-active-video (SAV) and end-of-active-video (EAV) are defined in SMPTE 125M and 244M. The sync detector supplies control signals to the SMPTE polynomial generator to identify the presence of valid video data, and to the EDH control block. In SMPTE mode, TRS character LSB-clipping as prescribed in ITU-R BT.601 is enabled. LSB-clipping causes all TRS characters with a value between 000h and 003h to be forced to 000h and all TRS characters with a value between 3FCh and 3FFh to be forced to 3FFh. Clipping is done prior to encoding or EDH character generation. This function is disabled in non-SMPTE mode operation. Outputs from the sync detector are: 1. H, V, and F or Line/Field ID--For component video, these are registered outputs corresponding to input TRS data bits 6, 7 and 8, respectively. These outputs are disabled in non-SMPTE mode. The outputs are active HIGH-true. For composite video, these outputs correspond to the line and field ID encoded as input parallel data bits 2 (MSB) through 0. These outputs are registered for the duration of the applicable field. 2. NSP--New Sync Position: A function and output indicating that a new or out-of-place TRS character has been detected. This output remains active for at least one horizontal line period (reset by EAV) or unless reactivated by a subsequent new or out-of-place TRS. Activation of this function flushes the existing state of the machine reseting the EDH generator, SMPTE polynomial generator, serializer and NRZ-NRZI converter. This function is disabled in non-SMPTE mode operation. The output is active HIGH-true. 3. ANC--Ancilliary data location output: Indicates that the ancilliary data header (component) or flag (composite) has been detected. The output is a pulse having a duration of one PCLK period. The output is active HIGH-true. SMPTE POLYNOMIAL GENERATOR AND CONTROLS The SMPTE Mode input allows the CLC021 to function both as a full SMPTE 259M encoder or general-purpose 8- or 10-bit serializer. SMPTE mode is enabled when this input is LOW. Non-SMPTE mode is enabled when this pin is HIGH. This pin is pulled internally to VSS when unconnected. When in SMPTE mode, the SMPTE polynomial generator; TRS sync detection circuitry; EDH control circuitry; H, V, F and NSP outputs and TRS clipping are enabled. The SMPTE polynomial generator accepts the parallel video data and encodes it using the polynomial X9 + X4 + 1 as specified in SMPTE 259M (1997 rev.), paragraph 5 and Annex C. The transmission bit order is LSB-first, per paragraph 6. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: CLC021 9 CLC021 SNLS068H - MAY 2000 - REVISED APRIL 2013 www.ti.com NRZ-TO-NRZI CONVERTER The NRZ-to-NRZI converter accepts NRZ serial data from the SMPTE and EDH polynomial genertors and converts it to NRZI using the polynomial (X + 1) per SMPTE 259M, paragraph 5.2 and Annex C. The converter's output goes to the output buffer amplifier. The NRZ/NRZI input enables this conversion function. Conversion from NRZ to NRZI is enabled when the input is a logic LOW. Conversion to NRZI is disabled when this input is a logic-HIGH. This function is not affected by the SMPTE mode control input. The input pin is pulled internally to VSS (NRZI enabled) when unconnected. EDH SYSTEM OPERATION The CLC021 has EDH character and flag generation and insertion circuitry which operates as proposed in SMPTE RP-165. Inputs and circuitry are provided to control generation and automatic insertion of the EDH check words at proper locations in the serial data output. The EDH polynomial generators accept parallel data from the input register and generate 16-bit serial check words using the polynomial X16 + X12 + X6 + 1. Separate calculations are made for each video field prior to serialization. Separate CRCs for the full-field and active picture along with status flags are inserted and serially transmitted with the other data. Upon being reset, the initial state of all EDH check characters is 00h. The EDH control system accepts input from the sync detector and controls the EDH polynomial generator and SMPTE/EDH polynomial insertion multiplexer. EDH Enable, an external TTL-compatible, low-true input, enables this circuitry. The controller inserts the EDH check words in the serial data stream at the correct positions in the ancilliary data space per SMPTE 259M paragraph 7.3, 8.4.4 or 9.4.4 and per SMPTE RP-165. Ancilliary data space is formatted per SMPTE 291M. The EDH Force control input causes the insertion of new EDH checkwords and flags into the serial output regardless of the previous condition of EDH checkwords and flags in the input parallel data. This function may be used in situations where video content has been editted thus making the previous EDH information invalid. The NTSC/PAL output indicates the type of component or composite data standard being input to the CLC021. This output is useful for troubleshooting or may be used to drive a panel indicator. The output is high when 625line PAL data is being input and low when 525-line NTSC data is being input. PHASE-LOCKED LOOP AND VCO The phase-locked loop (PLL) system generates the output serial data clock at 10x the parallel data clock frequency. This system consists of a VCO, divider chain, phase-frequency detector and internal loop filter. The VCO free-running frequency is internally set. The PLL automatically generates the appropriate frequency for the serial clock rate using the parallel data clock (PCLK) frequency as its reference. Loop filtering is internal to the CLC021. The VCO halts when no PCLK signal is present or is inactive. PCLK should be applied after power to the device. The VCO has separate VSSO and VDDO power supply feeds, pins 27 and 28, which may be supplied power via an external low-pass filter, if desired. The PLL acquisition (lock) time is less than 75 s @ 270 Mbps. LOCK DETECT The lock detect output (pin 26) of the phase-frequency detector is a logic HIGH when the loop is locked. The output is CMOS/TTL-compatible and is suitable for driving other CMOS devices or an LED indicator. The Lock Detect pin reports the status of the PLL. When PCLK is lost, it will switch low at the event. SERIAL DATA OUTPUT BUFFER The current-mode serial data outputs provide low-skew complimentary or differential signals. The output buffer design can drive 75 coaxial cables (AC-coupled) or 10K/100K ECL/PECL-compatible devices (DC-coupled). Output levels are 800 mVP-P 10% into 75 AC-coupled, back-matched loads. The output level is 400 mVP-P 10% when DC-coupled into 75. (See APPLICATION INFORMATION for details.) The 75 resistors connected to the SDO outputs are back-matching resistors. No series back-matching resistors should be used. Output level is controlled by the value of RREF connected to pin 35. The value of RREF is normally 1.69 k, 1%. The output buffer is static when the device is in an out-of-lock condition. Separate VSSSD and VDDSD power feeds, pins, 37 and 40 are provided for the serial output driver. 10 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: CLC021 CLC021 www.ti.com SNLS068H - MAY 2000 - REVISED APRIL 2013 POWER-ON RESET AND RESET INPUT The CLC021 has an internally controlled, automatic, power-on-reset circuit. Reset clears TRS detection circuitry, all latches, registers, counters and polynomial generators, sets the EDH characters to 00h and disables the serial output. The SDO outputs are tri-stated during power-on reset. The part will remain in the reset condition until the parallel input clock is applied. An active-HIGH-true, manual reset input is available at pin 1. It resets both the digital and PLL blocks. The reset input has an internal pull-down device and is inactive when unconnected. It is recommended that PCLK not be asserted until at least 30 s after power has reached VDDmin. See Figure 5. If manual reset is used during power-on, then PCLK may be asserted at any time as long as manual reset is not de-asserted until VDDmin is reached. See Figure 6. VDDmin VDD VSS 30Ps min PCLK 10% VSS Figure 5. Power-On Reset Sequence VDDmin VDD 0ns min VSS 90% 90% RESET 10% 10% VSS PCLK VSS Figure 6. Power-On Reset Sequence with Manual Reset Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: CLC021 11 CLC021 SNLS068H - MAY 2000 - REVISED APRIL 2013 www.ti.com BUILT-IN SELF-TEST (BIST) The CLC021 has a built-in self-test (BIST) function. The BIST performs a comprehensive go/no-go test of the device. The test uses either a full-field colour bar for NTSC or a PLL pathological for PAL as the test data pattern. Data is input internally in the input data register, processed through the device and tested for errors. A go/no-go indication is given at the Test_Output. Table 1 gives device pin functions and Table 2 gives the test pattern codes used for this function. The signal level at Test_Output, pin 3, indicates a pass or fail condition. The BIST is initiated by applying the code for the desired BIST to D0 through D3 (D9 through D4 are 00h) and a 27 MHz clock at the PCLK input. Since all parallel data inputs are equipped with an internal pull-down device, only those inputs D0 through D3 which require a logic-1 need be pulled high. After the Lock_Detect output goes high indicating the VCO is locked on frequency, TPG_Enable, pin 29, is taken to a logic high. The Lock_Detect output may be temporarily connected to TPG_Enable to automate BIST operation. Test_Output, pin 3, is monitored for a pass/fail indication. If no errors have been detected, this output will go to a logic high level approximately 2 field intervals after TPG_Enable is taken high. If errors have been detected in the internal circuitry of the CLC021, Test_Output will remain low until the test is terminated. The BIST is terminated by taking TPG _Enable to a logic low. Continuous serial data output is available during the test. Figure 7. Built-In Self-Test Control Sequence TEST PATTERN GENERATOR The CLC021 includes an on-board test pattern generator (TPG). Four full-field component video test patterns for both NTSC and PAL standards, and 4x3 and 16x9 raster sizes are produced. The test patterns are: flat-field black, PLL pathological, equalizer (EQ) pathological and a modified 75%, 8-colour vertical bar pattern. The pathologicals follow recommendations contained in SMPTE RP 178-1996 regarding the test data used. The colour bar pattern does not incorporate bandwidth limiting coding in the chroma and luma data when transitioning between the bars. For this reason, it may not be suitable for use as a visual test pattern or for input to video D-toA conversion devices unless measures are taken to restrict the production of out-of-band frequency components. The TPG is operated by applying the code for the desired test pattern to D0 through D3 (D4 through D9 are 00h). Since all parallel data inputs are equipped with internal pull-down devices, only those inputs D0 through D3 which require a logic-1 need be pulled high. Next, apply a 27 MHz or 36 MHz signal, appropriate to the raster size desired, at the PCLK input and wait until the Lock_Detect output goes true indicating the VCO is locked on frequency. Then, take TPG_Enable, pin 29, to a logic high. The serial test pattern data appears on the SDO outputs. The Lock_Detect output may be temporarily connected to TPG_Enable to automate TPG operation. The TPG mode is exited by taking TPG_Enable to a logic low. Table 1 gives device pin functions for this mode. Table 2 gives the available test patterns and selection codes. 12 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: CLC021 CLC021 www.ti.com SNLS068H - MAY 2000 - REVISED APRIL 2013 Figure 8. Test Pattern Generator Control Sequence Table 1. BIST and Test Pattern Generator Control Functions Pin Name 12 D0 TPG Code Input LSB Function 13 D1 TPG Code Input 14 D2 TPG Code Input 15 D3 TPG Code Input MSB 29 TPG_EN TPG Enable, Active High True 3 Test_Out BIST Pass/Fail Output. Pass=High (See text for Timing Requirements) Table 2. Component Video Test Pattern Selection (1) (1) Standard Frame NTSC 4x3 NTSC 4x3 NTSC Test Pattern D3 D2 D1 D0 Flat-Field Black 0 0 0 0 PLL Pathological 0 0 0 1 4x3 EQ Pathological 0 0 1 0 NTSC 4x3 Colour Bars, 75%, 8-Bars (modified, see text), BIST 0 0 1 1 PAL 4x3 Flat-Field Black 0 1 0 0 PAL 4x3 PLL Pathological, BIST 0 1 0 1 PAL 4x3 EQ Pathological 0 1 1 0 PAL 4x3 Colour Bars, 75%, 8-Bars (modified, see text) 0 1 1 1 NTSC 16x9 Flat-Field Black 1 0 0 0 NTSC 16x9 PLL Pathological 1 0 0 1 NTSC 16x9 EQ Pathological 1 0 1 0 NTSC 16x9 Colour Bars, 75%, 8-bars (modified, see text) 1 0 1 1 PAL 16x9 Flat-Field Black 1 1 0 0 PAL 16x9 PLL Pathological 1 1 0 1 PAL 16x9 EQ Pathological 1 1 1 0 PAL 16x9 Colour Bars, 75%, 8-Bars (modified, see text) 1 1 1 1 D9 through D4 = 0 (binary) Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: CLC021 13 CLC021 SNLS068H - MAY 2000 - REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (1) Pin (1) 14 Name Description 1 Reset Manual Reset Input (High True) 2 NRZ-NRZI NRZ-to-NRZI Conversion Control (NRZ=High, NRZI=Low) 3 Test Out Test Out (BIST Pass/Fail Indicator) 4 VSS Negative Power Supply Input (Digital Logic) 5 VSS Negative Power Supply Input (Digital Logic) 6 VDD Positive Power Supply Input (Digital Logic) 7 VDD Positive Power Supply Input (Digital Logic) 8 EDH Force Force Insertion of New EDH and Flags in Serial Output Data (High True) 9 EDH Enable EDH Enable Input (Low True) 10 SMPTE Mode SMPTE/non-SMPTE Mode Select Input (SMPTE Mode=Low) 11 N/C No Connect 12 D0 Parallel Data Input (Internal Pull-Down to VSS) 13 D1 Parallel Data Input (Internal Pull-Down to VSS) 14 D2 Parallel Data Input (Internal Pull-Down to VSS) 15 D3 Parallel Data Input (Internal Pull-Down to VSS) 16 D4 Parallel Data Input (Internal Pull-Down to VSS) 17 D5 Parallel Data Input (Internal Pull-Down to VSS) 18 D6 Parallel Data Input (Internal Pull-Down to VSS) 19 D7 Parallel Data Input (Internal Pull-Down to VSS) 20 D8 Parallel Data Input (Internal Pull-Down to VSS) 21 D9 Parallel Data Input (Internal Pull-Down to VSS) 22 PCLK Parallel Clock Input (Internal Pull-Down to VSS) 23 H/Line-Field b0 (LSB) H-Bit Output (Component); Line-Field ID (Composite) 24 V/Line-Field b1 V-Bit Output (Component); Line-Field ID (Composite) 25 F/Line-Field b2 (MSB) F-Bit Output (Component); Line-Field ID (Composite) 26 Lock Detect Lock Detector Output (High True) 27 VSSO Negative Power Supply Input (PLL Supply) 28 VDDO Positive Power Supply Input (PLL Supply) 29 TPG Enable TPG Enable (High True) 30 VSSOD Negative Power Supply Input (PLL Digital Supply) 31 VSSOD Negative Power Supply Input (PLL Digital Supply) 32 VDDOD Positive Power Supply Input (PLL Digital Supply) 33 VDDOD Positive Power Supply Input (PLL Digital Supply) 34 N/C No Connect 35 RREF Output Level Reference Resistor (1.69 k, 1% Nominal Value) 36 VDDOD Positive Power Supply Input (PLL Digital Supply) 37 VSSSD Negative Power Supply Input (Output Driver) 38 SDO Serial Data True Output 39 SDO Serial Data Complement Output 40 VDDSD Positive Power Supply Input (Output Driver) 41 Sync Detect Enable Parallel Data Sync Detection Enable Input (Low True) 42 NSP New Sync Position Output 43 ANC Ancilliary Data Header Flag Output 44 NTSC/PAL NTSC/PAL Mode Indicator Output (PAL=High, NTSC=Low) All CMOS/TTL inputs have internal pull-down devices. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: CLC021 CLC021 www.ti.com SNLS068H - MAY 2000 - REVISED APRIL 2013 APPLICATION INFORMATION A typical application circuit for the CLC021 is shown in Figure 9. This circuit demonstrates the capabilities of the CLC021 and allows its evaluation in a variety of configurations. Assembled demonstration boards with more comprehensive evaluation options are available, part number SD021-5EVK (5V device) or SD021-3EVK (3.3V device). The boards may be ordered through any of Texas Instruments' sales offices. Complete circuit board layouts and schematics including Gerber photoplot files, for the demonstration boards are available on Texas Instruments' website in the application information for this device. APPLICATION CIRCUIT Figure 9. Typical Application Circuit The SD021EVK application circuit boards, Figure 10, can accommodate different input and output drive and loading options. Pin headers are provided for input and control I/O signal access. Install the appropriate value resistor packs, 220 at RP1 and RP3 and 330 at RP2 and RP4, for TTL cabled interfaces before applying input signals. Install 51 resistor packs at RP2 and RP4 for signal sources requiring such loading. Remove any resistor packs at RP1 and RP3 when using 50 source loading. The board's outputs may be DC interfaced to PECL inputs by first installing 124 resistors at R1B and R2B, changing R1A and R2A to 187 and replacing C1 and C2 with short circuits. The PECL inputs should be directly connected to J1 and J2 without cabling. If 75 cabling is used to connect the CLC021 to the PECL inputs, the voltage dividers used on the CLC021 outputs must be removed and re-installed on the circuit board where the PECL device is mounted. This will provide correct termination for the cable and biasing for both the CLC021's outputs and the PECL inputs. It is most important to note that a 75 or equivalent DC loading (measured with respect to the negative supply rail) must always be installed at both of the CLC021's SDO outputs to obtain proper signal levels from device. When using 75 Thevenin-equivalent load circuits, the DC bias applied to the SDO outputs should not exceed +3V (+1.3V for CLC021AVGZ-3.3) with respect to the negative supply rail. Serial output levels should be reduced to 400 mVp-p by changing RREF to 3.4 k. This may be done by removing the Output Level shorting jumper on the post header. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: CLC021 15 CLC021 SNLS068H - MAY 2000 - REVISED APRIL 2013 www.ti.com The Test Out output is intended for monitoring by equipment having high impedance test loading (>500). If the Lock Detect output is to be externally monitored, the attached monitoring circuit should present a DC resistance greater than 5 k so as not to affect Lock Detect indicator operation. Connect LOCK DETECT to TPG ENABLE for test pattern generator function. Remove RP1 & RP3 and replace RP2 & RP4 with 50 resistor packs for coax interfacing. Install RP1-4 when using ribbon cable for input interfacing. This board is designed for use with TTL power supplies only. Figure 10. SD021EVK Schematic Diagram 16 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: CLC021 CLC021 www.ti.com SNLS068H - MAY 2000 - REVISED APRIL 2013 MEASURING JITTER The test method used to obtain the timing jitter value given in the AC Electrical Specification table is based on procedures and equipment described in SMPTE RP 192-1996. The recommended practice discusses several methods and indicator devices. An FFT method performed by standard video test equipment was used to obtain the data given in this data sheet. As such, the jitter characteristics (or jitter floor) of the measurement equipment, particularly the measurement analyzer, become integral to the resulting jitter value. The method and equipment were chosen so that the test can be easily duplicated by the design engineer using most standard digital video test equipment. In so doing, similar results should be achieved. The intrinsic jitter floor of the CLC021's PLL is approximately 25% of the typical jitter given in the electrical specifications. In production, device jitter is measured on automatic IC test equipment (ATE) using a different method compatible with that equipment. Jitter measured using this ATE yields values approximately 50% of those obtained using the video test equipment. The jitter test setup used to obtain values quoted in the data sheet consists of: * Texas Instruments SD021-5EVK (SD021-3EVK), CLC021 evaluation kit * Tektronix TG2000 signal generation platform with DVG1 option * Tektronix VM700T Option 1S Video Measurement Set * Tektronix TDS 794D, Option C2 oscilloscope * Tektronix P6339A passive probe * 75 coaxial cable, 3 ft., Belden 8281 or RG59 (2 required) * ECL-to-TTL/CMOS level converter/amplifier see Figure 12. Apply the black-burst reference clock from the TG2000 signal generator's BG1 module 27 MHz clock output to the level converter input. The clock amplitude converter schematic is shown in Figure 12. Adjust the input bias control to give a 50% duty cycle output as measured on the oscilloscope/probe system. Connect the level translator to the SD021EVK board, connector P1, PCLK pins (the outer-most row of pins is ground). Configure the SD021EVK to operate in the NTSC colour bars, BIST mode. Configure the VM700T to make the jitter measurement in the jitter FFT mode at the frame rate with 1 kHz filter bandwidth and Hanning window. Configure the setup as shown in Figure 11. Switch the test equipment on (from standby mode) and allow all equipment temperatures stabilize per manufacturer's recommendation. Measure the jitter value after allowing the instrument's reading to stabilize (about 1 minute). Consult the VM700T Video Measurement Set Option 1S Serial Digital Measurements User Manual (document number 071-0074-00) for details of equipment operation. The VM700T measurement system's jitter floor specification at 270 Mbps is given as 200 ps 20% (100 ps 5% typical) of actual components from 50 Hz to 1 MHz and 200 ps +60%, -30% of actual components from 1 MHz to 10 MHz. To obtain the actual residual jitter of the CLC021, a root-sum-square adjustment of the jitter reading must be made to compensate for the measurement system's jitter floor specification. For example, if the jitter reading is 250 ps, the CLC021 residual jitter is the square root of (2502 - 2002) = 150 ps. The accuracy limits of the reading as given above apply. Figure 11. Jitter Test Circuit Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: CLC021 17 CLC021 SNLS068H - MAY 2000 - REVISED APRIL 2013 www.ti.com Figure 12. ECL-to-TTL/CMOS Level Converter/Amplifer 18 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: CLC021 CLC021 www.ti.com SNLS068H - MAY 2000 - REVISED APRIL 2013 Figure 13. Jitter Plots PCB LAYOUT AND POWER SYSTEM BYPASS RECOMMENDATIONS Circuit board layout and stack-up for the CLC021 should be designed to provide noise-free power to the device. Good layout practice also will separate high frequency or high level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic capacitance of the PCB power system which improves power supply filtering, especially at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range 0.01 F to 0.1 F. Tantalum capacitors may be in the range 2.2 F to 10 F. Voltage rating for tantalum capacitors should be at least 5X the power supply voltage being used. It is recommended practice to use two vias at each power pin of the CLC021 as well as all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance by up to half, thereby reducing interconnect inductance and extending the effective frequency range of the bypass components. Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: CLC021 19 CLC021 SNLS068H - MAY 2000 - REVISED APRIL 2013 www.ti.com The outer layers of the PCB may be flooded with additional VSS (ground) plane. These planes will improve shielding and isolation as well as increase the intrinsic capacitance of the power supply plane system. Naturally, to be effective, these planes must be tied to the VSS power supply plane at frequent intervals with vias. Frequent via placement also improves signal integrity on signal transmission lines by providing short paths for image currents which reduces signal distortion. The planes should be pulled back from all transmission lines and component mounting pads a distance equal to the width of the widest transmission line or the thickness of the dielectric separating the transmission line from the internal power or ground plane(s) whichever is greater. Doing so minimizes effects on transmission line impedances and reduces unwanted parasitic capacitances at component mounting pads. In especially noisy power supply environments, such as is often the case when using switching power supplies, separate filtering may be used at the CLC021's VCO and output driver power pins. The CLC021 was designed for this situation. The digital section, VCO and output driver power supply feeds are independent (see and CONNECTION DIAGRAM for details). Supply filtering may take the form of L-section or pi-section, L-C filters in series with these VDD inputs. Such filters are available in a single package from several manufacturers. Despite being independent feeds, all device power supplies should be applied simultaneously as from a common source. The CLC021 is free from power supply latch-up caused by circuit-induced delays between the device's three separate power feed systems. 20 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: CLC021 CLC021 www.ti.com SNLS068H - MAY 2000 - REVISED APRIL 2013 REVISION HISTORY Changes from Revision G (April 2013) to Revision H * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 20 Submit Documentation Feedback Copyright (c) 2000-2013, Texas Instruments Incorporated Product Folder Links: CLC021 21 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) CLC021AVGZ-3.3/NOPB ACTIVE QFP PGB 44 96 RoHS & Green SN Level-3-260C-168 HR 0 to 70 CLC021A VGZ-3.3 CLC021AVGZ-5.0/NOPB ACTIVE QFP PGB 44 96 RoHS & Green SN Level-3-260C-168 HR 0 to 70 CLC021A VGZ-5.0 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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