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November 2017
Rev. 2 .0. 2
1/8 Rev. 2. 0.2
GENERAL DESCRIPTION
The SP809/SP810 are low power
microprocessor (μP) supervisory circuits used
to monitor power supplies in μP and digital
systems.
They provide applications with benefits of
circuit reliability and low cost by eliminating
external components. If the VCC supply
voltage falls below preset threshold then a
reset signal is asserted for at least 140ms
after VCC has risen above the reset threshold.
Both the SP809 and SP810 wer e design ed wit h
a reset comparator to help identify invalid
signals, which last less than 140ms. The only
difference between them is that they have an
active-low RESET output and active-high RESET
output, respectively. Low supply current (1μA)
makes SP809/SP810 ideal for portable
equipment.
The devices are available in 3 pin SOT-23
package.
Part Number Out pu t Type
SP809N
Open Drain Activ e Low
SP809
Push-Pull Low
SP810
Push-Pull Ac tiv e High
APPLICATIONS
Portable Electronic Devices
Electrical Power Meters
Digital Still Cameras
µP Power Monitoring
FEATURES
Ultra Low Supply Current 1µA (typ)
Guaranteed Reset valid to VCC = 0.9V
140ms Power-On Reset Pulse Width
Internally Fixed Threshold
2.3V, 2.6V, 2.9V, 3.1V, 4.4V, 4.6V
1.5% Voltage Threshold Tolerance
3 Pin SOT-23 Package
TYPICAL APPLICATION DIAGRAM
Fig. 1: S P809 / SP810 Applic ation D ia gr am
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2/8 Rev. 2. 0.2
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of
the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may affect
reliability.
VCC .......................................................... -0.3V to 6.5V
RESET, RESET ...................................... -0.3V to VCC+0.3V
Output Curr e nt (RESET, RESET) ............................... 20mA
Power Dissipation (TA=70°C) .............................. 320mW
Junction Temperature .......................................... 125°C
Stor age Temperature .............................. -65°C to 150°C
OPERATING RATINGS
Input Voltage Range VCC ................................ 0.9V to 6V
Junction Temperature Range ..................... -40°C to 85°C
ELECTRICAL SPECIFICATIONS
Specifications with standard type are for an Operating Temperature of TA = 25°C only; limits applying over the full
Operating Temperature range are denoted by a “•”. Minimum and Max imum limits are guaranteed thro ug h test, design, or
statistical c orr elatio n. Typical values repres ent the most likely parametric norm at TA = 25°C, and are prov i de d f or ref ere n c e
purpos es only . U nle ss otherw is e ind icated, TA= 25°C.
Parameter Min. Typ. Max. Units Conditions
Operating Vo ltage Range VCC
0.9
6.0
V
Supply Current ICC
1.0
3.0
µA
VCC=VTH+0.1V
Reset Threshold VTH
2.265
2.3
2.335
V
T
A
=+25°C
2.254
2.346
T
A
=-40°C to 85° C
2.561
2.6
2.639
TA=+25°C
2.548
2.652
TA=-40°C to 85°C
2.857
2.9
2.944
TA=+25°C
2.842
2.958
T
A
=-40°C to 85° C
3.054
3.1
3.147
TA=+25°C
3.038
3.162
TA=-40°C to 85°C
4.334
4.4
4.466
T
A
=+25°C
4.312
4.488
T
A
=-40°C to 85° C
4.531
4.6
4.669
T
A
=+25°C
4.508
4.692
TA=-40°C to 85°C
VCC Reset Delay tTRIP
20
µs
VCC=VTH to (V TH - 0.1V), VTH=3.1V
Rese t Active T imeo ut Period tRP
140
230 560 ms
T
A
=+25°C
100
1030
T
A
=-40°C to 85° C
RESET Output Voltage V
OH
0.8VCC
V
V
CC
=V
TH
- 0.1V, I
SOURCE
= 1.2mA
RESET Output Voltage VOL
0.3
VCC=VTH + 0.1V, ISINK = 1.2mA
RESET
Output Voltage V
OH
0.8VCC
V
V
CC
=V
TH
+ 0.1V , I
SOURCE
= 1 .2 mA
RESET Output Voltage V
OL
0.3
V
CC
=V
TH
- 0.1V, I
SINK
= 1.2mA
Note 1: RESET outp ut is for SP809; RES ET output is for S P810 .
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3/8 Rev. 2. 0.2
BLOCK DIAGRAM
Fig. 2: S P809 / SP810 Block Diagram
PIN ASSIGNMENT
Fig. 3: S P809 / SP810 Pin Assig nme nt
PIN DESCRIPTION
Name P in Numb er Description
Ground S ignal
RESET 2
Active Low O utp ut Pin.
RESET Outp ut rem ains hig h while V CC is belo w the re set threshold
RESET
Active High Output Pin.
RESET Output re mains high while VCC is below the rese t thresho ld
Supply Volta g e
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4/8 Rev. 2. 0.2
ORDERING INFORMATION(1)
Part Number Operating Temperature Range Lead-Free Package Packing Method
SP809EK-L-2-3/TR
-40°C≤TA≤+85°C Yes(2) SOT23-3 Tape & Reel
SP809EK-L-2-6/TR
SP809EK-L-2-9/TR
SP809EK-L-3-1/TR
(3)
SP809EK-L-4-6/TR(3)
SP809NEK-L-2-3/TR
(3)
SP809NEK-L-2-9/TR
(3)
SP809NEK-L-3-1/TR
SP809NEK-L-4-6/TR(3)
SP810EK-L-4-4/TR
(3)
NOTES:
1. Refer to www.exar.com/SP809 and www.exar.com/SP810 for most up-to-date Ordering Information.
2. Visit www.exar.com for add itional inform ation on Environmental R ating.
3. NRND Not Recommen ded for New Designs.
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5/8 Rev. 2. 0.2
TYPICA L P ERFORMANCE CHARACTERISTICS
All data taken at TA = 25°C, unless otherwise specified - Schematic and BOM from Application Information section of this
datasheet.
Fig. 4: Supp ly C urrent versus Temperatur e
Fig. 5: Power-Down Reset Delay versus Temperature
Fig. 6: Power-Down Reset Dela y versu s T emperature
Fig. 7: Power-Down Reset Dela y versu s T emperature
Fig. 8: Norma lize d Reset Threshold vers us Tem perature
Fig. 9: Power-Up Reset Time-out versus Temperatur e
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6/8 Rev. 2. 0.2
THEORY OF OPERATION
μP will be activated at a valid reset state.
These μP supervisory circuits assert reset to
prevent code execution errors during power-
up, power-down, or browno ut conditions.
Reset is guaranteed to be a logic low for
VTH>VCC>0.9V. Once VCC exceeded the reset
threshold, a n in tern a l tim er k eeps RESET low for
the reset timeout period; after this interval,
RESET goes high.
If a brownout condition occurs (VCC drops
below the reset threshold), RESET goes low.
Any time VCC goes below the reset threshold,
the internal timer resets to zero, and RESET
goes low. The internal timer is activated after
VCC returns above the reset threshold, and
RESET remains low for the reset timeout period.
BENEFIT OF HIGHLY ACCURATE RESET
THRESHOLD
SP809/810 with specified voltage as 5V±10%
or 3V±10% are ideal for systems using a
5V±5% or 3V±5% power supply. The reset is
guaranteed to assert after the power supply
falls below the minimum specified operating
voltage range of the system ICs. The pre-
trimmed thresholds are reducing the range
over wh ich an undesirable reset may occur.
Fig. 10: Timing Waveforms
APPLICATION INFORMATION
NEGATIVE GOING VCC TRANSIENTS
In addition to issuing a reset to the µP during
power-up, power-down, and brownout
conditions, SP809 series are relatively
resistant to short-duration negative-going VCC
transient.
ENSURING A VALID RESET OUTPUT DOWN
TO VCC=0
When VCC falls below 0.9V, SP809 RESET output
no longer sinks current; it becomes an open
circuit. In this case, high-impedance CMOS
logic inputs connecting to RESET can drift to
undetermined voltages. Therefore, SP809/810
with CMOS is perfect for most applications of
VCC down to 0.9V.
However in applications where RESET must be
valid down to 0V, adding a pull-down resistor
to RESET causes an y l eak age cu rr ent s to fl ow to
ground, holding RESET low.
INTERFACING TO µP WITH BIDIRECTIONAL
RESET PINS
The RESET output on the SP809N is open drain,
this device interfaces easily with μPs that have
bidirectional reset pins. Connecting the μP
supervisor's RESET output directly to the
microcontroller's RESET pin with a single pull-
up resistor allows either device to assert reset.
TEST CIRCUIT
Fig. 11: Test Circuit
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7/8 Rev. 2. 0.2
PACKAGE SPECIFICATION
3-PIN SOT23
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8/8 Rev. 2. 0.2
REVISION HISTORY
Revision Date Description
2.0.0 2011
Reformat of Datasheet
Correction of package drawing
2.0.1 August 2017
Correct Reset Del ay conditions. Updated to MaxLine ar log o. Upda te d format and
order ing info rmation table.
2.0.2 November 2017
Corrected typo from rev 2.0.1, added 2 missing overlines to RES ET in Electrical
Specifications.
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