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6/8 Rev. 2. 0.2
THEORY OF OPERATION
μP will be activated at a valid reset state.
These μP supervisory circuits assert reset to
prevent code execution errors during power-
up, power-down, or browno ut conditions.
Reset is guaranteed to be a logic low for
VTH>VCC>0.9V. Once VCC exceeded the reset
threshold, a n in tern a l tim er k eeps RESET low for
the reset timeout period; after this interval,
RESET goes high.
If a brownout condition occurs (VCC drops
below the reset threshold), RESET goes low.
Any time VCC goes below the reset threshold,
the internal timer resets to zero, and RESET
goes low. The internal timer is activated after
VCC returns above the reset threshold, and
RESET remains low for the reset timeout period.
BENEFIT OF HIGHLY ACCURATE RESET
THRESHOLD
SP809/810 with specified voltage as 5V±10%
or 3V±10% are ideal for systems using a
5V±5% or 3V±5% power supply. The reset is
guaranteed to assert after the power supply
falls below the minimum specified operating
voltage range of the system ICs. The pre-
trimmed thresholds are reducing the range
over wh ich an undesirable reset may occur.
Fig. 10: Timing Waveforms
APPLICATION INFORMATION
NEGATIVE GOING VCC TRANSIENTS
In addition to issuing a reset to the µP during
power-up, power-down, and brownout
conditions, SP809 series are relatively
resistant to short-duration negative-going VCC
transient.
ENSURING A VALID RESET OUTPUT DOWN
TO VCC=0
When VCC falls below 0.9V, SP809 RESET output
no longer sinks current; it becomes an open
circuit. In this case, high-impedance CMOS
logic inputs connecting to RESET can drift to
undetermined voltages. Therefore, SP809/810
with CMOS is perfect for most applications of
VCC down to 0.9V.
However in applications where RESET must be
valid down to 0V, adding a pull-down resistor
to RESET causes an y l eak age cu rr ent s to fl ow to
ground, holding RESET low.
INTERFACING TO µP WITH BIDIRECTIONAL
RESET PINS
The RESET output on the SP809N is open drain,
this device interfaces easily with μPs that have
bidirectional reset pins. Connecting the μP
supervisor's RESET output directly to the
microcontroller's RESET pin with a single pull-
up resistor allows either device to assert reset.
TEST CIRCUIT
Fig. 11: Test Circuit