July 1992 Rev C S8E D EL2071C/EL2171/EL2171C Features 150 MHz 3 dB bandwidth, Ay = 20 10 ns settling to 0.1% Vs = $5V@15mA 2.5 ns rise/fall times (2V step) Overload/short-circuit protected * +7 to 50 closed-loop gain range Low cost EL2171 is direct replacement for CLC401 * Disable capability on EL2071 Applications Line drivers * DC-coupled log amplifiers High-speed modems, radios High-speed A/D conversion * D/AI-V conversion * Photodiode, CCD preamps IF processors * High-speed communications Analog multiplexing (using disableEL2071) Power down mode (using disableEL2071) Ordering Information Part No. Temp.Range Package Outline# EL2171CN 40C to +85C 8-Pin P-DIP MDP0031 EL2171CS 40C to +85C_8-Lead 50 MDP0027 EL2171J/883B 55C to + 125C 8-Pin CerDIP MDP0010 EL2071CN 40C to +85C 8-Pin P-DIP MDP0031 EL2071CS 40C to +85C &Lead SO MDP0027 EL2071J/883B ~ 55C to + 125C 8-Pin CerDIP MDPO010 me 3329557 OO0e1735 TTS MELA 7407-10 5 ELANTEC INC General Description The EL2071 and EL2171 are wide bandwidth, fast settling monolithic amplifiers built using an advanced complementary bipolar process, The EL2071 has a disable/enable feature which allows power down and analog multiplexing. These amplifiers use current-mode feedback to achieve more bandwidth at a giv- en gain than conventional operational amplifiers. Designed for closed-loop gains of +7 to +50, the EL2071 and EL2171 have a 150 MHz 3 dB bandwidth (Ay = +20), and 2.5 ns rise/fall time, while consuming only 15 mA of supply current. The EL2071 consumes only 1.5 mA when disabled. The wide 150 MHz bandwidth and extremely linear phase (0.2 dB deviation from linear at 50 MHz) allow superior signal fidelity. These features make the EL2071 and EL2171 especially suited for many digital communication system applications. The EL2071s and EL2171s settling to 0.1% in 10 ns and ability to drive capacitive loads make them ideal in flash A/D applica- tions. D/A systems can also benefit from the EL2071 and EL2171, especially if linearity and drive levels are important. Elantec products and facilities comply with MIL-STD-883 Re- vision C, MIL-I-45208A, and other applicable quality specifica- tions. For information on Elantecs military processing, see Elantec document, Q@RA-2: Elantecs Military Processing, Monolithic Integrated Circuits. Connection Diagrams EL2171 EL2071 DIP and SO Package DIP and SO Package ar N/ ne [1] [3 ]nc ne [1] [6 | DISABLE in- [2 7] v+ in- [2] [7] v+ ine [3] [Jour we 6] our v- [a fs ]nc v-[] rs] nc 2074-1 2071-2 Top View Top View 1-186ML ANTEC INC S6E D MM 3329557 0002174 931 MELA fe eS bo Q ] ay OQ ~ E Absolute Maximum Ratings (1, = 25) bt Supply Voltage (Vs) 7V Lead Temperature 3 Output Current Output is short-circuit protect- DIP Package 300C ~ ed to ground, however, maxi- (Soldering: <5 Seconds-CN; ey mum reliability is obtained if <10 Seconds-J) 5 Tour does not exceed 70 mA. SO Package a Common Mode Input Voltage #Vs Vapor Phase (60 Seconds) 215C = Differential Input Voltage sv Infrared (15 seconds) 220C Q Power Dissipation See Curves : : : Operating Junction Temperature Operating Temperature c ic Packages 175C EL2171 55C to +125C Plate? . a6 50C EL2171C/EL2071C 40C to +85C astic Packages Storage Temperature 60C to + 150C Open Loop DC Electrical Characteristics Vs = +5V, Ry = 1000, unless otherwise specified Parameter | Description Test Tem Min | Typ | Max Units P Conditions P Vos Input Offset Voltage 25C 3 6 mV Twin, Tmax 10 mV TC Vos Average Offset (Note 1) it 0 50 Vi" Voltage Drift A 2 BEC +i + Input Current 25C, Tax 10 20 BA TMIN 36 BA TC (+]yn) Average + Input (Note 1) AN 100 200 nA? Current Drift iy ~ Input Current 25C 10 30 pA TMIN 46 BA Tax 40 pA TC (Iyy) Average Input (Note 1) all 100 200 A/C Current Drift 1-187S8E D MM 3129557 0002175 478 MELA mms EL ANTEC INC = Open Loop DC Electrical Characteristics Vs = 5V, Ry = 1000, unless otherwise specified Contd. Test Parameter Description Conditions Temp Min | Typ | Max Power Supply (Note 2) Rejection Ratio EL2071C/EL2171/EL2171C All Common-Mode All Rejection Ratio Supply Current No Load All Quiescent ! Supply Current EL2071C All Disabled (Note 3) + Input Resistance 25C, Tax TMIN Capacitance All Output Resistance (DC) All Output Resistance (DC) EL2071C I Disabled All Output Capacitance (DC) | EL2071C Disabled All Common-Mode Input (Note 4) 25C, TMax Range Tin lout Output Current 25C, Tmax TMIN Vour Output Voltage Swing 25C, Tmax TMIN Vout, Output Voltage Swing Ry = 1000 25C Roi Transimpedance 25C TLoaic Pin 8 Current @+ 5V EL2071C All VpIs Minimum Pin 8 EL2071C 25C V to Disable TMIN TMAX Maximum Pin 8 EL2071C V to Enable All Minimum Pin 8 EL2071C I to Disable All Maximum Pin 8 EL2071C Ito EnableS54E Dd = Jbe855? _Podel?s eO4 MBELA mu ELANTEC INC Closed Loop AC Electrical Characteristics Vg = 5V,Rp = 15k, Ay = +20, Ry = 1002 unless otherwise specified Parameter Description Test Conditions Temp Min Typ Max Units SSBW LSBW GFPL GFPH GFR LPD FREQUENCY RESPONSE 3 dB Bandwidth (Your <2.0 Vpp) 3 dB Bandwidth (Vour < 5.0 Vpp) GAIN FLATNESS Peaking Vout < 2.0 Vpp Peaking Rolloff Vout < 2.0 Vpp Linear Phase Deviation Vout < 2.0 Vpp TIME-DOMAIN RESPONSE ter th Rise Time, Fali Time tra, tee Rise Time, Fall Time ts Settling Time to 0.1% Os Overshoot SR Slew Rate DISTORTION HD2 2nd Harmonic Distortion @20 MHz HD3 3rd Harmonic Distortion @20 MHz 25C TMIN TMax 70 25C,Tyin | 65 Tax 55 25C Tins TMAx 25C Tin; TMAxX 25C TMIN TMAX <50 MHz 25C, TMIN TMax 2.0V Step 25C, Twn TMAX 5.0V Step 25C, Twn TMax 2.0V Step All 2.0V Step All 25C, Twn 800 TwMax 700 25C Tin: TMAX 25C TMIN TMax 10 0 1200 MHz MHz MHz dB ns ns ns ns ns % V/ ps V/us dBc dBc dBc dBc dBe 1-189 OLLI@TH/TL1@TH/OLL0e TaS6E D MM 3129557 GO0217?7 bYO MmMELA muummmems ELANTEC INC | ee Closed Loop AC Electrical Characteristics Vg = 5V, Rp = 15k, Ay = +20, Ry = 100M unless otherwise specified Contd. us Test Parameter Description Conditions Temp | Min | Typ Units EQUIVALENT INPUT NOISE NF EL2071C/EL2171/EL2171C Noise Floor > 100 kHz dBm (1 Hz) dBm (1 Hz) dBm (1 Hz) Integrated Noise 100 kHz to 200 MHz BV uv uv DISABLE/ENABLE PERFORMANCEEL2071C Torr Vout = 2 Vpp 20 MHz Disable Time All 70 200 ns to >40dB Ton Enable Time All 40 100 ns Iso Off Isolation 20 MHz All 50 55 dB Note 1: Measured from Tygqn to Tax: Note 2: PSRR is measured at Vg = +4.5V and Vg = +5.5V. Both supplies are changed simultaneously. Note 3: Supply current when disabled is measured at the negative supply. Note 4: Common-Mode Input Range for Rated Performance. 1-190S6E D MM 3129557 uo02178 5&8? MELA mmm ELANTEC INC Eo MAGNITUDE (NORMALIZED) (a8) TRANSIMPEDANCE (V/mA)} PSRR (dB) oO 72 Wk 0k lo) sO 0 i) 0 00k 1M OM Non-Inverting Frequency Response GAIN FREQUENCY (Hz) Open-Loop Transimpedance Gain and Phase LUA TT AR Li TCC TINY el HES 1M OM FREQUENCY (Hz) Single Power Supply Rejection Ratio Vg = 45V Veppie = 100mv FREQUENCY (Hz) PHASE () PHASE () MAGNITUDE (NORMALIZED) (dB) MAGNITUDE (48) CMRR (dB) 2 4 +4 -8 0 2 6 10K IM 10M Typical Performance Curves Inverting Frequency Response GAIN ne 360 270 g PHASE () iM 10M FREQUENCY (Hz) Frequency Response, Ay = -1, Rp = 25 k0 GAIN PHASE () i 10M FREQUENCY (Hz) Common Mode Rejection Ratio (Ay = + 20) FREQUENCY (Hz) MAGNITUDE (dB) NOISE VOLTAGE (nv/VHz') Rg (0) Frequency Response for Various Ris GAIN ~ & my = =x a FREQUENCY (Hz) Equivalent Input Noise 100 100 50 50 f: = ~~ 20 20 a e 0 0 6 & 5 5 2 be wi 2 2 ey il 2 2 1 1 10 hk 10k 100k 1M 10M 100M FREQUENCY (Hz) Recommended Rg vs Load Capacitance 100 1000 LOAD CAPACITANCE (pF) 2071-3 1-191 OTLIGTSE/ TLIC TA /OLL0t TaSe A S6E D MM 3329557? 0002179 413 MELA EL2071C/EL2171/EL2 (150 MHz Current Feedback Amplifier 17 DISTORTION (dB) a ELANTEC INC Typical Performance Curves Contd. 2nd and 3rd Harmonic Distortion 100k 2 Vpp INTO 1002, 1M 10M FREQUENCY (Hz) INPUT VOLTAGE 0.1V/div INPUT VOLTAGE 0.1V/div Pulse Response Ay = Pulse Response Ay = + 20 2-Tone 3rd Order Intermodulation Intercept INTERCEPT POINT (+dBm) Qo 2 4 ou oa mW FREQUENCY (MHz) 2071-4 AIP/Ab'0 ADVLIOA LNdLNO 1 ns/div AID/Ab0 SDVLIOA LNdLNO 1ns/div56E D MM 3129557 0 0135 GHELA ea ELANTEC INC es ee TS] So a] _ OQ kx NS | . me Typical Performance Curves Contd. ne Disabled Attenuation vs 5 Forward and Reverse Gain Time for Various bend during DisableEL2071C Output LevelsEL2071C ~ -20 wy = tf PINS 50 aq 7 oe 40 a bo z mt gq - a z & -50 OQ % -w E 2 -100 5 So ~60 120 10K 1M 10M 100M 2 100 1000 19000 FREQUENCY (Hz) TIME (ns) 2071-7 Disable ResponseEL2071C +1 wi og go n Zo 5 3 fn r 5 i a1 4 5 5 m 0 10 ns/div Time (ns) 2074-8 Enable ResponseEL2071C _ i % o < S mo wo w o | m > < FE > a-1 4 5 > 3 5h 0 10 ns/div Time (ns) 2071-9 1-193S8E D MM 3329557 0002141 O71 MBELA es EL ANTEC INC a Typical Performance Curves Contd. EL2071C/EL2171/EL2171C 8-Lead SO 8-Lead Plastic DIP 8-Lead CerDIP Maximum Power Dissipation Maximum Power Dissipation Maximum Power Dissipation vs Ambient Temperature vs Ambient Temperature vs Ambient Temperature 5.0 50 5.0 Ty MAX = 150C Ty MAX = 150C Ty MAX = 175C Ojo = 45C /W Bio = 50C/W ~ iq = 40C/W a a = 4 ay =175c/w] = 4 6, =95ec/w] = 4 Oj, = 125C/W 30 | g 3.0 | g 3.0 = - Ke A = L INFINITE = L INFINITE = INFINITE - 9 HEAT SINK % HEAT SINK 8 HEAT SINK a wy wo a 20 sy | 5B 20 SJ ' a 20 me \ 4 a IN = |, FREE AIR = FREE AIR = o 10 NO HEAT 2 1.0 NO HEAT a2 10 SINK SINK Rea a J hy | i NO HEAT SINK 0 0 0 3 6 B 8 3B 8&6 6B DB 6 6 FB B86 7 TEMPERATURE (C) TEMPERATURE (C) TEMPERATURE (C) 2071-10 2071-11 2071-42 Equivalent Circuit Qg DISABLE 6 pO OUT Q3 _ < Ris iN= 2 v= 90 > 2071-13 1-194S8E D MM 3129557 000e14e TOS MELA Mmmm = ELANTEC INC Burn-In Circuit 2071-14 ALL PACKAGES USE THE SAME SCHEMATIC. Applications Information Theory of Operation The EL2071/EL2171 have a unity gain buffer from the non-inverting input to the inverting in- put. The error signal of the EL2071/EL2171 is a current flowing into (or out of) the inverting in- put. A very small change in current flowing through the inverting input will cause a large change in the output voltage. This current ampli- fication is called the transimpedance (Roz) of the EL2071/EL2171 [Vour = (Roi) * (hw). Since Roz is very large, the current flowing into the inverting input in the steady-state (non-slew- ing) condition is very small. Therefore we can still use op-amp assumptions as a first-order approximation for circuit analysis, namely that: 1. The voltage across the inputs is approximately Ov. 2. The current into the inputs is approximately 0 mA. Resistor Value Selection and Optimization The value of the feedback resistor (and an inter- nal capacitor) sets the AC dynamics of the EL2071/EL2171. The nominal value for the feed- back resistor is 1.5 kM, which is the value used for production testing. This value guarantees stability. For a given closed-loop gain the band- width may be increased by decreasing the feed- back resistor and, conversely, the bandwidth may be decreased by increasing the feedback resistor. Reducing the feedback resistor too much will re- sult in overshoot and ringing, and eventually os- cillations. Increasing the feedback resistor results in a lower 3 dB frequency. Attenuation at high frequency is limited by a zero in the closed-loop transfer function which results from stray capaci- tance between the inverting input and ground. Consequently, it is very important to keep stray capacitance to a minimum at the inverting input. Capacitive Feedback The EL2071/EL2171 rely on their feedback resis- tor for proper compensation. A reduction of the impedance of the feedback element results in less stability, eventually resulting in oscillation. Therefore, circuit implementations which have capacitive feedback should not be used because of the capacitors impedance reduction with fre- quency. Similarly, oscillations can occur when us- ing the technique of placing a capacitor in paral- lel with the feedback resistor to compensate for shunt capacitances from the inverting input to ground. 1-195 OLLI TA/TL12 TH /OLL06 TahEL2071C/EL2171/EL2171C S6E D MM 312259557 0002183 944 MELA n Feedback EEE es EL ANTEC INC Applications Information Contd. Printed Circuit Layout As with any high frequency device, good PCB layout is necessary for optimum performance. Ground plane construction is a requirement, as is good power-supply bypassing close to the pack- age. The inverting input is sensitive to stray ca- pacitance, therefore connections at the inverting input should be minimal, close to the package, and constructed with as little coupling to the ground plane as possible. Capacitance at the output node will reduce stabil- ity, eventually resulting in peaking, and finally oscillation if the capacitance is large enough. The design of the EL2071/EL2171 allow a larger ca- pacitive load than comparable products, yet there are occasions when a series resistor before the ca- pacitance may be needed. Please refer to the graphs to determine the proper resistor value needed. Disable/Enable Operation for EL2071C The EL2071C has a disable/enable control input at pin 8. The device is enabled and operates nor- mally when pin 8 is left open or returned to ground. When the voltage at pin 8 is brought to within 0.4V of pin 7 (Vg+), the EL2071C is dis- abled. The output becomes a high impedance, the inverting input is no longer driven to the positive input voltage, and the supply current is reduced to less than 2.2. mA. There are internal resistors which limit the current at pin 8 to a safe level (~ 500 uA) if pin 8 is shorted to either supply. Typically, analog and digital circuits should have separate power supplies. This usually leads to slight differences between the power supply volt- ages. The EL2071Cs disable feature is dependent on the voltage at pins 8 and 7. Therefore, to oper- ate the disable feature of the EL2071C depend- ably over temperature, it is recommended that the logic circuitry which drives pin 8 of the EL2071C operate from the same +5V supply as the EL2071C to avoid voltage differences be- tween the digital and analog power supplies. Since Vpys is temperature dependent, it is recom- mended that 5V CMOS logic (with a Voy > 4.6V sourcing > 750 4A over temperature) be used to drive the disable pin of the EL2071C. When disabled, (as well as in enabled mode), care must be taken to prevent a differential voltage between the + and inputs greater than 5.0V. For example, in the figure below, the EL2071C is connected in a gain of +7 configuration and is disabled while the analog bus is driven externally to +5V. Pin 2 is consequently at +0.71V, and if Vin is driven to 5V, then 5.71V appears be- tween pins 3 and 2. Internally, this voltage ap- pears across a forward biased Vyx, in series with a reverse biased Vpx and is past the threshold for zenering the reverse biased Vgr. In a typical ap- plication, a 502 or 7529. terminating resistor from pin 3 to ground will prevent pin 3 from approach- ing 5V. ANALOG BUS 2071-15 1-196S8E D MM 3129557 0002184 880 MELA EL2071C/EL2171/EL2171C_ 150 MHz Current Feedback Amplifier MMMM ELANTEC INC ee Applications Information Contd. Using the EL2071C as a Multiplexer An interesting use of the enable feature is to com- bine several amplifiers in parallel with their out- puts in common. This combination then acts sim- ilar to a MUX in front of an amplifier. A typical circuit is shown. The series resistance at each out- put helps to further increase isolation between amplifiers. Rs OTLI@TH/TL12TA/OLL0e Ta When the EL2071C is disabled, the DC output impedance is > 100 kQ in parallel with 2 pF ca- pacitance. SN@ SOTYNY To operate properly, the decoder that is used must have a Voy > (Vg+) 0.4V with Igy = 750 wA, and should be connected to the same power supply as the EL2071C. 1 OF 8 DECODER 74FCT138 NDMP NAO 9900000 2071-16 1-197568 D MB 3129557 0002185 71? MELA a ELANTEC INC EL2071 Macromodel * Revision A. March 1992 * Enhancements include PSRR, CMRR, and Slew Rate Limiting EL2071C/EL2171/EL2171C * Connections: + input . | ~input * | | + Vsupply . ne Vsupply * | | | | output * Poof fT ssubckt M2071 3 2 7 4 6 * Input Stage * e1 1003010 vis 109 0V h2 9 12 vxx 1.0 r12112 111112 InH iinp 30 10nA iinm 20 10KA * * Slew Rate Limiting . *h1 130 vis 1K h1 13 0 vis 600 r2 13 14 100 di 140 dclamp d2 0 14 dclamp * High Frequency Pole * *e2 30:0 14 0 0,00166666666 e2 300 140 0.001 13 30 17 1.0,H c51700.1pF 15170500 * Transimpedance Stage * g10181701.0 rol 18 0 1Meg cdp 18 0 0.88pF * * Output Stage * ql 41819 qp q2 7 18 20 qn q3 71921 qn a4 4 20 22 ap 17 2162 18 2262 | 1-198S6E D MM 3229557 0002146 53 MELA mus EL ANTEC INC ee EL2071 Macromodel Contd. jos17192.5mA ios2 20 4 2.5mA * * Supply Current * ips 749mA OULT@TA/TL16 Tah /OTLOG TH * Error Terms + ivos 0 23 3mA vxx 23 0 0V e4 240601.0 e5 2507010 e6 260401.0 r9 24 23 316 r10 25 23 562 rll 26 23 562 * * Models * -model qn npn (is = 5e15 bf = 500 tf= 0.05nS) -model qp pnp (is = 5e 15 bf = 500 tf= 0.05nS) -model dclamp d(is = le 30 ibv= 1pA bv= 3.5 n=4) ends 1-199S58E D MM 3129557 oodel8? sat MELA o Te 4 /TIT 2 2] BL2071C/EL2171/EL2. aL (150 MHz Current. Feedback Amplifier Us 5 a eLANTEC INC ~~ 3 EL2071 Macromodel a 2, OQ E a | int 10 13 72 4 30 Ra]: te ht ww 2 POM 1-200