PIC18F67J60-I/PT - Microchip Technology

PIC18F97J60 FAMILY

The PIC18F97J60 family parts you have received

conform functionally to the Device Data Sheet

(DS39762D), except for the anomalies described

below. Any Data Sheet Clarification issues related to

the PIC18F97J60 family will be reported in a separate

Data Sheet errata. Please check the Microchip web site

for any existing issues.

The following silicon errata apply only to

PIC18F97J60 family devices with these

Device/Revision IDs:

1. Module: Resets

MCLR and BOR Resets behave as a POR Reset.

Special Function Registers’ Reset values after a

MCLR or BOR would have the same values as

those after a POR. All other Resets behave as

describ ed in the data shee t.

Work around

None.

Date Codes that pertain to this issue:

All engineering and production devices.

2. Module: I/O (PORTJ)

When configured to operate in Microcontroller

mode (CONFIG3L<EMB1:0> = 11), PORTJ pins

do not go to a high-impedance state immediately

after a POR Reset. Instead, PORTJ<4,0> are

driven low, while all other PORTJ pins are driven

high, until the device exits the Reset condition

(refer to Section 4.5.1 “Time-out Sequence” of

the Device Data Sheet for details on when device

exits Reset condition) before transitioning to a

high-impedance state. Note that since MCLR and

BOR Resets are also treated as a POR Reset (see

errata issue #1), PORTJ pins will also be driven as

outputs until the device exits these Reset

conditions.

Work around

If using a PORTJ pin as an input, make sure to

check that your c ircuit w ill not cre ate a short -circuit

condition during a Reset. For example, if you need

to have a direct pull-down to ground input, do this

on PORTJ<4> or PORTJ<0>, since they are

temporary driven low. If using a PORTJ pin as an

output, then use a pin that will temporarily drive

low for dri ving active-high loads, and use a p in that

temporarily will drive high for driving active-low

loads. This way, the temporary output signals are

in the Idle state.

Date Codes that pertain to this issue:

All engineering and production devices.

Part Number Device ID Revision ID

PIC18F66J60 0001 1000 000 00000

PIC18F66J65 0001 1111 000 00000

PIC18F67J60 0001 1111 001 00000

PIC18F86J60 0001 1000 001 00000

PIC18F86J65 0001 1111 010 00000

PIC18F87J60 0001 1111 011 00000

PIC18F96J60 0001 1000 010 00000

PIC18F96J65 0001 1111 100 00000

PIC18F97J60 0001 1111 101 00000

The Devic e IDs (DEVID1 an d DEVID2 ) are located at

addresses 3FFFFEh:3FFFFFh in the device’s

configuration space. They are shown in binary in the

format “DEVID2 DEVID1”.

Note: This issue is only applicable to the

100-pin dev ic e.

PIC18F97J60 Family Rev. A0 Silicon Errata

PIC18F97J60 FAMILY

3. Module: I/O (PORTJ) and External

Memory Bus

In an Extended Microcontroller mode

(CONFIG3L<EMB1:0> = 00, 01 or 10), each

control signal on PORTJ is supposed to be driven

to its Idle state. However, the control signals on

PORTJ pins go to a high-impedance state for a

brief i nte rval after a MC LR R eset. The brief lo ss of

control si gnals may cause the corrupti on of data in

memory devices connected to the External

Memory Bus (EMB).

Work around

To maintain the default states on the control lines,

use pull-up or pull-down resistors on all PORTJ

pins (pull-down on PORTJ<4,0>, pull-up on all

others).

Date Codes that pertain to this issue:

All engineering and production devices.

4. Module: Etherne t (Buffer Memory)

The receive hardware may corrupt the circular

receive buffer (including the Next Packet Pointer

and receive status vector fields) when an even value

is programmed into the ERXRDPTH:ERXRDPTL

registers.

Work around

Ensure that only odd addresses are written to the

ERXRDPT registers. Assuming that ERXND con-

tains an odd value, many applicat ions can de rive a

suitable value to write to ERXRDPT by subtracting 1

from the Next Packet Pointer (a value always

ensur ed to be even be cause o f hardw are paddin g)

and then compensating for a potential ERXST to

ERXND wraparound.

Assuming that the receive buffer area does not

span the 1FFFh to 0000h memory boundary, the

logic in Example 1 will ensure that ERXRDPT is

programmed with an odd value.

EXAMPLE 1:

Date Codes that pertain to this issue:

All engineering and production devices.

Note: This issue is only applicable to the

100-pin dev ic e.

if (Next Packet Pointer – 1 < ERXST) or

(Next Packet Pointer – 1 > ERXND)

then:

ERXRDPT = ERXND

else:

ERXRDPT = Next Packet Pointer – 1

PIC18F97J60 FAMILY

5. Module: Ethernet (MIIM)

When writing to a ny PHY register through the MIIM

interface’s MIWRL and MIWRH registers, the low

byte actually written to the PHY register may be

corrupted. The corruption occurs when the

following actio ns are taken:

• The application writes to MIWRL

•The PIC

® MCU core executes any instruction

that reads or writes to any m emory address th at

has the Le ast Significant six ad dress bits of 36h

(‘b110110)

• The application writes to MIWRH

For example, the following sequence will result in

a corrupted write to a PHY register:

In this example, 0xCF5 and 0xCF6 are GPR

memory locations that the application wishes to

write to the current PHY register defined by the

MIREGADR SFR. When the PIC MCU core

reads from the GPR at address 0xCF6

(‘b110011110110), the value or iginal ly writt en to

MIWRL will be corrupted.

Work around 1

Ensure that following a write to MIWRL, the firm-

ware do es not a cc es s a ny of th e problem me mo ry

locations prior to writing to MIWRH. After finished

writing to MIWRH, normal operation can resume.

If interrup ts a re enabled , disable t hem prior to wr it-

ing to MIWRL and MIWRH to prevent an Interrupt

Service Routine (ISR) from performing any reads

or writes to a problem memory address.

Special care must be taken to ensure that the

source data to be written to MIWRH does not

result in a problem memory access.

The following PHY write sequence avoids the

problem:

1. Copy the low byte, to be written to the PHY, into

the PRODL register.

PRODL is at address FF3h and not subject to

the memory address issue.

2. Copy the high byte, to be written to the PHY,

into the PRODH register.

PRODH is at ad d r es s FF4 h and no t su bj ec t to

the memory address issue.

3. Disable all interrupts by clearing GIEH and

GIEL in the INTCON regist er.

4. Move PRODL into MIWRL.

5. Wait one instruction cycle, as required by the

MAC host inte rfac e log ic .

6. Move PRODH into MIWRH.

7. Enable all interrupts that are needed by

restoring GIEH and GIEL in INTCON.

Work around 2

If you cannot disable interrupts, as specified in

Work around 1, because the application cannot

tolerate interrupt latency variations:

• Perform the write (with interrupts enabled), but

• Verify the correct valu es were wr itte n by

reading the PHY register

If a cor rupted v alue was writte n due to a n interru pt

occurring, perform the write again and reverify.

The source data must be stored in a non-problem

location.

The application should follow the following

procedure:

1. Copy the low byte, to be written to the PHY, into

the PRODL register.

PRODL is at address FF3h and not subject to

the memory address issue.

2. Copy the high byte, to be written to the PHY,

into the PRODH regi ste r.

PRODH i s at ad d res s F F4h an d no t su bj e ct to

the memory address issue.

3. Move PRODL into MIWRL.

4. Wait one instruction cycle, as required by the

MAC host interface logic.

5. Move PRODH into MIWRH.

6. Wait two TCY and then poll the BUSY bit

(MISTAT<0>) until it is clear.

7. Perform a PHY register read of the same

location.

8. Comp are the read result with the ori ginal valu e

copied t o the PRODH:PROD L registers. I f they

do not match, return to step 1.

Date Codes that pertain to this issue:

All engineering and production devices.

6. Module: Ethernet (RX Filter)

When enabled, the Pattern Match receive filter

may allow some packets with an incorrect data

pattern to be received. Also, in certain configura-

tions, packets with a valid pattern may be

incorrectly discarded.

Work around

Do not use the Pattern Match hardware filter.

Instead, u se th e Uni cast, Mutl icast , Br oadca st an d

Hash Table receive filters to accept all needed

packets and filter out unwanted ones in software.

Date Codes that pertain to this issue:

All engineering and production devices.

MOVFF 0xCF5, MIWRL

NOP

MOVFF 0xCF6, MIWRH

PIC18F97J60 FAMILY

7. Module: Ethernet (TX)

When configured for half duplex and a transmit

operation encounters unusual collision timing,

there is a small chance that the Ethernet transmit

engine will internally deadlock. The PHY will stop

transmitting the packet and normal RX operations

will continue. However, the TXRTS bit

(ECON1<3>) will stay set indefinitely. The TXIF

(EIR<3>) and TXERIF (EIR<1>) bits will not

become set.

This deadlock condition applies only to half-duplex

operation and is most readily observable when the

network has a duplex mismatch (i.e., PIC18F97J60

family device is configured for half duplex and the

remote node is configured for full duplex). In most

cases, high netw ork utilization is needed to observe

the issue.

Work around

To prevent most transmit deadlock conditions,

issue a TX Logic Reset prior to transmitting each

packet:

1. Set TXRST (ECON1<7>)

2. Clear TXRST

3. Wait 1.6 μs or longer

4. Set TXRTS to start the transmission.

Issuing a TX Logic Reset may cause the Ethernet

transmit erro r interrupt to oc cur and the a ssociated

TXERIF bit to become set, which can be ignored.

To detect and recover from any possible deadlock

conditions, applications should implement a timer to

poll the TXRTS bit. If the Ethernet hardware enters

the deadlock state and fails to clear this bit by the

time the timer expires, software should manually

clear the TXRTS bit, issue a TX Logic Reset and

then set the TXRTS bit to retry transmission. The

timer should be cle ared and restarted whenever the

application sets TXRTS. The timer expiration time

should be chosen to allow adequate time for

ordinary packets to finish transmitting, after

accounting for possible delays due to the medium

being occupied by other nodes. For example, a

time-out value of 3 ms is suit able since it will allow a

maximum length 1518-byte packet to be transmit-

ted at 10Base-T speeds while giving reasonable

margin to acco unt for potential coll isions .

Date Codes that pertain to this issue:

All engineering and production devices.

8. Module: Ethernet (DMA )

When the DMA is configured to compute an IP

checksum, there is a small chance that an incom-

ing packet receive event will cause the DMA to

internal ly deadlock. In th ese cases, the DMAST bit

(ECON1<5>) stays set indefinitely, and the DMA

done interrupt never occurs.

Work around

Perform checksum calculations in software. Use

the DMA only for copy operations.

Date Codes that pertain to this issue:

All engineering and production devices.

9. Module: I/O (PORTJ)

The weak internal pull-up resistors on pins RJ4

and RJ5 cannot be enabled on the PIC18F86J60,

PIC18F86J65 and PIC18F87J60 devices. Setting

the RJPU bi t (POR TA<7>) has no e ffe ct on the I/O

pin state.

Work around

Install external pull-up resistors on RJ4 and RJ5.

Alternatively, use any of the PORTB, PORTD or

PORTE pin s whic h all ha ve weak i nternal pull ups .

Date Codes that pertain to this issue:

All engineering and production devices.

Note: This issue is only applicable to the

80-pin device.

PIC18F97J60 FAMILY

REVISION HISTORY

Rev A Document (9/2006)

Original version of this document. Includes silicon

issues 1 (Resets), 2 (I/O – PORTJ), 3 (I/O (PORTJ) and

External Memory Bus), 4 (Ethernet – Buffer Memory)

and 5 (Ethernet – PHY).

Rev B Document (2/2007)

Modified issue 5 (Ethernet – PHY) and added issue 6

(Ethernet – Buffer Memory).

Rev C Document (6/2007)

Removed previous silicon issues 5 (Ethernet – PHY)

and 6 (Ethernet – Buffer Memory). Added new silicon

issues 5 (Ethernet – MIIM) and 6 (Ethernet – RX

Filter).

Rev D Document (6/2008)

Added new silicon issues 7 (Ethernet – TX),

8 (Ethernet – DMA) and 9 (I/O – PORTJ).

PIC18F97J60 FAMILY

NOTES:

Information contained in this publication regarding device

applications and the like is p ro vid ed only for yo ur con ve nience

and may be supers eded by updat es . It is y our res po ns i bil it y to

ensure that your application meets with your specifications.

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