ANALOG DEVICES FEATURES Low Cost Fast Settling: 100ns Low Power Dissipation Low Feedthrough: %LSB @ 200kHz Full Four-Quadrant Multiplying APPLICATIONS Battery Operated Equipment Low Power, Ratiometric A/D Converters Digitally Controlled Gain Circuits Digitally Controlled Attenuators CRT Character Generation Low Noise Audio Gain Control GENERAL DESCRIPTION The AD7523 is a low cost, monolithic multiplying digital-to- analog converter packaged in a 16-pin DIP. The device uses an advanced monolithic, thin-film-on-CMOS technology to pro- vide 8-bit resolution with accuracy to 10-bits and very low power dissipation. The AD7523s excellent multiplying characteristics and low cost allow it to be used in a wide ranging field of applications such as: low noise audio gain control, CRT character genera- tion, motor speed control, digitally controlled attenuators, etc. ORDERING INFORMATION Model Linearity Package Teraperacure Range AD7523)N 21/2L5B AD7523KN- +1/4LSB. F PIN te, 470C AD7523LN#1/8LSB OP stic CMOS 8-Bit Multiplying D/A Converter ae FUNCTIONAL DIAGRAM 10k 10k 10k VaerF 20k 20k 20k 20k 20k i eo I O OUT2 | \ 1 0UTI ' [20% 4 WAO RreepBack BiT 8 (LSB) I I t | ! i | ! | i | | ! | | i I I 6 BIT use BIT 2 2 3 DIGITAL INPUTS PIN CONFIGURATION ouT1 =n 16] Reeeogack our2 [2] 15] Vac IN GND By 14] Vop (+) BiT 1 (MSB) [4] 1345 NC sit2 [5] 12] Nc ait 3 L&] 11] BIT 8 (LSB) BIT 4 7 10} BT 7 gaits [8] [9] sits TOP VIEW D/A CONVERTERS 313 SPECIFICATIONS (Vopp = +15V, Vrer = +10V unless otherwise noted) PARAMETER Ta = +25C Ta = 0 to 470C TEST CONDITION STATIC ACCURACY Resolution 8 Bits min 8 Bits min Nonlinearity! AD7523JN +1/2LSB max (+0.2% FSR max) +1/2LSB max (40.2% FSR max) Vouri = Yout2 = OV AD7523KN +1/4LSB max '+0.1% FSR max) +1/4LSB max (+0.1% FSR max) AD7523LN +1/8LSB max -+0.05% FSR max) +1/8LSB max (+0.05% FSR max) Monotonicity Gain Error! >? Power Supply Rejection (Gain)!:? Output Leakage Current Guaranteed over 0 to +70C -1.5% of FSR nin, +1.5% of FSR max 0.02% per % max -1.8% of FSR min, +1.8% of FSR max 0.03% per % max Vout = Yourz2 = OV Digital Inputs = Ving Vpp =+14Vto+15V Digital Inputs = Vingy louri (pin 1) +50nA max +200nA max Vouti = Yout2 = OV: Veer = t10V ; Digital Inputs = Viyy lout2 (pin 2) +50nA max +200nA max Vouti = Your2 = OV: Veer = F10V Digital Inputs = Viniy DYNAMIC PERFORMANCE Output Current _ Settling Time? 150ns max 200ns max To 0.2% FSR, Load = 100Q Digital Inputs = Viyqy to Viny OF / og Vin ' Vin Feedthrough Error +1/2LSB max +1LSB max Digital Inputs = Vip Veer = 20V p-p, 200kHz sinewave REFERENCE INPUT input Resistance (pin 15) Temperature Coefficient kQ min, 20k92 max -500ppm/C max Vout = Vour2 = &V ANALOG OUTPUTS? Output Capacitance Couti (Pin 1) 100pF max 100pF max Digital Inputs = Ving Coutz2 (pin 2) 30pF max 30pF max Couri (Pin D 30pF max 30pF max Digital Inputs = Vigy Cout2 (pin 2) 100pF max 100pF max DIGITAL INPUTS Logic Thresholds Vinu +14.5V min +14.5V min Vint +0.5V max +0.5V max Input Leakage Current lin (per input) +1uA max +1uA max Vin = OV or +15V Input Capacitance 3 4pF max 4pF max IN Input Coding Unipolar Binary or Offset Binary (see next page) POWER REQUIREMENTS Vpp Range +5V min, +16 max +5V min, +16V max Device Functionality. Accuracy is tested and guaranteed only at Vop = t15V lpp 100uA max 100uA max Digital Inputs = Vigy OF Vint NOTES: FSR is Full Scale Range. ? Using internal feedback resistor, Full Scale Range (FSR) is equal to (Vggp -1LSB) in the unipolar circuit on next page. 3 Guaranteed by design. Not subject to test. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS (Ty = +25C unless otherwise noted) Vpp toGND .. 0... ee eee -OV, +17V VaEptOGND. 0.00... +25V Digital Input Voltage (Vj,y) toGND........ ~0.3V to Vpp Vout1> Yout2 (pin 1, pin 2) toGND....... -0.3V to Vpp 314 D/A CONVERTERS Power Dissipation (package) To +70C Derate Above +70C by Operating Temperature. .... Storage Temperature ...... Lead Temperature (Soldering, 10 seconds)........ 670mW +300C CAUTION: 1. ESD sensitive device. The digital control inputs are Zener protected; however, permanent damage may occur on unconnected devices subjected to high energy electrostatic fields. Unused devices must be stored in con- ductive foam or shunts. 2. Do not apply voltages lower than ground or higher the Vpyp to any pin except Vppr (pin 15) and Rpg (pin 16). 3. The inputs of some IC amplifiers (especially wide bandwidth types) present a low impedance to V_ during power-up or power-down sequencing. To prevent the AD7523 OUT1 or OUT2Z terminals from exceeding ~300mV (which causes catastrop:ic substrate current) a Schottky diode (HP5082-2811 or equivalent) is recommended. The diode should be connected between OUT1 (OUT2) and ground as shown in Figures 1 and Z, BASIC OPERATION 10V +15V Veer Voo R1 2k 15 14 o MSBL| 4 DATA 1 INPUTS | AD7523 Vout | LSB O-411 NOTES: GND 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2. CR1PROTECTS AD7523 AGAINST NEGATIVE TRANSIENTS. SEE CAUTION NOTE 3 AT TOP OF THIS PAGE. Figure 1. Unipolar Binary Operation (2-Quadrant Multiplication} t10V +15V Vater Vpp rg RI 2k R, R2 1k 18 FB WN Ww MSB CcRi LSB Vout Oe 11 3 RS 100k . ~ J ne R7 1MQ WW RG 10k NOTES: . R3/R4 MATCH 0.1% OR BETTER. R1, R2 USED ONLY IF GAIN ADJUSTMENT iS REQUIRED . R5--R7 USED) TO ADJUST Voy = OV AT INPUT CODE 10000000. . CR1& CR2 PROTECT AD7523 AGAINST NEGATIVE TRANSIENTS. SEE CAUTION NOTE 3 AT TOP OF THIS PAGE. N= Pw Figure 2. Bipolar (4-Quadrant) Operation DIGITALINPUT ANALOG OUTPUT MSB LSB 111141111 ~Vaer (32) 129 10000001 -VREF (336) | 1128 Bie 10000000 -VREF (356 )=- 01111111 Vv. (x 56 | ~Y REF (5 00000001 ~VREF (ste) 0 4 00000000 ~VREF (553 )=0 . = (778 = Note: 1LSB = (2)(Vppp) = 256 (Veep) Table 1. Unipolar Binary Code Table DIGITAL INPUT ANALOG OUTPUT MSB LSB 11111111 -VREF (37) 10000001 VREF (35) 10000000 0 01111111 *Varr (i393) 00000001 *VREF (i358) 00000000 +VREF (3s) Note: 1LSB = (27)(Vppp) = (i) (Vapr) Table 2. Bipolar (Offset Binary} Code Table D/A CONVERTERS 315 APPLICATIONS DIVIDER (DIGITALLY CONTROLLED GAIN) OUT2 oul \ , __--0 Vout EQUATIONS Vv, Vout = - aon a, = Your =. 4 Vin > where: Ay = Vcltage Gain and where: .BIT1, BIT2 , BITS 2 2 28 (BIT N = 1 or O) oO EXAMPLES 1 = 00000000, Ay = -Ag, (OP AMP} 1D = 00000001, A, = -256 D = 10000000, Ay = - 26 =-2 D = 11111111, Ay =- 28 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16 PIN PLASTIC DIP RABAAAAAA e 0.26 (6.61) 0.24 (6.1) USP SP PSP VAN 0.755 (19.18) 0.306 (7.78) ef S08 0.745 (18.93) 0.294 (7.47) iT 0.14 (3.56) ! 15 0 . >| i | [M | 0.12 (3.05) 0.065 (1.66) 0.02 (0.508) 0.105 (2.67) 0.008 (2.03) 0.045 (115) 0.015 (0.381) 0.095 (2.42) LEAD NO. 1 IOENTIFIED BY DOT OR NOTCH 316 D/A CONVERTERS 0.12 (3.05) POWER GENERATION +10V +15V Vaer Vop BIT 1 (MSB) DATA j AD7523 7 v INPUT D PO | pits (LSB) 2 f Out2 + > " 3 GND +15V Vop 16 14 ' 4 o 1 AD7523 _ #2 pO V2 Ld 11 t 3 GND Lt +15V oF 1S 14 ~~44 | AD7523 Vv ' #in n ' + 1 GND CIRCUIT EQUATIONS V1 = -(Vper)(D) V2 = +{Vper (D2) V, = -(VRer)(D"), n an odd integer Va = +(Vrer )(D"}, n an even integer BONDING DIAGRAM 0.057 (1.45) -~<_- 0.062 (157) NOTES: 1. Pad numbers correspond to pin numbers shown on pin configuration, page 1. 2. Dimensions in inches (mm). 3. Pad 3, GND, should be bonded 1st. 4, Pads are 0.004 x 0.004 (0.102 x 0.102mm).