CA3140AT - Harris Semiconductor

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.

SEMICONDUCTOR

Description

The CA3140A and CA3140 are integrated circuit operational ampliﬁers

that combine the advantages of high voltage PMOS transistors with

high voltage bipolar transistors on a single monolithic chip. Because of

this unique combination of technologies, this device can now provide

designers, for the ﬁrst time, with the special performance features of

the CA3130 CMOS operational ampliﬁers and the versatility of the 741

series of industry standard operational ampliﬁers.

The CA3140A and CA3140 BiMOS operational ampliﬁers feature gate

protected MOSFET (PMOS) transistors in the input circuit to provide

very high input impedance, very low input current, and high speed per-

formance. The CA3140A and CA3140 operate at supply voltage from

4V to 36V (either single or dual supply). These operational ampliﬁers

are internally phase compensated to achieve stable operation in unity

gain follower operation, and additionally, have access terminal for a

supplementary external capacitor if additional frequency roll-off is

desired. Terminals are also provided for use in applications requiring

input offset voltage nulling. The use of PMOS ﬁeld effect transistors in

the input stage results in common mode input voltage capability down

to 0.5V below the negative supply terminal, an important attribute for

single supply applications. The output stage uses bipolar transistors

and includes built-in protection against damage from load terminal

short circuiting to either supply rail or to ground.

The CA3140 Series has the same 8-lead pinout used for the “741” and

other industry standard op amps. The CA3140A and CA3140 are

intended for operation at supply voltages up to 36V (±18V).

Ordering Information

PART NUMBER TEMP. RANGE PACKAGE

CA3140AE -55oC to +125oC 8 Lead Plastic DIP

CA3140AM -55oC to +125oC 8 Lead SOIC

CA3140AS -55oC to +125oC 8 Pin Can, Lead Formed

CA3140AT -55oC to +125oC 8 Pin Can

CA3140BT -55oC to +125oC 8 Pin Can

CA3140E -55oC to +125oC 8 Lead Plastic DIP

CA3140M -55oC to +125oC 8 Lead SOIC

CA3140M96 -55oC to +125oC 8 Lead SOIC*

CA3140T -55oC to +125oC 8 Pin Can

* Denotes Tape and Reel

Features

• MOSFET Input Stage

- Very High Input Impedance (ZIN) -1.5TΩ (Typ.)

- Very Low Input Current (Il) -10pA (Typ.) at ±15V

- Wide Common Mode Input Voltage Range

(VlCR) - Can be Swung 0.5V Below Negative

Supply Voltage Rail

- Output Swing Complements Input Common

Mode Range

• Directly Replaces Industry Type 741 in Most

Applications

• Ground-Referenced Single Supply Ampliﬁers in

Automobile and Portable Instrumentation

• Sample and Hold Ampliﬁers

• Long Duration Timers/Multivibrators

(µseconds-Minutes-Hours)

• Photocurrent Instrumentation

• Peak Detectors

• Active Filters

• Comparators

• Interface in 5V TTL Systems and Other Low

Supply Voltage Systems

• All Standard Operational Ampliﬁer Applications

• Function Generators

• Tone Controls

• Power Supplies

• Portable Instruments

• Intrusion Alarm Systems

April 1994

Pinouts

CA3140 (TO-5 STYLE CAN)

TOP VIEW CA3140 (PDIP, SOIC)

TOP VIEW

TAB

OUTPUT

INV.

V- AND CASE

OFFSET

NON-INV.

V+

OFFSET

–

NULL

INPUT

NULL

INPUT

STROBE

INV. INPUT

NON-INV.

V-

STROBE

V+

OUTPUT

OFFSET

NULL

OFFSET

NULL

INPUT

–

CA3140

BiMOS Operational Ampliﬁer

with MOSFET Input/Bipolar Output

File Number 957.2

2-124

Speciﬁcations CA3140, CA3140A

Absolute Maximum Ratings Operating Conditions

DC Supply Voltage (Between V+ and V- Terminals). . . . . . . . . . 36V

Differential Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 8V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . .(V+ +8V) To (V- -0.5V)

Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1mA

Output Short Circuit Duration* . . . . . . . . . . . . . . . . . . . . . . Indeﬁnite

Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

Junction Temperature (Plastic Package) . . . . . . . . . . . . . . . +150oC

Lead Temperature (Soldering 10 Sec.). . . . . . . . . . . . . . . . . +300oC

* Short circuit may be applied to ground or to either supply.

OperatingTemperature Range (All Types). . . . . . . .-55oC to +125oC

Storage Temperature Range (All Types). . . . . . . . .-65oC to +150oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

Electrical Speciﬁcations V+ = +15V, V- = -15V, TA = +25oC

PARAMETERS SYMBOL TEST CONDITIONS CA3140A CA3140 UNITS

Input Offset Voltage Adjustment Resistor Typical Value of Resistor

Between Term. 4 and 5 or 4

and 1 to Adjust Max. VI0

18 4.7 kΩ

Input Resistance RI1.5 1.5 TΩ

Input Capacitance CI44pF

Output Resistance RO60 60 Ω

Equivalent Wideband Input Noise Voltage

(See Figure 35) eNBW = 140kHz

RS = 1 MΩ48 48 µV

Equivalent Input Noise Voltage (See Figure 7) eNf = 1kHz RS = 100Ω40 40 nV/√Hz

f = 10 kHz 12 12 nV/√Hz

Short Circuit Current to Opposite Supply

Source IOM+4040 mA

Sink IOM-1818mA

Gain-Bandwidth Product, (See Figures 2 & 15) fT4.5 4.5 MHz

Slew Rate, (See Figure 3) SR 9 9 V/µs

Sink Current From Terminal 8 To Terminal 4 to Swing

Output Low 220 220 µA

Transient Response: RL = 2kΩ

CL = 100pF

Rise Time tR0.08 0.08 µs

Overshoot (See Figure 34) OS 10 10 %

Settling Time at 10 VP-P, (See Figure 14) tSRL = 2kΩ

CL = 100pF

Voltage Follower1mV 4.5 4.5 µs

10mV 1.4 1.4 µs

2-125

Speciﬁcations CA3140, CA3140A

Electrical Speciﬁcations For Equipment Design. At V+ = 15V, V- = 15V, TA = +25oC, Unless Otherwise Speciﬁed

PARAMETERS SYMBOL

LIMITS

UNITS

CA3140A CA3140

MIN TYP MAX MIN TYP MAX

Input Offset Voltage |VIO| - 2 5 - 5 15 mV

Input Offset Current |IIO| - 0.5 20 - 0.5 30 pA

Input Current II- 10 40 - 10 50 pA

Large Signal Voltage Gain (Note 1)

(See Figures 1, 15) AOL 20 l00 - 20 100 - kV/V

86 100 - 86 100 - dB

Common Mode Rejection Ratio

(See Figure 6) CMRR - 32 320 - 32 320 µV/V

70 90 - 70 90 - dB

Common Mode Input Voltage Range

(See Figure 17) VICR -15 -15.5

+12.5

12 -15 -15.5

+12.5

11 V

Power-Supply Rejection Ratio,

∆VIO/∆VS (See Figure 8) PSRR - 100 150 - 100 150 µV/V

76 80 - 76 80 - dB

Max. Output Voltage (Note 2)

(See Figures 10, 17) VOM+ +12 13 - +12 13 - V

VOM- -14 -14.4 - -14 -14.4 - V

Supply Current (See Figure 4) I+ - 4 6 - 4 6 mA

Device Dissipation PD- 120 180 - 120 180 mW

Input Offset Voltage Temp. Drift,

∆VIO/∆T-6--8-µV/oC

NOTES:

1. At VO = 26Vp-p, +12V, 14V and RL = 2kΩ.

2. At RL = 2kΩ.

Electrical Speciﬁcations For Design Guidance. At V+ = 5 V, V- = 0V, TA = +25oC

PARAMETERS SYMBOL CA3140A CA3140 UNITS

Input Offset Voltage |VIO|2 5mV

Input Offset Current |IIO| 0.1 0.1 pA

Input Current II22pA

Input Resistance RI11TΩ

Large Signal Voltage Gain

(See Figures 1, 15) AOL 100 100 kV/V

100 100 dB

2-126

Speciﬁcations CA3140, CA3140A

Common Mode Rejection Ratio, CMRR 32 32 µV/V

90 90 dB

Common Mode Input Voltage Range (See Figure 17) VICR -0.5 -0.5 V

2.6 2.6 V

Power Supply Rejection Ratio PSRR

∆VI0/∆VS

100 100 µV/V

80 80 dB

Maximum Output Voltage (See Figures 10, 17) VOM+3 3V

OM- 0.13 0.13 V

Maximum Output Current:

Source IOM+ 10 10 mA

Sink IOM- 1 1 mA

Slew Rate (See Figure 3) SR 7 7 V/µs

Gain-Bandwidth Product (See Figure 2) fT3.7 3.7 MHz

Supply Current (See Figure 4) I+ 1.6 1.6 mA

Device Dissipation PD88mW

Sink Current from Term. 8 to Term. 4 to Swing Output Low 200 200 µA

Electrical Speciﬁcations For Design Guidance. At V+ = 5 V, V- = 0V, TA = +25oC(Continued)

PARAMETERS SYMBOL CA3140A CA3140 UNITS

2-127

CA3140A, CA3140

Block Diagram

Schematic Diagram

A≈10 A≈

10,000

12pF

A≈1

1 8

OFFSET STROBE

NULL

OUTPUT

INPUT

200µA 200µA1.6mA 2µA 2mA

2mA 4mA V+

V-

BIAS CIRCUIT

CURRENT SOURCES

AND REGULATOR

500Ω

Q11 Q12

500ΩR3

500Ω

Q10Q9

D4D3

5 1 8

STROBEOFFSET NULL

NON-INVERTING

INPUT

INVERTING

INPUT +

ALL RESISTANCE VALUES ARE IN Ω

12pF

Q13

Q15 Q16

Q21

Q20

Q19

Q18

Q17

R11

20Ω

50Ω

R12

12k

R14

20k

R13

R10

OUTPUT

V-

V+

DYNAMIC CURRENT SINKOUTPUT STAGESECOND STAGEINPUT STAGEBIAS CIRCUIT

Q14

30Ω

50Ω

2-128

CA3140A, CA3140

As shown in the block diagram, the input terminals may be

operated down to 0.5V below the negative supply rail. Two

class A ampliﬁer stages provide the voltage gain, and a

unique class AB ampliﬁer stage provides the current gain

necessary to drive low-impedance loads.

A biasing circuit provides control of cascoded constant

current ﬂow circuits in the ﬁrst and second stages. The

CA3140 includes an on chip phase compensating capacitor

that is sufﬁcient for the unity gain voltage follower

conﬁguration.

Input Stages

The schematic diagram consists of a differential input stage

using PMOS ﬁeld-effect transistors (Q9, Q10) working into a

mirror pair of bipolar transistors (Q11, Q12) functioning as

load resistors together with resistors R2 through R5. The

mirror pair transistors also function as a differential-to-single-

ended converter to provide base current drive to the second

stage bipolar transistor (Q13). Offset nulling, when desired,

can be effected with a 10k Ω potentiometer connected across

terminals 1 and 5 and with its slider arm connected to

terminal 4. Cascode connected bipolar transistors Q2, Q5

are the constant current source for the input stage. The base

biasing circuit for the constant current source is described

subsequently. The small diodes D3, D4, D5 provide gate

oxide protection against high voltage transients, e.g., static

electricity.

Second Stage

Most of the voltage gain in the CA3140 is provided by the

second ampliﬁer stage, consisting of bipolar transistor Q13

and its cascode connected load resistance provided by

bipolar transistors Q3, Q4. On-chip phase compensation,

sufﬁcient for a majority of the applications is provided by C1.

Additional Miller-Effect compensation (roll off) can be

accomplished, when desired, by simply connecting a small

capacitor between terminals 1 and 8. Terminal 8 is also used

to strobe the output stage into quiescence. When terminal 8

is tied to the negative supply rail (terminal 4) by mechanical

or electrical means, the output terminal 6 swings low, i.e.,

approximately to terminal 4 potential.

Output Stage

The CA3140 Series circuits employ a broad band output

stage that can sink loads to the negative supply to

complement the capability of the PMOS input stage when

operating near the negative rail. Quiescent current in the

emitter-follower cascade circuit (Q17, Q18) is established by

transistors (Q14, Q15) whose base currents are “mirrored” to

current ﬂowing through diode D2 in the bias circuit section.

When the CA3140 is operating such that output terminal 6 is

sourcing current, transistor Q18 functions as an emitter-

follower to source current from the V+ bus (terminal 7), via

D7, R9, and R11. Under these conditions, the collector

potential of Q13 is sufﬁciently high to permit the necessary

ﬂow of base current to emitter follower Q17 which, in turn,

drives Q18.

When the CA3140 is operating such that output terminal 6 is

sinking current to the V- bus, transistor Q16 is the current

sinking element. Transistor Q16 is mirror connected to D6,

R7, with current fed by way of Q21, R12, and Q20. T ransistor

Q20, in turn, is biased by current ﬂow through R13, zener

D8, and R14. The dynamic current sink is controlled by

voltage level sensing. For purposes of explanation, it is

assumed that output terminal 6 is quiescently established at

the potential midpoint between the V+ and V- supply rails.

When output current sinking mode operation is required, the

collector potential of transistor Q13 is driven below its

quiescent level, thereby causing Q17, Q18 to decrease the

output voltage at terminal 6. Thus, the gate terminal of

PMOS transistor Q21 is displaced toward the V - bus, thereby

reducing the channel resistance of Q21. As a consequence,

there is an incremental increase in current ﬂow through Q20,

R12, Q21, D6, R7, and the base of Q16. As a result, Q16

sinks current from terminal 6 in direct response to the

incremental change in output voltage caused by Q18. This

sink current ﬂows regardless of load; any excess current is

internally supplied by the emitter-follower Q18. Short circuit

protection of the output circuit is provided by Q19, which is

driven into conduction by the high voltage drop developed

across R11 under output short circuit conditions. Under

these conditions, the collector of Q19 diverts current from

Q4 so as to reduce the base current drive from Q17, thereby

limiting current ﬂow in Q18 to the short circuited load

terminal.

Bias Circuit

Quiescent current in all stages (except the dynamic current

sink) of the CA3140 is dependent upon bias current ﬂow in

R1. The function of the bias circuit is to establish and

maintain constant current ﬂow through D1, Q6, Q8 and D2.

D1 is a diode connected transistor mirror connected in

parallel with the base emitter junctions of Q1, Q2, and Q3.

D1 may be considered as a current sampling diode that

senses the emitter current of Q6 and automatically adjusts

the base current of Q6 (via Q1) to maintain a constant

current through Q6, Q8, D2. The base currents in Q2, Q3

are also determined by constant current ﬂow D1.

Furthermore, current in diode connected transistor Q2

establishes the currents in transistors Q14 and Q15.

Circuit Description

2-129

CA3140, CA3140A

Metallization Mask Layout

Typical Performance Curves

FIGURE 1. OPEN LOOP VOLTAGE GAIN vs SUPPLY

VOLTAGE AND TEMPERATURE FIGURE 2. GAIN BANDWIDTH PRODUCT vs SUPPLY

VOLTAGE AND TEMPERATURE

Dimensions in parenthesis are in millimeters and are derived

from the basic inch dimensions as indicated. Grid graduations

are in mils (10-3 inch).

The photographs and dimensions represent a chip when it is

part of the wafer. When the wafer is cut into chips, the cleavage

angles are 57o instead of 90ο with respect to the face of the

chip. Therefore, the isolated chip is actually 7 mils (0.17mm)

larger in both dimensions.

62-70

(1.575-1.778)

4-10

(0.102-0.254)

58-66

(1.473-1.676)

5040302010

0 60 65

125

100

OPEN-LOOP VOLTAGE GAIN (dB)

0 5 10 15 20

SUPPLY VOLTAGE (V)

+125oC

+25oC

TA = -55oC

RL = 2kΩ

GAIN BANDWIDTH PRODUCT (MHz)

+125oC

+25oC

TA = -55oC

RL = 2kΩ

0 5 10 15 20

SUPPLY VOLTAGE (V) 25

CL = 100pF

2-130

CA3140, CA3140A

FIGURE 3. SLEW RATE vs SUPPLY VOLTAGE AND

TEMPERATURE FIGURE 4. QUIESCENT SUPPLY CURRENT vs SUPPLY

VOLTAGE AND TEMPERATURE

FIGURE 5. MAXIMUM OUTPUT VOLTAGE SWING vs

FREQUENCY FIGURE 6. COMMON MODE REJECTION RATIO vs FREQUENCY

FIGURE 7. EQUIVALENT INPUT NOISE VOLTAGE vs

FREQUENCY FIGURE 8. POWER SUPPLY REJECTION RATIO vs FREQUENCY

Typical Performance Curves

(Continued)

+125oC

+25oC

TA = -55oC

RL = 2kΩ

5101520

SUPPLY VOLTAGE (V) 25

CL = 100pF

SLEW RATE (V/µs)

0 5 10 15 20

SUPPLY VOLTAGE (V)

+125oC

TA = -55oC

RL = ∞

+25oC

QUIESCENT SUPPLY CURRENT (mA)

OUTPUT SWING (VP-P)

10K 2468

100K

FREQUENCY (Hz) 1M 4M

2468 2

SUPPLY VOLTAGE: V+ = 15V, V- = -15V

TA = +25oC120

100

COMMON-MODE REJECTION RATIO (dB)

101102103104105106107

FREQUENCY (Hz)

CA3140B

SUPPLY VOLTAGE: V+ = 15V, V- = -15V

TA = +25oC

CA3140, CA3140A

SUPPLY VOLTAGE: V+ = 15V, V- = -15V

TA = +25oC

FREQUENCY (Hz)

110

1102103104105

EQUIVALENT INPUT NOISE VOLTAGE (nV √Hz)

100

1000

102103104105106107

FREQUENCY (Hz)

POWER SUPPLY REJECTION RATIO (dB)

100

CA3140B

CA3140,

CA3140A

+PSRR

-PSRR

SUPPLY VOLTAGE: V+ = 15V, V- = -15V

TA = +25oC

POWER SUPPLY REJECTION RATIO

(PSRR) = ∆VIO/∆VS

101

2-131

CA3140, CA3140A

Wide dynamic range of input and output characteristics with

the most desirable high input impedance characteristics is

achieved in the CA3140 by the use of an unique design based

upon the PMOS Bipolar process. Input common mode voltage

range and output swing capabilities are complementary,

allowing operation with the single supply down to 4V.

The wide dynamic range of these parameters also means

that this device is suitable for many single supply applica-

tions, such as, for example, where one input is driven below

the potential of terminal 4 and the phase sense of the output

signal must be maintained – a most important consideration

in comparator applications.

Output Circuit Considerations

Excellent interfacing with TTL circuitry is easily achieved

with a single 6.2V zener diode connected to terminal 8 as

shown in Figure 9. This connection assures that the maxi-

mum output signal swing will not go more positive than the

zener voltage minus two base-to-emitter voltage drops within

the CA3140. These voltages are independent of the operat-

ing supply voltage.

FIGURE 9. ZENER CLAMPING DIODE CONNECTED TO TERMI-

NALS 8 AND 4 TO LIMIT CA3140 OUTPUT SWING

TO TTL LEVELS

FIGURE 10. VOLTAGE ACROSS OUTPUT TRANSISTORS Q15

AND Q16 vs LOAD CURRENT

CA3140

V+

5V TO 36V

6.2V

≈5V

LOGIC

SUPPLY

TYPICAL

TTL GATE

10.01 0.1

LOAD (SINKING) CURRENT (mA)

1.0 10

246824682468

100

1000

OUTPUT STAGE TRANSISTOR (Q15, Q16)

SATURATION VOLTAGE (mV)

SUPPLY VOLTAGE (V-) = 0V

TA = +25oC

SUPPLY VOLTAGE (V+) = +5V +15V

+30V

Figure 10 shows output current sinking capabilities of the

CA3140 at various supply voltages. Output voltage swing to

the negative supply rail permits this device to operate both

power transistors and thyristors directly without the need for

level shifting circuitry usually associated with the 741 series

of operational ampliﬁers.

Figure 13 shows some typical conﬁgurations. Note that a

series resistor, RL, is used in both cases to limit the drive

available to the driven device. Moreover, it is recommended

that a series diode and shunt diode be used at the thyristor

input to prevent large negative transient surges that can

appear at the gate of thyristors, from damaging the inte-

grated circuit.

FIGURE 11. TYPICAL INCREMENTAL OFFSET VOLTAGE SHIFT

vs OPERATING LIFE

Offset Voltage Nulling

The input offset voltage can be nulled by connecting a 10kΩ

potentiometer between terminals 1 and 5 and returning its

wiper arm to terminal 4, see Figure 12(A). This technique,

however, gives more adjustment range than required and

therefore, a considerable portion of the potentiometer rota-

tion is not fully utilized. Typical values of series resistors that

may be placed at either end of the potentiometer, see Figure

12(B), to optimize its utilization range are given in the table

“Electrical Speciﬁcations” shown in this bulletin.

An alternate system is shown in Figure 12(C). This circuit

uses only one additional resistor of approximately the value

shown in the table. For potentiometers, in which the resis-

tance does not drop to zero Ω at either end of rotation, a

value of resistance 10% lower than the values shown in the

table should be used.

Low Voltage Operation

Operation at total supply voltages as low as 4V is possible

with the CA3140. A current regulator based upon the PMOS

threshold voltage maintains reasonable constant operating

current and hence consistent performance down to these

lower voltages.

The low voltage limitation occurs when the upper extreme of

the input common mode voltage range extends down to the

OFFSET-VOLTAGE SHIFT (mV)

0 500 1000 1500 2000 2500 3000 3500 4000 4500

TIME (HOURS)

DIFFERENTIAL DC VOLTAGE

(ACROSS TERMS 2 AND 3) = 2V

OUTPUT STAGE TOGGLED

DIFFERENTIAL DC VOLTAGE

(ACROSS TERMS 2 AND 3) = 0V

OUTPUT VOLTAGE = V+ / 2

TA = +125oC

FOR TO-5 PACKAGES

Applications Considerations

2-132

CA3140, CA3140A

FIGURE 12. THREE OFFSET VOLTAGE NULLING METHODS

FIGURE 13. METHODS OF UTILIZING THE VCE(SAT) SINKING CURRENT CAPABILITY OF THE CA3140 SERIES

FIGURE 14. INPUT VOLTAGE vs SETTLING TIME

CA3140

V+

V-

10kΩ

(A) BASIC

CA3140

V+

V-

10kΩ

CA3140

V+

V-

10kΩ

(B) IMPROVED

RESOLUTION (C) SIMPLER

IMPROVED

RESOLUTION

CA3140

V+ +HV

LOAD

CA3140

LOAD

MT2

MT1

30V

NO LOAD

120VAC

CA3140 6

SIMULATED

LOAD

-15V 0.1µF5.11kΩ

0.1µF

+15V

5kΩ

2kΩ

100pF

5kΩ

INVERTING

SETTLING POINT

200Ω

4.99kΩ

IN914

CA3140 6

SIMULATED

LOAD

-15V 0.1µF

0.1µF

+15V

2kΩ

100pF

0.05µF

2kΩ

10kΩ

SETTLING TIME (µs)

(B) TEST CIRCUITS

0.1

INPUT VOLTAGE (V)

1.0 10

2468

SUPPLY VOLTAGE: V+ = +15V, V- = -15V

TA = +25oC

1mV

10mV

(A)

2468

10mV

1mV

1mV1mV

10mV 10mV

FOLLOWER

INVERTING

LOAD RESISTANCE (R L) = 2kΩ

LOAD CAPACITANCE (CL) = 100pF

FOLLOWER

-2

-4

-6

-8

-10

2-133

CA3140, CA3140A

voltage at terminal 4. This limit is reached at a total supply

voltage just below 4V. The output voltage range also begins

to extend down to the negative supply rail, but is slightly

higher than that of the input. Figure 17 shows these

characteristics and shows that with 2V dual supplies, the

lower extreme of the input common mode voltage range is

below ground potential.

Bandwidth and Slew Rate

For those cases where bandwidth reduction is desired, for

example, broadband noise reduction, an external capacitor

connected between terminals 1 and 8 can reduce the open

loop -3dB bandwidth. The slew rate will, however, also be

proportionally reduced by using this additional capacitor.

Thus, a 20% reduction in bandwidth by this technique will

also reduce the slew rate by about 20%.

Figure 14 shows the typical settling time required to reach

1mV or 10mV of the ﬁnal value for various levels of large

signal inputs for the voltage follower and inverting unity gain

ampliﬁers. The exceptionally fast settling time characteristics

are largely due to the high combination of high gain and wide

bandwidth of the CA3140; as shown in Figure 15.

Input Circuit Considerations

As mentioned previously, the ampliﬁer inputs can be driven

below the terminal 4 potential, but a series current limiting

resistor is recommended to limit the maximum input terminal

current to less than 1mA to prevent damage to the input pro-

tection circuitry.

Moreover, some current limiting resistance should be

provided between the inverting input and the output when

the CA3140 is used as a unity gain voltage follower. This

resistance prevents the possibility of extremely large input

signal transients from forcing a signal through the input

protection network and directly driving the internal constant

current source which could result in positive feedback via the

output terminal. A 3.9kΩ resistor is sufﬁcient.

FIGURE 15. OPEN LOOP VOLTAGE GAIN AND PHASE vs

FREQUENCY FIGURE 16. INPUT CURRENT vs AMBIENT TEMPERATURE

FIGURE 17. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE AND

TEMPERATURE

101103104105106107108

FREQUENCY (Hz)

OPEN LOOP VOLTAGE GAIN (dB)

100

SUPPLY VOLT AGE: V+ = 15V , V- = -15V

TA = +25oC

102

OPEN LOOP PHASE

-75

-90

-105

-120

-135

-150

(DEGREES)

RL = 2k Ω,

CL = 0pF

RL = 2kΩ,

CL = 100pF

φOL

SUPPLY VOLTAGE: V+ = 15V, V- = -15V

AMBIENT TEMPERATURE (oC)

-60 -40 -20 0 20 40 60 80 100 120 140

INPUT CURRENT (pA)

100

10K

SUPPLY VOLTAGE (V+, V-)

0 5 10 15 20 25

-1.5

-2.0

-1.0

-2.5

RL = ∞

+VOUT AT TA = +125oC

+VOUT AT TA = +25oC

+VOUT AT TA = -55oC

+VICR AT TA = +125oC

+VICR AT TA = +25oC

+VICR AT TA = -55oC

-3.0

-0.5

INPUT AND OUTPUT VOLTAGE EXCURSIONS

FROM TERMINAL 7 (V+)

SUPPLY VOLTAGE (V+, V-)

0 5 10 15 20 25

-VICR AT TA = +125oC

-VICR AT TA = +25oC

-VICR AT TA = -55oC

-VOUT FOR TA =

-55oC to +125oC

INPUT AND OUTPUT VOLTAGE EXCURSIONS

FROM TERMINAL 4 (V-)

-0.5

0.5

-1.0

-1.5

1.5

1.0

2-134

CA3140, CA3140A

The typical input current is in the order of 10pA when the

inputs are centered at nominal device dissipation. As the

output supplies load current, device dissipation will increase,

raising the chip temperature and resulting in increased input

current. Figure 16 shows typical input terminal current ver-

sus ambient temperature for the CA3140.

It is well known that MOSFET devices can exhibit slight

changes in characteristics (for example, small changes in

input offset voltage) due to the application of large differen-

tial input voltages that are sustained over long periods at ele-

vated temperatures.

Both applied voltage and temperature accelerate these

changes. The process is reversible and offset voltage shifts

of the opposite polarity reverse the offset. Figure 11 shows

the typical offset voltage change as a function of various

stress voltages at the maximum rating of +125oC (for TO-5);

at lower temperatures (TO-5 and plastic), for example, at

+85oC, this change in voltage is considerably less. In typical

linear applications, where the differential voltage is small and

symmetrical, these incremental changes are of about the

same magnitude as those encountered in an operational

ampliﬁer employing a bipolar transistor input stage.

Super Sweep Function Generator

A function generator having a wide tuning range is shown in

Figure 18. The 1,000,000/1 adjustment range is accom-

plished by a single variable potentiometer or by an auxiliary

sweeping signal. The CA3140 functions as a non-inverting

readout ampliﬁer of the triangular signal developed across

the integrating capacitor network connected to the output of

the CA3080A current source.

Buffered triangular output signals are then applied to a sec-

ond CA3080 functioning as a high speed hysteresis switch.

Output from the switch is returned directly back to the input

of the CA3080A current source, thereby, completing the pos-

itive feedback loop

The triangular output level is determined by the four 1N914

level limiting diodes of the second CA3080 and the resistor

divider network connected to terminal No. 2 (input) of the

CA3080. These diodes establish the input trip level to this

switching stage and, therefore, indirectly determine the

amplitude of the output triangle.

Compensation for propagation delays around the entire loop

is provided by one adjustment on the input of the CA3080.

This adjustment, which provides for a constant generator

amplitude output, is most easily made while the generator is

sweeping. High frequency ramp linearity is adjusted by the

single 7-to-6pF capacitor in the output of the CA3080A.

It must be emphasized that only the CA3080A is

characterized for maximum output linearity in the current

generator function.

Meter Driver and Buffer Ampliﬁer

Figure 19 shows the CA3140 connected as a meter driver

and buffer ampliﬁer. Low driving impedance is required of

the CA3080A current source to assure smooth operation of

the Frequency Adjustment Control. This low-driving

impedance requirement is easily met by using a CA3140

connected as a voltage follower. Moreover, a meter may be

placed across the input to the CA3080A to give a logarithmic

analog indication of the function generators frequency.

Analog frequency readout is readily accomplished by the

means described above because the output current of the

CA3080A varies approximately one decade for each 60mV

change in the applied voltage, VABC (voltage between

terminals 5 and 4 of the CA3080A of the function generator).

Therefore, six decades represent 360mV change in VABC.

Now, only the reference voltage must be established to set

the lower limit on the meter. The three remaining transistors

from the CA3086 Array used in the sweep generator are

used for this reference voltage. In addition, this reference

generator arrangement tends to track ambient temperature

variations, and thus compensates for the effects of the nor-

mal negative temperature coefﬁcient of the CA3080A VABC

terminal voltage.

Another output voltage from the reference generator is used

to insure temperature tracking of the lower end of the

Frequency Adjustment Potentiometer. A large series

resistance simulates a current source, assuring similar

temperature coefﬁcients at both ends of the Frequency

Adjustment Control.

To calibrate this circuit, set the Frequency Adjustment

Potentiometer at its low end. Then adjust the Minimum

Frequency Calibration Control for the lowest frequency. To

establish the upper frequency limit, set the Frequency

Adjustment Potentiometer to its upper end and then adjust

the Maximum Frequency Calibration Control for the

maximum frequency. Because there is interaction among

these controls, repetition of the adjustment procedure may

be necessary. Two adjustments are used for the meter. The

meter sensitivity control sets the meter scale width of each

decade, while the meter position control adjusts the pointer

on the scale with negligible effect on the sensitivity

adjustment. Thus, the meter sensitivity adjustment control

calibrates the meter so that it deﬂects 1/6 of full scale for

each decade change in frequency.

Sine Wave Shaper

The circuit shown in Figure 20 uses a CA3140 as a voltage

follower in combination with diodes from the CA3019 Array

to convert the triangular signal from the function generator to

a sine-wave output signal having typically less than 2% THD.

The basic zero crossing slope is established by the 10kΩ

potentiometer connected between terminals 2 and 6 of the

CA3140 and the 9.1kΩ resistor and 10kΩ potentiometer

from terminal 2 to ground. Two break points are established

by diodes D1 through D4. Positive feedback via D5 and D6

establishes the zero slope at the maximum and minimum

levels of the sine wave. This technique is necessary because

the voltage follower conﬁguration approaches unity gain

rather than the zero gain required to shape the sine wave at

the two extremes.

2-135

CA3140, CA3140A

(A) CIRCUIT

(B1) FUNCTION GENERATOR SWEEPING

Top Trace: Output at junction of 2.7Ω and 51Ω resistors

5V/Div and 500ms/Div

Center Trace: External output of triangular function generator

2V/Div and 500ms/Div

Bottom Trace: Output of “Log” generator; 10V/Div and 500ms/Div

(B2) FUNCTION GENERATOR WITH FIXED FREQUENCIES

1V/Div and 1sec/Div

Three tone test signals, highest frequency ≥0.5MHz. Note the slight

asymmetry at the three second/cycle signal. This asymmetry is due

to slightly different positive and negative integration from the

CA3080A and from the pc board and component leakages at the

100pA level.

FIGURE 18. FUNCTION GENERATOR

0.1

µF

IN914

0.1

µF

5.1

kΩ

10kΩ

2.7kΩ

-15V

13kΩ

+15V

CENTERING

10kΩ

-15V

910

kΩ62kΩ

11kΩ

10kΩ

EXTERNAL

OUTPUT

11kΩ

HIGH

FREQUENCY

LEVEL

7-60pF EXTERNAL

OUTPUT

TO OUTPUT

AMPLIFIER

OUTPUT

AMPLIFIER

SINE WAVE

SHAPER

2kΩ

FREQUENCY

ADJUSTMENT

HIGH

FREQ.

SHAPE

SYMMETRY

THIS NETWORK IS USED WHEN THE

OPTIONAL BUFFER CIRCUIT IS NOT USED

-15V +15V

10kΩ120Ω

39Ω

100kΩ

7.5kΩ+15V+15V

15kΩ

360Ω

2MΩ

7-60

-15V

-15V +15V

CA3080A

-CA3140 CA3080

-15V

FROM BUFFER METER

DRIVER (OPTIONAL)

FREQUENCY

ADJUSTMENT

METER DRIVER

AND BUFFER

AMPLIFIER

FUNCTION

GENERATOR

SINE WAVE

SHAPER

POWER

SUPPLY ±15V -15V

+15V

DC LEVEL

ADJUST

51Ω

WIDEBAND

LINE DRIVER

SWEEP

GENERATOR

GATE

SWEEP

V-

SWEEP

LENGTH

EXTERNAL

INPUT

OFF

V-

COARSE

RATE

FINE

RATE

EXT.

INT.

2-136

CA3140, CA3140A

FIGURE 19. METER DRIVER AND BUFFER AMPLIFIER FIGURE 20. SINE WAVE SHAPER

FIGURE 21. SWEEPING GENERATOR

FREQUENCY

CALIBRATION

MINIMUM 200µA

METER

FREQUENCY

CALIBRATION

MAXIMUM

METER

SENSITIVITY

ADJUSTMENT

METER

POSITION

ADJUSTMENT

CA3080A

CA3140

FREQUENCY

ADJUSTMENT

10kΩ

620Ω

4.7kΩ

0.1µF12

2kΩ

500kΩ

620kΩ

51kΩ

3MΩ

510Ω510Ω

2kΩ

3.6kΩ

-15V

3/5 OF CA3086

TO CA3080A

OF FUNCTION

GENERATOR

(FIGURE 18)

1kΩ

2.4kΩ

2.5

kΩ

+15V

SWEEP IN

kΩ

CA3140

2856

5.1kΩ

0.1µF-15V

D1 D4

D2D3 D6

CA3019

DIODE ARRAY

EXTERNAL

OUTPUT

+15V

-15V

100

kΩ

SUBSTRATE

OF CA3019

WIDEBAND

OUTPUT

AMPLIFIER

7.5

5.6

-15V

R3 10kΩ10kΩ

0.1µF

1MΩ

9.1kΩ

10kΩ

1kΩ

430Ω

kΩ

CA3140

0.1

+15V

-15V

µF

0.1

µF

COARSE

RATE

SAWTOOTH

SYMMETRY

0.47µF

0.047µF

4700pF

470pF

CA3140

-5

51kΩ6.8kΩ91kΩ10kΩ

100Ω390Ω

3.9Ω

25kΩ

+15V

-15V

10kΩ

100kΩ

30kΩ

43kΩ

LOGVIO

50kΩ

LOG

RATE

10kΩGATE

PULSE

OUTPUT

-15V

EXTERNAL OUTPUT

TO FUNCTION GENERATOR “SWEEP IN”

SWEEP WIDTH

TO OUTPUT

AMPLIFIER

36kΩ

51kΩ

75kΩ

50kΩ

SAWTOOTH

“LOG”

TRIANGLE

+15V

CA3140

+15V

TRANSISTORS

FROM CA3086

ARRAY

ADJUST

TRIANGLE

SAWTOOTH

“LOG”

8.2kΩ

100kΩ

FINE

RATE

SAWTOOTH

22MΩ1MΩ

18MΩ

750kΩ

“LOG”

IN914

IN914 SAWTOOTH AND

RAMP LOW LEVEL

SET (-14.5V)

-15V

2-137

CA3140, CA3140A

This circuit can be adjusted most easily with a distortion

analyzer, but a good ﬁrst approximation can be made by

comparing the output signal with that of a sine wave

generator. The initial slope is adjusted with the

potentiometer R1, followed by an adjustment of R2. The ﬁnal

slope is established by adjusting R3, thereby adding

additional segments that are contributed by these diodes.

Because there is some interaction among these controls,

repetition of the adjustment procedure may be necessary.

Sweeping Generator

Figure 21 shows a sweeping generator. Three CA3140's are

used in this circuit. One CA3140 is used as an integrator, a

second device is used as a hysteresis switch that deter-

mines the starting and stopping points of the sweep. A third

CA3140 is used as a logarithmic shaping network for the log

function. Rates and slopes, as well as sawtooth, triangle,

and logarithmic sweeps are generated by this circuit.

Wideband Output Ampliﬁer

Figure 22 shows a high slew rate, wideband ampliﬁer

suitable for use as a 50Ω transmission line driver. This

circuit, when used in conjunction with the function generator

and sine wave shaper circuits shown in Figures 18 and 20

provides 18V peak-to-peak output open circuited, or 9V

peak-to-peak output when terminated in 50Ω. The slew rate

required of this ampliﬁer is 28V/µs (18V peak-to-peak x π x

0.5MHz).

FIGURE 22. WIDEBAND OUTPUT AMPLIFIER

Power Supplies

High input impedance, common mode capability down to the

negative supply and high output drive current capability are

key factors in the design of wide range output voltage

supplies that use a single input voltage to provide a

regulated output voltage that can be adjusted from

essentially 0V to 24V.

Unlike many regulator systems using comparators having a

bipolar transistor input stage, a high impedance reference

voltage divider from a single supply can be used in

connection with the CA3140 (see Figure 23).

CA3140

50µF

25V 2.2

kΩ2N3053

IN914

2.2

kΩ

IN914

2.7Ω

2N4037

-50µF

25V

SIGNAL

LEVEL

ADJUSTMENT

2.5kΩ

200Ω

2.4pF

2pF -15V

+15V

OUTPUT

DC LEVEL

ADJUSTMENT

-15V

+15V

3kΩ

200Ω1.8kΩ

51Ω

OUT

NOMINAL BANDWIDTH = 10MHz

tr = 35ns

FIGURE 23. BASIC SINGLE SUPPLY VOLTAGE REGULATOR

SHOWING VOLTAGE FOLLOWER CONFIGURATION

Essentially, the regulators, shown in Figures 24 and 25, are

connected as non inverting power operational ampliﬁers with

a gain of 3.2. An 8V reference input yields a maximum out-

put voltage slightly greater than 25V. As a voltage follower,

when the reference input goes to 0V the output will be 0V.

Because the offset voltage is also multiplied by the 3.2 gain

factor, a potentiometer is needed to null the offset voltage.

Series pass transistors with high ICBO levels will also prevent

the output voltage from reaching zero because there is a

ﬁnite voltage drop (VCEsat) across the output of the CA3140

(see Figure 10). This saturation voltage level may indeed set

the lowest voltage obtainable.

The high impedance presented by terminal 8 is advanta-

geous in effecting current limiting. Thus, only a small signal

transistor is required for the current-limit sensing ampliﬁer.

Resistive decoupling is provided for this transistor to mini-

mize damage to it or the CA3140 in the event of unusual

input or output transients on the supply rail.

Figures 24 and 25, show circuits in which a D2201 high

speed diode is used for the current sensor. This diode was

chosen for its slightly higher forward voltage drop character-

istic, thus giving greater sensitivity. It must be emphasized

that heat sinking of this diode is essential to minimize varia-

tion of the current trip point due to internal heating of the

diode. That is, 1A at 1V forward drop represents one watt

which can result in signiﬁcant regenerative changes in the

current trip point as the diode temperature rises. Placing the

small signal reference ampliﬁer in the proximity of the current

sensing diode also helps minimize the variability in the trip

level due to the negative temperature coefﬁcient of the

diode. In spite of those limitations, the current limiting point

can easily be adjusted over the range from 10mA to 1A with

a single adjustment potentiometer. If the temperature stabil-

ity of the current limiting system is a serious consideration,

the more usual current sampling resistor type of circuitry

should be employed.

A power Darlington transistor (in a heat sink TO-3 case), is used

as the series pass element for the conventional current limiting

system, Figure 24, because high power Darlington dissipation

will be encountered at low output voltage and high currents.

A small heat sink VERSAWATT transistor is used as the

series pass element in the fold back current system, Figure

25, since dissipation levels will only approach 10W. In this

system, the D2201 diode is used for current sampling. Fold-

CA3140

VOLTAGE

REFERENCE

VOLTAGE ADJUSTMENT

REGULATED

OUTPUT

INPUT

2-138

CA3140, CA3140A

back is provided by the 3kΩ and 100kΩ divider network con-

nected to the base of the current sensing transistor.

FIGURE 24. REGULATED POWER SUPPLY

FIGURE 25. REGULATED POWER SUPPLY WITH “FOLDBACK”

CURRENT LIMITING

75Ω

3kΩ

100Ω

1kΩ1kΩ

D2201

CURRENT

LIMITING

ADJUST

2N6385

POWER DARLINGTON

1kΩ

2N2102

1kΩ

+30V

INPUT 4

CA3140

100kΩ

180kΩ

56pF

1kΩ82kΩ

250µF

0.01µF

100kΩ

50kΩ

5µF

CA3086

2.2kΩ

62kΩ

VOLTAGE

ADJUST

10µF+

2.7kΩ

1kΩ

HUM AND NOISE OUTPUT <200 µVRMS

(MEASUREMENT BANDWIDTH ~10MHz)

LINE REGULATION 0.1%/VOLT

LOAD REGULATION

(NO LOAD TO FULL LOAD)

<0.02%

OUTPUT

0.1 ⇒ 24V

AT 1A

1kΩ200Ω

D2201

“FOLDBACK” CURRENT

LIMITER

2N5294

3kΩ

2N2102

1kΩ

+30V

INPUT 4

CA3140

100kΩ

180kΩ

56pF

1kΩ82kΩ

250µF

0.01µF

100kΩ

50kΩ

5µF

CA3086

2.2kΩ

62kΩ

VOLTAGE

ADJUST

10µF+

2.7kΩ

1kΩ

HUM AND NOISE OUTPUT <200 µVRMS

(MEASUREMENT BANDWIDTH ~10MHz)

LINE REGULATION 0.1%/VOLT

LOAD REGULATION

(NO LOAD TO FULL LOAD)

<0.02%

OUTPUT ⇒ 0V TO 25V

25V AT 1A

100kΩ

“FOLDS BACK”

TO 40mA

100kΩ

Both regulators, Figures 24 and 25, provide better than 0.02%

load regulation. Because there is constant loop gain at all volt-

age settings, the regulation also remains constant. Line regu-

lation is 0.1% per volt. Hum and noise voltage is less than

200µV as read with a meter having a 10MHz bandwidth.

Figure 28 (a) shows the turn ON and turn OFF characteris-

tics of both regulators. The slow turn on rise is due to the

slow rate of rise of the reference voltage. Figure 26 (B)

shows the transient response of the regulator with the

switching of a 20Ω load at 20V output.

Tone Control Circuits

High slew rate, wide bandwidth, high output voltage capabil-

ity and high input impedance are all characteristics required

of tone control ampliﬁers. Two tone control circuits that

exploit these characteristics of the CA3140 are shown in Fig-

ures 27 and 28.

(A) SUPPLY TURN-ON AND TURNOFF CHARACTERISTICS

5V/Div and -1s/Div

(B) TRANSIENT RESPONSE

Top Trace: Output voltage

200mV/Div and 5µs/Div

Bottom Trace: Collector of load switching transistor, load = 1A

5V/Div and 5µs/Div

FIGURE 26. WAVEFORMS OF DYNAMIC CHARACTERISTICS

OF POWER SUPPLY CURRENTS SHOWN IN FIG-

URES 24 AND 25

2-139

CA3140, CA3140A

The ﬁrst circuit, shown in Figure 28, is the Baxandall tone

control circuit which provides unity gain at midband and uses

standard linear potentiometers. The high input impedance of

the CA3140 makes possible the use of low-cost, low-value,

small size capacitors, as well as reduced load of the driving

stage.

Bass treble boost and cut are ±15dB at 100Hz and 10kHz,

respectively. Full peak-to-peak output is available up to at

least 20kHz due to the high slew rate of the CA3140. The

ampliﬁer gain is 3dB down from its “ﬂat” position at 70kHz.

Figure 27 shows another tone control circuit with similar

boost and cut speciﬁcations. The wideband gain of this cir-

cuit is equal to the ultimate boost or cut plus one, which in

this case is a gain of eleven. For 20dB boost and cut, the

input loading of this circuit is essentially equal to the value of

the resistance from terminal No. 3 to ground. A detailed

analysis of this circuit is given in “An IC Operational

T ransconductanceAmpliﬁer (OTA) With Power Capability” by

L. Kaplan and H. Wittlinger, IEEE T ransactions on Broadcast

and Television Receivers, Vol. BTR-18, No. 3, August, 1972.

FIGURE 27. TONE CONTROL CIRCUIT USING CA3130 SERIES (20dB MIDBAND GAIN)

FIGURE 28. BAXANDALL TONE CONTROL CIRCUIT USING CA3140 SERIES

CA3140

+30V

0.1µF

0.005µF

0.1

µF

2.2MΩ

5.1

MΩ

0.012µF 0.001µF

0.022µF

2µF

18kΩ

0.0022µF

200kΩ

(LINEAR)

100

pF 100pF

BOOST TREBLE CUT

BOOST BASS CUT

10kΩ1MΩ

CCW (LOG) 100kΩ

TONE CONTROL NETWORK

FOR SINGLE SUPPLY

+15V

30.1µF

0.005µF

5.1MΩ

0.1µF

-15V

CA3140

TONE CONTROL NETWORK

FOR DUAL SUPPLIES

20dB Flat Position Gain

±15dB Bass and Treble Boost and Cut at

100Hz and 10kHz, respectively

25VP-P output at 20kHz

-3dB at 24kHz from 1kHz reference

CA3140

+32V

0.1

2.2MΩ

MΩ

FOR SINGLE SUPPLY

µF

0.1

µF

20pF

750

2.2MΩ

0.047µF

BOOST TREBLE CUT

51kΩ5MΩ

(LINEAR) 51kΩ

TONE CONTROL NETWORK

BOOST BASS CUT

240kΩ5MΩ

(LINEAR) 240kΩ

+15V

30.1µF

0.047µF

0.1µF

-15V

CA3140

TONE CONTROL

FOR DUAL SUPPLIES

NETWORK

±15dB Bass and Treble Boost and Cut at

100Hz and 10kHz, respectively

25VP-P output at 20kHz

-3dB at 70kHz from 1kHz reference

0dB Flat Position Gain

2-140

CA3140, CA3140A

Wien Bridge Oscillator

Another application of the CA3140 that makes excellent use

of its high input impedance, high slew rate, and high voltage

qualities is the Wien Bridge sine wave oscillator. A basic Wien

Bridge oscillator is shown in Figure 29. When R1 = R2 = R and

C1 = C2 = C, the frequency equation reduces to the familiar

f=1

2π RC and the gain required for oscillation, AOSC is

equal to 3. Note that if C2 is increased by a factor of four and

R2 is reduced by a factor of four, the gain required for

oscillation becomes 1.5, thus permitting a potentially higher

operating frequency closer to the gain bandwidth product of

the CA3140.

FIGURE 29. BASIC WIEN BRIDGE OSCILLATOR CIRCUIT US-

ING AN OPERATIONAL AMPLIFIER

Oscillator stabilization takes on many forms. It must be

precisely set, otherwise the amplitude will either diminish or

reach some form of limiting with high levels of distortion. The

element, RS, is commonly replaced with some variable

resistance element. Thus, through some control means, the

value of RS is adjusted to maintain constant oscillator output.

A FET channel resistance, a thermistor , a lamp bulb, or other

device whose resistance is made to increase as the output

amplitude is increased are a few of the elements often

utilized.

Figure 30 shows another means of stabilizing the oscillator

with a zener diode shunting the feedback resistor (Rf of

Figure 29). As the output signal amplitude increases, the

zener diode impedance decreases resulting in more

feedback with consequent reduction in gain; thus stabilizing

the amplitude of the output signal. Furthermore, this

combination of a monolithic zener diode and bridge rectiﬁer

circuit tends to provide a zero temperature coefﬁcient for this

regulating system. Because this bridge rectiﬁer system has

no time constant, i.e., thermal time constant for the lamp

bulb, and RC time constant for ﬁlters often used in detector

networks, there is no lower frequency limit. For example,

with 1µF polycarbonate capacitors and 22MΩ for the

frequency determining network, the operating frequency is

0.007Hz.

As the frequency is increased, the output amplitude must be

reduced to prevent the output signal from becoming slew-

rate limited. An output frequency of 180kHz will reach a slew

rate of approximately 9V/µs when its amplitude is 16V peak-

to-peak.

NOTES:f1

2πR1C1R2C2

----------------------------=

AOS 1C1

------- R2

-------++=

CL 1Rf

-------+=

OUTPUT

-FIGURE 30. WIEN BRIDGE OSCILLATOR CIRCUIT USING

CA3140 SERIES

Simple Sample-and-Hold System

Figure 31 shows a very simple sample-and-hold system

using the CA3140 as the readout ampliﬁer for the storage

capacitor. The CA3080A serves as both input buffer ampli-

ﬁer and low feed-through transmission switch.* System off-

set nulling is accomplished with the CA3140 via its offset

nulling terminals. A typical simulated load of 2kΩ and 30pF

is shown in the schematic.

FIGURE 31. SAMPLE AND HOLD CIRCUIT

In this circuit, the storage compensation capacitance (C1) is

only 200pF. Larger value capacitors provide longer “hold”

periods but with slower slew rates. The slew rate

* ICAN-6668 “Applications of the CA3080 and CA 3080A High Per-

formance Operational Transconductance Ampliﬁers”.

Pulse “droop” during the hold interval is 170pA/200pF which

is = 0.85µV/µs; (i.e., 170pA/200pF). In this case, 170pA

5 4

CA3109

DIODE

ARRAY

+15V

0.1µF

-15V

CA3140

-SUBSTRATE

OF CA3019

0.1µF

7.5kΩ

3.6kΩ

500Ω

OUTPUT

19VP-P TO 22VP-P

THD <0.3%

C2 1000pF

1000

R1 = R2 = R

50Hz, R = 3.3MΩ

100Hz, R = 1.6MΩ

1kHz, R = 160MΩ

10kHz, R = 16MΩ

30kHz, R = 5.1MΩ

+15V

3.5kΩ

30pF

CA3140

SIMULATED LOAD

NOT REQUIRED

100kΩ

INPUT

0.1

0.1µF

µF

0.1µF

-15V 2kΩ

400Ω

200pF

CA3080A

0.1µF

+15V

-15V

200pF

2kΩ

STROBE SAMPLE

HOLD-15

30kΩ

IN914

2kΩ

------ ic

--- 0.5mA 200pF⁄2.5V µs⁄== =

2-141

CA3140, CA3140A

represents the typical leakage current of the CA3080A when

strobed off. If C1 were increased to 2000 pF, the “hold-droop”

rate will decrease to 0.085µV/µs, but the slew rate would

decrease to 0.25V/µs. The parallel diode network connected

between terminal 3 of the CA3080A and terminal 6 of the

CA3140 prevents large input signal feedthrough across the

input terminals of the CA3080A to the 200pF storage capacitor

when the CA3080A is strobed off. Figure 32 shows dynamic

characteristic waveforms of this sample-and-hold system.

Top Trace: Output; 50mV/Div and 200ns/Div

Bottom Trace: Input; 50mV/Div and 200ns/Div

LARGE SIGNAL RESPONSE AND SETTLING TIME

Top Trace: Output Signal; 5V/Div and 2µs/Div

Center Trace: Difference of Input and Output Signals through

Tektronix Ampliﬁer 7A13; 5mV/Div and 2µs/Div

Bottom Trace: Input Signal; 5V/Div and 2µs/Div

SAMPLING RESPONSE

Top Trace: Output; 100mV/Div and 500ns/Div

Bottom Trace: Input; 20V/Div and 500ns/Div

FIGURE 32. SAMPLE AND HOLD SYSTEM DYNAMIC CHARAC-

TERISTICS WAVEFORMS

Current Ampliﬁer

The low input terminal current needed to drive the CA3140

makes it ideal for use in current ampliﬁer applications such

as the one shown in Figure 33.* In this circuit, low current is

supplied at the input potential as the power supply to load

resistor RL. This load current is increased by the multiplica-

tion factor R2/R1, when the load current is monitored by the

power supply meter M. Thus, if the load current is 100nA,

with values shown, the load current presented to the supply

will be 100µA; a much easier current to measure in many

systems.

FIGURE 33. BASIC CURRENT AMPLIFIER FOR LOW CURRENT

MEASUREMENT SYSTEMS

Note that the input and output voltages are transferred at the

same potential and only the output current is multiplied by

the scale factor.

The dotted components show a method of decoupling the

circuit from the effects of high output load capacitance and

the potential oscillation in this situation. Essentially, the

necessary high frequency feedback is provided by the

capacitor with the dotted series resistor providing load

decoupling.

Figure 34 shows a single supply, absolute value, ideal full-

wave rectiﬁer with associated waveforms. During positive

excursions, the input signal is fed through the feedback

network directly to the output. Simultaneously, the positive

excursion of the input signal also drives the output terminal

(No. 6) of the inverting ampliﬁer in a negative going

excursion such that the 1N914 diode effectively disconnects

the ampliﬁer from the signal path. During a negative going

excursion of the input signal, the CA3140 functions as a

normal inverting ampliﬁer with a gain equal to -R2/R1. When

the equality of the two equations shown in Figure 34 is

satisﬁed, the full wave output is symmetrical.

* “Operational Ampliﬁers Design and Applications”, J. G. Graeme,

McGraw-Hill Book Company, page 308 - “Negative Immittance

Converter Circuits”.

+15V

100kΩ

0.1µF

-15V

CA3140

-0.1µF

4.3kΩ

10kΩ

POWER

SUPPLY

10MΩ

ILR2

2-142

CA3140, CA3140A

FIGURE 34. SINGLE SUPPLY, ABSOLUTE V ALUE, IDEAL FULL

WA VE RECTIFIER WITH ASSOCIA TED WAVEFORMS

(A) SMALL SIGNAL RESPONSE

50mV/Div and 200ns/Div

Top Trace: Output; 50mV/Div and 200ns/Div

Bottom Trace: Input; 50mV/Div and 200ns/Div

(B) INPUT-OUTPUT DIFFERENCE SIGNAL

SHOWING SETTLING TIME

(measurement made with Tektronix 7A13 differential ampliﬁer)

Top Trace: Output Signal; 5V/Div and 5µs/Div

Center Trace: Difference Signal; 5mV/Div and 5µs/Div

Bottom Trace: Input Signal; 5V/Div and 5µs/Div

FIGURE 36. SPLIT SUPPLY VOLTAGE FOLLOWER TEST CIR-

CUIT AND ASSOCIATED WAVEFORMS

FIGURE 35. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR

WIDEBAND NOISE MEASUREMENT

+15V

0.1µF

5kΩ

10kΩ

1N914

10kΩ

100kΩ

OFFSET

ADJUST

PEAK

ADJUST

10kΩ

CA3140

GAIN R2

------- XR3

R1 R2 R3

----------------------------------===

R3 XX

1X–

----------------







R1=

FORX 0.5 5kΩ

10kΩ

------------- R2

-------==

R3 10kΩ0.75

0.5

----------





15kΩ==

20Vp-p Input BW(-3dB) 290kHz=DCOutput (Avg),3.2V=

OUTPUT

INPUT

+15V

-15V

CA3140

0.1µF

0.05µF

2kΩ

100kΩ

100pF

SIMULATED

LOAD

2kΩ

BW (-3dB) = 4.5MHz

SR = 9V/µs

+15V

-15V

CA3140

0.01µF

1MΩNOISE VOLTAGE

OUTPUT

30.1kΩ

1kΩ

BW (-3dB) = 140kHz

TOTAL NOISE VOLTAGE

(REFERRED TO INPUT ) = 48µV TYP.