PCA9575PW1,118 - NXP Semiconductors / Philips Semiconductors

1. General description

The PCA9575 is a CMOS device that provides 16 bits of General Purpose parallel

Input/Output (GPIO) expansion in low voltage processor and handheld battery powered

mobile applications and was developed to enhance the NXP family of I2C-bus I/O

expanders. The improvements include lower supply current, lower operating voltage of

1.1 V to 3.6 V, separate supply rails to allow voltage level translation anywhere between

1.1 V and 3.6 V, 400 kHz clock frequency, and smaller packaging. Any of the 16 I/O ports

can be conﬁgured as an input or output independent of each other and default on start-up

to inputs.

I/O expanders provide a simple solution when additional I/Os are needed while keeping

interconnections to a minimum; for example in battery powered mobile applications and

clamshell devices for interfacing to sensors, push buttons, keypad, etc. In addition to

providing a ﬂexible set of GPIOs, it simpliﬁes interconnection of a processor running at

one voltage level to I/O devices operating at a different (usually higher) voltage level.

PCA9575 has built-in level shifting feature that makes these devices extremely ﬂexible in

mixed signal environments where communication between incompatible I/Os is required.

The core of PCA9575 can operate at a voltage as low as 1.1 V while each I/O bank can

operate in the range 1.1 V to 3.6 V. Bus hold with programmable on-chip pull-up or

pull-down feature for I/Os is also provided.

The output stage consists of two banks each of 8-bit conﬁguration registers, input

registers, interrupt mask registers, output registers, bus-hold and pull-up/pull-down

registers and polarity inversion registers. These registers allow the system master to

program and conﬁgure 16 GPIOs through the I2C-bus.

The system master can enable the I/Os as either inputs or outputs by writing to the I/O

conﬁguration register bits. The data for each input or output is kept in the corresponding

Input or Output register. The polarity of the read registers can be inverted with the Polarity

Inversion register (active HIGH or active LOW operation). Either a bus-hold function or

pull-up/pull-down feature can be selected by programming corresponding registers. The

bus-hold provides a valid logic level when the I/O bus is not actively driven. When

bus-hold feature is not selected, the I/O ports can be conﬁgured to have pull-up or

pull-down by programming the pull-up/pull-down conﬁguration register.

An open-drain interrupt output pin (INT) allows monitoring of the input pins and is

asserted each time a change occurs on an input port unless that port is masked

(default = masked). A ‘GPIO All Call’ command allows programming multiple PCA9575s

at the same time even if they have different individual I2C-bus addresses. This allows

optimal code programming when more than one device needs to be programmed with the

same instruction or if all outputs need to be turned on or off at the same time. The internal

PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

with reset and interrupt

Rev. 03 — 9 November 2009 Product data sheet

Product data sheet Rev. 03 — 9 November 2009 2 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

Power-On Reset (POR) or hardware reset pin (RESET) initializes the two banks of 8 I/Os

as inputs, sets the registers to their default values and initializes the device state machine.

The I/O banks are held in its default state when the logic supply (VDD) is off.

The PCA9575 is available in 24-pin TSSOP, 28-pin TSSOP and HWQFN24 packages,

and is speciﬁed over the −40 °C to +85 °C industrial temperature range.

The 28-pin package provides four address select pins, allowing up to 16 PCA9575

devices to be connected with 16 different addresses on the same I2C-bus.

2. Features

nSeparate supply rails for core logic and each of the two I/O banks provides voltage

level shifting

n1.1 V to 3.6 V operation with level shifting feature

nVery low standby current: < 2 µA

n16 conﬁgurable I/O pins organized as 2 banks that default to inputs at power-up

nOutputs:

uTotem pole: 1 mA source and 3 mA sink

uIndependently programmable 100 kΩ pull-up or pull-down for each I/O pin

uOpen-drain active LOW interrupt (INT) output pin allows monitoring of logic level

change of pins programmed as inputs

nInputs:

uProgrammable bus hold provides valid logic level when inputs are not actively

driven

uProgrammable Interrupt Mask Control for input pins that do not require an interrupt

when their states change or to prevent spurious interrupts default to mask at

power-up

uPolarity Inversion register allows inversion of the polarity of the I/O pins when read

n400 kHz I2C-bus serial interface

nCompliant with I2C-bus Standard-mode (100 kHz)

nActive LOW reset (RESET) input pin resets device to power-up default state

nGPIO All Call address allows programming of more than one device at the same time

with the same parameters

n16 programmable slave addresses using 4 address pins (28-pin TSSOP only)

n−40 °C to +85 °C operation

nESD protection exceeds 6000 V HBM per JESD22-A114, 500 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

nLatch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

nPackages offered: TSSOP28, TSSOP24, HWQFN24

Product data sheet Rev. 03 — 9 November 2009 3 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

3. Applications

nCell phones

nMedia players

nMulti-voltage environments

nBattery operated mobile gadgets

nMotherboards

nServers

nRAID systems

nIndustrial control

nMedical equipment

nPLCs

nGaming machines

nInstrumentation and test measurement

4. Ordering information

Table 1. Ordering information

Type number Topside mark Package

Name Description Version

PCA9575PW2 PCA9575PW2 TSSOP28 plastic thin shrink small outline package; 28 leads;

body width 4.4 mm SOT361-1

PCA9575PW1 PA9575PW1 TSSOP24 plastic thin shrink small outline package; 24 leads;

body width 4.4 mm SOT355-1

PCA9575HF 575F HWQFN24 plastic thermal enhanced very very thin quad ﬂat package;

no leads; 24 terminals; body 4 ×4×0.75 mm SOT994-1

Product data sheet Rev. 03 — 9 November 2009 4 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

5. Block diagram

Remark: All I/Os are set to inputs at power-up and RESET.

(1) PCA9575PW2 only.

Fig 1. Block diagram of PCA9575

PCA9575

POWER-ON

RESET

002aad562

I2C-BUS/SMBus

CONTROL

INPUT

FILTER

SCL

SDA

VDD

INPUT/

OUTPUT

PORTS

BANK 0

P0_0

VSS

8-bit

write pulse

read pulse

P0_2

P0_4

P0_6

P0_1

P0_3

P0_5

P0_7

FILTER

VDD

INT

RESET

VDD(IO)0

INPUT/

OUTPUT

PORTS

BANK 1

P1_0

8-bit

write pulse

read pulse

P1_2

P1_4

P1_6

P1_1

P1_3

P1_5

P1_7

VDD(IO)1

(1)

Product data sheet Rev. 03 — 9 November 2009 5 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

Fig 2. Simpliﬁed schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7)

INTERRUPT

MASK

VDD(IO)

P0_0 to P0_7

P1_0 to P1_7

output port

configuration

CK Q

data from

shift register

write

configuration

pulse

output port

write pulse

polarity

inversion

data from

shift register

write polarity

pulse

input port

read pulse

input port

polarity

inversion

002aad566

data from

shift register

VSS

to INT

BUS-HOLD

AND

PULL-UP/PULL-DOWN

CONTROL

ESD

protection

diode

100 kΩ

VDD(IO)

Product data sheet Rev. 03 — 9 November 2009 6 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

6. Pinning information

6.1 Pinning

Fig 3. Pin conﬁguration for TSSOP24 Fig 4. Pin conﬁguration for TSSOP28

Fig 5. Pin conﬁguration for HWQFN24

SCL

SDA

P1_0

P1_1

P1_2

P1_3

VDD(IO)1

P1_4

P1_5

P1_6

P1_7

VSS

VDD(IO)0

P0_4

P0_5

P0_6

P0_7

INT

VDD

RESET

P0_0

P0_1

P0_2

P0_3 PCA9575PW1

002aad564

PCA9575PW2

A0 SCL

VDD SDA

RESET P1_0

P0_0 P1_1

P0_1 P1_2

P0_2 P1_3

P0_3 A3

A1 VDD(IO)1

VDD(IO)0 P1_4

P0_4 P1_5

P0_5 P1_6

P0_6 P1_7

P0_7 VSS

INT A2

002aad563

002aad575

PCA9575HF

Transparent top view

P1_5

P0_4

P0_5

P1_4

VDD(IO)0 VDD(IO)1

P0_3 P1_3

P0_2 P1_2

P0_1 P1_1

P0_6

P0_7

INT

VSS

P1_7

P1_6

P0_0

RESET

VDD

SCL

SDA

P1_0

terminal 1

index area

613

514

4 15

3 16

2 17

118

Product data sheet Rev. 03 — 9 November 2009 7 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

6.2 Pin description

[1] HWQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must

be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board

level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad

on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the

PCB in the thermal pad region.

Table 2. Pin description

Symbol Pin Type Description

TSSOP28 TSSOP24 HWQFN24

A0 1 - - I address input 0

VDD 2 1 22 power supply supply voltage

RESET 3 2 23 I active LOW reset input

P0_0 4 3 24 I/O port 0 input/output 0

P0_1 5 4 1 I/O port 0 input/output 1

P0_2 6 5 2 I/O port 0 input/output 2

P0_3 7 6 3 I/O port 0 input/output 3

A1 8 - - I address input 1

VDD(IO)0 9 7 4 power supply I/O supply voltage for bank 0

P0_4 10 8 5 I/O port 0 input/output 0

P0_5 11 9 6 I/O port 0 input/output 1

P0_6 12 10 7 I/O port 0 input/output 2

P0_7 13 11 8 I/O port 0 input/output 3

INT 14 12 9 O interrupt output (open-drain;

active LOW)

A2 15 - - I address input 2

VSS 16 13 10[1] ground supply ground

P1_7 17 14 11 I/O port 1 input/output 4

P1_6 18 15 12 I/O port 1 input/output 5

P1_5 19 16 13 I/O port 1 input/output 6

P1_4 20 17 14 I/O port 1 input/output 7

VDD(IO)1 21 18 15 power supply I/O supply voltage for bank 1

A3 22 - - I address input 3

P1_3 23 19 16 I/O port 1 input/output 3

P1_2 24 20 17 I/O port 1 input/output 2

P1_1 25 21 18 I/O port 1 input/output 1

P1_0 26 22 19 I/O port 1 input/output 0

SDA 27 23 20 I/O serial data line

SCL 28 24 21 I serial clock line

Product data sheet Rev. 03 — 9 November 2009 8 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

7. Functional description

7.1 I/O ports

The 16 I/O ports are organized as two banks of 8 ports each. The system master can

enable the I/Os as either inputs or outputs by writing to the I/O conﬁguration register bits.

The data for each input or output is kept in the corresponding Input or Output register. The

polarity of the read register can be inverted with the Polarity Inversion register. Either a

bus-hold function or pull-up/pull-down feature can be selected by programming

corresponding registers. A bus-hold provides a valid logic level when the I/O bus is not

actively driven. It consists of a pair of buffers, one being weak (low drive-strength), that

latch the input at the last driven value. This prevents the input from ﬂoating while it is being

driven by a 3-state output. Latching the last valid logic state of input prevents it from

settling at a midpoint between VDD and ground that in turn consumes power. An active bus

driver can easily override the logic level set by the bus-keeper.

When bus-hold feature is not selected, the I/O ports can be conﬁgured to have pull-up or

pull-down by programming the pull-up/pull-down conﬁguration register.

7.2 Device address

Following a START condition, the bus master must send the address of the slave it is

accessing and the operation it wants to perform (read or write). Address conﬁguration for

the device depends on the package type chosen. The device offered in a 24-pin package

will have a ﬁxed slave address for the PCA9575 as shown in Figure 6.

The last bit of the ﬁrst byte deﬁnes the operation to be performed. When set to logic 1 a

read is selected, while logic 0 selects a write operation.

The slave address for the 28-pin version of the PCA9575 is shown in Figure 7.

Fig 6. PCA9575 device address for 24-pin version

Fig 7. PCA9575 device address for 28-pin version

002aad567

0 1 0 0 0 0 0 R/W

fixed

slave address

002aad583

0 1 0 A3 A2 A1 A0 R/W

fixed

slave address

hardware selectable

Product data sheet Rev. 03 — 9 November 2009 9 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

7.3 Command register

Following the successful acknowledgement of the slave address + R/W bit, the bus master

will send a byte to the PCA9575, which will be stored in the Command register.

The lowest 4 bits are used as a pointer to determine which register will be accessed. Only

a Command register code with the 4 least signiﬁcant bits equal to the 16 allowable values

as deﬁned in Table 3 “Register summary” will be acknowledged. Reserved or undeﬁned

command codes will not be acknowledged. At power-up, this register defaults to 00h, with

the AI bit set to logic 0, and the lowest 4 bits set to logic 0.

If the Auto-Increment ﬂag is set (AI = 1), the 4 least signiﬁcant bits of the Command

program and/or read the 16 command registers (listed in Table 3) sequentially. It will then

roll over to register 00h after the last register is accessed and the selected registers will be

overwritten or re-read.

If the Auto-Increment ﬂag is cleared (AI = 0), the 4 least signiﬁcant bits are not

incremented after data is read or written, only one register will be repeatedly read or

written.

7.4 Register deﬁnitions

Reset state = 00h

Remark: The Command register does not apply to Software Reset I2C-bus address.

Fig 8. Command register

002aad568

AI 0 0 0 D3 D2 D1 D0

Auto-Increment flag

Table 3. Register summary

00h 0 0 0 0 IN0 read only Input port 0 register

01h 0 0 0 1 IN1 read only Input port 1 register

02h 0 0 1 0 INVRT0 read/write Polarity inversion port 0 register

03h 0 0 1 1 INVRT1 read/write Polarity inversion port 1 register

04h 0 1 0 0 BKEN0 read/write Bus-hold enable 0 register

05h 0 1 0 1 BKEN1 read/write Bus-hold enable 1 register

06h 0 1 1 0 PUPD0 read/write Pull-up/pull-down selector port 0 register

07h 0 1 1 1 PUPD1 read/write Pull-up/pull-down selector port 1 register

08h 1 0 0 0 CFG0 read/write Conﬁguration port 0 register

09h 1 0 0 1 CFG1 read/write Conﬁguration port 1 register

0Ah 1 0 1 0 OUT0 read/write Output port 0 register

0Bh 1 0 1 1 OUT1 read/write Output port 1 register

0Ch 1 1 0 0 MSK0 read/write Interrupt mask port 0 register

Product data sheet Rev. 03 — 9 November 2009 10 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

7.5 Writing to port registers

Data is transmitted to the PCA9575 by sending the device address and setting the least

signiﬁcant bit to logic 0 (see Figure 6 or Figure 7 for device address). The command byte

is sent after the address and determines which register will receive the data following the

command byte. Each 8-bit register may be updated independently of the other registers.

7.6 Reading the port registers

In order to read data from the PCA9575, the bus master must ﬁrst send the PCA9575

address with the least signiﬁcant bit set to a logic 0 (see Figure 6 or Figure 7 for device

address). The command byte is sent after the address and determines which register will

be accessed. After a restart, the device address is sent again but this time, the least

signiﬁcant bit is set to logic 1. Data from the register deﬁned by the command byte will

then be sent by the PCA9575. Data is clocked into the register on the falling edge of the

acknowledge clock pulse. After the ﬁrst byte is read, additional bytes may be read using

the auto-increment feature.

7.6.1 Register 0 - Input port 0 register

This register is read-only. It reﬂects the incoming logic levels of the pins, regardless of

whether the pin is deﬁned as an input or an output by the Conﬁguration register. Writes to

this register will be acknowledged but will have no effect.

The default ‘X’ is determined by the externally applied logic level.

0Dh 1 1 0 1 MSK1 read/write Interrupt mask port 1 register

0Eh 1 1 1 0 INTS0 read only Interrupt status port 0 register

0Fh 1 1 1 1 INTS1 read only Interrupt status port 1 register

Table 3. Register summary

…continued

Table 4. Register 0 - Input port 0 register (address 00h) bit description

Bit Symbol Access Value Description

7 IO0.7 read only X determined by externally applied logic level

6 IO0.6 read only X

5 IO0.5 read only X

4 IO0.4 read only X

3 IO0.3 read only X

2 IO0.2 read only X

1 IO0.1 read only X

0 IO0.0 read only X

Product data sheet Rev. 03 — 9 November 2009 11 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

7.6.2 Register 1 - Input port 1 register

This register is read-only. It reﬂects the incoming logic levels of the pins, regardless of

whether the pin is deﬁned as an input or an output by the Conﬁguration register. Writes to

this register will be acknowledged but will have no effect.

The default ‘X’ is determined by the externally applied logic level.

7.6.3 Register 2 - Polarity inversion port 0 register

This register allows the user to invert the polarity of the Input port register data. If a bit in

this register is set (written with ‘1’), the corresponding Input port data is inverted. If a bit in

this register is cleared (written with a ‘0’), the Input port data polarity is retained.

Table 5. Register 1 - Input port 1 register (address 01h) bit description

Bit Symbol Access Value Description

7 IO1.7 read only X determined by externally applied logic level

6 IO1.6 read only X

5 IO1.5 read only X

4 IO1.4 read only X

3 IO1.3 read only X

2 IO1.2 read only X

1 IO1.1 read only X

0 IO1.0 read only X

Table 6. Register 2 - Polarity Inversion port 0 register (address 02h) bit description

Legend: * default value.

Bit Symbol Access Value Description

7 N0.7 R/W 0* inverts polarity of Input port 0 register data

0 = Input port 0 register data retained (default value)

1 = Input port 0 register data inverted

6 N0.6 R/W 0*

5 N0.5 R/W 0*

4 N0.4 R/W 0*

3 N0.3 R/W 0*

2 N0.2 R/W 0*

1 N0.1 R/W 0*

0 N0.0 R/W 0*

Product data sheet Rev. 03 — 9 November 2009 12 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

7.6.4 Register 3 - Polarity inversion port 1 register

This register allows the user to invert the polarity of the Input port register data. If a bit in

this register is set (written with ‘1’), the corresponding Input port data is inverted. If a bit in

this register is cleared (written with a ‘0’), the Input port data polarity is retained.

7.6.5 Register 4 - Bus-hold/pull-up/pull-down enable 0 register

Bit 0 of this register allows the user to enable/disable the bus-hold feature for the I/O pins.

Setting the bit 0 to logic 1 enables bus-hold feature for the I/O bank 0. In this mode, the

pull-up/pull-downs will be disabled for I/O bank 0. Setting the bit 0 to logic 0 disables

bus-hold feature.

Bit 1 of this register allows the user to enable/disable pull-up/pull-downs on the I/O pins.

Setting the bit 1 to logic 1 enables selection of pull-up/pull-down using Register 6. Setting

the bit 1 to logic 0 disables pull-up/pull-downs on the I/O bank 0 pins and contents of

Table 7. Register 3 - Polarity Inversion port 1 register (address 03h) bit description

Legend: * default value.

Bit Symbol Access Value Description

7 N1.7 R/W 0* inverts polarity of Input port 1 register data

0 = Input port 1 register data retained (default value)

1 = Input port 1 register data inverted

6 N1.6 R/W 0*

5 N1.5 R/W 0*

4 N1.4 R/W 0*

3 N1.3 R/W 0*

2 N1.2 R/W 0*

1 N1.1 R/W 0*

0 N1.0 R/W 0*

Table 8. Register 4 - Bus-hold/pull-up/pull-down enable 0 register (address 04h)

bit description

Legend: * default value.

Bit Symbol Access Value Description

7 E0.7 R/W X not used

6 E0.6 R/W X

5 E0.5 R/W X

4 E0.4 R/W X

3 E0.3 R/W X

2 E0.2 R/W X

1 E0.1 R/W 0* allows the user to enable/disable pull-up/pull-downs on the

I/O bank 0 pins

0 = disables pull-up/pull-downs on the I/O bank 0 pins and

contents of Register 6 will have no effect on the I/O bank 0

(default value)

1 = enables selection of pull-up/pull-down using Register 6

0 E0.0 R/W 0* allows user to enable/disable the bus-hold feature for the

I/O bank 0 pins

0 = disables bus-hold feature (default value)

1 = enables bus-hold feature

Product data sheet Rev. 03 — 9 November 2009 13 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

7.6.6 Register 5 - Bus-hold/pull-up/pull-down enable 1 register

Bit 0 of this register allows the user to enable/disable the bus-hold feature for the I/O pins.

Setting the bit 0 to logic 1 enables bus-hold feature for the I/O bank 1. In this mode, the

pull-up/pull-downs will be disabled for I/O bank 1. Setting the bit 0 to logic 0 disables

bus-hold feature.

Bit 1 of this register allows the user to enable/disable pull-up/pull-downs on the I/O pins.

Setting the bit 1 to logic 1 enables selection of pull-up/pull-down using Register 7. Setting

the bit 1 to logic 0 disables pull-up/pull-downs on the I/O bank 1 pins and contents of

Table 9. Register 5 - Bus-hold/pull-up/pull-down enable 1 register (address 05h)

bit description

Legend: * default value.

Bit Symbol Access Value Description

7 E1.7 R/W X not used

6 E1.6 R/W X

5 E1.5 R/W X

4 E1.4 R/W X

3 E1.3 R/W X

2 E1.2 R/W X

1 E1.1 R/W 0* allows the user to enable/disable pull-up/pull-downs on the

I/O bank 1 pins

0 = disables pull-up/pull-downs on the I/O bank 1 pins and

contents of Register 7 will have no effect on the I/O bank 0

(default value)

1 = enables selection of pull-up/pull-down using Register 7

0 E1.0 R/W 0* allows user to enable/disable the bus-hold feature for the

I/O bank 1 pins

0 = disables bus-hold feature (default value)

1 = enables bus-hold feature

Product data sheet Rev. 03 — 9 November 2009 14 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

7.6.7 Register 6 - Pull-up/pull-down select port 0 register

When bus-hold feature is not selected and bit 1 of Register 4 is set to logic 1, the I/O

port 0 can be conﬁgured to have pull-up or pull-down by programming the

pull-up/pull-down register. Setting a bit to logic 1 will select a 100 kΩ pull-up resistor for

that I/O pin. Setting a bit to logic 0 will select a 100 kΩpull-down resistor for that I/O pin. If

the bus-hold feature is enabled, writing to this register will have no effect on

pull-up/pull-down selection.

7.6.8 Register 7 - Pull-up/pull-down select port 1 register

When bus-hold feature is not selected and bit 1 of Register 5 is set to logic 1, the I/O

port 1 can be conﬁgured to have pull-up or pull-down by programming the

pull-up/pull-down register. Setting a bit to logic 1 will select a 100 kΩ pull-up resistor for

that I/O pin. Setting a bit to logic 0 will select a 100 kΩpull-down resistor for that I/O pin. If

the bus-hold feature is enabled, writing to this register will have no effect on

pull-up/pull-down selection.

Table 10. Register 6 - Pull-up/pull-down select port 0 register (address 06h) bit description

Legend: * default value.

Bit Symbol Access Value Description

7 P0.7 R/W 1* conﬁgures I/O port 0 pin to have pull-up or pull-down when

bus-hold feature not selected and bit 1 of Register 4 is logic 1

0 = selects a 100 kΩ pull-down resistor for that I/O pin

1 = selects a 100 kΩpull-up resistor for that I/O pin (default

value)

6 P0.6 R/W 1*

5 P0.5 R/W 1*

4 P0.4 R/W 1*

3 P0.3 R/W 1*

2 P0.2 R/W 1*

1 P0.1 R/W 1*

0 P0.0 R/W 1*

Table 11. Register 7 - Pull-up/pull-down select port 1 register (address 07h) bit description

Legend: * default value.

Bit Symbol Access Value Description

7 P1.7 R/W 1* conﬁgures I/O port 1 pin to have pull-up or pull-down when

bus-hold feature not selected and bit 1 of Register 5 is logic 1

0 = selects a 100 kΩ pull-down resistor for that I/O pin

1 = selects a 100 kΩpull-up resistor for that I/O pin (default

value)

6 P1.6 R/W 1*

5 P1.5 R/W 1*

4 P1.4 R/W 1*

3 P1.3 R/W 1*

2 P1.2 R/W 1*

1 P1.1 R/W 1*

0 P1.0 R/W 1*

Product data sheet Rev. 03 — 9 November 2009 15 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

7.6.9 Register 8 - Conﬁguration port 0 register

This register conﬁgures the direction of the I/O pins. If a bit in this register is set (written

with logic 1), the corresponding port 0 pin is enabled as an input with high-impedance

output driver. If a bit in this register is cleared (written with logic 0), the corresponding

port 0 pin is enabled as an output. At reset, the device’s ports are inputs.

7.6.10 Register 9 - Conﬁguration port 1 register

This register conﬁgures the direction of the I/O pins. If a bit in this register is set (written

with logic 1), the corresponding port 1 pin is enabled as an input with high-impedance

output driver. If a bit in this register is cleared (written with logic 0), the corresponding

port 1 pin is enabled as an output. At reset, the device’s ports are inputs.

Table 12. Register 8 - Conﬁguration port 0 register (address 08h) bit description

Legend: * default value.

Bit Symbol Access Value Description

7 C0.7 R/W 1* conﬁgures the direction of the I/O pins

0 = corresponding port pin enabled as an output

1 = corresponding port pin conﬁgured as input

(default value)

6 C0.6 R/W 1*

5 C0.5 R/W 1*

4 C0.4 R/W 1*

3 C0.3 R/W 1*

2 C0.2 R/W 1*

1 C0.1 R/W 1*

0 C0.0 R/W 1*

Table 13. Register 9 - Conﬁguration port 1 register (address 09h) bit description

Legend: * default value.

Bit Symbol Access Value Description

7 C1.7 R/W 1* conﬁgures the direction of the I/O pins

0 = corresponding port pin enabled as an output

1 = corresponding port pin conﬁgured as input

(default value)

6 C1.6 R/W 1*

5 C1.5 R/W 1*

4 C1.4 R/W 1*

3 C1.3 R/W 1*

2 C1.2 R/W 1*

1 C1.1 R/W 1*

0 C1.0 R/W 1*

Product data sheet Rev. 03 — 9 November 2009 16 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

7.6.11 Register 10 - Output port 0 register

This register is an output-only port. It reﬂects the outgoing logic levels of the pins deﬁned

as outputs by Register 8. Bit values in this register have no effect on pins deﬁned as

inputs. In turn, reads from this register reﬂect the value that is in the ﬂip-ﬂop controlling the

output selection, not the actual pin value.

7.6.12 Register 11 - Output port 1 register

This register is an output-only port. It reﬂects the outgoing logic levels of the pins deﬁned

as outputs by Register 9. Bit values in this register have no effect on pins deﬁned as

inputs. In turn, reads from this register reﬂect the value that is in the ﬂip-ﬂop controlling the

output selection, not the actual pin value.

Table 14. Register 10 - Output port 0 register (address 0Ah) bit description

Legend: * default value.

Bit Symbol Access Value Description

7 O0.7 R/W 0* reﬂects outgoing logic levels of pins deﬁned as

outputs by Register 8

6 O0.6 R/W 0*

5 O0.5 R/W 0*

4 O0.4 R/W 0*

3 O0.3 R/W 0*

2 O0.2 R/W 0*

1 O0.1 R/W 0*

0 O0.0 R/W 0*

Table 15. Register 11 - Output port 1 register (address 0Bh) bit description

Legend: * default value.

Bit Symbol Access Value Description

7 O1.7 R/W 0* reﬂects outgoing logic levels of pins deﬁned as

outputs by Register 9

6 O1.6 R/W 0*

5 O1.5 R/W 0*

4 O1.4 R/W 0*

3 O1.3 R/W 0*

2 O1.2 R/W 0*

1 O1.1 R/W 0*

0 O1.0 R/W 0*

Product data sheet Rev. 03 — 9 November 2009 17 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

7.6.13 Register 12 - Interrupt mask port 0 register

All the bits of Interrupt mask port 0 register are set to logic 1 upon power-on or software

reset, thus disabling interrupts. Interrupts may be enabled by setting corresponding mask

bits to logic 0.

7.6.14 Register 13 - Interrupt mask port 1 register

All the bits of Interrupt mask port 1 register are set to logic 1 upon power-on or software

reset, thus disabling interrupts. Interrupts may be enabled by setting corresponding mask

bits to logic 0.

Table 16. Register 12 - Interrupt mask port 0 register (address 0Ch) bit description

Legend: * default value.

Bit Symbol Access Value Description

7 M0.7 R/W 1* enable or disable interrupts

0 = enable interrupt

1 = disable interrupt (default value)

6 M0.6 R/W 1*

5 M0.5 R/W 1*

4 M0.4 R/W 1*

3 M0.3 R/W 1*

2 M0.2 R/W 1*

1 M0.1 R/W 1*

0 M0.0 R/W 1*

Table 17. Register 13 - Interrupt mask port 1 register (address 0Dh) bit description

Legend: * default value.

Bit Symbol Access Value Description

7 M1.7 R/W 1* enable or disable interrupts

0 = enable interrupt

1 = disable interrupt (default value)

6 M1.6 R/W 1*

5 M1.5 R/W 1*

4 M1.4 R/W 1*

3 M1.3 R/W 1*

2 M1.2 R/W 1*

1 M1.1 R/W 1*

0 M1.0 R/W 1*

Product data sheet Rev. 03 — 9 November 2009 18 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

7.6.15 Register 14 - Interrupt status port 0 register

This register is read-only. It is used to identify the source of interrupt.

Remark: If the interrupts are masked, this register will return all zeros.

7.6.16 Register 15 - Interrupt status port 1 register

This register is read-only. It is used to identify the source of interrupt.

Remark: If the interrupts are masked, this register will return all zeros.

7.7 Power-on reset

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9575 in

a reset condition until VDD has reached VPOR. At that point, the reset condition is released

and the PCA9575 registers and state machine will initialize to their default states. The

power-on reset typically completes the reset and enables the part by the time the power

supply is above VPOR. However, when it is required to reset the part by lowering the power

supply, it is necessary to lower it below 0.2 V.

7.8 RESET input

A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The

PCA9575 registers and I2C-bus state machine will be held in their default state until the

RESET input is once again HIGH.

Table 18. Register 14 - Interrupt status port 0 register (address 0Eh) bit description

Legend: * default value.

Bit Symbol Access Value Description

7 S0.7 read only 0* identiﬁes source of interrupt

6 S0.6 read only 0*

5 S0.5 read only 0*

4 S0.4 read only 0*

3 S0.3 read only 0*

2 S0.2 read only 0*

1 S0.1 read only 0*

0 S0.0 read only 0*

Table 19. Register 15 - Interrupt status port 1 register (address 0Fh) bit description

Legend: * default value.

Bit Symbol Access Value Description

7 S1.7 read only 0* identiﬁes source of interrupt

6 S1.6 read only 0*

5 S1.5 read only 0*

4 S1.4 read only 0*

3 S1.3 read only 0*

2 S1.2 read only 0*

1 S1.1 read only 0*

0 S1.0 read only 0*

Product data sheet Rev. 03 — 9 November 2009 19 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

7.9 Software reset

The Software Reset Call allows all the devices in the I2C-bus to be reset to the power-up

state value through a speciﬁc formatted I2C-bus command. To be performed correctly, it

implies that the I2C-bus is functional and that there is no device hanging the bus.

The Software Reset sequence is deﬁned as following:

1. A START command is sent by the I2C-bus master.

2. The reserved General Call I2C-bus address ‘0000 000’ with the R/W bit set to 0 (write)

is sent by the I2C-bus master.

3. The PCA9575 device(s) acknowledge(s) after seeing the General Call address

‘0000 0000’ (00h) only. If the R/W bit is set to logic 1 (read), no acknowledge is

returned to the I2C-bus master.

4. Once the General Call address has been sent and acknowledged, the master sends

1 byte. The value of the byte must be equal to 06h (1000 0011).The PCA9575

acknowledges this value only. If the byte is not equal to 06h, the PCA9575 does not

acknowledge it. If more than 1 byte of data is sent, the PCA9575 does not

acknowledge anymore.

5. Once the right byte has been sent and correctly acknowledged, the master sends a

STOP command to end the Software Reset sequence: the PCA9575 then resets to

the default value (power-up value) and is ready to be addressed again within the

speciﬁed bus free time. If the master sends a Repeated START instead, no reset is

performed. The I2C-bus master must interpret a non-acknowledge from the PCA9575

(at any time) as a ‘Software Reset Abort’. The PCA9575 does not initiate a software

reset.

7.10 Interrupt output (INT)

The open-drain active LOW interrupt is activated when one of the port pins changes state

and the port pin is conﬁgured as an input and the interrupt on it is not masked. The

interrupt is deactivated when the port pin input returns to its previous state or the Input

Port register is read. It is highly recommended to program the MSK register, and the CFG

registers during the initialization sequence after power-up, since any change to them

during Normal mode operation may cause undesirable interrupt events to happen.

Remark: Changing an I/O from an output to an input may cause a false interrupt to occur

if the state of the pin does not match the contents of the Input Port register. Only a Read of

the Input Port register that contains the bit(s) image of the input(s) that generated the

interrupt clears the interrupt condition.

7.11 Standby

The PCA9575 goes into standby when the I2C-bus is idle. Standby supply current is lower

than 2.0 µA (typical).

Product data sheet Rev. 03 — 9 November 2009 20 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

8. Characteristics of the I2C-bus

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 9).

8.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is deﬁned as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP

condition (P) (see Figure 10).

8.2 System conﬁguration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 11).

Fig 9. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 10. Deﬁnition of START and STOP conditions

mba608

SDA

SCL P

STOP condition

START condition

Product data sheet Rev. 03 — 9 November 2009 21 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

8.3 Acknowledge

The number of data bytes transferred between the START and the STOP conditions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable

LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold

time must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Fig 11. System conﬁguration

002aaa966

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER MASTER

TRANSMITTER/

RECEIVER

SDA

SCL

I2C-BUS

MULTIPLEXER

SLAVE

Fig 12. Acknowledgement on the I2C-bus

002aaa987

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from master

Product data sheet Rev. 03 — 9 November 2009 22 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

9. Bus transactions

Data is transmitted to the PCA9575 registers using ‘Write Byte’ transfers (see Figure 13

and Figure 14).

Data is read from the PCA9575 registers using ‘Read Byte’ transfers (see Figure 15 and

Figure 16).

(1) Slave address shown in this example is for the 24-pin version.

Fig 13. Write to Output port register

0 AS

slave address(1)

START condition R/W acknowledge

from slave

002aad569

00010100

command byte

acknowledge

from slave

12345678SCL 9

SDA DATA 1 A

write to port

data out from port

tv(Q)

acknowledge

from slave

DATA 1 VALID

data to port

1000000P

STOP

condition

(1) Slave address shown in this example is for the 24-pin version.

Fig 14. Write to Polarity inversion, Bus-hold enable, Pull-up/pull-down select, Conﬁguration, Interrupt mask and

Interrupt status registers

0 AS

slave address(1)

START condition R/W acknowledge

from slave

002aad570

000XXXX0

command byte

acknowledge

from slave

12345678SCL 9

SDA DATA A

data to register

acknowledge

from slave

data to register

1000000P

STOP

condition

Product data sheet Rev. 03 — 9 November 2009 23 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

(1) Slave address shown in this example is for the 24-pin version.

Fig 15. Read from register

1000000AS0

START condition R/W

acknowledge

from slave

002aad571

acknowledge

from slave

SDA

A P

command byte

acknowledge

from master

data from register

DATA (first byte)

slave address(1)

STOP

condition

(repeated)

START condition

(cont.)

(cont.) 1000001A0

R/W

acknowledge

from slave

slave address(1)

at this moment master-transmitter becomes master-receiver

and slave-receiver becomes slave-transmitter

no acknowledge

from master

data from register

DATA (last byte)

This ﬁgure assumes the command byte has previously been programmed with 00h.

Transfer of data can be stopped at any moment by a STOP condition.

(1) Slave address shown in this example is for the 24-pin version.

Fig 16. Read Input port register

1000001AS0

slave address(1)

START condition R/W acknowledge

from slave

002aad572

data from port

acknowledge

from master

SDA 1

no acknowledge

from master

read from

port

data into

port

data from port

DATA 1

DATA 4

INT

DATA 4

DATA 2

DATA 3

STOP

condition

tv(INT) trst(INT)

th(D) tsu(D)

12345678SCL 9

Product data sheet Rev. 03 — 9 November 2009 24 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

10. Application design-in information

11. Limiting values

Address pin connections shown are for the 28-pin version.

Device address conﬁgured as 0100 101Xb for this example.

P0_0, P0_2, P0_3 conﬁgured as outputs; P0_1, P0_4 to P0_7 and P1_0 to P1_7 conﬁgured as inputs.

Fig 17. Typical application

PCA9575 P0_0

P0_1

SCL

SDA

VDD

SCL

SDA P0_2

P0_3

VDD

VSS

MASTER

CONTROLLER

VSS

VDD = 1.1 V

to 3.6 V

SUBSYSTEM 1

(e.g., temp. sensor)

INT

SUBSYSTEM 2

(e.g., counter)

RESET

controlled switch

(e.g., CBT device)

enable

INT

VDD(IO)0

INT

1.1 kΩ2 kΩ

SUBSYSTEM 3

(e.g., alarm system)

ALARM

P0_4

P0_5

VDD(IO)0

P0_6

P0_7

1.6 kΩ1.6 kΩ

RESETRESET

VDD(IO)0 = 3.6 V

002aad573

P1_0

P1_1

P1_2

P1_3

P1_4

P1_5

P1_6

P1_7

VDD(IO)1

VDD(IO)1 = 3.6 V

SUBSYSTEM 4

(e.g., RF module)

CTRL

10 DIGIT

NUMERIC

KEYPAD

Table 20. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 +4.0 V

VDD(IO)0 input/output supply voltage 0 VSS −0.5 VDD + 0.5 V

VDD(IO)1 input/output supply voltage 1 VSS −0.5 VDD + 0.5 V

II/O input/output current - ±5mA

IIinput current - ±20 mA

IDD supply current - 90 mA

ISS ground supply current - 90 mA

Ptot total power dissipation - 75 mW

Tstg storage temperature −65 +150 °C

Tamb ambient temperature −40 +85 °C

Product data sheet Rev. 03 — 9 November 2009 25 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

12. Static characteristics

Table 21. Static characteristics

= 1.1 V to 3.6 V; V

DD(IO)0

= 1.1 V to 3.6 V; V

DD(IO)1

= 1.1 V to 3.6 V; V

=0V; T

amb

−

C to +85

C; unless

otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VDD supply voltage 1.1 - 3.6 V

VDD(IO)0 input/output supply voltage 0 1.1 - VDD + 0.5 V

VDD(IO)1 input/output supply voltage 1 1.1 - VDD + 0.5 V

IDD supply current operating mode; VDD = 3.6 V;

no load; fSCL = 100 kHz; I/O = inputs - 135 200 µA

IstbL LOW-level standby current Standbymode;VDD = 3.6 V;no load;

VI=V

SS; fSCL = 0 kHz; I/O = inputs - 0.25 2 µA

IstbH HIGH-level standby current Standbymode;VDD = 3.6 V;no load;

VI=V

DD(IO)0 =V

DD(IO)1;

fSCL = 0 kHz; I/O = inputs

- 0.25 2 µA

VPOR power-on reset voltage no load; VI=V

DD or VSS (rising VDD) - 0.7 1.0 V

Input SCL; input/output SDA

VIL LOW-level input voltage −0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD - 3.6 V

IOL LOW-level output current VOL = 0.2 V; VDD = 1.1 V 1 - - mA

VOL = 0.4 V; VDD = 2.3 V 3 - - mA

ILleakage current VI=V

DD or VSS −1-+1 µA

Ciinput capacitance VI=V

SS - 6 10 pF

I/Os

VIL LOW-level input voltage −0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.3VDD - 3.6 V

IOL LOW-level output current VOL = 0.2 V; VDD(IO)0 = 1.1 V;

VDD(IO)1 = 1.1 V 1-- mA

VOL = 0.5 V; VDD(IO)0 = 3.6 V;

VDD(IO)1 = 3.6 V 23- mA

VOH HIGH-level output voltage IOH =−1 mA; VDD(IO)0 = 1.1 V;

VDD(IO)1 = 1.1 V 0.8 - - V

Rpu(int) internal pull-up resistance 50 100 150 kΩ

ILIH HIGH-level input leakage

current VDD(IO)0 = 3.6 V; VDD(IO)1 = 3.6 V;

VI=V

DD(IO)0; VI=V

DD(IO)1

--1µA

IHholding current VI= 0.3 V; VDD(IO)0 = 1.1 V;

VDD(IO)1 = 1.1 V; VDD = 3.6 V 10 - - µA

VI= 0.8 V; VDD(IO)0 = 1.1 V;

VDD(IO)1 = 1.1 V; VDD = 3.6 V −10 - - µA

ILIL LOW-level input leakage

current VDD(IO)0 = 3.6 V; VDD(IO)1 = 3.6 V;

VI=V

--−1µA

Ciinput capacitance - 3.7 5 pF

Cooutput capacitance - 3.7 5 pF

Product data sheet Rev. 03 — 9 November 2009 26 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

Interrupt INT

IOL LOW-level output current VOL = 0.4 V; VDD = 1.1 V 3 - - mA

Select inputs (reset and address)

VIL LOW-level input voltage - - +0.2 V

VIH HIGH-level input voltage VDD −0.2 - - V

ILI input leakage current −1-+1 µA

Ciinput capacitance - 2 4 pF

Table 21. Static characteristics

…continued

= 1.1 V to 3.6 V; V

DD(IO)0

= 1.1 V to 3.6 V; V

DD(IO)1

= 1.1 V to 3.6 V; V

=0V; T

amb

−

C to +85

C; unless

otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Fig 18. VOH at VDD = 3.3 V, VDD(IO)n = 1.2 V, IOH =−1 mA Fig 19. VOH at VDD = 3.3 V, VDD(IO)n = 3.3 V, IOH =−1mA

1.0

2.0

3.0

VOH

(V)

Tamb (°C)

−40 100−20

002aae767

0 20 40 60 80

4.0

VOH

(V)

Tamb (°C)

−40 100−20

002aae768

0 20 40 60 80

1.0

2.0

3.0

a. VDD(IO)0 or VDD(IO)1 = 1.8 V b. VDD(IO)0 or VDD(IO)1 = 2.6 V

Fig 20. IOL versus VOL

IOL

(mA)

VOL(typ) (V)

0 800600200 400

002aaf069

Tamb = −40 °C

+25 °C

+85 °C

IOL

(mA)

VOL(typ) (V)

0 800600200 400

002aaf070

Tamb = −40 °C

+25 °C

+85 °C

Product data sheet Rev. 03 — 9 November 2009 27 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

13. Dynamic characteristics

a. VDD(IO)0 or VDD(IO)1 = 1.8 V b. VDD(IO)0 or VDD(IO)1 = 2.6 V

Fig 21. IOH versus VOH

IOH

(mA)

VDD − VOH (V)

0 0.80.60.2 0.4

002aaf071

Tamb = −40 °C

+25 °C

+85 °C

IOL

(mA)

VDD − VOH (V)

0 0.80.60.2 0.4

002aaf072

Tamb = −40 °C

+25 °C

+85 °C

Table 22. Dynamic characteristics

= 1.1 V to 3.6 V; V

DD(IO)0

= 1.1 V to 3.6 V; V

DD(IO)1

= 1.1 V to 3.6 V; V

=0V; T

amb

−

C to +85

C; unless

otherwise speciﬁed.

Symbol Parameter Conditions Standard-mode

I2C-bus Fast-mode I2C-bus Unit

Min Max Min Max

fSCL SCL clock frequency 0 100 0 400 kHz

tBUF bus free time between a STOP and

START condition 4.7 - 1.3 - µs

tHD;STA hold time (repeated) START

condition 4.0 - 0.6 - µs

tSU;STA set-up time for a repeated START

condition 4.7 - 0.6 - µs

tSU;STO set-up time for STOP condition 4.0 - 0.6 - µs

tVD;ACK data valid acknowledge time [1] 0.3 3.45 0.1 0.9 µs

tHD;DAT data hold time 0 - 0 - ns

tVD;DAT data valid time [2] 300 - 50 - ns

tSU;DAT data set-up time 250 - 100 - ns

tLOW LOW period of the SCL clock 4.7 - 1.3 - µs

tHIGH HIGH period of the SCL clock 4.0 - 0.6 - µs

tffall time of both SDA and SCL

signals - 300 20 + 0.1Cb[3] 300 ns

trrise time of both SDA and SCL

signals - 1000 20 + 0.1Cb[3] 300 ns

tSP pulse width of spikes that must be

suppressed by the input ﬁlter - 50 - 50 ns

Product data sheet Rev. 03 — 9 November 2009 28 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

[1] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW.

[2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.

[3] Cb = total capacitance of one bus line in pF.

Port timing

tv(Q) data output valid time VDD(IO)0, VDD(IO)1 =

VDD = 1.1 V - 350 - 350 ns

VDD(IO)0, VDD(IO)1 =

VDD = 2.3 V to 3.6 V - 300 - 300 ns

tsu(D) data input set-up time 150 - 150 - ns

th(D) data input hold time 1 - 1 - µs

Interrupt timing

tv(INT) valid time on pin INT - 4 - 4 µs

trst(INT) reset time on pin INT - 4 - 4 µs

Reset

tw(rst) reset pulse width VDD(IO)0, VDD(IO)1 =

VDD = 1.1 V 8- 8 -ns

VDD(IO)0, VDD(IO)1 =

VDD = 2.3 V to 3.6 V 4- 4 -ns

trec(rst) reset recovery time 0 - 0 - ns

trst(SDA) SDA reset time Figure 23 - 400 - 400 ns

trst(GPIO) GPIO reset time Figure 23 - 400 - 400 ns

Table 22. Dynamic characteristics

…continued

= 1.1 V to 3.6 V; V

DD(IO)0

= 1.1 V to 3.6 V; V

DD(IO)1

= 1.1 V to 3.6 V; V

=0V; T

amb

−

C to +85

C; unless

otherwise speciﬁed.

Symbol Parameter Conditions Standard-mode

I2C-bus Fast-mode I2C-bus Unit

Min Max Min Max

Fig 22. Deﬁnition of timing

tSP

tBUF

tHD;STA PP S

tLOW

tHD;DAT

tHIGH tSU;DAT tSU;STA

tHD;STA

tSU;STO

SDA

SCL

002aaa986

Product data sheet Rev. 03 — 9 November 2009 29 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

14. Test information

Fig 23. Reset timing

SDA

SCL

002aad574

trst(GPIO)

50 %

30 %

50 % 50 %

50 %

trec(rst) tw(rst)

RESET

P0_0 to P0_7

P1_0 to P1_7 output off

START

trst(SDA)

ACK or read cycle

30 %

RL = load resistance.

CL = load capacitance includes jig and probe capacitance.

RT = termination resistance should be equal to the output impedance Zo of the pulse generators.

(1) For SDA, no 500 Ω pull-down.

Fig 24. Test circuitry for switching times

PULSE

GENERATOR

50 pF

500 Ω

002aad582

VDD

DUT

2VDD

open

VSS

500 Ω(1)

Product data sheet Rev. 03 — 9 November 2009 30 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

15. Package outline

Fig 25. Package outline SOT355-1 (TSSOP24)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 7.9

7.7 4.5

4.3 0.65 6.6

6.2 0.4

0.3 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT355-1 MO-153 99-12-27

03-02-19

0.25 0.5

0.2

112

24 13

pin 1 index

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1

max.

1.1

Product data sheet Rev. 03 — 9 November 2009 31 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

Fig 26. Package outline SOT361-1 (TSSOP28)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 9.8

9.6 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.8

0.5 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT361-1 MO-153 99-12-27

03-02-19

0.25

114

28 15

pin 1 index

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1

max.

1.1

Product data sheet Rev. 03 — 9 November 2009 32 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

Fig 27. Package outline SOT994-1 (HWQFN24)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT994-1 - - -

MO-220

- - -

SOT994-1

07-02-07

07-03-03

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

UNIT A(1)

max

mm 0.8 0.05

0.00 0.30

0.18 4.1

3.9 2.25

1.95 4.1

3.9 2.25

1.95 2.5 2.5 0.1

DIMENSIONS (mm are the original dimensions)

HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads;

24 terminals; body 4 x 4 x 0.75 mm

0 2.5 5 mm

scale

b c

0.2

D(1) DhE(1) Ehe

0.5

e1e2L

0.5

0.3

v w

0.05

0.1

B A

terminal 1

index area E

detail X

A1c

1/2 e

AC B

∅ vMC∅ wM

terminal 1

index area

613

127

24 19

Product data sheet Rev. 03 — 9 November 2009 33 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

16. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under

normal handling. When handling ensure that the appropriate precautions are taken as

described in

JESD625-A

or equivalent standards.

17. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note

AN10365 “Surface mount reﬂow

soldering description”

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

17.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

•Board speciﬁcations, including the board ﬁnish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

17.3 Wave soldering

Key characteristics in wave soldering are:

Product data sheet Rev. 03 — 9 November 2009 34 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

•Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath speciﬁcations, including temperature and impurities

17.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

•Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 28) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 23 and 24

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 28.

Table 23. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 24. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 03 — 9 November 2009 35 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

For further information on temperature proﬁles, refer to Application Note

AN10365

“Surface mount reﬂow soldering description”

18. Abbreviations

MSL: Moisture Sensitivity Level

Fig 28. Temperature proﬁles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 25. Abbreviations

Acronym Description

CBT Cross Bar Technology

CDM Charged Device Model

CMOS Complementary Metal Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

GPIO General Purpose Input/Output

HBM Human Body Model

I/O Input/Output

I2C-bus Inter-Integrated Circuit bus

IC Integrated Circuit

LED Light Emitting Diode

LP Low Pass

MM Machine Model

PLC Programmable Logic Controller

POR Power-On Reset

RAID Redundant Array of Independent Discs

RF Radio Frequency

SMBus System Management Bus

Product data sheet Rev. 03 — 9 November 2009 36 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

19. Revision history

Table 26. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCA9575_3 20091109 Product data sheet - PCA9575_2

Modiﬁcations: •Added Figure 20 “IOL versus VOL”.

•Added Figure 21 “IOH versus VOH”.

PCA9575_2 20090727 Product data sheet - PCA9575_1

PCA9575_1 20081002 Product data sheet - -

Product data sheet Rev. 03 — 9 November 2009 37 of 38

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

20. Legal information

20.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

20.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

20.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

20.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

21. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors PCA9575

16-bit I2C-bus and SMBus, level translating, low voltage GPIO

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 9 November 2009

Document identifier: PCA9575_3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

22. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

7 Functional description . . . . . . . . . . . . . . . . . . . 8

7.1 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.2 Device address. . . . . . . . . . . . . . . . . . . . . . . . . 8

7.3 Command register . . . . . . . . . . . . . . . . . . . . . . 9

7.4 Register deﬁnitions. . . . . . . . . . . . . . . . . . . . . . 9

7.5 Writing to port registers . . . . . . . . . . . . . . . . . 10

7.6 Reading the port registers . . . . . . . . . . . . . . . 10

7.6.1 Register 0 - Input port 0 register. . . . . . . . . . . 10

7.6.2 Register 1 - Input port 1 register. . . . . . . . . . . 11

7.6.3 Register 2 - Polarity inversion port 0 register . 11

7.6.4 Register 3 - Polarity inversion port 1 register . 12

7.6.5 Register 4 - Bus-hold/pull-up/pull-down

enable 0 register. . . . . . . . . . . . . . . . . . . . . . . 12

7.6.6 Register 5 - Bus-hold/pull-up/pull-down

enable 1 register. . . . . . . . . . . . . . . . . . . . . . . 13

7.6.7 Register 6 - Pull-up/pull-down select port 0

7.6.8 Register 7 - Pull-up/pull-down select port 1

7.6.9 Register 8 - Conﬁguration port 0 register . . . . 15

7.6.10 Register 9 - Conﬁguration port 1 register . . . . 15

7.6.11 Register 10 - Output port 0 register . . . . . . . . 16

7.6.12 Register 11 - Output port 1 register . . . . . . . . 16

7.6.13 Register 12 - Interrupt mask port 0 register . . 17

7.6.14 Register 13 - Interrupt mask port 1 register . . 17

7.6.15 Register 14 - Interrupt status port 0 register. . 18

7.6.16 Register 15 - Interrupt status port 1 register. . 18

7.7 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 18

7.8 RESET input. . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.9 Software reset. . . . . . . . . . . . . . . . . . . . . . . . . 19

7.10 Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 19

7.11 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8 Characteristics of the I2C-bus. . . . . . . . . . . . . 20

8.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8.1.1 START and STOP conditions . . . . . . . . . . . . . 20

8.2 System conﬁguration . . . . . . . . . . . . . . . . . . . 20

8.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 21

9 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 22

10 Application design-in information. . . . . . . . . 24

11 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 24

12 Static characteristics . . . . . . . . . . . . . . . . . . . 25

13 Dynamic characteristics. . . . . . . . . . . . . . . . . 27

14 Test information. . . . . . . . . . . . . . . . . . . . . . . . 29

15 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 30

16 Handling information . . . . . . . . . . . . . . . . . . . 33

17 Soldering of SMD packages. . . . . . . . . . . . . . 33

17.1 Introduction to soldering. . . . . . . . . . . . . . . . . 33

17.2 Wave and reﬂow soldering. . . . . . . . . . . . . . . 33

17.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 33

17.4 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 34

18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 35

19 Revision history . . . . . . . . . . . . . . . . . . . . . . . 36

20 Legal information . . . . . . . . . . . . . . . . . . . . . . 37

20.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 37

20.2 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

20.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 37

20.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 37

21 Contact information . . . . . . . . . . . . . . . . . . . . 37

22 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38