SSTUB32866EC/G,518 - NXP Semiconductors

1. General description

The SSTUB32866 is a 1.8 V configurable register specifically designed for use on DDR2

memory modules requiring a parity checking function. The register is configurable (using

configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter

configuration can be designated as Regi ster A or Register B on the DIMM.

The SSTUB32866 accepts a parity bit from the memory controll er on its parity bit

(PAR_IN) input, compares it with the data received on the DIMM-independent D-input s

and indicates whether a parity error has occurred on its open-drain QERR pin

(active LOW). The convention is even parity, that is, valid parity is defined as an even

number of ones across the DIMM-ind ependent data inputs combined with the par ity input

bit.

The SSTUB32866 is p ackaged in a 96-ball, 6 ×16 grid, 0.8 mm ball pitch LFBGA packa ge

(13.5 mm ×5.5 mm).

2. Features and benefits

Configurable register supporting DDR2 up to 800 MT/s Registered DIMM applications

Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode

Controlled output impedance drivers enable optimal signal integrity and speed

Meets or exceeds SSTUB32866 JEDEC standard speed performance

Supports up to 450 MHz clock frequency of operation

Optimized pinout for high-density DDR2 module design

Chip-selects minimize power consumption by gating data outpu ts from changing state

Supports SSTL_18 data inputs

Checks parity on the DIMM-independent data inputs

Partial par ity output and input allows cascading of two SSTUB328 66s for correct parity

error processing

Differential clock (CK and CK) inputs

Supports LVCMOS switching levels on the control and RESET inputs

Single 1.8 V supply operation (1.7 V to 2.0 V)

Available in 96-ball, 13.5 mm ×5.5 mm, 0.8 mm ball pitch LFBGA package

3. Applications

400 MT/s to 800 MT/s DDR2 registered DIMMs desiring parity checking functionality

SSTUB32866

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer

with parity for DDR2-800 RDIMM applications

Rev. 04 — 15 April 2010 Product data sheet

Product data sheet Rev. 04 — 15 April 2010 2 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

4. Ordering information

4.1 Ordering options

Table 1. Ordering information

Type number Solder process Package

Name Description Version

SSTUB32866EC/G Pb-free (SnAgCu solder

ball compound) LFBGA96 plastic low profile fine-pitch ball grid array package;

96 balls; body 13.5 ×5.5 ×1.05 mm SOT536-1

SSTUB32866EC/S Pb-free (SnAgCu solder

ball compound) LFBGA96 plastic low profile fine-pitch ball grid array package;

96 balls; body 13.5 ×5.5 ×1.05 mm SOT536-1

Table 2. Ordering opti ons

Type number Temperatu re range

SSTUB32866EC/G Tamb = 0 °C to +70 °C

SSTUB32866EC/S Tamb = 0 °C to +85 °C

Product data sheet Rev. 04 — 15 April 2010 3 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

5. Functional diagram

(1) Disabled in 1 : 1 configuration.

Fig 1. Functional diagram of SSTUB32866; 1 : 2 Register A configuration with C0 = 0

and C1 = 1 (positive logic)

002aac01

QCKEA

QCKEB(1)

QODTA

QODTB(1)

QCSA

QCSB(1)

CSR

DCS

DODT

DCKE

D2 0

11D

Q2A

Q2B(1)

to 10 other channels

(D3, D5, D6, D8 to D14)

VREF

RESET

SSTUB32866

Product data sheet Rev. 04 — 15 April 2010 4 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

Fig 2. Pari ty logic diagram for 1 : 2 Register A configuration (pos itive logic); C0 = 0, C1 = 1

002aaa650

Q2A, Q3A,

Q5A, Q6A,

Q8A to Q14A

Q2B, Q3B,

Q5B, Q6B,

Q8B to Q14B

CLK

PAR_IN

D2, D3, D5, D6,

D8 to D14

RESET

LPS0

(internal node)

VREF

PARITY

CHECK

CLK

LPS1

(internal node)

2-BIT

COUNTER

QERR

PPO

D2, D3, D5, D6,

D8 to D14

D2, D3, D5, D6,

D8 to D14

Product data sheet Rev. 04 — 15 April 2010 5 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

6. Pinning information

6.1 Pinning

Fig 3. Pin confi gura tio n for LFBG A9 6

Fig 4. Ball mapping, 1 : 1 register (C0 = 0, C1 = 0)

002aac011

Transparent top view

246

135

ball A1

index area

SSTUB32866EC/

DCKE PPO VREF VDD QCKE DNU

123456

D2 D15 GND GND Q2 Q15

D3 D16 VDD VDD Q3 Q16C

DODT GND GND QODT DNUD

D5 D17 VDD VDD Q5 Q17E

D6 D18 GND GND Q6 Q18F

PAR_IN RESET VDD VDD C1 C0G

CK DCS GND GND QCS DNUH

CK CSR VDD VDD n.c. n.c.J

D8 D19 GND GND Q8 Q19K

D9 D20 VDD VDD Q9 Q20L

D10 D21 GND GND Q10 Q21M

D11 D22 VDD VDD Q11 Q22N

D12 D23 GND GND Q12 Q23P

D13 D24 VDD VDD Q13 Q24R

D14 D25 VREF VDD Q14 Q25T

002aab10

QERR

Product data sheet Rev. 04 — 15 April 2010 6 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

Fig 5. Ball mapping, 1 : 2 Register A (C0 = 0, C1 = 1)

Fig 6. Ball mapping, 1 : 2 Register B (C0 = 1, C1 = 1)

DCKE PPO VREF VDD QCKEA QCKEB

123456

D2 DNU GND GND Q2A Q2B

D3 DNU VDD VDD Q3A Q3BC

DODT QERR GND GND QODTA QODTBD

D5 n.c. VDD VDD Q5A Q5BE

D6 n.c. GND GND Q6A Q6BF

PAR_IN RESET VDD VDD C1 C0G

CK DCS GND GND QCSAH

CK CSR VDD VDD n.c. n.c.J

D8 DNU GND GND Q8A Q8BK

D9 DNU VDD VDD Q9A Q9BL

D10 DNU GND GND Q10A Q10BM

D11 DNU VDD VDD Q11A Q11BN

D12 DNU GND GND Q12A Q12BP

D13 DNU VDD VDD Q13A Q13BR

D14 DNU VREF VDD Q14A Q14BT

002aab10

QCSB

D1 PPO VREF VDD Q1A Q1B

123456

D2 DNU GND GND Q2A Q2B

D3 DNU VDD VDD Q3A Q3BC

D4 GND GND Q4A Q4BD

D5 DNU VDD VDD Q5A Q5BE

D6 DNU GND GND Q6A Q6BF

PAR_IN RESET VDD VDD C1 C0G

CK DCS GND GND QCSAH

CK CSR VDD VDD n.c. n.c.J

D8 DNU GND GND Q8A Q8BK

D9 DNU VDD VDD Q9A Q9BL

D10 DNU GND GND Q10A Q10BM

DODT DNU VDD VDD QODTA QODTBN

D12 DNU GND GND Q12A Q12BP

D13 DNU VDD VDD Q13A Q13BR

DCKE DNU VREF VDD QCKEA QCKEBT

002aab11

QCSB

QERR

Product data sheet Rev. 04 — 15 April 2010 7 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

6.2 Pin description

[1] Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.

Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.

Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.

[2] Depends on configuration. See Figure 4, Figure 5, and Figure 6 for ball number.

Table 3. Pin description

Symbol Pin Type Description

GND B3, B4, D3, D4, F3, F4,

H3, H4, K3, K4, M3,

M4, P3, P4

ground input ground

VDD A4, C3, C4, E3, E4,

G3, G4, J3, J4, L3, L4,

N3, N4, R3, R4, T4

1.8 V nominal power supply voltage

VREF A3, T3 0.9 V nominal input reference voltage

CK H1 differential input positive master clock input

CK J1 differential input negative master clock input

C0 G6 LVCMOS inputs Configuration control inputs; Register A or Register B and

1 : 1 mode or 1 : 2 mode select.

C1 G5

RESET G2 LVCMOS input Asynchronous reset input (active LOW). Resets registers and

disables VREF data and clock.

CSR J2 SSTL_18 input Chip select inputs (active LOW). Disables D1 to D25[1]

outputs switching when both inputs are HIGH.

DCS H2

D1 to D25 [2] SSTL_18 input Data input. Clocked in on the crossing of the rising edge of

CK and the falling edge of CK.

DODT [2] SSTL_18 input The outputs of this register bit will not be suspended by the

DCS and CSR control.

DCKE [2] SSTL_18 input The outputs of this regist er bit will not be suspended by the

DCS and CSR control.

PAR_IN G1 SSTL_18 input Parity input. Arrives one clock cycle after the corresponding

data input.

Q1 to Q25,

Q2A to Q14A,

Q1B to Q14B

[2] 1.8 V CMOS

outputs Data outputs that are suspended by the DCS and CSR

control.[3]

PPO A2 1.8 V CMOS

output Partial parity out. Indicates odd parity of inputs D1 to D25.[1]

QCS, QCSA,

QCSB [2] 1.8 V CMOS

output Data output that will not be suspended by the DCS and CSR

control.

QODT , QODTA,

QODTB [2] 1.8 V CMOS

output Data output that will not be suspended by the DCS and CSR

control.

QCKE,

QCKEA,

QCKEB

[2] 1.8 V CMOS

output Data output that will not be suspended by the DCS and CSR

control.

QERR D2 open-drain

output Output error bit (active L OW). Generated one clock cycle

after the corresponding data output.

n.c. [2] - Not connected. Ball present but no internal connection to th e

die.

DNU [2] - Do not use. Inputs are in standby-equivalent mode and

output s are driven LOW.

Product data sheet Rev. 04 — 15 April 2010 8 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

[3] Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0.

Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1.

Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1.

7. Functional description

The SSTUB32866 is a 25 -bit 1 : 1 or 14-bit 1 : 2 configurable registered buf fer with parity,

designed for 1.7 V to 2.0 V VDD operation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The

control and reset (RESET) inputs are LVCMOS. All data outputs are 1.8 V CMOS drivers

that have been optimized to drive the DDR2 DIMM load, and meet SSTL_18

specifications . Th e er ro r (Q ERR ) output is 1.8 V open-drain driver.

The SSTUB32866 oper ates from a dif ferential clock (CK and CK). Data are r egistered at

the crossing of CK going HIGH, and CK going LOW.

The C0 input controls the pinout configuration for the 1 : 2 pinout from A configuration

(when LOW) to B conf ig u ra tio n (whe n HIG H ). The C1 input controls the pinout

configuration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH).

The SSTUB32866 accepts a parity bit from the memory controller on its parity bit

(PAR_IN) input, compares it with the data received on the DIMM-independent D-input s

and indicates whether a parity error has occurred on its open-drain QERR pin

(active LOW). The convention is even parity, that is, valid parity is defined as an even

number of ones across the DIMM-ind ependent data inputs combined with the par ity input

bit.

When used as a single device, the C0 and C1 inputs are tied LOW. In this configuration,

parity is che cked on the PAR_IN input which arrives one cycle after the input dat a to which

it applies. The Partial-Parity-Out (PPO) and QERR signals are produced three cycles after

the corresponding data inputs.

When used in pairs, the C0 input of the first register is tied LOW and the C0 input of the

second register is tied HIGH. The C1 input of both registers are tied HIGH. Parity, which

arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of

the first device. The PPO and QERR signals are produced on the second device three

clock cycles after the corresponding data inputs. The PPO output of the first register is

cascaded to the PAR_IN of the second register. The QERR output of the first register is

left floating and the valid error information is latched on the QERR output of the second

If an error occurs and the QERR output is driven LOW, it stays latched LOW for two clock

cycles or until RESET is driven LOW. The DIMM-dep enden t sig nals (DCKE, DCS, DODT,

and CSR) are not included in the parity check computation.

The device supports low-power standby operation. When RESET is LOW, the differential

input receivers are disab led, and undriven (floating) data, clock and reference voltage

(VREF) inputs are allowed. In addition, when RESET is LOW all registers ar e re se t, an d

all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid

logic HIGH or LOW level.

Product data sheet Rev. 04 — 15 April 2010 9 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

The device also supports low-power active operation by monitoring both system chip

select (DCS and CSR) inputs and will gate the Qn and PPO outputs from changing st ates

when both DCS and CSR inputs are HIGH. If either DCS or CSR input is LOW, the Qn

and PPO outputs will function normally. The RESET input has priority over the DCS and

CSR control and when driven LOW will force the Qn and PPO outputs LOW, and the

QERR output HIGH. If the DCS control functionality is not desired, then the CSR input can

be hard-wired to groun d, in which case, the set-up time requirement for DCS would be the

same as for the other Dn data inputs. To control the low-power mode with DCS only, then

the CSR input should be pulled up to VDD through a pull-up resistor.

To ensure defined outputs from the register before a stable clock has been supplied,

RESET must be held in the LOW state during power-up.

In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with

respect to CK and CK. Therefore, no timing relationship can be guaranteed between the

two. When entering reset, the register will be cleared and the Qn outputs will be driven

LOW quickly, relative to the time to disable the dif f erential input r eceivers. However, when

coming out of reset, the register will become active quickly, relative to the time to enable

the diffe rential input receivers. As long as the d ata inpu ts are LOW, and the clock is sta ble

during the time from the LOW to HIGH transition of RESET until the input receivers are

fully enabled, the design of the SSTUB32866 must ensure that the outputs will remain

LOW, thus ensuring no glitches on the output.

7.1 Function table

[1] Q0 is the previous state of the associated output.

Table 4. Function tabl e (e ac h flip-flop)

L = LOW voltage level; H = HIGH voltage level; X = don’t care;

↑

= L OW to HIGH transition;

↓

= HIGH to LOW transition.

Inputs Outputs[1]

RESET DCS CSR CK CK Dn, DODTn,

DCKEn Qn QCS QODT,

QCKE

HL L ↑↓LLLL

HL L ↑↓HHLH

H L L L or H L or H X Q0Q0Q0

HL H ↑↓LLLL

HL H ↑↓HHLH

H L H L or H L or H X Q0Q0Q0

HH L ↑↓LLHL

HH L ↑↓HHHH

H H L L or H L or H X Q0Q0Q0

HH H ↑↓LQ

0HL

HH H ↑↓HQ

0HH

H H H L or H L or H X Q0Q0Q0

L X or floating X or floating X or floating X or floating X or floating L L L

Product data sheet Rev. 04 — 15 April 2010 10 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

[1] PPO0 is the previous state of output PPO; QERR0 is the previous state of output QERR.

[2] Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.

Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.

Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.

[3] PAR_IN arrives one clock cycle (C0 = 0), or two clock cycles (C0 = 1), after the data to which it applies.

[4] This condition assumes QERR is HIGH at the crossing of CK going HIGH and CK going LOW. If QERR is LOW , it stays latched LOW for

two clock cycles or until RESET is driven LOW.

8. Limiting values

[1] The input and output negative voltage ratings may be exceeded if the input and output clamping current ratings are observed.

[2] This value is limited to 2.5 V maximum.

Table 5. Parity and standby function table

L = LOW voltage level; H = HIGH voltage level; X = don’t care;

↑

= L OW to HIGH transition;

↓

= HIGH to LOW transition.

Inputs Outputs[1]

RESET DCS CSR CK CK ∑ of inputs = H

(D1 to D25) PAR_IN[2] PPO[3] QERR[4]

HL X ↑↓ even L L H

HL X ↑↓ odd L H L

HL X ↑↓ even H H L

HL X ↑↓ odd H L H

HH L ↑↓ even L L H

HH L ↑↓ odd L H L

HH L ↑↓ even H H L

HH L ↑↓ odd H L H

HH H ↑↓ X X PPO0QERR0

H X X L or H L or H X X PPO0QERR0

L X or floating X or floating X or floating X or floating X or floating X or floating L H

Table 6. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 +2.5 V

VIinput voltage receiver −0.5[1] +2.5[2] V

VOoutput voltage driver −0.5[1] VDD +0.5

[2] V

IIK input clamping current VI<0V or V

I>V

DD -−50 mA

IOK output clamping current VO<0V or V

O>V

DD -±50 mA

IOoutput current continuous; 0 V < VO< VDD -±50 mA

ICCC continuous current through

each VDD or GND pin -±100 mA

Tstg storage temperature −65 +150 °C

VESD electrostatic discharge

voltage Human Body Model (HBM); 1.5 kΩ; 100 pF 2 - kV

Machine Model (MM); 0 Ω; 200 pF 200 - V

Product data sheet Rev. 04 — 15 April 2010 11 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

9. Recommended operating conditions

[1] The RESET and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation.

[2] The differential inputs must not be floating, unless RESET is LOW.

Table 7. Recommended operating con ditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 1.7 - 2.0 V

Vref reference voltage 0.49 ×VDD 0.50 ×VDD 0.51 ×VDD V

VTtermination voltage Vref −0.040 Vref Vref +0.040 V

VIinput voltage 0 - VDD V

VIH(AC) AC HIGH-level input voltage data (Dn ), CSR, and

PAR_IN inputs Vref +0.250 - - V

VIL(AC) AC LOW-level input voltage data (Dn), CSR, and

PAR_IN inputs --V

ref −0.250 V

VIH(DC) DC HIGH-level input voltage data (Dn), CSR, and

PAR_IN inputs Vref +0.125 - - V

VIL(DC) DC LOW-level input voltage data (Dn), CSR, and

PAR_IN inputs --V

ref −0.125 V

VIH HIGH-level input voltage RESET, Cn [1] 0.65 ×VDD -- V

VIL LOW-level input voltage RESET , Cn [1] - - 0.35 ×VDD V

VICR common mode input voltage

range CK, CK [2] 0.675 - 1.125 V

VID differential input voltage CK, CK [2] 600 - - mV

IOH HIGH-level output current - - −8mA

IOL LOW-level output current - - 8 m A

Tamb ambient temperature operating in free air

SSTUB32866EC/G 0 - 70 °C

SSTUB32866EC/S 0 - 85 °C

Product data sheet Rev. 04 — 15 April 2010 12 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

10. Characteristics

Table 8. Characteristics

At recommended operating conditions (see Table 7); unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

VOH HIGH-level output voltage IOH =−6mA; V

DD = 1.7 V 1.2 - - V

VOL LOW-level output voltage IOL =6mA; V

DD =1.7V - - 0.5 V

IIinput current all inputs; VI=V

DD or GND; VDD =2.0V - - ±5μA

IDD supply current static Standby mode; RESET = GND;

IO=0mA; V

DD =2.0V --2 mA

static Operating mode; RESET =V

DD;

IO=0mA; V

DD =2.0V;

VI=V

IH(AC) or VIL(AC)

--40mA

IDDD dynamic operating current

per MHz clock only; RESET =V

DD;

VI=V

IH(AC) or VIL(AC); CK and CK

switching at 50 % duty cycle; IO=0mA;

VDD =1.8V

-16- μA

per each data input, 1 : 1 mode;

RESET =V

DD; VI=V

IH(AC) or VIL(AC);

CK and CK switching at 50 % duty

cycle; one data input switching at half

clock frequency, 50 % duty cycle;

IO=0mA; V

DD =1.8V

-11- μA

per each data input, 1 : 2 mode;

RESET =V

DD; VI=V

IH(AC) or VIL(AC);

CK and CK switching at 50 % duty

cycle; one data input switching at half

clock frequency, 50 % duty cycle;

IO=0mA; V

DD =1.8V

-19- μA

Ciinput capacitance data and CSR inputs;

VI=V

ref ±250 mV; V DD =1.8V 2.5 - 3.5 pF

CK and CK inputs; VICR =0.9V;

Vi(p-p) = 600 mV; VDD =1.8V 2-3 pF

RESET input; VI=V

DD or GND;

VDD =1.8V 3-4 pF

Input RESET

VIL LOW-level input voltage −0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD -2.5V

IIinput current VI=V

DD −5-+5 μA

ILleakage current VI=V

SS −100 −25 −10 μA

Product data sheet Rev. 04 — 15 April 2010 13 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

[1] This parameter is not necessarily production tested.

[2] VREF must be held at a valid input voltage level and data inputs must be held LOW for a minimum time of tACT(max) after RESET is taken

HIGH.

[3] VREF, data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max) after RESET is taken LOW.

[1] Includes 350 ps of test load transmission line delay.

[2] This parameter is not necessarily production tested.

Table 9. Timing requirements

At recommended operating conditions (see Table 7), unless otherwise specified. See Section 11.1.

Symbol Parameter Conditions Min Typ Max Unit

fclock clock frequency - - 450 MHz

tWpulse width CK, CK HIGH or LOW 1 - - ns

tACT differential inputs active time [1][2] - - 10 ns

tINACT differential inputs inactive time [1][3] - - 15 ns

tsu set-up time DCS before CK↑, CK↓, CSR HIGH;

CSR before CK↑, CK↓, DCS HIGH 0.6 - - ns

DCS before CK↑, CK↓, CSR LOW 0.5 - - ns

DODT, DCKE and dat a (Dn) before CK↑,

CK↓0.5 - - ns

PAR_IN before CK↑, CK↓0.5 - - ns

thhold time DCS, DODT, DCKE and data (Dn) after

CK↑,CK↓0.4 - - ns

PAR_IN after CK↑, CK↓0.4 - - ns

Table 10. Switching characteristics

At recommended operating conditions (see Table 7), unless otherwise specified. See Section 11.1.

Symbol Parameter Conditions Min Typ Max Unit

fmax maximum input clock frequency 450 - - MHz

tPDM peak propagation delay single bit switching;

from CK↑and CK↓ to Qn [1] 1.1 - 1.5 ns

tPD propagation delay from CK↑ and CK↓ to PPO 0.5 - 1.7 ns

tLH LOW to HIGH delay from CK↑ and CK↓ to QERR 1.2 - 3 ns

tHL HIGH to LOW delay from CK↑ and CK↓ to QERR 1- 2.4ns

tPDMSS simultaneous switching peak

propagation delay from CK↑ and CK↓ to Qn [1][2] --1.6ns

tPHL HIGH to LOW propagation delay from RESET↓ to Qn↓--3ns

from RESET↓ to PPO↓--3ns

tPLH LOW to HIGH propagation delay from RESET↓ to QERR↑--3ns

Table 11. Data output edge rates

At recommended operating conditions (see Table 7), unless otherwise specified. See Section 11.2.

Symbol Parameter Conditions Min Typ Max Unit

dV/dt_r rising edge slew rate from 20 % to 80 % 1 - 4 V/ns

dV/dt_f falling edg e slew rate from 80 % to 20 % 1 - 4 V/ns

dV/dt_Δabsolute difference between dV/dt_r

and dV/dt_f from 20 % or 80 %

to 80 % or 20 % --1V/ns

Product data sheet Rev. 04 — 15 April 2010 14 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

10.1 T iming diagrams

Fig 7. Timing diagram for SSTUB32866 used as a single device; C0 = 0, C1 = 0

RESET

DCS

CSR

D25

Q25

PAR_IN

PPO

QERR

tsu th

m m + 1 m + 2 m + 3 m + 4

tPD

CK to Q

tsu th

tPD

CK to PPO

tPD

CK to QERR

002aaa655

tPD

CK to QERR

Product data sheet Rev. 04 — 15 April 2010 15 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

Fig 8. Timing diagram for the first SSTUB32866 (1 : 2 Register A configuration) device used in pair; C0 = 0,

C1 = 1

RESET

DCS

CSR

D14

Q14

PAR_IN

PPO

QERR

(not used)

tsu th

m m + 1 m + 2 m + 3 m + 4

tPD

CK to Q

tsu th

tPD

CK to PPO

tPD

CK to QERR

002aaa656

tPD

CK to QERR

Product data sheet Rev. 04 — 15 April 2010 16 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

(1) PAR_IN is driven from PPO of the first SSTUB32866 device.

Fig 9. Timing diagram for the second SSTUB32866 (1 : 2 Register B configuratio n) device used in pair;

C0 = 1, C1 = 1

RESET

DCS

CSR

D14

Q14

PAR_IN(1)

PPO

(not used)

QERR

tsu th

m m + 1 m + 2 m + 3 m + 4

tPD

CK to Q

tsu th

tPD

CK to PPO

tPD

CK to QERR

002aaa657

tPD

CK to QERR

Product data sheet Rev. 04 — 15 April 2010 17 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

11. Test information

11.1 Parameter measurement information for data output load circuit

VDD =1.8V±0.1 V.

All input pulses are supplied by generators ha ving the following characteristics:

PRR ≤10 MHz; Zo=50Ω; input slew rate = 1 V/ns ±20 %, unless otherwise specified.

The outputs are measured one at a time with one transition per measur ement.

(1) CL includes probe and jig capacitance.

Fig 10. Load circuit, da ta output measurements

(1) IDD tested with clock and data inputs held at VDD or GND, and IO=0mA.

Fig 11. Voltage and current waveforms; inputs active and inactive times

VID = 600 mV.

VIH =V

ref + 250 mV (AC voltage levels) for differential inputs. VIH =V

DD for LVCMOS inputs.

VIL =V

ref −250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.

Fig 12. Volta ge waveforms; pulse duration

RL = 100 Ω

RL = 1000 Ω

VDD

50 Ω

CK inputs

CK OUT

DUT

test point

002aaa37

test point

delay = 350 ps

Zo = 50 Ω

RL = 1000 Ω

CL = 30 pF(1)

LVCMOS

RESET

10 %

DD(1)

INACT

0.5V

ACT

90 %

0 V

002aaa37

0.5V

VICR VICR

VIH

VIL

input

VID

002aaa37

Product data sheet Rev. 04 — 15 April 2010 18 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

VID = 600 mV.

Vref =0.5V

DD.

VIH =V

ref + 250 mV (AC voltage levels) for differential inputs. VIH =V

DD for LVCMOS inputs.

VIL =V

ref −250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.

Fig 13. Voltag e wa v efo rms ; se t-u p an d hold times

tPLH and tPHL are the same as tPD.

Fig 14. Voltage waveforms; propagation delay times (clock to output)

tPLH and tPHL are the same as tPD.

VIH =V

ref + 250 mV (AC voltage levels) for differential inputs. VIH =V

DD for LVCMOS inputs.

VIL =V

ref −250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.

Fig 15. Voltage waveforms; propagation delay times (reset to output)

tsu

VIH

VIL

VID

input Vref Vref

VICR

002aaa374

VOH

VOL

output

tPLH

002aaa37

VICR VICR

tPHL

Vi(p-p)

PHL

002aaa37

LVCMOS

RESET

output V

0.5V

Product data sheet Rev. 04 — 15 April 2010 19 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

11.2 Dat a output slew rate measurement information

VDD =1.8V±0.1 V.

All input pulses are supplied by generators ha ving the following characteristics:

PRR ≤10 MHz; Zo=50Ω; input slew rate = 1 V/ns ±20 %, unless otherwise specified.

(1) CL includes probe and jig capacitance.

Fig 16. Load circuit, HIGH-to- LOW slew measurement

Fig 17. Voltage waveforms, HIGH-to-LOW slew rate measurement

(1) CL includes probe and jig capacitance.

Fig 18. Load circuit, LOW-to-HIGH slew measurement

Fig 19. Voltage waveforms, LOW-to-HIGH slew rate measurement

CL = 10 pF(1)

VDD

OUT

DUT

test point

RL = 50 Ω

002aaa37

VOH

VOL

output

80 %

20 %

dv_f

dt_f 002aaa378

= 10 pF

(1)

OUT

DUT

test point

= 50 Ω

002aaa37

80 %

20 %

dv_r

dt_r

output

002aaa380

Product data sheet Rev. 04 — 15 April 2010 20 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

11.3 Error output load circuit and voltage measurement information

VDD =1.8V±0.1 V.

All input pulses are supplied by generators ha ving the following characteristics:

PRR ≤10 MHz; Zo=50Ω; input slew rate = 1 V/ns ±20 %, unless otherwise specified.

(1) CL includes probe and jig capacitance.

Fig 20. Load circuit, error output measurements

Fig 21. Voltage waveforms, open-drain output LOW to HIGH tr ansition time with respect

to RESET input.

Fig 22. Voltage waveforms, open-drain output HIGH to LOW transition time with respect

to clock inputs

CL = 10 pF(1)

VDD

OUT

DUT

test point

RL = 1 kΩ

002aaa50

0.5VDD

tPLH

VDD

0 V

0.15 V

VOH

0 V

output

waveform 2

RESET

002aaa50

LVCMOS

VICR

tHL

0.5VDD

VDD

VOL

timing

inputs

output

waveform 1

Vi(p-p)

VICR

002aaa502

Product data sheet Rev. 04 — 15 April 2010 21 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

11.4 Partial parity out load circuit and voltage measurement information

VDD =1.8V±0.1 V.

All input pulses are supplied by generators ha ving the following characteristics:

PRR ≤10 MHz; Zo=50Ω; input slew rate = 1 V/ns ±20 %, unless otherwise specified.

Fig 23. Voltage waveforms, open-drain output LOW to HIGH tr ansition time with respect

to clock inputs

ICR

0 V

timing

inputs

output

waveform 2

i(p-p)

ICR

0.15 V

002aaa503

(1) CL includes probe and jig capacitance.

Fig 24. Partial parity out load circuit

VT=0.5V

DD.

tPLH and tPHL are the same as tPD.

Vi(p-p) = 600 mV.

Fig 25. Partial parity out voltage waveforms; propagation delay times with respect to

clock inputs

= 5 pF

(1)

OUT

DUT

test point

= 1 kΩ

002aaa65

VOH

VOL

output

tPLH

002aaa37

VICR VICR

tPHL

Vi(p-p)

Product data sheet Rev. 04 — 15 April 2010 22 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

VT=0.5V

DD.

tPLH and tPHL are the same as tPD.

VIH =V

ref + 250 mV (AC voltage levels) for differential inputs. VIH =V

DD for LVCMOS inputs.

VIL =V

ref −250 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS inputs.

Fig 26. Partial parity out voltage waveforms; propagation delay times with respect to

RESET input

PHL

002aaa37

LVCMOS

RESET

output V

0.5V

Product data sheet Rev. 04 — 15 April 2010 23 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

12. Package outline

Fig 27. Package outline SOT536-1 (LFBGA96)

0.8

A1bA2

UNIT Dye

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

00-03-04

03-02-05

IEC JEDEC JEITA

mm 1.5 0.41

0.31

1.2

0.9

5.6

5.4

13.6

13.4

0.51

0.41 0.1 0.2

DIMENSIONS (mm are the original dimensions)

SOT536-1

0.15

0.1

0 5 10 mm

scale

SOT536

-1

FBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm

max.

AA2

detail X

246135

ball A1

index area

ball A1

index area

y1C

∅ vM

∅ wM

1/2 e

Product data sheet Rev. 04 — 15 April 2010 24 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on on e printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reflow soldering

W ave soldering is a joining te chnology in which the joints are m ade by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadle ss

packages which have solde r lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads ha ving a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded p ackages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder th ieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering ve rsus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave pa rameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 04 — 15 April 2010 25 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

13.4 Reflow soldering

Key characteristics in reflow soldering are :

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 28) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) an d cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on p ackage thickness and volume and is classified in accordance with

Table 12 and 13

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 28.

Table 12. SnPb eutectic proc ess (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 13. Lead-fr ee process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 04 — 15 April 2010 26 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

For further informa tion on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

14. Abbreviations

MSL: Moisture Sensitivity Level

Fig 28. Temperature profiles for large and small components

001aac84

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Table 14. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor

DDR Double Data Rate

DIMM Dual In-line Memory Module

LVCMOS Low Voltage Complementary Metal Oxide Semiconductor

PPO Partial Parity Out

PRR Pulse Repetition Rate

RDIMM Registered Dual In-line Memory Module

SSTL Stub Series Terminated Logic

Product data sheet Rev. 04 — 15 April 2010 27 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

15. Revision history

Table 15. Revision history

Document ID Release date Data sh eet status Change notice Supersedes

SSTUB32866_4 20100415 Product data sheet - SSTUB32866_3

Modifications: •Section 1 “General description”, first paragraph: deleted second sentence

•Table 8 “Characteristics”: added sub-section “Input RESET”

SSTUB32866_3 20070423 Product data sheet - SSTUB32866_2

SSTUB32866_2 20061009 Product data sheet - SSTUB32866_1

SSTUB32866_1 20060518 Product data sheet - -

Product data sheet Rev. 04 — 15 April 2010 28 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full da ta sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificatio n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however ,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

16.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indire ct, incidental,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulat ive liability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for an y of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

NXP Semiconductors does not accept any liabil i ty related to any default,

damage, costs or problem which is based on a weakness or default in the

customer application /use or t he application/use of customer’s third party

customer(s) (hereinafter both referred to as “Application”). It is customer’s

sole responsibility to check whether the NXP Semiconductors product is

suitable and fit for the Appl ica tion plann ed. Customer has to do all necessary

testing for the Application in order to avoid a default of the Application and t he

product. NXP Semiconductors does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that t his specific NXP Semiconductors product is automotive qualified,

the product is not suit ab le for aut omotive u se. It is neit her qua lifi ed n or test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclu sio n and/or use of

non-automotive qualifie d products in automotive equipment or applica tions.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and st andards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contain s data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

Product data sheet Rev. 04 — 15 April 2010 29 of 30

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

product for such au tomotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive appl ications beyond NXP Semiconductors’

standard warrant y and NXP Semiconductors’ product specifications.

16.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 15 April 2010

Document identifier: SSTUB32866_4

Please be aware that important notices concerning this document and the product(s)

described herei n, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7

7 Functional description . . . . . . . . . . . . . . . . . . . 8

7.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 9

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10

9 Recommended operating conditions. . . . . . . 11

10 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 12

10.1 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 14

11 Test information. . . . . . . . . . . . . . . . . . . . . . . . 17

11.1 Parameter measurement information for

data output load circuit . . . . . . . . . . . . . . . . . . 17

11.2 Data output slew rate measurement

information . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

11.3 Error output load circuit and voltage

measurement information. . . . . . . . . . . . . . . . 20

11.4 Partial parity out load circuit and voltage

measurement information. . . . . . . . . . . . . . . . 21

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23

13 Soldering of SMD packages . . . . . . . . . . . . . . 24

13.1 Introduction to soldering . . . . . . . . . . . . . . . . . 24

13.2 Wave and reflow soldering . . . . . . . . . . . . . . . 24

13.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 24

13.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 25

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 26

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 27

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 28

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 28

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 29

17 Contact information. . . . . . . . . . . . . . . . . . . . . 29

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30