VIPer100/SP VIPer100A/ASP SMPS PRIMARY I.C. Table 1. Figure 2. General Features Type VDSS In RDS(on) VIPer100/SP 620V 3A 2.5 VIPer100A/ASP 700V 3A 2.8 ADJUSTABLE SWITCHING FREQUENCY UP TO 200 kHz CURRENT MODE CONTROL SOFT START AND SHUTDOWN CONTROL AUTOMATIC BURST MODE OPERATION IN STAND-BY CONDITION ABLE TO MEET "BLUE ANGEL" NORM (<1w TOTAL POWER CONSUMPTION) INTERNALLY TRIMMED ZENER REFERENCE UNDERVOLTAGE LOCK-OUT WITH HYSTERESIS INTEGRATED START-UP SUPPLY OVER-TEMPERATURE PROTECTION LOW STAND-BY CURRENT ADJUSTABLE CURRENT LIMITATION Figure 1. Package PENTAWATT HV PENTAWATT HV (022Y) DESCRIPTION VIPer100TM/100A, made using VIPower M0 Technology, combines on the same silicon chip a state-of-the-art PWM circuit together with an optimized, high voltage, Vertical Power MOSFET (620V or 700V / 3A). Typical applications cover offline power supplies with a secondary power capability of 50 W in wide range condition and 100W in single range or with doubler configuration. It is compatible from both primary or secondary regulation loop despite using around 50% less components when compared with a discrete solution. Burst mode operation is an additional feature of this device, offering the ability to operate in stand-by mode without extra components. Block Diagram DRAIN OSC ON/OFF OSCILLATOR SECURITY LATCH UVLO LOGIC VDD R/S FF Q S PWM LATCH S R1 FF Q R2 R3 OVERTEMP. DETECTOR 0.5 V + _ 1.7 s DELAY 250 ns BLANKING 4.5 V FC00231 + COMP June 2005 1 V/A CURRENT AMPLIFIER ERROR _ AMPLIFIER 13 V 0.5V _ + + _ SOURCE Rev 2 1/24 www.st.com 24 VIPer100/SP - VIPer100A/ASP Table 2. Absolute Maximum Rating Symbol VDS ID Parameter Value Continuous Drain-Source Voltage (TJ = 25 to 125C) for VIPer100/SP for VIPer100A/ASP -0.3 to 620 -0.3 to 700 Maximum Current Unit V V Internally limited A 0 to 15 V VDD Supply Voltage VOSC Voltage Range Input 0 to VDD V VCOMP Voltage Range Inpu 0 to 5 V ICOMP Maximum Continuous Current 2 mA VESD Electrostatic Discharge (R =1.5k; C=100pF) 4000 V ID(AR) Avalanche Drain-Source Current, Repetitive or Not Repetitive (Tc=100C; Pulse width limited by TJ max; < 1%) for VIPer100/SP for VIPer100A/ASP 2 1.4 A A Power Dissipation at Tc=25C 82 W Internally limited C -65 to 150 C PENTAWATT HV Unit Ptot Tj Tstg Table 3. Junction Operating Temperature Storage Temperature Thermal data Symbol Parameter Rthj-case Thermal Resistance Junction-case Max 1.4 C/W R thj-amb Thermal Resistance Ambient-case Max 60 C/W Figure 3. Connection Diagrams (Top View) PENTAWATT HV (022Y) PENTAWATT HV Table 4. Current and Voltage Convention IDD ID VDD IOSC DRAIN OSC 13V + COMP SOURCE VDD VDS ICOMP VOSC VCOMP FC00020 2/24 VIPer100/SP - VIPer100A/ASP Table 5. Ordering Numbers PENTAWATT HV PENTAWATT HV (022Y) VIPer100 VIPer100A VIPer100 (022Y) VIPer100A (022Y) Pins Functional Description Drain Pin (Integrated Power MOSFET Drain): Integrated Power MOSFET drain pin. It provides internal bias current during start-up via an integrated high voltage current source which is switched off during normal operation. The device is able to handle an unclamped current during its normal operation, assuring self protection against voltage surges, PCB stray inductance, and allowing a snubberless operation for low output power. Suorce Pin: Power MOSFET source pin. Primary side circuit common ground connection. VDD Pin (Power Supply): This pin provides two functions : It corresponds to the low voltage supply of the control part of the circuit. If VDD goes below 8V, the startup current source is activated and the output power MOSFET is switched off until the VDD voltage reaches 11V. During this phase, the internal current consumption is reduced, the VDD pin is sourcing a current of about 2mA and the COMP pin is shorted to ground. After that, the current source is shut down, and the device tries to start up by switching again. This pin is also connected to the error amplifier, in order to allow primary as well as secondary regulation configurations. In case of primary regulation, an internal 13V trimmed reference voltage is used to maintain VDD at 13V. For secondary regulation, a voltage between 8.5V and 12.5V will be put on VDD pin by transformer design, in order to stuck the output of the transconductance amplifier to the high state. The COMP pin behaves as a constant current source, and can easily be connected to the output of an optocoupler. Note that any overvoltage due to regulation loop failure is still detected by the error amplifier through the VDD voltage, which cannot overpass 13V. The output voltage will be somewhat higher than the nominal one, but still under control. Compensation Pin This pin provides two functions : It is the output of the error transconductance amplifier, and allows for the connection of a compensation network to provide the desired transfer function of the regulation loop. Its bandwidth can be easily adjusted to the needed value with usual components value. As stated above, secondary regulation configurations are also implemented through the COMP pin. When the COMP voltage is going below 0.5V, the shut-down of the circuit occurs, with a zero duty cycle for the power MOSFET. This feature can be used to switch off the converter, and is automatically activated by the regulation loop (no matter what the configuration is) to provide a burst mode operation in case of negligible output power or open load condition. OSC Pin (Oscillator Frequency): An Rt-Ct network must be connected on that to define the switching frequency. Note that despite the connection of Rt to VDD, no significant frequency change occurs for V DD varying from 8V to 15V. It provides also a synchronisation capability, when connected to an external frequency source. 3/24 VIPer100/SP - VIPer100A/ASP Table 6. Avalance Characteristics Symbol Parameter Max Value Unit ID(AR) Avalanche Current, Repetitive or Not Repetitive (pulse width limited by TJ max; < 1%) for VIPer100/SP (see Figure 15) for VIPer100A/ASP (*) (see Figure 15) 2 1.4 A A E(AR) Single Pulse Avalanche Energy (starting TJ = 25C, ID = ID(ar)) (*) 60 mJ Electrical Chracteristics (TJ = 25C; VDD = 13V, unless otherwise specified) Table 7. Power Section Symbol Parameter Test Conditions BVDS Drain-Source Voltage for VIPer100/SP for VIPer100A/ASP (see Figure 8) IDSS Off-State Drain Current Min Typ Max Unit ID = 1mA; VCOMP = 0V 620 700 V V VCOMP = 0V; T j = 125C VDS = 620V for VIPer100/SP VDS = 700V for VIPer100A/ASP 1 1 mA mA 2.5 2.8 4.5 5.0 ID = 2A RDS(on) Static Drain-Source On Resistance for VIPer100/SP for VIPer100A/ASP ID = 2A; Tj = 100C 2.0 2.3 for VIPer100/SP for VIPer100A/ASP tf Fall Time ID = 0.2A; VIN =300V (1)Figure 6 100 ns tr Rise Time ID = 0.4A; VIN = 300V (1)Figure 6 50 ns Output Capacitance VDS = 25V 150 pF Coss (1) On Inductive Load, Clamped. 4/24 VIPer100/SP - VIPer100A/ASP Table 8. Symbol Supply Section Parameter IDDch Start-Up Charging Current IDD0 Operating Supply Current IDD1 Test Conditions` Min VDD = 5V; V DS = 35V Typ Max -2 (see Figure 5)(see Figure 18) VDD = 12V; FSW = 0kHz 12 (see Figure 5) Unit mA 16 mA VDD = 12V; Fsw = 100kHz 15.5 mA VDD = 12V; Fsw = 200kHz 19 mA Operating Supply Current VDDoff Undervoltage Shutdown (see Figure 5) VDDon Undervoltage Reset (see Figure 5) VDDhyst Hysteresis Start-up (see Figure 5) Table 9. Symbol 7.5 8 9 V 11 12 V 2.4 3 V Min Typ Max Unit 90 100 110 KHz Oscillator Section Parameter Test Conditions` RT=8.2K; CT=2.4nF FSW Oscillator Frequency Total Variation VDD=9 to 15V; with RT 1%; CT 5% (see Figure 9)(see Figure 12) VOSCIH Oscillator Peak Voltage 7.1 V VOSCIL Oscillator Valley Voltage 3.7 V Table 10. Error Amplifier Section Symbol Parameter Test Conditions` VDDREG VDD Regulation Point ICOMP=0mA (see Figure 4) VDDreg Total Variation Tj=0 to 100C Min Typ Max Unit 12.6 13 13.4 V 2 % 150 KHz dB From Input =VDD to Output = VCOMP GBW Unity Gain Bandwidth AVOL Open Loop Voltage Gain COMP pin is open (see Figure 13) 45 52 Gm DC Transconductance VCOMP=2.5V(see Figure 4) 1.1 1.5 VCOMPLO Output Low Level ICOMP=-400A; V DD=14V 0.2 V VCOMPHI Output High Level ICOMP=400A; VDD=12V 4.5 V ICOMPLO Output Low Current Capability VCOMP=2.5V; VDD=14V -600 A ICOMPHI Output High Current Capability 600 A COMP pin is open (see Figure 13) VCOMP=2.5V; VDD=12V 1.9 mA/V 5/24 VIPer100/SP - VIPer100A/ASP Table 11. Symbol HID VCOMPoff IDpeak PWM Comparator Section Parameter Test Conditions` VCOMP / IDPEAK VCOMP = 1 to 3 V VCOMP Offset IDPEAK = 10mA Peak Current Limitation VDD = 12V; COMP pin open Min Typ Max Unit 0.7 1 1.3 V/A 0.5 3 4 5.3 A td Current Sense Delay to TurnID = 1A Off 250 tb Blanking Time 250 360 ns Minimum On Time 350 1200 ns Typ Max Unit ton(min) Table 12. Symbol VCOMPth Parameter Test Conditions` Min (see Figure 7) 0.5 Disable Set Up Time (see Figure 7) 1.7 Ttsd Thermal Shutdown Temperature (see Figure 7) Thyst Thermal Shutdown Hysteresis (see Figure 7) tDISsu ns Shutdown and Overtemperature Section Restart Threshold 6/24 V 140 V 5 s 170 C 40 C VIPer100/SP - VIPer100A/ASP Figure 4. VDD Regulation Point ICOMP Figure 5. Undervoltage Lockout IDD Slope = Gmin mA/V ICOMPHI IDD0 VDD 0 VDDhyst ICOMPLO VDDoff VD S= 35 V Fsw = 0 VDDon VDD IDDch VDDreg FC00170 FC00150 Figure 6. Transition Time Figure 7. Shutdown Action VOSC ID t VCOMP tDISsu 10% Ipeak t VDS VCOMPth t 90% VD ID 10% VD t tf tr t FC00160 ENABLE ENABLE DISABLE FC00060 Figure 8. Breakdown Voltage vs. Temperature Figure 9. FC00190 FC00180 1.15 (%) BVDSS Typical Frequency Variation 1 0 (Normalized) 1.1 -1 -2 1.05 -3 1 0.95 -4 -5 0 20 40 60 80 100 120 Temperature (C) 0 20 40 60 80 100 120 140 Temperature (C) 7/24 VIPer100/SP - VIPer100A/ASP Figure 10. Start-Up Waveforms Figure 11. Over-temperature Protection T Tts c J Ttsd -Th yst t Vd d Vdd on Vdd off t Id t V co mp t SC101 91 8/24 VIPer100/SP - VIPer100A/ASP Figure 12. Oscillator For R t >1.2K and C t 15nF if FSW 40KHz VDD Rt OSC 550 F = ---2.3 -------- 1 - ------------------- SW R C R - 150 CLK t t ~360 t FC00050 Ct Forbidden area 880 Ct(nF) = 22nF Fsw(kHz) 15nF Forbidden area 40kHz Fsw Oscillator frequency vs Rt and Ct FC00030 1,000 Ct = 1.5 nF 500 Ct = 2.7 nF Frequency (kHz) Ct 300 Ct = 4.7 nF 200 Ct = 10 nF 100 50 30 1 2 3 5 10 20 30 50 Rt (k) 9/24 VIPer100/SP - VIPer100A/ASP Figure 13. Error Amplifier frequency Response FC00200 60 RCOMP = + Voltage Gain (dB) RCOMP = 270k 40 RCOMP = 82k RCOMP = 27k 20 RCOMP = 12k 0 (20) 0.001 0.01 0.1 1 10 Frequency (kHz) 100 1,000 Figure 14. Error Amplifier Phase Response FC00210 200 RCOMP = + 150 RCOMP = 270k Phase () RCOMP = 82k RCOMP = 27k 100 RCOMP = 12k 50 0 (50) 0.001 10/24 0.01 0.1 1 10 Frequency (kHz) 100 1,000 VIPer100/SP - VIPer100A/ASP Figure 15. Avalanche Test Circuit L1 1mH 2 VDD 1 3 DRAIN OSC 13V BT1 0 to 20V + COMP BT2 12V C1 47uF 16V Q1 2 x STHV102FI in parallel R1 SOURCE 5 4 47 GENERATOR INPUT 500us PULSE U1 VIPer100 R2 1k R3 100 FC00195 11/24 VIPer100/SP - VIPer100A/ASP Figure 16. Offline Power Supply With Auxiliary Supply Feedback F1 BR1 TR2 C1 TR1 D2 AC IN L2 +Vcc D1 R9 C2 C7 C9 R1 C3 GND D3 C10 R7 C4 R2 VDD DRAIN - U1 OSC VIPer100 + 13V COMP SOURCE C5 C6 C11 R3 FC00081 Figure 17. Offline Power Supply With Optocoupler Feedback F1 BR1 TR2 C1 TR1 D2 AC IN L2 +Vcc D1 R9 C2 C7 C9 R1 C3 GND D3 C10 R7 C4 R2 VDD DRAIN - U1 OSC 13V VIPer100 + COMP SOURCE C5 C11 C6 R3 R6 ISO1 R4 C8 U2 R5 FC00091 12/24 VIPer100/SP - VIPer100A/ASP Operation Description: Current Mode Topology: The current mode control method, like the one integrated in the VIPer100/100A, uses two control loops an inner current control loop and an outer loop for voltage control. When the Power MOSFET output transistor is on, the inductor current (primary side of the transformer) is monitored with a SenseFET technique and converted into a voltage VS proportional to this current. When VS reaches VCOMP (the amplified output voltage error) the power switch is switched off. Thus, the outer voltage control loop defines the level at which the inner loop regulates peak current through the power switch and the primary winding of the transformer. Excellent open loop D.C. and dynamic line regulation is ensured due to the inherent input voltage feedforward characteristic of the current mode control. This results in improved line regulation, instantaneous correction to line changes, and better stability for the voltage regulation loop. Current mode topology also ensures good limitation in case there is a short circuit. During the first phase the output current increases slowly following the dynamic of the regulation loop. Then it reaches the maximum limitation current internally set and finally stops because the power supply on VDD is no longer correct. For specific applications the maximum peak current internally set can be overridden by externally limiting the voltage excursion on the COMP pin. An integrated blanking filter inhibits the PWM comparator output for a short time after the integrated Power MOSFET is switched on. This function prevents anomalous or premature termination of the switching pulse in case there are current spikes caused by primary side capacitance or secondary side rectifier reverse recovery time. Stand-by Mode Stand-by operation in nearly open load conditions automatically leads to a burst mode operation allowing voltage regulation on the secondary side. The transition from normal operation to burst mode operation happens for a power PSTBY given by : Where: 1 2 F P STBY = --- L P I STBY SW 2 LP is the primary inductance of the transformer. FSW is the normal switching frequency. ISTBY is the minimum controllable current, corresponding to the minimum on time that the device is able to provide in normal operation. This current can be computed as : ( t b + t d )V IN I STBY = ----------------------------Lp tb + td is the sum of the blanking time and of the propagation time of the internal current sense and comparator, and represents roughly the minimum on time of the device. Note: that PSTBY may be affected by the efficiency of the converter at low load, and must include the power drawn on the primary auxiliary voltage. As soon as the power goes below this limit, the auxiliary secondary voltage starts to increase above the 13V regulation level, forcing the output voltage of the transconductance amplifier to low state (VCOMP < VCOMPth). This situation leads to the shutdown mode where the power switch is maintained in the Off state, resulting in missing cycles and zero duty cycle. As soon as VDD gets back to the regulation level and the VCOMPth threshold is reached, the device operates again. The above cycle repeats indefinitely, providing a burst mode of which the effective duty cycle is much lower than the minimum one when in normal operation. The equivalent switching frequency is also lower than the normal one, leading to a reduced consumption on the input main supply lines. This mode of operation allows the VIPer100/100A to meet the new German "Blue Angel" Norm with less than 1W total power consumption for the system when working in stand-by mode. The output voltage remains regulated around the normal level, with a low frequency ripple corresponding to the burst mode. The amplitude of this ripple is low, because of the output capacitors and low output current drawn in such conditions.The normal operation resumes automatically when the power gets back to higher levels than PSTBY. 13/24 VIPer100/SP - VIPer100A/ASP High Voltage Start-up Current Suorce An integrated high voltage current source provides a bias current from the DRAIN pin during the start-up phase. This current is partially absorbed by internal control circuits which are placed into a standby mode with reduced consumption and also provided to the external capacitor connected to the VDD pin. As soon as the voltage on this pin reaches the high voltage threshold VDDon of the UVLO logic, the device becomes active mode and starts switching. The start-up current generator is switched off, and the converter should normally provide the needed current on the VDD pin through the auxiliary winding of the transformer, as shown on (see Figure 18). In case there are abnormal conditions where the auxiliary winding is unable to provide the low voltage supply current to the VDD pin (i.e. short circuit on the output of the converter), the external capacitor discharges to the low threshold voltage VDDoff of the UVLO logic, and the device goes back to the inactive state where the internal circuits are in standby mode and the start-up current source is activated. The converter enters a endless start-up cycle, with a start-up duty cycle defined by the ratio of charging current towards discharging when the VIPer100/100A tries to start. This ratio is fixed by design to 2A to 15A, which gives a 12% start-up duty cycle while the power dissipation at start-up is approximately 0.6W, for a 230Vrms input voltage. This low value start-up duty cycle prevents the application of stress to the output rectifiers as well as the transformer when a short circuit occurs. The external capacitor CVDD on the VDD pin must be sized according to the time needed by the converter to start up, when the device starts switching. This time tSS depends on many parameters, among which transformer design, output capacitors, soft start feature, and compensation network implemented on the COMP pin. The following formula can be used for defining the minimum capacitor needed: I t where: DD SS C VDD > -------------------V DDhyst IDD is the consumption current on the VDD pin when switching. Refer to specified IDD1 and I DD2 values. tSS is the start up time of the converter when the device begins to switch. Worst case is generally at full load. VDDhyst is the voltage hysteresis of the UVLO logic (refer to the minimum specified value). The soft start feature can be implemented on the COMP pin through a simple capacitor which will be also used as the compensation network. In this case, the regulation loop bandwidth is rather low, because of the large value of this capacitor. In case a large regulation loop bandwidth is mandatory, the schematics of (see Figure 19) can be used. It mixes a high performance compensation network together with a separate high value soft start capacitor. Both soft start time and regulation loop bandwidth can be adjusted separately. If the device is intentionally shut down by tying the COMP pin to ground, the device is also performing start-up cycles, and the VDD voltage is oscillating between VDDon and VDDoff. This voltage can be used for supplying external functions, provided that their consumption does not exceed 0.5mA. (see Figure 20) page 17 shows a typical application of this function, with a latched shutdown. Once the "Shutdown" signal has been activated, the device remains in the Off state until the input voltage is removed. 14/24 VIPer100/SP - VIPer100A/ASP Figure 18. Behaviour of the high voltage current source at start-up VDD 2 mA VDDon VDDoff 3 mA VDD 15 mA DRAIN 1 mA 15 mA CVDD Ref. t Auxiliary primary winding UNDERVOLTAGE LOCK OUT LOGIC VIPer100 SOURCE Start up duty cycle ~ 12% FC00100 15/24 VIPer100/SP - VIPer100A/ASP Transconductance Error Amplifier The VIPer100/100A includes a transconductance error amplifier. Transconductance Gm is the change in output current (ICOMP) versus change in input voltage (VDD). Thus: G m I OM P = ------C ----------------- V DD The output impedance ZCOMP at the output of this amplifier (COMP pin) can be defined as: Z CO MP VCOMP 1 VCOMP = -------------------------- = --------- x -------------------------G I CO MP VDD m This last equation shows that the open loop gain AVOL can be related to Gm and ZCOMP: AVOL = Gm x ZCOMP where Gm value for VIPer100/100A is 1.5 mA/V typically. Gm is defined by specification, but ZCOMP and therefore AVOL are subject to large tolerances. An impedance Z can be connected between the COMP pin and ground in order to define the transfer function F of the error amplifier more accurately, according to the following equation (very similar to the one above): F(S) = Gm x Z(S) The error amplifier frequency response is reported in figure 10 page 8 for different values of a simple resistance connected on the COMP pin. The unloaded transconductance error amplifier shows an internal ZCOMP of about 330K. More complex impedance can be connected on the COMP pin to achieve different compensation level. A capacitor will provide an integrator function, thus eliminating the DC static error, and a resistance in series leads to a flat gain at higher frequency, insuring a correct phase margin. This configuration is illustrated in (see Figure 21) page 17. As shown in (see Figure 21) an additional noise filtering capacitor of 2.2nF is generally needed to avoid any high frequency interference. Is also possible to implement a slope compensation when working in continuous mode with duty cycle higher than 50%. (see Figure 22) shows such a configuration. Note: R1 and C2 build the classical compensation network, and Q1 is injecting the slope compensation with the correct polarity from the oscillator sawtooth. External Clock Synchronization: The OSC pin provides a synchronisation capability when connected to an external frequency source. (see Figure 23) page17 shows one possible schematic to be adapted, depending the specific needs. If the proposed schematic is used, the pulse duration must be kept at a low value (500ns is sufficient) for minimizing consumption. The optocoupler must be able to provide 20mA through the optotransistor. Primary Peak Current Limitation The primary IDPEAK current and, consequently, the output power can be limited using the simple circuit shown in (see Figure 24) page 18. The circuit based on Q1, R1 and R2 clamps the voltage on the COMP pin in order to limit the primary peak current of the device to a value: V - 0.5 where: R 1 + R2 V COM P = 0.6 x -------------------R 2 The suggested value for R1+R2 is in the range of 220K. 16/24 I D PEAK = ------C----OM -----------P--------------H ID VIPer100/SP - VIPer100A/ASP Over-Temperature Protection Over-temperature protection is based on chip temperature sensing. The minimum junction temperature at which over-temperature cut-out occurs is 140C, while the typical value is 170C. The device is automatically restarted when the junction temperature decreases to the restart temperature threshold that is typically 40C below the shutdown value (see Figure 11) page 8.. Figure 19. Mixed Soft Start and Compensation Figure 20. Latched Shut Down D2 U1 VIPER100 VDD D3 DRAIN VDD - - OSC R3 + + 13V COMP SOURCE COMP SOURCE D1 C4 R3 AUXILIARY WINDING R2 R1 R4 R2 + C3 DRAIN Q2 OSC 13V U1 VIPER100 R1 Shutdown D1 Q1 + C2 C1 FC00110 FC00131 Figure 21. Typical Compensation Network Figure 22. Slope Compensation U1 VIPER100 VDD DRAIN R2 R1 U1 V IP E R 1 0 0 - OSC 13V VD D + COMP D R A IN - O SC SOURCE 13 V + CO M P SO UR CE C2 C2 R1 Q1 C3 C1 C1 R3 FC 00 1 4 1 FC00121 Figure 23. External Clock Sinchronisation Figure 24. Current Limitation Circuit Example U1 V IP E R 1 0 0 V DD U1 VIPER100 VDD D R A IN - O SC 13V + COMP DRAIN SO U RC E - OSC 13V + COMP SOURCE R1 10 k Q1 R2 FC00220 FC 00240 17/24 VIPer100/SP - VIPer100A/ASP Figure 25. Input Voltage Surges Protection R1 D1 (Optional) R2 39R Auxilliary winding C1 Bulk capacitor VDD C2 22nF DRAIN OSC 13V VIPerXX0 + COMP SOURCE Electrical Over Stress Ruggedness The VIPer may be submitted to electrical over-stress, caused by violent input voltage surges or lightning. Following the Layout Considerations is sufficient to prevent catastrophic damages most of the time. However in some cases, the voltage surges coupled through the transformer auxiliary winding can exceed the VDD pin absolute maximum rating voltage value. Such events may trigger the VDD internal protection circuitry which could be damaged by the strong discharge current of the VDD bulk capacitor. The simple RC filter shown in (see Figure 25) page 17 can be implemented to improve the application immunity to such surges. 18/24 VIPer100/SP - VIPer100A/ASP Figure 26. Recommended Layout T1 D1 C7 D2 To secondary filtering and load R1 VDD DRAIN - C1 OSC 13V From input diodes bridge C5 + COMP SOURCE U1 VIPerXX0 R2 C6 C2 C3 ISO1 C4 FC00500 Layout Considerations Some simple rules insure a correct running of switching power supplies. They may be classified into two categories: - Minimizing power loops: The switched power current must be carefully analysed and the corresponding paths must be as small an inner loop area as possible. This avoids radiated EMC noises, conducted EMC noises by magnetic coupling, and provides a better efficiency by eliminating parasitic inductances, especially on secondary side. - Using different tracks for low level and power signals: Interference due to mixing of signal and power may result in instabilities and/or anomalous behaviour of the device in case of violent power surge (Input overvoltages, output short circuits...). In case of VIPer, these rules apply as shown on (see Figure 26). * Loops C1-T1-U1, C5-D2-T1, and C7-D1-T1 must be minimized. * C6 must be as close as possible to T1. * Signal components C2, ISO1, C3, and C4 are using a dedicated track connected directly to the power source of the device. 19/24 VIPer100/SP - VIPer100A/ASP Pentawatt HV Mechanical Data mm. inch Dim Min. Typ. Maw. Min. Typ. A 4.30 4.80 0.169 0.189 C 1.17 1.37 0.046 0.054 D 2.40 2.80 0.094 0.11 E 0.35 0.55 0.014 0.022 F 0.60 0.80 0.024 0.031 G1 4.91 5.21 0.193 0.205 G2 7.49 7.80 0.295 0.307 H1 9.30 9.70 0.366 0.382 H2 10.40 0.409 H3 10.05 10.40 L 15.60 17.30 6.14 0.681 L1 14.60 15.22 0.575 0.599 L2 21.20 21.85 0.835 0.860 L3 22.20 22.82 0.874 0.898 L5 2.60 3 0.102 0.118 L6 15.10 15.80 0.594 0.622 L7 6 6.60 0.236 0.260 M 2.50 3.10 0.098 0.122 M1 4.50 5.60 0.177 0.220 R 0.50 Diam 0.396 0.409 0.02 90 V4 3.65 3.85 0.144 0.152 P023H3 20/24 Max. VIPer100/SP - VIPer100A/ASP Pentawatt HV 022Y ( Vertical High Pitch ) Mechanical Data mm. inch Dim Min. Typ. Maw. Min. Typ. Max. A 4.30 4.80 0.169 0.189 C 1.17 1.37 0.046 0.054 D 2.40 2.80 0.094 0.110 E 0.35 0.55 0.014 0.022 F 0.60 0.80 0.024 0.031 G1 4.91 5.21 0.193 0.205 G2 7.49 7.80 0.295 0.307 H1 9.30 9.70 0.366 0.382 H2 10.40 0.409 H3 10.05 10.40 0.396 0.409 L 16.42 17.42 0.646 0.686 L1 14.60 15.22 0.575 0.599 L3 20.52 21.52 0.808 0.847 L5 2.60 3.00 0.102 0.118 L6 15.10 15.80 0.594 0.622 L7 6.00 6.60 0.236 0.260 M 2.50 3.10 0.098 0.122 M1 5.00 5.70 0.197 0.224 R 0.50 V4 90 Diam 0.02 0.020 90 3.65 3.85 0.144 0.154 L L1 E A M M1 C D R Resin between leads L6 L7 V4 H2 H3 H1 G1 G2 F DIA L5 L3 21/24 VIPer100/SP - VIPer100A/ASP Figure 27. Pentawatt HV Tube Shipment ( no suffix ) Base Q.ty 50 Bulk Q.ty 1000 Tube length ( 0.5 ) 532 A 18 B 33.1 C ( 0.1) 1 All dimensions are in mm. 22/24 VIPer100/SP - VIPer100A/ASP Table 13. Revision history Date Revision Changes 02-May-2005 1 Initial release. 08-JUn-2005 2 Update without PowerSO-10 TM 23/24 VIPer100/SP - VIPer100A/ASP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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