VIPER100ASP(022Y) - STMicroelectronics, Inc.

Rev 2

June 2005 1/24

FC00231

VDD

OSC

COMP

DRAIN

SOURCE

13 V

UVLO

LOGIC

SECURITY

LATCH PWM

LATCH

R/S SQS

R2 R3Q

OSCILLATOR

OVERTEMP.

DETECTOR

ERROR

AMPLIFIER_

0.5 V +

_1.7

DELAY 250 ns

BLANKING CURRENT

AMPLIFIER

ON/OFF

0.5V

1 V/A

4.5 V

VIPer100/SP

VIPer100A/ASP

SMPS PRIMARY I.C.

Table 1. Ge nera l Fea tures

■ADJUSTABLE SWITCHING FREQUENCY UP

TO 200 kHz

■CURRENT MODE CONTROL

■SOFT START AND SHUTDOWN CONTROL

■AUTOMATIC BURST MODE OPERATION IN

STAND - BY COND ITION ABLE TO MEET

“BLUE ANGEL” NORM (<1w TOTAL POWER

CONSUMPTION)

■INTERNALLY TRIMMED ZENER

REFERENCE

■UNDERVOLTAGE LOCK-OUT WITH

HYSTERESIS

■INT EGRATED START-UP SUPPLY

■OVER-TEMPERATURE PROTECTIO N

■LOW STAND-BY CURRENT

■ADJUSTABLE CURRENT LIMITA T ION

Figure 1. Block Diagram

Figure 2. Package

DESCRIPTION

VIPer100™/100A, made using VIPower M0

Technology, combines on the same silicon chip a

state-of-the-art PWM circuit together with an

optimized, high voltage, Vertical Power MOSFET

(620V or 700V / 3A).

Typical applications cover offline power supplies

with a secondary power capability of 50 W in wide

range cond iti on and 100W in single range or with

doubler configuration. It is compatible from both

primary or secondary regulation loop despite

using around 50% less components when

compared with a discrete solution. Burst mode

operation is an additional feature of this device,

offering the ability to operate in stand-by mode

without extra components.

Type VDSS InRDS(on)

VIPer100/SP 620V 3 A 2.5 Ω

VIPer100A/ASP 700V 3 A 2.8 Ω

PENTAWATT HV PENTAWATT HV (022Y)

www.st.com

VIPer100/SP - VIPer100A/ASP

2/24

Table 2. Absolute Maximum Rating

Tabl e 3. Thermal data

Figur e 3. Connectio n Diagrams (To p View)

Table 4. Current and Voltage Co nve ntion

Symbol Parameter Value Unit

VDS

Contin uous Drain-Source Voltage (T J = 25 to 125°C)

for VIPer100/SP

for VIPer100A/ASP –0.3 to 620

–0.3 to 700

IDMaxi mu m Current Internally limited A

VDD Supply Voltage 0 to 15 V

VOSC Volt age Range Input 0 to VDD V

VCOMP Voltage Range Inpu 0 to 5 V

ICOMP Maximum Continuous Current ±2 mA

VESD Electrostatic Dischar ge (R =1.5kΩ; C=100pF) 4000 V

ID(AR)

Avalanche Drain-Source Current, Repetitive or Not Repetitive

(Tc=100°C; Pul se width limit ed by TJ max; δ < 1%)

for VIPer100/SP

for VIPer100A/ASP 2

1.4 A

Ptot Power Dissipati on at Tc=25ºC 82 W

TjJuncti on O perating Tem peratur e Internally limited °C

Tstg Storage Tem peratur e -65 to 150 °C

Symbol Parameter PENTAWATT HV Unit

Rthj-case Thermal Resistance Junction-case Max 1.4 °C/W

Rthj-amb Thermal Resistance Ambient-case Max 60 °C/W

PENTAWATT HV PENTAWATT HV (022Y)

13V

OSC

COMP SOURCE

DRAINVDD

VCOMP

VOSC

VDD VDS

ICOMP

IOSC

FC00020

VIPer100/SP - VIPer100A/ASP

3/24

Tabl e 5. Orderi ng Numbers

Pins Functional Description

Drain Pin (Integrated P ower MOSFET Drain):

Integrated Power MOSFET drain pin. It provides internal bias current during start-up via an integrated

high voltage curren t source which is switched off during normal o peration. The device is a ble to handle

an unc lamped c urrent during its normal operation, assuring sel f protection against voltage surges, PCB

stray inductance, and allowing a snubberless operation for low output power.

Suorce Pin:

Power MOS FET source pin. Primary side circuit common ground connec tion.

VDD Pin (Power Supply ):

This pin provides two functions :

■It corresponds to the low voltage supply of the control part of the circuit. If VDD goes below 8V, the start-

up current source is activated and the output power MOS FET is switched off until the VDD voltage

reache s 11V. During this phase, the internal current c onsum pt ion is reduced, the VDD pin is sourcing

a current of about 2mA and the COMP pin is shorted to ground. After t hat, the current source is shut

down, and the dev ice tries to start up b y switching agai n.

■This pin is also c onn ec ted to the error am pl ifier, in order to allow primary as well as secondary

regulation configurat ions. In c ase of primary regulation, an internal 13V trimmed reference voltage is

used to maintain VDD at 13V. For secondary regulation, a voltage between 8.5V and 12.5V will be put

on VDD pin by transformer design, in order to stuck the output of the transconductance amplifier to the

high state. The COMP pin behaves as a constant curr ent source, and can easily be connected to the

output of an optocoupler. Note that any overvoltage due to regulation loop failure is still detected by the

error amplifier through the VDD voltag e, which cannot overpas s 13V. The output voltage will be

somewhat higher than the nominal one, but still under control.

Compensation Pin

This pin provides two functions :

■It is the output of the error transconductance amplifier, and allows for the connection of a compensation

network to provide the desired transfer function of the regulation loop. Its bandwidth can be easily

adjuste d to the needed value with usual compon ents value. As stated above, secondary regulati on

configu rations are also implemented through the COMP pin.

■When the COMP voltage is going below 0.5V, the shut-down of the circuit occurs, with a zero duty cycle

for the power MOSFET. This featu re can be used to switch off the converter, and is automatically

activated by the regulation loop (no matter what the configuration is) t o provide a burst mode operation

in case of negligible output power or open load condition.

OSC Pin (Osc illator Fre quency):

An Rt-Ct network must be connected on that to define the switching frequency. Note that despite the

connection of Rt to VDD, no significant frequency change occurs for VDD varying from 8V to 15V. It

provides also a synchronisation capability, when connect ed to an external frequ enc y source.

PENTAW ATT HV PENTAWATT HV (022Y)

VIPer100

VIPer100A VIPer100 (022Y)

VIPer100A (02 2Y)

VIPer100/SP - VIPer100A/ASP

4/24

Table 6. Ava lan ce Chara cteristics

El ectrical C h ra cter i sti cs (TJ = 25°C ; VDD = 13V, unles s otherwis e spec if ied)

Tabl e 7. Power Section

(1) On Inductive Load, Clamped.

Symbol Parameter Max Value Unit

ID(AR)

Avalanche Current, Re petitive or Not Repetitive

(pulse width limited by TJ max; δ < 1%)

for VIPer100/SP (see F igure 15)

for VIPer100A/ A SP (* ) (see Figure 15) 2

1.4 A

E(AR) Single Pulse Avalanche Energy

(starting TJ = 25ºC, ID = I D(ar)) (*) 60 mJ

Symbol Parameter Test Conditions Min Typ Max Uni t

BVDS Drain-Source Voltage ID = 1mA; VCOMP = 0V

for VIPer100/SP

for VIPer100A/ASP (see Figure 8) 620

700 V

IDSS Of f-S tate Drain

Current

VCOMP = 0V; Tj = 125°C

VDS = 620V for VIPer100/SP

VDS = 700V for VIPer100A/ASP 1

1mA

RDS(on) Stat ic Drain-Sour ce

On Resista nce

ID = 2A

for VIPer100/SP

for VIPer100A/ASP

ID = 2A; Tj = 100°C

for VIPer100/SP

for VIPer100A/ASP

2.0

2.3

2.5

2.8

4.5

5.0

tfFa ll Time ID = 0.2A; VIN =300V (1 )Figure 6 100 ns

tr Ri se Time ID = 0.4A; VIN = 300V (1)Figure 6 50 ns

Coss Output Capacitance VDS = 25V 150 pF

VIPer100/SP - VIPer100A/ASP

5/24

Table 8. Supply Section

Table 9. Oscil lator Section

Table 10. Error Amplifier Section

Symbol Parameter Test Conditions‘ Min Typ Max Uni t

IDDch Start- Up Charging Current VDD = 5 V; V DS = 35V

(see Fig ure 5)(see Figure 18) -2 mA

IDD0 Operati ng Supply Current VDD = 12V; FSW = 0kHz

(see Fig ure 5) 12 16 mA

IDD1 Operati ng Supply Current VDD = 12V; Fsw = 100k Hz 15.5 mA

VDD = 12V; Fsw = 200k Hz 19 mA

VDDoff Undervoltage Shutdown (see Figure 5) 7.5 8 9 V

VDDon Undervoltage Reset (see Figure 5) 11 12 V

VDDhyst Hysteresis Start-up (see Figure 5) 2.4 3 V

Symbol Parameter Test Conditions‘ Min Typ Max Uni t

FSW Oscillator Frequency Total

Variation

RT=8.2KΩ; CT=2.4nF

VDD= 9 to 1 5 V;

with RT± 1%; CT± 5%

(see Fig ure 9)(see Figure 12)

90 100 110 KHz

VOSCIH Oscillator Peak Voltage 7.1 V

VOSCIL Oscillator Valley Voltage 3.7 V

Symbol Parameter Test Conditions‘ Min Typ Max Unit

VDDREG VDD Regulat ion Point ICOMP=0 mA (see Figure 4) 12.6 13 13.4 V

ΔVDDreg Total Va ri at io n Tj=0 to 100°C 2%

GBW Unity Gain Bandwidth

F r o m In put =VDD to

Output = VCOMP

COMP pi n is open

(see Figure 13)

150 KHz

AVOL Open Loop Voltage Gain COMP pi n is open

(see Figure 13) 45 52 dB

GmDC Transconductance VCOMP=2.5V(see Figure 4) 1.1 1.5 1.9 mA/V

VCOMPLO Output Low Level ICOMP=-400µA; VDD=14V 0.2 V

VCOMPHI Output High Level ICOMP=400µA; VDD=12V 4.5 V

ICOMPLO Output Low Cur rent Capabil ity VCOMP=2.5V; VDD=14V -600 µA

ICOMPHI Output High Current

Capability VCOMP=2.5V; VDD=12V 600 µA

VIPer100/SP - VIPer100A/ASP

6/24

Table 11. PWM Com parator S ec tion

Tabl e 12. Shutdown and Overtem pe rature Section

Symbol Parameter Test Conditions‘ Min Typ Max Uni t

HID ΔVCOMP / ΔIDPEAK VCOMP = 1 to 3 V 0.7 1 1.3 V/A

VCOMPoff VCOMP Offset IDPEAK = 10mA 0.5 V

IDpeak Peak Current Limitation VDD = 12V; COMP pin open 345.3A

tdCurrent Sense Delay to Turn-

Off ID = 1A 250 ns

tbBlanking Ti m e 250 360 ns

ton(min) M inimum On Ti me 350 1200 ns

Symbol Parameter Test Conditions‘ Min Typ Max Uni t

VCOMPth Restart Threshold (see Figure 7) 0.5 V

tDISsu Disable Set Up Time (see Fig ure 7) 1.7 5 µs

Ttsd Thermal Shutdown

Temperature (see Figure 7) 140 1 70 °C

Thyst Thermal Shutdown Hysteresis (see Fig ure 7) 40 °C

VIPer100/SP - VIPer100A/ASP

7/24

Figure 4. VDD Regulatio n P oin t Fi gure 5 . Under voltage Lock out

Fi gure 6. Tr an sition Time Fi gure 7 . Shutdown Action

Figure 8. Brea kdo wn Voltage vs. Temper ature Figure 9. Typica l Freque ncy Variation

ICOMP

ICOMPHI

COMPLO VDDreg

Slope =

Gm in mA/V

FC00150

VDDon

DDch

IDD0

VDDoff

VDS= 35 V

Fsw = 0

IDD

VDDhyst

FC00170

tf tr

10% Ipe ak

10% VD

90% VD

FC00160

VCOMP

VOSC

tDISsu

ENABLE DISABLEENABLE

COMPth

FC0006

Temperature (°C)

FC00180

0 20406080100120

0.95

1.05

1.1

1.15

BVDSS

(

Normalized)

Temperat ur e ( °C )

0 20 40 60 80 100 120

140

-5

-4

-3

-2

-1

1FC00190

(

VIPer100/SP - VIPer100A/ASP

8/24

Figure 10. Start-Up W aveforms

Figure 11. Over-temperature Protection

SC101 91

tsd-Thyst

Tts c

Vdd

Vddon

Vddoff

Vcomp

VIPer100/SP - VIPer100A/ASP

9/24

Figure 12. Oscillator

OSC

VDD

~360Ω

CLK

FC00050

For R

>1.2K

and

Ct ≥ 15nF if FSW ≤ 40KHz

2.3

RtCt

----------- 1

550

Rt150–

-------------------

–

⎝⎠

⎛⎞

⋅

40kHz

15nF

22nF

Forbidden are a

Forbidden area

Ct(nF) = Fsw(kHz)

880

1 2 3 5 10 20 30 50

100

200

300

500

1,000

Rt (kΩ)

Frequency (kHz)

Oscillator frequency vs Rt and Ct

Ct = 1.5 nF

Ct = 2.7 nF

Ct = 4.7 nF

Ct = 10 nF

FC00030FC00030

VIPer100/SP - VIPer100A/ASP

10/24

Figure 13. Error Amplifier frequency Response

Figure 14. Error Amplifier Phase Response

0.001 0.01 0.1 1 10 100 1,00

(20)

Frequency (kHz)

Volta ge Gain (dB )

RCOMP = +∞

RCOMP = 270k

RCOMP = 82k

RCOMP = 27k

RCOMP = 12k

FC00200

0.001 0.01 0.1 1 10 100 1,00

(50)

100

150

200

Fre que n c y ( kH z )

Phase (°)

RCOMP = +∞

RCOMP = 270k

RCOMP = 82k

RCOMP = 27k

RCOMP = 12k

FC00210

VIPer100/SP - VIPer100A/ASP

11/24

Figure 15. Avalanche Test Circuit

FC00195

VIPer100

13V

OSC

COMP SOURCE

DRAINVDD

100

BT2

12V

47uF

16V

2 x STHV102FI in parallel

1mH

GENERATOR INPUT

500us PULSE

BT1

0 to 20

VIPer100/SP - VIPer100A/ASP

12/24

Figure 16. Offline Power Supply With Auxiliary Supply Feedback

Figure 17. Offline Power Supply With Optocoupler Feedback

AC IN +Vcc

GND

BR1

TR2

C10

TR1

VIPer100

13V

OSC

COMP SOURCE

DRAINVDD

FC00081

C11

FC00091

AC IN

BR1

TR2

C10

TR1

L2 +Vcc

GND

VIPer100

ISO1 R6

13V

OSC

COMP SOURCE

DRAINVDD

C11

VIPer100/SP - VIPer100A/ASP

13/24

Operation De scription:

Current Mode Topology :

The current mode c ont rol metho d, like the one integrated in the VIPer100/1 00A , uses two control loops -

an inner current control loop and an outer loop for voltage control. When the Power MOSFET output

transistor is on, the inductor current (primary side of the transformer) is monitored with a SenseFET

technique and converted into a voltage VS proportional to this current. When VS reaches VCOMP (the

amplified output voltage error) the power switch is switched off. Thus, the outer voltage control loop

defines the level at which the inner loop regulates peak current through the power switch and the primary

winding of the transformer.

Excellent open loop D.C. and dynamic line regulation is ensured due to the inherent input voltage

feedforward characteristic of the current mode control. This results in improved line regulation,

instantaneous correction to line changes, and better stabili ty for the volta ge regulation loop .

Current mode topology also ensures good limit ation in case there is a short circuit. During the fi rst phase

the output current increases slowly following the dynamic of the regulation loop. Then it reaches the

maxim um limitation current internally set and finally s tops because the power supply on VDD i s no longer

correct. For specific applications the maximum peak current internally set can be overridden by externally

limiting the voltage excursion on the COMP pin. An integrated blanking filter inhibit s the PWM comparator

output for a short time after the integrated Power MOSFET is switched on. This function prevents

anoma lous or premature termination of the switching pulse in case there are current spikes caused by

primary side capacitance or secondary side rectifier re verse recovery time.

Stand-by Mode

Stand-by operation in nearly open load conditions automatically leads to a burst mode operation allowing

voltage reg ulation on the secondary s ide. Th e transition from normal operation t o burst mode opera tion

happens for a power P STBY given by :

Where:

LP is the primary inductance of the transformer. FSW is the normal switching frequency.

ISTBY is the minimum con trollable current, corresponding to the minim um on time that the device is able

to provide in normal operation. This current can be computed as :

tb + td is the sum of the blanking time and of the propagation time of the internal current sense and

comparator, and represents roughly the minimum on time of the device. Note: that PSTBY may be

affected by the efficiency of the converter at low load , and must i ncl ude the power drawn on the primary

auxiliary voltage.

As so on a s the power goes below this lim it, the auxiliar y secondar y voltage starts to increase above the

13V regulation le ve l, forcing t he output voltage of the transcondu cta nce amplifier to low state (VCOMP <

VCOMPth). This situation leads to the shutdown mode where the power switch is maintained in the Off

state, resulting in missing cycles and zero duty cycle. As soon as VDD gets back to the regulation level

and the VCOMPth threshold is reached, the device operates again. The above cycle repeats indefinitely,

providing a burst mode of which the effective duty cycle is much lower than the minimum one when in

normal operation. The equivalent switching frequency is also lower than the normal one, leading to a

reduce d consumption on t he input ma in supply lines. This mode of operation a llows the VIPer1 00/100A

to meet the new Germ an "Blue A ngel" Norm with less than 1 W total powe r consum ption for the system

when working in stand-by mode. The output voltage remains regulated around the normal level, with a

low frequ ency ripple correspondi ng to the burst mod e. The am plitude of th is ripple is low, because of the

output capacitors and low output current drawn in such conditions.The normal operation resumes

automatically when the power gets back to higher levels than PSTBY.

PSTBY 1

---LPI2STBYFSW=

ISTBY tbtd

+()VIN

-----------------------------=

VIPer100/SP - VIPer100A/ASP

14/24

High Voltage Start-up Current S uorce

An integrated hig h voltage current source provides a bias current from the DRAIN pin during the start- up

phase. This current is partially absorbed by internal control circuits which are placed into a standby mode

with reduced consumption and also provided to the external capacitor connected to the VDD pin. As soon

as the voltage on this pin reaches the high voltage threshold VDDon of the UVLO logic, the device

becomes active mode and starts switching. The start-up current generator is switched off, and the

converter should normally provide the needed current on the VDD pin through the auxiliary winding of the

transfo rmer, as shown on (see Figure 18).

In case there are abnormal conditions where the auxiliary winding is unable to provide the low voltage

supply current to the VDD pin (i.e. short circuit on the output of the converter), the external capacitor

discharges to the low threshold voltage VDDoff of the UVLO logic, and the device goes back to the inactive

state where the internal circuits are in standby mode and the start-up current source is activated. The

converter enters a endless start-up cycle, with a start-up duty cycle defined by the ratio of charging

current towards discharging when the V IPer100/100A tries to s tart. This ra tio is fixed by design to 2A to

15A, which gives a 12% st art -up duty cycl e while the power dissipatio n at st art-up is approximately 0.6W,

for a 230Vrms input voltage.

This low value start-up duty cycle prevents the application of stress to the out put rectifiers as well as the

transformer when a short circuit occurs.

The external cap acitor CVDD on the VDD pin must be sized accor ding to the time needed by the converter

to start up, when the dev ice starts s witch ing. This time tSS de pends on m any parameters, am ong which

transfo rm er design, output capa citors, soft s tart feat ure, and compensation network implemented on the

COMP pin. The following formula can be used for defining the minimum capacitor needed:

where:

IDD is the consumption current on the VDD pi n w hen switching. Refer to specified IDD1 and IDD2 values.

tSS is the s tart u p tim e of the converter whe n the d evice begins to swit ch . Worst case is generally at full

load.

VDDhyst is the voltage hysteresis of the UVLO logic (refer to the minimum specified value).

The soft st art feature can be implemented on the COMP pin through a simple capacitor which will be also

used as the com pensation network. In th is case, the re gulation loop bandwidth is rather low, because of

the large value of this capac itor. In case a large regulation loop bandwidth is mandatory, the schemat ics

of (see Figure 19) can be used. It mixes a high performance compensation network together with a

separate high value soft start capacitor. Both soft start time and regulation loop bandwidth can be

adjusted separately.

If the device is i ntentionally shut down by tying the COMP pin to ground, the device is also perform ing

sta rt-u p cycles, and the VDD volta ge is oscillating between V DDon and VDDoff.

This voltage can be used for supplying external functions, provided that their consumption does not

exceed 0.5mA. (see Figure 20) page 17 shows a typical application of this function, with a latched

shutdown. Once t he "Shutdown" s ignal has been act ivated, the d evice remain s in th e Off state until the

input voltage is removed.

CVDD

IDDtSS

VDDhyst

-------------------->

VIPer100/SP - VIPer100A/ASP

15/24

Figure 18. Beha viour of the high vol tag e curr ent sou rce at star t-up

Ref.

UNDERVOLTAGE

LOCK OUT LOGIC

15 mA

1 mA

3 mA

2 mA

15 mA

VDD DRAIN

SOURC

VIPer100

A ux il iary pr im a r y

winding

VDD

DDoff

VDDon

Start up du ty cycle ~ 12%

CVDD

FC00100

VIPer100/SP - VIPer100A/ASP

16/24

Transconducta nce Error Amplifier

The V IPer100/100A includes a tran scond uctance error amplifier. Trans conduc tance G m is the change in

output curren t (ICOMP) ve rsus change in input voltage (VDD). Thus:

The outp ut impeda nce ZCOMP at the output of this amplifier (COMP pin) can be defined as:

This last equation shows that the open loop gain AVOL can be related to G m and ZCOMP:

AVOL = Gm x ZCOMP

where Gm value for VIPer100/100A is 1.5 mA/V typically.

Gm is defined by specification, but ZCOMP and therefore AVOL are subject to large tolerances. An

impedance Z can be connected between the COMP pin and ground in order to define the transfer

function F of the error amplifier mo re accurately, according to the following equation (very similar to the

one above):

F(S) = Gm x Z(S )

The error amplifier frequency response is reported in figure 10 page 8 for different values of a simple

resistance connected on the COMP pin. The unloaded transconductance error amplifier shows an

int e rn al Z COMP of about 330KΩ. More complex impedance can be connected on the COMP pin to achieve

different compensation level. A capacitor will provide an integrator function, thus eliminati ng the DC static

error, and a resistance in series leads to a flat gain at h igher frequency, insuring a correct phas e ma rgin.

This configuration is illustrated in (see F igure 21) page 17.

As shown in (see F igure 21) an additional no ise fi lteri ng capacitor of 2.2nF is generally needed to avoid

any high frequency interferen ce.

Is also possible to implement a slope compensation when working in continuous mode with duty cycle

higher than 50%. (see Figure 22) shows such a configuration. Note: R1 and C2 build the classical

compensation network, and Q1 is injecting the slope compensation with the correct polarity from the

oscillator sawtooth.

External Clock Synchronization:

The OSC pin provides a synchronisation capability when connected to an external frequency source.

(see Figure 23) page17 shows one possible schematic to be adapted, depen ding the specific needs. If

the proposed schematic is used, the pulse duration must be kept at a low value (500ns is sufficient) for

minimi zing consu mption . The optocoupl er must be able to provide 20mA through the optotransist or.

Primary P eak Current Limitation

The primary IDPEAK current and, consequently, the output power can be limited using the simple circuit

shown in (see Figure 24) page 18. The circuit based on Q1, R1 and R2 clamps the voltage on the COMP

pin in order to limit the primary peak current of the device to a valu e:

where:

The suggested value for R1+R2 is in the range of 220KΩ.

∂

COM

∂VDD

------------------- -

----

COMP

∂

COMP

∂ICO MP

-------------------------- 1

---------∂

COM

∂VDD

----------------------

----

DPEAK

COMP

0.5–

HID

-------------------- ------------

----

COMP 0.6

------------------

VIPer100/SP - VIPer100A/ASP

17/24

Over-Temperatu re Protection

Over-temperature protecti on is based on chip temperature sensing. The minimum junction temperature at

which over-temperature cut-out occurs is 140ºC, while the typical value is 170ºC. The device is

automatically restarted when the junction temperature decreases to the restart temperature threshold that

is typically 40ºC below the shutdown value (see Figure 11) page 8..

Figure 19. M ixe d Soft Start and Co m pensati on Figure 20. Latched Shu t Down

Figure 21. Typical Compen sation Netwo rk Figure 22. Slope Comp ensa tion

Figu re 23 . External Cl ock S in chroni sa ti on Figure 24. Curr e nt Li m itati on Ci rc u it Exam pl e

AUXILIAR

WINDING

13V

OSC

COMP SOURCE

DRAINVDD

VIPER100

C1 +C2

+C3

FC00131

13V

OSC

COMP SOURCE

DRAINVDD

VIPER100

Shutdown

R2R3

R4 D1

FC00110

13V

OSC

COMP SOURCE

DRAINVDD

VIPER100

FC00121

FC00141

13V

OSC

COMP SOURCE

DRAINVDD

VIPER100

R1R2

C1 R3

13V

OSC

COMP SOURCE

DRAINVDD

VIPER100

10 kΩ

FC00220

13V

OSC

COMP SOURCE

DRAINVDD

VIPER100

FC00240

VIPer100/SP - VIPer100A/ASP

18/24

Figure 25. Input Voltage Surges Pr otecti on

El ectrical Over Stre ss Ru g ge d n ess

The VIPer may be submitted to electrical over-stress, caused by violent input voltage surges or lightning.

Following the Layout Considerations is sufficient to prevent catastrophic damages most of the time.

However in some cases, the voltage surges coupled through the transformer auxiliary winding can

exceed the VDD pin absolute maximum rating voltage value. Such events may trigger the VDD internal

protection circuitry which cou ld b e damaged by the strong discharge current of the VDD bulk capacitor.

The simple RC filter shown in (see Figure 25) page 17 can be implemented to improve the application

immuni ty to such surge s.

ul k cap aci t or

(Optional)

22nF

Auxilliary windin

13V

OSC

COMP SOURCE

DRAIN

VDD

VIPerXX0

39R

VIPer100/SP - VIPer100A/ASP

19/24

Figure 26. Recommended Layout

Layout Conside rations

Some simple rules insure a correct running of switching power supplies. They may be classified into two

categorie s:

- Minimizing power loop s: The switched power current must be carefully analysed and the corr esponding

paths must be as small an inner loop area as possible. This avoids radiated EMC noises, conducted EMC

noises by magnetic coupling, and provides a better efficiency by eliminating parasitic inductances,

espe cially on secondary side.

- Using different tracks for low level and power sig nals: Interference due to mixin g of signal and power

may re su lt in in stabilit ies and/ or anom alous behaviour of the device in case of violent power surge (Input

overvoltages, output short circuits...).

In case of VIPer, these rules apply as shown on (see Figure 26).

• Loops C1-T1-U1, C5-D2-T1, and C7-D1-T1 must be minim ized.

• C6 must be as close as possible to T1.

• Signal com ponents C2, ISO1, C3, and C4 are using a dedi cated track connec ted directly to the power

source of the device.

VIPerXX0

13V

OSC

COMP SOURCE

DRAINVDD

ISO1

From input

iodes bridge

To s ec ondary

filtering and loa

FC00500

VIPer100/SP - VIPer100A/ASP

20/24

Pentawatt HV Mechanical Data

Dim mm. inch

Min. Typ. Maw. Min. Typ. Max.

A 4.30 4.80 0.169 0.189

C 1.17 1.37 0.046 0.054

D 2.40 2.80 0.094 0.11

E 0.35 0.55 0.014 0.022

F 0.60 0.80 0.024 0.031

G1 4.91 5.21 0.193 0.205

G2 7.49 7.80 0.295 0.307

H1 9.30 9.70 0.366 0.382

H2 10.40 0.409

H3 10.05 10.40 0.396 0.409

L 15.60 17.30 6.14 0.681

L1 14.60 15.22 0.575 0.599

L2 21.20 21.85 0.835 0.860

L3 22.20 22.82 0.874 0.898

L5 2.60 3 0.102 0.118

L6 15.10 15.80 0.594 0.622

L7 6 6.60 0.236 0.260

M 2.50 3.10 0.098 0.122

M1 4.50 5.60 0.177 0.220

R0.50 0.02

V4 90°

Diam 3.65 3.85 0.144 0.152

P023H3

VIPer100/SP - VIPer100A/ASP

21/24

Pentawatt HV 022Y ( Vertical High Pitch ) Mechanical Data

Dim mm. inch

Min. Typ. Maw. Min. Typ. Max.

A 4.30 4.80 0.169 0.189

C 1.17 1.37 0.046 0.054

D 2.40 2.80 0.094 0.110

E 0.35 0.55 0.014 0.022

F 0.60 0.80 0.024 0.031

G1 4.91 5.21 0.193 0.205

G2 7.49 7.80 0.295 0.307

H1 9.30 9.70 0.366 0.382

H2 10.40 0.409

H3 10.05 10.40 0.396 0.409

L 16.42 17.42 0.646 0.686

L1 14.60 15.22 0.575 0.599

L3 20.52 21.52 0.808 0.847

L5 2.60 3.00 0.102 0.118

L6 15.10 15.80 0.594 0.622

L7 6.00 6.60 0.236 0.260

M 2.50 3.10 0.098 0.122

M1 5.00 5.70 0.197 0.224

R 0.50 0.02 0.020

V4 90°90°

Diam 3.65 3.85 0.144 0.154

DIA

LL1

EResi n between

leads

VIPer100/SP - VIPer100A/ASP

22/24

Figure 27. Pentawatt HV Tube Shipment ( no suffix )

A ll di m e ns i o ns ar e in mm.

Base Q.t y 50

Bulk Q.ty 1000

Tube lengt h ( ± 0.5 )532

A18

B33.1

C ( ± 0.1)1

VIPer100/SP - VIPer100A/ASP

23/24

Table 13. Revision histor y

Date Revision Changes

02-Ma y-2005 1 Ini ti al rel ease.

08-JUn-2005 2 Update without PowerSO-10TM

VIPer100/SP - VIPer100A/ASP

24/24

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