ADC121S101CIMF/NOPB - Texas Instruments High-Performance Analog

3 4

VACS

GND SDATA

VIN SCLK

ADC121S101

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SNAS304F –JANUARY 2006–REVISED MAY 2013

ADC121S101/ADC121S101–Q1 Single Channel, 0.5 to 1 Msps, 12-Bit A/D Converter

Check for Samples: ADC121S101

1FEATURES DESCRIPTION

The ADC121S101 is a low-power, single channel

2• Specified Over a Range of Sample Rates CMOS 12-bit analog-to-digital converter with a high-

• 6-lead WSON and SOT-23 Packages speed serial interface. Unlike the conventional

• Variable Power Management practice of specifying performance at a single sample

rate only, the ADC121S101 is fully specified over a

• Single Power Supply with 2.7V - 5.25V Range sample rate range of 500 ksps to 1 Msps. The

• SPI™/QSPI™/MICROWIRE/DSP Compatible converter is based upon a successive-approximation

• AEC-Q100 Grade 1 Qualified register architecture with an internal track-and-hold

circuit.

APPLICATIONS The output serial data is straight binary, and is

• Portable Systems compatible with several standards, such as SPI™,

QSPI™, MICROWIRE, and many common DSP

• Remote Data Acquisition serial interfaces.

• Instrumentation and Control Systems The ADC121S101 operates with a single supply that

• Automotive can range from +2.7V to +5.25V. Normal power

consumption using a +3V or +5V supply is 2.0 mW

KEY SPECIFICATIONS and 10 mW, respectively. The power-down feature

• DNL: +0.5 / −0.3 LSB (typ) reduces the power consumption to as low as 2.6 µW

using a +5V supply.

• INL: ±0.40 LSB (typ) The ADC121S101 is packaged in 6-lead WSON and

• Power Consumption SOT-23 packages. Operation over the temperature

– 3V Supply: 2.0 mW(typ) range of −40°C to +125 °C is specified.

– 5V Supply: 10 mW (typ)

PIN-COMPATIBLE ALTERNATIVES BY RESOLUTION AND SPEED(1)

Resolution Specified for Sample Rate Range of:

50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps

12-bit ADC121S021 ADC121S051 ADC121S101

10-bit ADC101S021 ADC101S051 ADC101S101

8-bit ADC081S021 ADC081S051 ADC081S101

(1) All devices are fully pin and function compatible.

CONNECTION DIAGRAM

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

T/H

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

SCLK

SDATA

CONTROL

LOGIC

VIN

ADC121S101

SNAS304F –JANUARY 2006–REVISED MAY 2013

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

BLOCK DIAGRAM

PIN DESCRIPTIONS

Pin No. Symbol Description

ANALOG I/O

3 VIN Analog input. This signal can range from 0V to VA.

DIGITAL I/O

4 SCLK Digital clock input. This clock directly controls the conversion and readout processes.

5 SDATA Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin.

6 CS Chip select. On the falling edge of CS, a conversion process begins.

POWER SUPPLY

Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to

1 VAGND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin.

2 GND The ground return for the supply and signals.

PAD GND For package suffix CISD(X) only, it is recommended that the center pad should be connected to ground.

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ADC121S101

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ABSOLUTE MAXIMUM RATINGS(1)(2)(3)

Analog Supply Voltage VA−0.3V to 6.5V

Voltage on Any Digital Pin to GND −0.3V to 6.5V

Voltage on Any Analog Pin to GND −0.3V to (VA+0.3V)

Input Current at Any Pin(4) ±10 mA

Package Input Current(4) ±20 mA

Power Consumption at TA= 25°C See(5)

Human Body Model 3500V

ESD Susceptibility(6) Machine Model 300V

Junction Temperature +150°C

Storage Temperature −65°C to +150°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see

the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics

may degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(4) When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin should be limited to

10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an

input current of 10 mA to two. The Absolute Maximum Rating specification does not apply to the VApin. The current into the VApin is

limited by the Analog Supply Voltage specification.

(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by

TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula

PDmax = (TJmax −TA) / θJA. The values for maximum power dissipation listed above will be reached only when the device is operated

in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is

reversed). Obviously, such conditions should always be avoided.

(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩresistor. Machine model is 220 pF discharged through zero ohms.

OPERATING RATINGS(1)(2)

Operating Temperature Range −40°C ≤TA≤+125°C

VASupply Voltage +2.7V to +5.25V

Digital Input Pins Voltage Range (regardless of supply voltage) −0.3V to 5.25V

Analog Input Pins Voltage Range 0V to VA

Clock Frequency 25 kHz to 20 MHz

Sample Rate up to 1 Msps

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see

the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics

may degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.

PACKAGE THERMAL RESISTANCE(1)(2)

Package θJA

6-lead WSON 94°C / W

6-lead SOT-23 265°C / W

(1) Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to

www.national.com/packaging

(2) Reflow temperature profiles are different for lead-free and non-lead-free packages.

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ADC121S101

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ADC121S101 CONVERTER ELECTRICAL CHARACTERISTICS(1)(2)

The following specifications apply for VA= +2.7V to 5.25V, GND = 0V, fSCLK = 10 MHz to 20 MHz, CL= 15 pF, fSAMPLE = 500

ksps to 1 Msps, unless otherwise noted. Boldface limits apply for TA= -40°C to +125°C: all other limits TA= 25°C unless

otherwise noted.

Symbol Parameter Conditions Typical Limits(2) Units

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing VA= +2.7v to +3.6V −40°C ≤TA≤125°C 12 Bits

Codes +0.4 LSB (max)

SOT-23 ±1.0

-0.4 LSB (min)

−40°C ≤TA≤+85°C, VA= +2.7V to

+3.6V +0.4 +1.0 LSB (max)

WSON -0.4 -1.2 LSB (min)

INL Integral Non-Linearity +1.0 LSB (max)

SOT-23 -1.1 LSB (min)

TA= 125°C, VA= +2.7v to +3.6V +1.0 LSB (max)

WSON -1.3 LSB (min)

+0.5 +1.0 LSB (max)

−40°C ≤TA≤+85°C, VA= +2.7V to +3.6V

DNL Differential Non-Linearity −0.3 -0.9 LSB (min)

TA= 125°C, VA= +2.7v to +3.6V ±1.0 LSB (max)

LSB (max)

VOFF Offset Error −40°C ≤TA≤125°C, VA= +2.7v to +3.6V ±0.1 ±1.2 LSB (min)

SOT-23 ±0.20 ±1.2 LSB (max)

GE Gain Error −40°C ≤TA≤125°C, VA= +2.7 to +3.6V WSON ±0.20 ±1.5 LSB (max)

DYNAMIC CONVERTER CHARACTERISTICS

Signal-to-Noise Plus VA= +2.7 to 5.25V, −40°C ≤TA≤125°C

SINAD 72 70 dB (min)

Distortion Ratio fIN = 100 kHz, −0.02 dBFS

VA= +2.7 to 5.25V, −40°C ≤TA≤+85°C 72.5 70.8

fIN = 100 kHz, −0.02 dBFS

SNR Signal-to-Noise Ratio dB (min)

VA= +2.7 to 5.25V, TA= +125°C 70.6

fIN = 100 kHz, −0.02 dBFS

THD Total Harmonic Distortion VA= +2.7 to 5.25V, fIN = 100 kHz, −0.02 dBFS −80 dB (max)

Spurious-Free Dynamic

SFDR VA= +2.7 to 5.25V, fIN = 100 kHz, −0.02 dBFS 82 dB (min)

Range

ENOB Effective Number of Bits VA= +2.7 to 5.25V, fIN = 100 kHz, −0.02 dBFS 11.6 11.3 Bits (min)

Intermodulation Distortion, VA= +5.25V, fa= 103.5 kHz, fb= 113.5 kHz −78 dB

Second Order Terms

IMD Intermodulation Distortion, VA= +5.25V, fa= 103.5 kHz, fb= 113.5 kHz −78 dB

Third Order Terms VA= +5V 11 MHz

FPBW -3 dB Full Power Bandwidth VA= +3V 8 MHz

ANALOG INPUT CHARACTERISTICS

VIN Input Range 0 to VAV

IDCL DC Leakage Current ±1 µA (max)

Track Mode 30 pF

CINA Input Capacitance Hold Mode 4 pF

(1) Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

(2) Data sheet min/max specification limits are guaranteed by design, test, or statistical analysis.

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ADC121S101

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ADC121S101 CONVERTER ELECTRICAL CHARACTERISTICS(1)(2) (continued)

The following specifications apply for VA= +2.7V to 5.25V, GND = 0V, fSCLK = 10 MHz to 20 MHz, CL= 15 pF, fSAMPLE = 500

ksps to 1 Msps, unless otherwise noted. Boldface limits apply for TA= -40°C to +125°C: all other limits TA= 25°C unless

otherwise noted.

Symbol Parameter Conditions Typical Limits(2) Units

DIGITAL INPUT CHARACTERISTICS

VA= +5.25V 2.4 V (min)

VIH Input High Voltage VA= +3.6V 2.1 V (min)

VA= +5V 0.8 V (max)

VIL Input Low Voltage VA= +3V 0.4 V (max)

IIN Input Current VIN = 0V or VA±0.1 ±1 µA (max)

CIND Digital Input Capacitance 2 4pF (max)

DIGITAL OUTPUT CHARACTERISTICS

ISOURCE = 200 µA VA−0.07 VA−0.2 V (min)

VOH Output High Voltage ISOURCE = 1 mA VA−0.1 V

ISINK = 200 µA 0.03 0.4 V (max)

VOL Output Low Voltage ISINK = 1 mA 0.1 V

IOZH, TRI-STATE Leakage ±0.1 ±10 µA (max)

IOZL Current

TRI-STATE Output

COUT 24pF (max)

Capacitance

Output Coding Straight (Natural) Binary

POWER SUPPLY CHARACTERISTICS

2.7 V (min)

VASupply Voltage 5.25 V (max)

VA= +5.25V, fSAMPLE = 1 Msps 2.0 3.2 mA (max)

Supply Current, Normal

Mode (Operational, CS low) VA= +3.6V, fSAMPLE = 1 Msps 0.6 1.5 mA (max)

IAfSCLK = 0 MHz, VA= +5V, fSAMPLE = 0 ksps 500 nA

Supply Current, Shutdown

(CS high) fSCLK = 20 MHz, VA= +5V, fSAMPLE = 0 ksps 60 µA

Power Consumption, VA= +5V 10 16 mW (max)

Normal Mode (Operational, VA= +3V 2.0 4.5 mW (max)

CS low)

PDfSCLK = 0 MHz, VA= +5V, fSAMPLE = 0 ksps 2.5 µW

Power Consumption,

Shutdown (CS high) fSCLK = 20 MHz, VA= +5V, fSAMPLE = 0 ksps 300 µW

AC ELECTRICAL CHARACTERISTICS

10 MHz (min)

fSCLK Clock Frequency(3) See(4) 20 MHz (max)

500 ksps (min)

fSSample Rate See(4) 1Msps (max)

40 % (min)

DC SCLK Duty Cycle fSCLK = 20 MHz 50 60 % (max)

Minimum Time Required for

tACQ 350 ns (max)

Acquisition

tQUIET See(5) 50 ns (min)

tAD Aperture Delay 3 ns

tAJ Aperture Jitter 30 ps

(3) This condition is for fSCLK = 20 MHz.

(4) This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is

specified under Operating Ratings.

(5) Minimum Quiet Time required by bus relinquish and the start of the next conversion.

Product Folder Links: ADC121S101

IOL

200 PA

IOH

200 PA

1.6 V

To Output Pin CL

25 pF

ADC121S101

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ADC121S101 TIMING SPECIFICATIONS

The following specifications apply for VA= +2.7V to 5.25V, GND = 0V, fSCLK = 10.0 MHz to 20.0 MHz, CL= 25 pF, fSAMPLE =

500 ksps to 1 Msps, Boldface limits apply for TA= -40°C to +125°C; all other limits TA= 25°C.

Symbol Parameter Conditions Typical Limits Units

tCS Minimum CS Pulse Width 10 ns (min)

tSU CS to SCLK Setup Time 10 ns (min)

tEN Delay from CS Until SDATA TRI-STATE Disabled(1) 20 ns (max)

VA= +2.7 to +3.6 40 ns (max)

tACC Data Access Time after SCLK Falling Edge(2) VA= +4.75 to +5.25 20 ns (max)

tCL SCLK Low Pulse Width 0.4 x tSCLK ns (min)

tCH SCLK High Pulse Width 0.4 x tSCLK ns (min)

VA= +2.7V to +3.6V 7ns (min)

tHSCLK to Data Valid Hold Time VA= +4.75V to +5.25V 5ns (min)

25 ns (max)

VA= +2.7V to +3.6V 6ns (min)

tDIS SCLK Falling Edge to SDATA High Impedance(3) 25 ns (max)

VA= +4.75V to +5.25V 5ns (min)

tPOWER-UP Power-Up Time from Full Power-Down 1 µs

(1) Measured with the timing test circuit shown in TIMING DIAGRAMS and defined as the time taken by the output signal to cross 1.0V.

(2) Measured with the timing test circuit shown in TIMING DIAGRAMS and defined as the time taken by the output signal to cross 1.0V or

2.0V.

(3) tDIS is derived from the time taken by the outputs to change by 0.5V with the timing test circuit shown in TIMING DIAGRAMS. The

measured number is then adjusted to remove the effects of charging or discharging the output capacitance. This means that tDIS is the

true bus relinquish time, independent of the bus loading.

TIMING DIAGRAMS

Figure 1. Timing Test Circuit

Product Folder Links: ADC121S101

Z2 Z1 Z0 DB11 DB3 DB2 DB1 DB0

tQUIET

Track

3 leading zero bits 12 data bits

SCLK

SDATA

1 2 3 4 5 12 13 14 15 16

TRI-STATE

tSU tCL

tEN tCH tACC tHtDIS

tCS

Hold

tACQ

17 18 19 20

ADC121S101

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Figure 2. ADC121S101 Serial Timing Diagram

SPECIFICATION DEFINITIONS

ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold

capacitor to charge up to the input voltage. Acquisition time is measured backwards from the falling edge of CS

when the signal is sampled and the part moves from Track to Hold. The start of the time interval that contains

tACQ is the 13th rising edge of SCLK of the previous conversion when the part moves from hold to track. The user

must ensure that the time between the 13th rising edge of SCLK and the falling edge of the next CS is not less

than tACQ to meet performance specifications.

APERTURE DELAY is the time after the falling edge of CS to when the input signal is acquired or held for

conversion.

APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.

Aperture jitter manifests itself as noise in the output.

CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input

voltage to a digital word. This is from the falling edge of CS when the input signal is sampled to the 16th falling

edge of SCLK when the SDATA output goes into TRI-STATE.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB.

DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The

specification here refers to the SCLK.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion or SINAD. ENOB is defined as (SINAD −1.76) / 6.02 and says that the converter is equivalent to

a perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input.

GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF −1.5

LSB), after adjusting for offset error.

INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from

negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code

transition). The deviation of any given code from this straight line is measured from the center of that code value.

Product Folder Links: ADC121S101

‡

THD = 20 log10 Af12



Af22 + + Af62

ADC121S101

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INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two

sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in

the second and third order intermodulation products to the sum of the power in both of the original frequencies.

IMD is usually expressed in dB.

MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC121S101 is

guaranteed not to have any missing codes.

OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +

0.5 LSB).

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms

value of the sum of all other spectral components below one-half the sampling frequency, not including

harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral components below half the clock frequency, including

harmonics but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal

amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is

any signal present in the output spectrum that is not present at the input and may or may not be a harmonic.

TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first five

harmonic components at the output to the rms level of the input signal frequency as seen at the output. THD is

calculated as

(1)

where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the

first 5 harmonic frequencies.

THROUGHPUT TIME is the minimum time required between the start of two successive conversion. It is the

acquisition time plus the conversion time.

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ADC121S101

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TYPICAL PERFORMANCE CHARACTERISTICS

TA= +25°C, fSAMPLE = 500 ksps to 1 Msps,fSCLK = 10 MHz to 20 MHz, fIN = 100 kHz unless otherwise stated.

DNL fSCLK = 10 MHz INL fSCLK = 10 MHz

Figure 3. Figure 4.

DNL fSCLK = 20 MHz INL fSCLK = 20 MHz

Figure 5. Figure 6.

DNL vs. Clock Frequency INL vs. Clock Frequency

Figure 7. Figure 8.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

TA= +25°C, fSAMPLE = 500 ksps to 1 Msps,fSCLK = 10 MHz to 20 MHz, fIN = 100 kHz unless otherwise stated.

SNR vs. Clock Frequency SINAD vs. Clock Frequency

Figure 9. Figure 10.

SFDR vs. Clock Frequency THD vs. Clock Frequency

Figure 11. Figure 12.

Spectral Response, VA= 5.25V Spectral Response, VA= 5.25V

fSCLK = 10 MHz fSCLK = 20 MHz

Figure 13. Figure 14.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

TA= +25°C, fSAMPLE = 500 ksps to 1 Msps,fSCLK = 10 MHz to 20 MHz, fIN = 100 kHz unless otherwise stated.

Power Consumption vs.

Throughput, fSCLK = 20 MHz

Figure 15.

Product Folder Links: ADC121S101

GND

SAMPLING

CAPACITOR

SW1 -

+CONTROL

LOGIC

CHARGE

REDISTRIBUTION

DAC

SW2

VIN

GND

SAMPLING

CAPACITOR

SW1 -

+CONTROL

LOGIC

CHARGE

REDISTRIBUTION

DAC

SW2

VIN

ADC121S101

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APPLICATIONS INFORMATION

ADC121S101 OPERATION

The ADC121S101 is a successive-approximation analog-to-digital converter designed around a charge-

redistribution digital-to-analog converter core. Simplified schematics of the ADC121S101 in both track and hold

modes are shown in Figure 16 and Figure 17, respectively. In Figure 16, the device is in track mode: switch SW1

connects the sampling capacitor to the input, and SW2 balances the comparator inputs. The device is in this

state until CS is brought low, at which point the device moves to hold mode.

Figure 17 shows the device in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining

the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-

redistribution DAC to add or subtract fixed amounts of charge from the sampling capacitor until the comparator is

balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of

the analog input voltage. The device moves from hold mode to track mode on the 13th rising edge of SCLK.

Figure 16. ADC121S101 in Track Mode

Figure 17. ADC121S101 in Hold Mode

USING THE ADC121S101

The serial interface timing diagram for the ADC is shown in Figure 2. CS is chip select, which initiates

conversions on the ADC and frames the serial data transfers. SCLK (serial clock) controls both the conversion

process and the timing of serial data. SDATA is the serial data out pin, where a conversion result is found as a

serial data stream.

Basic operation of the ADC begins with CS going low, which initiates a conversion process and data transfer.

Subsequent rising and falling edges of SCLK will be labelled with reference to the falling edge of CS; for

example, "the third falling edge of SCLK" shall refer to the third falling edge of SCLK after CS goes low.

At the fall of CS, the SDATA pin comes out of TRI-STATE, and the converter moves from track mode to hold

mode. The input signal is sampled and held for conversion on the falling edge of CS. The converter moves from

hold mode to track mode on the 13th rising edge of SCLK (see Figure 2). It is at this point that the interval for the

tACQ specification begins. In the worst case, 350ns must pass between the 13th rising edge and the next falling

edge of SCLK. The SDATA pin will be placed back into TRI-STATE after the 16th falling edge of SCLK, or at the

rising edge of CS, whichever occurs first. After a conversion is completed, the quiet time tQUIET must be satisfied

before bringing CS low again to begin another conversion.

Product Folder Links: ADC121S101

000...001

000...010

011...111

111...000

000...000

111...111

111...110

ADC CODE

ANALOG INPUT

1 LSB = VA/4096

0.5 LSB +VA-1.5 LSB

ADC121S101

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Sixteen SCLK cycles are required to read a complete sample from the ADC. The sample bits (including leading

zeroes) are clocked out on falling edges of SCLK, and are intended to be clocked in by a receiver on subsequent

falling edges of SCLK. The ADC will produce three leading zero bits on SDATA, followed by twelve data bits,

most significant first.

If CS goes low before the rising edge of SCLK, an additional (fourth) zero bit may be captured by the next falling

edge of SCLK.

Determining Throughput

Throughput depends on the frequency of SCLK and how much time is allowed to elapse between the end of one

conversion and the start of another. At the maximum specified SCLK frequency, the maximum guaranteed

throughput is obtained by using a 20 SCLK frame. As shown in Figure 2, the minimum allowed time between CS

falling edges is determined by 1) 12.5 SCLKs for Hold mode, 2) the larger of two quantities: either the minimum

required time for Track mode (tACQ) or 2.5 SCLKs to finish reading the result and 3) 0, 1/2 or 1 SCLK padding to

ensure an even number of SCLK cycles so there is a falling SCLK edge when CS next falls.

For example, at the fastest rate for this family of parts, SCLK is 20MHz and 2.5 SCLKs are 125ns, so the

minimum time between CS falling edges is calculated by

12.5*50ns + 350ns + 0.5*50ns = 1000ns (2)

(12.5 SCLKs + tACQ + 1/2 SCLK) which corresponds to a maximum throughput of 1MSPS. At the slowest rate for

this family, SCLK is 1MHz. Using a 20 cycle conversion frame as shown in Figure 2 yields a 20µs time between

CS falling edges for a throughput of 50KSPS.

It is possible, however, to use fewer than 20 clock cycles provided the timing parameters are met. With a 1MHz

SCLK, there are 2500ns in 2.5 SCLK cycles, which is greater than tACQ. After the last data bit has come out, the

clock will need one full cycle to return to a falling edge. Thus the total time between falling edges of CS is

12.5*1µs +2.5*1µs +1*1µs=16µs which is a throughput of 62.5KSPS.

ADC TRANSFER FUNCTION

The output format of the ADC is straight binary. Code transitions occur midway between successive integer LSB

values. The LSB width for the ADC is VA/4096. The ideal transfer characteristic is shown in Figure 18. The

transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB, or a voltage of

VA/8192. Other code transitions occur at steps of one LSB.

Figure 18. Ideal Transfer Characteristic

Product Folder Links: ADC121S101

VIN

26 pF

4 pF

Conversion Phase - Switch Open

Track Phase - Switch Closed

MICROPROCESSOR

DSP

SCLK

SDATA

GND

ADC121S101

LP2950 5V

1 PF0.1 PF 0.1 PF1 PF

VIN

ADC121S101

SNAS304F –JANUARY 2006–REVISED MAY 2013

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TYPICAL APPLICATION CIRCUIT

A typical application of the ADC is shown in Figure 19. Power is provided in this example by the National

Semiconductor LP2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output

voltages. The power supply pin is bypassed with a capacitor network located close to the ADC. Because the

reference for the ADC is the supply voltage, any noise on the supply will degrade device noise performance. To

keep noise off the supply, use a dedicated linear regulator for this device, or provide sufficient decoupling from

other circuitry to keep noise off the ADC supply pin. Because of the ADC's low power requirements, it is also

possible to use a precision reference as a power supply to maximize performance. The three-wire interface is

shown connected to a microprocessor or DSP.

Figure 19. Typical Application Circuit

ANALOG INPUTS

An equivalent circuit for the ADC's input is shown in Figure 20. Diodes D1 and D2 provide ESD protection for the

analog inputs. At no time should the analog input go beyond (VA+ 300 mV) or (GND −300 mV), as these ESD

diodes will begin conducting, which could result in erratic operation. For this reason, the ESD diodes should not

be used to clamp the input signal.

The capacitor C1 in Figure 20 has a typical value of 4 pF, and is mainly the package pin capacitance. Resistor

R1 is the on resistance of the track / hold switch, and is typically 500Ω. Capacitor C2 is the ADC sampling

capacitor and is typically 26 pF. The ADC will deliver best performance when driven by a low-impedance source

to eliminate distortion caused by the charging of the sampling capacitance. This is especially important when

using the ADC to sample AC signals. Also important when sampling dynamic signals is an anti-aliasing filter.

Figure 20. Equivalent Input Circuit

DIGITAL INPUTS AND OUTPUTS

The ADC digital inputs (SCLK and CS) are not limited by the same maximum ratings as the analog inputs. The

digital input pins are instead limited to +5.25V with respect to GND, regardless of VA, the supply voltage. This

allows the ADC to be interfaced with a wide range of logic levels, independent of the supply voltage.

Product Folder Links: ADC121S101

ADC121S101

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SNAS304F –JANUARY 2006–REVISED MAY 2013

MODES OF OPERATION

The ADC has two possible modes of operation: normal mode, and shutdown mode. The ADC enters normal

mode (and a conversion process is begun) when CS is pulled low. The device will enter shutdown mode if CS is

pulled high before the tenth falling edge of SCLK after CS is pulled low, or will stay in normal mode if CS remains

low. Once in shutdown mode, the device will stay there until CS is brought low again. By varying the ratio of time

spent in the normal and shutdown modes, a system may trade-off throughput for power consumption, with a

sample rate as low as zero.

Normal Mode

The fastest possible throughput is obtained by leaving the ADC in normal mode at all times, so there are no

power-up delays. To keep the device in normal mode continuously, CS must be kept low until after the 10th

falling edge of SCLK after the start of a conversion (remember that a conversion is initiated by bringing CS low).

If CS is brought high after the 10th falling edge, but before the 16th falling edge, the device will remain in normal

mode, but the current conversion will be aborted, and SDATA will return to TRI-STATE (truncating the output

word).

Sixteen SCLK cycles are required to read all of a conversion word from the device. After sixteen SCLK cycles

have elapsed, CS may be idled either high or low until the next conversion. If CS is idled low, it must be brought

high again before the start of the next conversion, which begins when CS is again brought low.

After sixteen SCLK cycles, SDATA returns to TRI-STATE. Another conversion may be started, after tQUIET has

elapsed, by bringing CS low again.

Shutdown Mode

Shutdown mode is appropriate for applications that either do not sample continuously, or it is acceptable to trade

throughput for power consumption. When the ADC is in shutdown mode, all of the analog circuitry is turned off.

To enter shutdown mode, a conversion must be interrupted by bringing CS high anytime between the second

and tenth falling edges of SCLK, as shown in Figure 21. Once CS has been brought high in this manner, the

device will enter shutdown mode; the current conversion will be aborted and SDATA will enter TRI-STATE. If CS

is brought high before the second falling edge of SCLK, the device will not change mode; this is to avoid

accidentally changing mode as a result of noise on the CS line.

Figure 21. Entering Shutdown Mode

Figure 22. Entering Normal Mode

To exit shutdown mode, bring CS back low. Upon bringing CS low, the ADC will begin powering up (power-up

time is specified in the ADC121S101 TIMING SPECIFICATIONS table). This power-up delay results in the first

conversion result being unusable. The second conversion performed after power-up, however, is valid, as shown

in Figure 22.

Product Folder Links: ADC121S101

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If CS is brought back high before the 10th falling edge of SCLK, the device will return to shutdown mode. This is

done to avoid accidentally entering normal mode as a result of noise on the CS line. To exit shutdown mode and

remain in normal mode, CS must be kept low until after the 10th falling edge of SCLK. The ADC will be fully

powered-up after 16 SCLK cycles.

POWER MANAGEMENT

The ADC takes time to power-up, either after first applying VA, or after returning to normal mode from shutdown

mode. This corresponds to one "dummy" conversion for any SCLK frequency within the specifications in this

document. After this first dummy conversion, the ADC will perform conversions properly. Note that the tQUIET time

must still be included between the first dummy conversion and the second valid conversion.

When the VAsupply is first applied, the ADC may power up in either of the two modes: normal or shutdown. As

such, one dummy conversion should be performed after start-up, as described in the previous paragraph. The

part may then be placed into either normal mode or the shutdown mode, as described in Normal Mode and

Shutdown Mode.

When the ADC is operated continuously in normal mode, the maximum throughput is fSCLK / 20 at the maximum

specified fSCLK. Throughput may be traded for power consumption by running fSCLK at its maximum specified rate

and performing fewer conversions per unit time, raising the ADC CS line after the 10th and before the 15th fall of

SCLK of each conversion. A plot of typical power consumption versus throughput is shown in the TYPICAL

PERFORMANCE CHARACTERISTICS section. To calculate the power consumption for a given throughput,

multiply the fraction of time spent in the normal mode by the normal mode power consumption and add the

fraction of time spent in shutdown mode multiplied by the shutdown mode power consumption. Note that the

curve of power consumption vs. throughput is essentially linear. This is because the power consumption in the

shutdown mode is so small that it can be ignored for all practical purposes.

POWER SUPPLY NOISE CONSIDERATIONS

The charging of any output load capacitance requires current from the power supply, VA. The current pulses

required from the supply to charge the output capacitance will cause voltage variations on the supply. If these

variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore,

discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current

into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise in the

substrate that will degrade noise performance if that current is large enough. The larger the output capacitance,

the more current flows through the die substrate and the greater is the noise coupled into the analog channel,

degrading noise performance.

To keep noise out of the power supply, keep the output load capacitance as small as practical. It is good practice

to use a 100 Ωseries resistor at the ADC output, located as close to the ADC output pin as practical. This will

limit the charge and discharge current of the output capacitance and improve noise performance.

Product Folder Links: ADC121S101

ADC121S101

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SNAS304F –JANUARY 2006–REVISED MAY 2013

REVISION HISTORY

Changes from Revision E (May 2013) to Revision F Page

• Changed layout of National Data Sheet to TI format. ......................................................................................................... 16

Product Folder Links: ADC121S101

PACKAGE OPTION ADDENDUM

www.ti.com 7-Oct-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

ADC121S101CIMF/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 X01C

ADC121S101CIMFX/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 X01C

ADC121S101CISD/NOPB ACTIVE WSON NGF 6 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 X1C

ADC121S101CISDX/NOPB ACTIVE WSON NGF 6 4500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 X1C

ADC121S101QIMF/NOPB ACTIVE SOT-23 DBV 6 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 X07Q

ADC121S101QIMFX/NOPB ACTIVE SOT-23 DBV 6 3000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 X07Q

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

PACKAGE OPTION ADDENDUM

www.ti.com 7-Oct-2013

Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF ADC121S101, ADC121S101-Q1 :

•Catalog: ADC121S101

•Automotive: ADC121S101-Q1

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADC121S101CIMF/NOPB SOT-23 DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

ADC121S101CIMFX/NOP

BSOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

ADC121S101CISD/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1

ADC121S101CISDX/NOP

BWSON NGF 6 4500 330.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Sep-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADC121S101CIMF/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0

ADC121S101CIMFX/NOP

BSOT-23 DBV 6 3000 210.0 185.0 35.0

ADC121S101CISD/NOPB WSON NGF 6 1000 210.0 185.0 35.0

ADC121S101CISDX/NOP

BWSON NGF 6 4500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Sep-2013

Pack Materials-Page 2

MECHANICAL DATA

NGF0006A

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